module qsys_top ( input wire clk_100_clk, // clk_100.clk input wire reset_reset_n, // reset.reset_n output wire ninit_done_ninit_done, // ninit_done.ninit_done output wire h2f_reset_reset, // h2f_reset.reset output wire [3:0] subsys_hps_hps2fpga_awid, // subsys_hps_hps2fpga.awid output wire [37:0] subsys_hps_hps2fpga_awaddr, // .awaddr output wire [7:0] subsys_hps_hps2fpga_awlen, // .awlen output wire [2:0] subsys_hps_hps2fpga_awsize, // .awsize output wire [1:0] subsys_hps_hps2fpga_awburst, // .awburst output wire subsys_hps_hps2fpga_awlock, // .awlock output wire [3:0] subsys_hps_hps2fpga_awcache, // .awcache output wire [2:0] subsys_hps_hps2fpga_awprot, // .awprot output wire subsys_hps_hps2fpga_awvalid, // .awvalid input wire subsys_hps_hps2fpga_awready, // .awready output wire [127:0] subsys_hps_hps2fpga_wdata, // .wdata output wire [15:0] subsys_hps_hps2fpga_wstrb, // .wstrb output wire subsys_hps_hps2fpga_wlast, // .wlast output wire subsys_hps_hps2fpga_wvalid, // .wvalid input wire subsys_hps_hps2fpga_wready, // .wready input wire [3:0] subsys_hps_hps2fpga_bid, // .bid input wire [1:0] subsys_hps_hps2fpga_bresp, // .bresp input wire subsys_hps_hps2fpga_bvalid, // .bvalid output wire subsys_hps_hps2fpga_bready, // .bready output wire [3:0] subsys_hps_hps2fpga_arid, // .arid output wire [37:0] subsys_hps_hps2fpga_araddr, // .araddr output wire [7:0] subsys_hps_hps2fpga_arlen, // .arlen output wire [2:0] subsys_hps_hps2fpga_arsize, // .arsize output wire [1:0] subsys_hps_hps2fpga_arburst, // .arburst output wire subsys_hps_hps2fpga_arlock, // .arlock output wire [3:0] subsys_hps_hps2fpga_arcache, // .arcache output wire [2:0] subsys_hps_hps2fpga_arprot, // .arprot output wire subsys_hps_hps2fpga_arvalid, // .arvalid input wire subsys_hps_hps2fpga_arready, // .arready input wire [3:0] subsys_hps_hps2fpga_rid, // .rid input wire [127:0] subsys_hps_hps2fpga_rdata, // .rdata input wire [1:0] subsys_hps_hps2fpga_rresp, // .rresp input wire subsys_hps_hps2fpga_rlast, // .rlast input wire subsys_hps_hps2fpga_rvalid, // .rvalid output wire subsys_hps_hps2fpga_rready, // .rready output wire subsys_hps_h2f_warm_reset_handshake_reset_req, // subsys_hps_h2f_warm_reset_handshake.reset_req input wire subsys_hps_h2f_warm_reset_handshake_reset_ack, // .reset_ack input wire hps_io_hps_osc_clk, // hps_io.hps_osc_clk inout wire hps_io_sdmmc_data0, // .sdmmc_data0 inout wire hps_io_sdmmc_data1, // .sdmmc_data1 output wire hps_io_sdmmc_cclk, // .sdmmc_cclk inout wire hps_io_sdmmc_data2, // .sdmmc_data2 inout wire hps_io_sdmmc_data3, // .sdmmc_data3 inout wire hps_io_sdmmc_cmd, // .sdmmc_cmd input wire hps_io_usb0_clk, // .usb0_clk output wire hps_io_usb0_stp, // .usb0_stp input wire hps_io_usb0_dir, // .usb0_dir inout wire hps_io_usb0_data0, // .usb0_data0 inout wire hps_io_usb0_data1, // .usb0_data1 input wire hps_io_usb0_nxt, // .usb0_nxt inout wire hps_io_usb0_data2, // .usb0_data2 inout wire hps_io_usb0_data3, // .usb0_data3 inout wire hps_io_usb0_data4, // .usb0_data4 inout wire hps_io_usb0_data5, // .usb0_data5 inout wire hps_io_usb0_data6, // .usb0_data6 inout wire hps_io_usb0_data7, // .usb0_data7 output wire hps_io_emac0_tx_clk, // .emac0_tx_clk output wire hps_io_emac0_tx_ctl, // .emac0_tx_ctl input wire hps_io_emac0_rx_clk, // .emac0_rx_clk input wire hps_io_emac0_rx_ctl, // .emac0_rx_ctl output wire hps_io_emac0_txd0, // .emac0_txd0 output wire hps_io_emac0_txd1, // .emac0_txd1 input wire hps_io_emac0_rxd0, // .emac0_rxd0 input wire hps_io_emac0_rxd1, // .emac0_rxd1 output wire hps_io_emac0_txd2, // .emac0_txd2 output wire hps_io_emac0_txd3, // .emac0_txd3 input wire hps_io_emac0_rxd2, // .emac0_rxd2 input wire hps_io_emac0_rxd3, // .emac0_rxd3 inout wire hps_io_mdio0_mdio, // .mdio0_mdio output wire hps_io_mdio0_mdc, // .mdio0_mdc output wire hps_io_uart1_tx, // .uart1_tx input wire hps_io_uart1_rx, // .uart1_rx inout wire hps_io_i2c1_sda, // .i2c1_sda inout wire hps_io_i2c1_scl, // .i2c1_scl inout wire hps_io_gpio28, // .gpio28 inout wire hps_io_gpio34, // .gpio34 inout wire hps_io_gpio40, // .gpio40 inout wire hps_io_gpio41, // .gpio41 input wire [31:0] f2h_irq1_in_irq, // f2h_irq1_in.irq input wire [31:0] f2sdram_araddr, // f2sdram.araddr input wire [1:0] f2sdram_arburst, // .arburst input wire [3:0] f2sdram_arcache, // .arcache input wire [4:0] f2sdram_arid, // .arid input wire [7:0] f2sdram_arlen, // .arlen input wire f2sdram_arlock, // .arlock input wire [2:0] f2sdram_arprot, // .arprot input wire [3:0] f2sdram_arqos, // .arqos output wire f2sdram_arready, // .arready input wire [2:0] f2sdram_arsize, // .arsize input wire f2sdram_arvalid, // .arvalid input wire [31:0] f2sdram_awaddr, // .awaddr input wire [1:0] f2sdram_awburst, // .awburst input wire [3:0] f2sdram_awcache, // .awcache input wire [4:0] f2sdram_awid, // .awid input wire [7:0] f2sdram_awlen, // .awlen input wire f2sdram_awlock, // .awlock input wire [2:0] f2sdram_awprot, // .awprot input wire [3:0] f2sdram_awqos, // .awqos output wire f2sdram_awready, // .awready input wire [2:0] f2sdram_awsize, // .awsize input wire f2sdram_awvalid, // .awvalid output wire [4:0] f2sdram_bid, // .bid input wire f2sdram_bready, // .bready output wire [1:0] f2sdram_bresp, // .bresp output wire f2sdram_bvalid, // .bvalid output wire [255:0] f2sdram_rdata, // .rdata output wire [4:0] f2sdram_rid, // .rid output wire f2sdram_rlast, // .rlast input wire f2sdram_rready, // .rready output wire [1:0] f2sdram_rresp, // .rresp output wire f2sdram_rvalid, // .rvalid input wire [255:0] f2sdram_wdata, // .wdata input wire f2sdram_wlast, // .wlast output wire f2sdram_wready, // .wready input wire [31:0] f2sdram_wstrb, // .wstrb input wire f2sdram_wvalid, // .wvalid input wire [7:0] f2sdram_aruser, // .aruser input wire [7:0] f2sdram_awuser, // .awuser input wire [7:0] f2sdram_wuser, // .wuser output wire [7:0] f2sdram_buser, // .buser input wire [3:0] f2sdram_arregion, // .arregion output wire [7:0] f2sdram_ruser, // .ruser input wire [3:0] f2sdram_awregion, // .awregion output wire [0:0] emif_hps_emif_mem_0_mem_cs, // emif_hps_emif_mem_0.mem_cs output wire [5:0] emif_hps_emif_mem_0_mem_ca, // .mem_ca output wire [0:0] emif_hps_emif_mem_0_mem_cke, // .mem_cke inout wire [31:0] emif_hps_emif_mem_0_mem_dq, // .mem_dq inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_t, // .mem_dqs_t inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_c, // .mem_dqs_c inout wire [3:0] emif_hps_emif_mem_0_mem_dmi, // .mem_dmi output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_t, // emif_hps_emif_mem_ck_0.mem_ck_t output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_c, // .mem_ck_c output wire emif_hps_emif_mem_reset_n_mem_reset_n, // emif_hps_emif_mem_reset_n.mem_reset_n input wire emif_hps_emif_oct_0_oct_rzqin, // emif_hps_emif_oct_0.oct_rzqin input wire emif_hps_emif_ref_clk_0_clk, // emif_hps_emif_ref_clk_0.clk input wire [3:0] button_pio_external_connection_export, // button_pio_external_connection.export input wire [3:0] dipsw_pio_external_connection_export, // dipsw_pio_external_connection.export input wire [2:0] led_pio_external_connection_in_port, // led_pio_external_connection.in_port output wire [2:0] led_pio_external_connection_out_port // .out_port ); endmodule