thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
31176 lines
1.0 MiB
Plaintext
31176 lines
1.0 MiB
Plaintext
<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="qsys_top" kind="qsys_top" version="1.0" fabric="QSYS">
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<!-- Format version 26.1 110 (Future versions may contain additional information.) -->
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<!-- 2026.05.11.21:03:55 -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<value>0</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>GENERATION_ID</sysinfo_type>
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</parameter>
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<parameter name="AUTO_UNIQUE_ID">
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<type>java.lang.String</type>
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<value></value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>UNIQUE_ID</sysinfo_type>
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</parameter>
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<parameter name="AUTO_DEVICE_FAMILY">
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<type>java.lang.String</type>
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<value>Agilex 5</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
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</parameter>
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<parameter name="AUTO_DEVICE">
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<type>java.lang.String</type>
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<value>A5EB013BB23BE4SCS</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>DEVICE</sysinfo_type>
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</parameter>
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<parameter name="AUTO_DEVICE_SPEEDGRADE">
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<type>java.lang.String</type>
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<value>4</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
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</parameter>
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<parameter name="AUTO_BOARD">
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<type>java.lang.String</type>
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<value>default</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>BOARD</sysinfo_type>
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</parameter>
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<parameter name="AUTO_CLK_100_CLOCK_RATE">
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<type>java.lang.Long</type>
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<value>-1</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>CLOCK_RATE</sysinfo_type>
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<sysinfo_arg>clk_100</sysinfo_arg>
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</parameter>
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<parameter name="AUTO_CLK_100_CLOCK_DOMAIN">
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<type>java.lang.Integer</type>
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<value>-1</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
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<sysinfo_arg>clk_100</sysinfo_arg>
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</parameter>
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<parameter name="AUTO_CLK_100_RESET_DOMAIN">
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<type>java.lang.Integer</type>
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<value>-1</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>RESET_DOMAIN</sysinfo_type>
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<sysinfo_arg>clk_100</sysinfo_arg>
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</parameter>
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<parameter name="AUTO_SUBSYS_HPS_HPS2FPGA_ADDRESS_MAP">
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<type>com.altera.entityinterfaces.moduleext.AddressMap</type>
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<value></value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>ADDRESS_MAP</sysinfo_type>
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<sysinfo_arg>subsys_hps_hps2fpga</sysinfo_arg>
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</parameter>
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<parameter name="AUTO_SUBSYS_HPS_HPS2FPGA_ADDRESS_WIDTH">
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<type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
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<value>-1</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
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<sysinfo_arg>subsys_hps_hps2fpga</sysinfo_arg>
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</parameter>
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<parameter name="AUTO_F2H_IRQ1_IN_INTERRUPTS_USED">
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<type>java.math.BigInteger</type>
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<value>-1</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>INTERRUPTS_USED</sysinfo_type>
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<sysinfo_arg>f2h_irq1_in</sysinfo_arg>
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</parameter>
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<parameter name="AUTO_F2SDRAM_CPU_INFO_ID">
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<type>java.lang.String</type>
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<value></value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>CPU_INFO_ID</sysinfo_type>
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<sysinfo_arg>f2sdram</sysinfo_arg>
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</parameter>
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<parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_0_CLOCK_RATE">
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<type>java.lang.Long</type>
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<value>-1</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>CLOCK_RATE</sysinfo_type>
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<sysinfo_arg>emif_hps_emif_ref_clk_0</sysinfo_arg>
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</parameter>
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<parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_0_CLOCK_DOMAIN">
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<type>java.lang.Integer</type>
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<value>-1</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
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<sysinfo_arg>emif_hps_emif_ref_clk_0</sysinfo_arg>
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</parameter>
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<parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_0_RESET_DOMAIN">
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<type>java.lang.Integer</type>
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<value>-1</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>RESET_DOMAIN</sysinfo_type>
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<sysinfo_arg>emif_hps_emif_ref_clk_0</sysinfo_arg>
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</parameter>
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<parameter name="deviceFamily">
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<type>java.lang.String</type>
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<value>Agilex 5</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
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</parameter>
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<parameter name="generateLegacySim">
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<type>boolean</type>
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<value>false</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>true</visible>
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<valid>true</valid>
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</parameter>
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<module
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name="clk_100"
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kind="altera_clock_bridge"
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version="19.2.0"
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entity="clk_100"
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library="clk_100"
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path="clk_100"
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hpath="clk_100"
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className="altera_generic_component">
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<!-- Describes a single module. Module parameters are
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the requested settings for a module instance. -->
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<parameter name="componentDefinition">
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<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
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<value><![CDATA[<componentDefinition>
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<boundary>
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<interfaces>
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<interface>
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<name>in_clk</name>
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<type>clock</type>
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<isStart>false</isStart>
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<ports>
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<port>
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<name>in_clk</name>
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<role>clk</role>
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<direction>Input</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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</ports>
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<assignments>
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<assignmentValueMap/>
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</assignments>
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<parameters>
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<parameterValueMap>
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<entry>
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<key>clockRate</key>
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<value>0</value>
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</entry>
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<entry>
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<key>externallyDriven</key>
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<value>false</value>
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</entry>
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<entry>
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<key>ptfSchematicName</key>
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</entry>
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</parameterValueMap>
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</parameters>
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</interface>
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<interface>
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<name>out_clk</name>
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<type>clock</type>
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<isStart>true</isStart>
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<ports>
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<port>
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<name>out_clk</name>
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<role>clk</role>
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<direction>Output</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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</ports>
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<assignments>
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<assignmentValueMap/>
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</assignments>
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<parameters>
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<parameterValueMap>
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<entry>
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<key>associatedDirectClock</key>
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<value>in_clk</value>
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</entry>
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<entry>
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<key>clockRate</key>
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<value>100000000</value>
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</entry>
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<entry>
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<key>clockRateKnown</key>
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<value>true</value>
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</entry>
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<entry>
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<key>externallyDriven</key>
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<value>false</value>
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</entry>
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<entry>
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<key>ptfSchematicName</key>
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</entry>
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</parameterValueMap>
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</parameters>
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</interface>
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</interfaces>
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</boundary>
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<originalModuleInfo>
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<className>altera_clock_bridge</className>
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<version>19.2.0</version>
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<displayName>Clock Bridge IP</displayName>
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</originalModuleInfo>
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<systemInfoParameterDescriptors>
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<descriptors>
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<descriptor>
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<parameterDefaultValue>0</parameterDefaultValue>
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<parameterName>DERIVED_CLOCK_RATE</parameterName>
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<parameterType>java.lang.Long</parameterType>
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<systemInfoArgs>in_clk</systemInfoArgs>
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<systemInfotype>CLOCK_RATE</systemInfotype>
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</descriptor>
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</descriptors>
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</systemInfoParameterDescriptors>
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<systemInfos>
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<connPtSystemInfos>
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<entry>
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<key>in_clk</key>
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<value>
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<connectionPointName>in_clk</connectionPointName>
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<suppliedSystemInfos/>
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<consumedSystemInfos>
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<entry>
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<key>CLOCK_RATE</key>
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<value>0</value>
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</entry>
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</consumedSystemInfos>
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</value>
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</entry>
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<entry>
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<key>out_clk</key>
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<value>
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<connectionPointName>out_clk</connectionPointName>
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<suppliedSystemInfos>
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<entry>
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<key>CLOCK_RATE</key>
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<value>100000000</value>
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</entry>
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</suppliedSystemInfos>
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<consumedSystemInfos/>
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</value>
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</entry>
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</connPtSystemInfos>
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</systemInfos>
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</componentDefinition>]]></value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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</parameter>
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<parameter name="generationInfoDefinition">
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<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
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<value><![CDATA[<generationInfoDefinition>
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<hdlLibraryName>clk_100</hdlLibraryName>
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<fileSets>
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<fileSet>
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<fileSetName>clk_100</fileSetName>
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<fileSetFixedName>clk_100</fileSetFixedName>
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<fileSetKind>QUARTUS_SYNTH</fileSetKind>
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<fileSetFiles/>
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<fileSetFileChangeDefs/>
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</fileSet>
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<fileSet>
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<fileSetName>clk_100</fileSetName>
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<fileSetFixedName>clk_100</fileSetFixedName>
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<fileSetKind>SIM_VERILOG</fileSetKind>
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<fileSetFiles/>
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<fileSetFileChangeDefs/>
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</fileSet>
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<fileSet>
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<fileSetName>clk_100</fileSetName>
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<fileSetFixedName>clk_100</fileSetFixedName>
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<fileSetKind>SIM_VHDL</fileSetKind>
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<fileSetFiles/>
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<fileSetFileChangeDefs/>
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</fileSet>
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<fileSet>
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<fileSetName>clk_100</fileSetName>
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<fileSetFixedName>clk_100</fileSetFixedName>
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<fileSetKind>CDC</fileSetKind>
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<fileSetFiles/>
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<fileSetFileChangeDefs/>
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</fileSet>
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<fileSet>
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<fileSetName>clk_100</fileSetName>
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<fileSetFixedName>clk_100</fileSetFixedName>
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<fileSetKind>CDC_VHDL</fileSetKind>
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<fileSetFiles/>
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<fileSetFileChangeDefs/>
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</fileSet>
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</fileSets>
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</generationInfoDefinition>]]></value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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</parameter>
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<parameter name="hlsFile">
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<type>java.lang.String</type>
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<value></value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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</parameter>
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<parameter name="logicalView">
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<type>java.lang.String</type>
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<value>ip/qsys_top/clk_100.ip</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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</parameter>
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<parameter name="defaultBoundary">
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<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
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<value><![CDATA[<boundaryDefinition>
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<interfaces>
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<interface>
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<name>in_clk</name>
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<type>clock</type>
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<isStart>false</isStart>
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<ports>
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<port>
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<name>in_clk</name>
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<role>clk</role>
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<direction>Input</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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</ports>
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<assignments>
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<assignmentValueMap/>
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</assignments>
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<parameters>
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<parameterValueMap>
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<entry>
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<key>clockRate</key>
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<value>0</value>
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</entry>
|
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<entry>
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<key>externallyDriven</key>
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<value>false</value>
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</entry>
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<entry>
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<key>ptfSchematicName</key>
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</entry>
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</parameterValueMap>
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</parameters>
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</interface>
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<interface>
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<name>out_clk</name>
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<type>clock</type>
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<isStart>true</isStart>
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<ports>
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<port>
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<name>out_clk</name>
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<role>clk</role>
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<direction>Output</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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</ports>
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<assignments>
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<assignmentValueMap/>
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</assignments>
|
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<parameters>
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<parameterValueMap>
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<entry>
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<key>associatedDirectClock</key>
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<value>in_clk</value>
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</entry>
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<entry>
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<key>clockRate</key>
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<value>100000000</value>
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</entry>
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<entry>
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<key>clockRateKnown</key>
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<value>true</value>
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</entry>
|
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<entry>
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<key>externallyDriven</key>
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<value>false</value>
|
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</entry>
|
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<entry>
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<key>ptfSchematicName</key>
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|
</entry>
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</parameterValueMap>
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</parameters>
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</interface>
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</interfaces>
|
|
</boundaryDefinition>]]></value>
|
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<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
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<value><![CDATA[<assignmentDefinition>
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<assignmentValueMap/>
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</assignmentDefinition>]]></value>
|
|
<derived>false</derived>
|
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<enabled>true</enabled>
|
|
<visible>false</visible>
|
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<valid>true</valid>
|
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</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<transformParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value>altera_clock_bridge_inst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="DERIVED_CLOCK_RATE">
|
|
<type>java.lang.Long</type>
|
|
<value>0</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>in_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="in_clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>0</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>in_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="out_clk" kind="clock_source" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedDirectClock">
|
|
<type>java.lang.String</type>
|
|
<value>in_clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>long</type>
|
|
<value>100000000</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>out_clk</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
<clockDomainMember>
|
|
<isBridge>true</isBridge>
|
|
<moduleName>subsys_periph_periph_clk</moduleName>
|
|
<slaveName>in_clk</slaveName>
|
|
<name>subsys_periph_periph_clk.in_clk</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_sysid</moduleName>
|
|
<slaveName>clk</slaveName>
|
|
<name>subsys_periph_sysid.clk</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_pb_cpu_0</moduleName>
|
|
<slaveName>clk</slaveName>
|
|
<name>subsys_periph_pb_cpu_0.clk</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_led_pio</moduleName>
|
|
<slaveName>clk</slaveName>
|
|
<name>subsys_periph_led_pio.clk</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_dipsw_pio</moduleName>
|
|
<slaveName>clk</slaveName>
|
|
<name>subsys_periph_dipsw_pio.clk</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_button_pio</moduleName>
|
|
<slaveName>clk</slaveName>
|
|
<name>subsys_periph_button_pio.clk</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_hps_agilex_hps</moduleName>
|
|
<slaveName>f2sdram_axi_clock</slaveName>
|
|
<name>subsys_hps_agilex_hps.f2sdram_axi_clock</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_hps_agilex_hps</moduleName>
|
|
<slaveName>hps2fpga_axi_clock</slaveName>
|
|
<name>subsys_hps_agilex_hps.hps2fpga_axi_clock</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_hps_agilex_hps</moduleName>
|
|
<slaveName>lwhps2fpga_axi_clock</slaveName>
|
|
<name>subsys_hps_agilex_hps.lwhps2fpga_axi_clock</name>
|
|
</clockDomainMember>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="rst_in"
|
|
kind="altera_reset_bridge"
|
|
version="19.2.0"
|
|
entity="rst_in"
|
|
library="rst_in"
|
|
path="rst_in"
|
|
hpath="rst_in"
|
|
className="altera_generic_component">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<parameter name="componentDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
|
|
<value><![CDATA[<componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>in_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>out_reset</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>out_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_reset_bridge</className>
|
|
<version>19.2.0</version>
|
|
<displayName>Reset Bridge IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue>-1</parameterDefaultValue>
|
|
<parameterName>AUTO_CLK_CLOCK_RATE</parameterName>
|
|
<parameterType>java.lang.Long</parameterType>
|
|
<systemInfoArgs>clk</systemInfoArgs>
|
|
<systemInfotype>CLOCK_RATE</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos/>
|
|
</systemInfos>
|
|
</componentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generationInfoDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
|
|
<value><![CDATA[<generationInfoDefinition>
|
|
<hdlLibraryName>rst_in</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>rst_in</fileSetName>
|
|
<fileSetFixedName>rst_in</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>rst_in</fileSetName>
|
|
<fileSetFixedName>rst_in</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>rst_in</fileSetName>
|
|
<fileSetFixedName>rst_in</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>rst_in</fileSetName>
|
|
<fileSetFixedName>rst_in</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>rst_in</fileSetName>
|
|
<fileSetFixedName>rst_in</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hlsFile">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="logicalView">
|
|
<type>java.lang.String</type>
|
|
<value>ip/qsys_top/rst_in.ip</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultBoundary">
|
|
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
|
<value><![CDATA[<boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>in_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>out_reset</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>out_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
|
|
<value><![CDATA[<assignmentDefinition>
|
|
<assignmentValueMap/>
|
|
</assignmentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<transformParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value>altera_reset_bridge_inst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="AUTO_CLK_CLOCK_RATE">
|
|
<type>java.lang.Long</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="in_reset" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>in_reset_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset_n</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="out_reset" kind="reset_source" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedDirectReset">
|
|
<type>java.lang.String</type>
|
|
<value>in_reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedResetSinks">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value>in_reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>out_reset_n</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>reset_n</role>
|
|
</port>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="user_rst_clkgate_0"
|
|
kind="intel_user_rst_clkgate"
|
|
version="1.0.1"
|
|
entity="user_rst_clkgate_0"
|
|
library="user_rst_clkgate_0"
|
|
path="user_rst_clkgate_0"
|
|
hpath="user_rst_clkgate_0"
|
|
className="altera_generic_component">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<parameter name="componentDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
|
|
<value><![CDATA[<componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>ninit_done</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>ninit_done</name>
|
|
<role>ninit_done</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>intel_user_rst_clkgate</className>
|
|
<version>1.0.1</version>
|
|
<displayName>Reset Release IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>DEVICE_FAMILY</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_FAMILY</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos/>
|
|
</systemInfos>
|
|
</componentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generationInfoDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
|
|
<value><![CDATA[<generationInfoDefinition>
|
|
<hdlLibraryName>user_rst_clkgate_0</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>user_rst_clkgate_0</fileSetName>
|
|
<fileSetFixedName>user_rst_clkgate_0</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>user_rst_clkgate_0</fileSetName>
|
|
<fileSetFixedName>user_rst_clkgate_0</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>user_rst_clkgate_0</fileSetName>
|
|
<fileSetFixedName>user_rst_clkgate_0</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>user_rst_clkgate_0</fileSetName>
|
|
<fileSetFixedName>user_rst_clkgate_0</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>user_rst_clkgate_0</fileSetName>
|
|
<fileSetFixedName>user_rst_clkgate_0</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hlsFile">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="logicalView">
|
|
<type>java.lang.String</type>
|
|
<value>ip/qsys_top/user_rst_clkgate_0.ip</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultBoundary">
|
|
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
|
<value><![CDATA[<boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>ninit_done</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>ninit_done</name>
|
|
<role>ninit_done</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
|
|
<value><![CDATA[<assignmentDefinition>
|
|
<assignmentValueMap/>
|
|
</assignmentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<transformParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value>intel_user_rst_clkgate_inst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="ninit_done" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>ninit_done</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ninit_done</role>
|
|
</port>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="subsys_hps"
|
|
kind="hps_subsys"
|
|
version="1.0"
|
|
entity="hps_subsys"
|
|
library="qsys_top"
|
|
path="subsys_hps"
|
|
hpath="subsys_hps"
|
|
className="hps_subsys">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<parameter name="AUTO_GENERATION_ID">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_UNIQUE_ID">
|
|
<type>java.lang.String</type>
|
|
<value>qsys_top_subsys_hps</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
|
<type>java.lang.String</type>
|
|
<value>4</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_BOARD">
|
|
<type>java.lang.String</type>
|
|
<value>default</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>BOARD</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_HPS2FPGA_CLK_CLOCK_RATE">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>hps2fpga_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_HPS2FPGA_CLK_CLOCK_DOMAIN">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
<sysinfo_arg>hps2fpga_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_HPS2FPGA_CLK_RESET_DOMAIN">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
<sysinfo_arg>hps2fpga_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_HPS2FPGA_ADDRESS_MAP">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressMap</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_MAP</sysinfo_type>
|
|
<sysinfo_arg>hps2fpga</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_HPS2FPGA_ADDRESS_WIDTH">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
|
|
<value>-1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
|
|
<sysinfo_arg>hps2fpga</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_LWHPS2FPGA_CLK_CLOCK_RATE">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>lwhps2fpga_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_LWHPS2FPGA_CLK_CLOCK_DOMAIN">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
<sysinfo_arg>lwhps2fpga_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_LWHPS2FPGA_CLK_RESET_DOMAIN">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
<sysinfo_arg>lwhps2fpga_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_LWHPS2FPGA_ADDRESS_MAP">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressMap</type>
|
|
<value><![CDATA[<address-map><slave name='subsys_periph.sysid.control_slave' start='0x10000' end='0x10008' datawidth='32' /><slave name='subsys_periph.button_pio.s1' start='0x10060' end='0x10070' datawidth='32' /><slave name='subsys_periph.dipsw_pio.s1' start='0x10070' end='0x10080' datawidth='32' /><slave name='subsys_periph.led_pio.s1' start='0x10080' end='0x10090' datawidth='32' /></address-map>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_MAP</sysinfo_type>
|
|
<sysinfo_arg>lwhps2fpga</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_LWHPS2FPGA_ADDRESS_WIDTH">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
|
|
<value>17</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
|
|
<sysinfo_arg>lwhps2fpga</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_F2H_IRQ1_IN_INTERRUPTS_USED">
|
|
<type>java.math.BigInteger</type>
|
|
<value>-1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>INTERRUPTS_USED</sysinfo_type>
|
|
<sysinfo_arg>f2h_irq1_in</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_F2H_IRQ0_IN_INTERRUPTS_USED">
|
|
<type>java.math.BigInteger</type>
|
|
<value>3</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>INTERRUPTS_USED</sysinfo_type>
|
|
<sysinfo_arg>f2h_irq0_in</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_F2SDRAM_CLK_CLOCK_RATE">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>f2sdram_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_F2SDRAM_CLK_CLOCK_DOMAIN">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
<sysinfo_arg>f2sdram_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_F2SDRAM_CLK_RESET_DOMAIN">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
<sysinfo_arg>f2sdram_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_F2SDRAM_CPU_INFO_ID">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CPU_INFO_ID</sysinfo_type>
|
|
<sysinfo_arg>f2sdram</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_CLOCK_RATE">
|
|
<type>java.lang.Long</type>
|
|
<value>-1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>emif_hps_emif_ref_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_CLOCK_DOMAIN">
|
|
<type>java.lang.Integer</type>
|
|
<value>2</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
<sysinfo_arg>emif_hps_emif_ref_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_RESET_DOMAIN">
|
|
<type>java.lang.Integer</type>
|
|
<value>2</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
<sysinfo_arg>emif_hps_emif_ref_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="h2f_reset" kind="reset_source" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedDirectReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedResetSinks">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value>none</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>h2f_reset_reset</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>reset</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="hps2fpga_clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>java.lang.Boolean</type>
|
|
<value>true</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>hps2fpga_clk_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="hps2fpga_rst" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>hps2fpga_rst_reset</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="hps2fpga" kind="altera_axi4_master" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>hps2fpga_clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>hps2fpga_rst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="optionalAssociatedReset">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="trustzoneAware">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wakeupSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="uniqueIdSupport">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="poison">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="traceSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isTranslator">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingReads">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingWrites">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingTransactions">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dataCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="securityAttribute">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="userData">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="combinedIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="enableConcurrentSubordinateAccess">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="noRepeatedIdsBetweenSubordinates">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesINCRBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesWRAPBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesFIXEDBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>axi4</type>
|
|
<span>274877906944</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>hps2fpga_awid</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>awid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awaddr</name>
|
|
<direction>Output</direction>
|
|
<width>38</width>
|
|
<role>awaddr</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awlen</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>awlen</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awsize</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>awsize</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awburst</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>awburst</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awlock</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>awlock</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awcache</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>awcache</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>awprot</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>awvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>awready</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wdata</name>
|
|
<direction>Output</direction>
|
|
<width>128</width>
|
|
<role>wdata</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wstrb</name>
|
|
<direction>Output</direction>
|
|
<width>16</width>
|
|
<role>wstrb</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wlast</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>wlast</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>wvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>wready</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bid</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>bid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>bresp</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>bvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>bready</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arid</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>arid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_araddr</name>
|
|
<direction>Output</direction>
|
|
<width>38</width>
|
|
<role>araddr</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlen</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>arlen</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arsize</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>arsize</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arburst</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>arburst</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlock</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>arlock</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arcache</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>arcache</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>arprot</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>arvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>arready</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rid</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>rid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rdata</name>
|
|
<direction>Input</direction>
|
|
<width>128</width>
|
|
<role>rdata</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>rresp</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rlast</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>rlast</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>rvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>rready</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="lwhps2fpga_clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>java.lang.Boolean</type>
|
|
<value>true</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>lwhps2fpga_clk_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="lwhps2fpga_rst" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>lwhps2fpga_rst_reset</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="lwhps2fpga" kind="altera_axi4_master" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>lwhps2fpga_clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>lwhps2fpga_rst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="optionalAssociatedReset">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="trustzoneAware">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wakeupSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="uniqueIdSupport">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="poison">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="traceSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isTranslator">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingReads">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingWrites">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingTransactions">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dataCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="securityAttribute">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="userData">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="combinedIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="enableConcurrentSubordinateAccess">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="noRepeatedIdsBetweenSubordinates">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesINCRBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesWRAPBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesFIXEDBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>axi4</type>
|
|
<span>536870912</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>lwhps2fpga_awid</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>awid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awaddr</name>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<role>awaddr</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlen</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>awlen</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awsize</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>awsize</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awburst</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>awburst</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlock</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>awlock</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awcache</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>awcache</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>awprot</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>awvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>awready</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wdata</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>wdata</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wstrb</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>wstrb</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wlast</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>wlast</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>wvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>wready</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bid</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>bid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>bresp</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>bvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>bready</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arid</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>arid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_araddr</name>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<role>araddr</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlen</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>arlen</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arsize</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>arsize</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arburst</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>arburst</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlock</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>arlock</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arcache</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>arcache</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>arprot</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>arvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>arready</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rid</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>rid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rdata</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>rdata</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>rresp</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rlast</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>rlast</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>rvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>rready</role>
|
|
</port>
|
|
<memoryBlock>
|
|
<isBridge>true</isBridge>
|
|
<moduleName>subsys_periph_pb_cpu_0</moduleName>
|
|
<slaveName>s0</slaveName>
|
|
<name>subsys_periph_pb_cpu_0.s0</name>
|
|
<baseAddress>0</baseAddress>
|
|
<span>131072</span>
|
|
</memoryBlock>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_sysid</moduleName>
|
|
<slaveName>control_slave</slaveName>
|
|
<name>subsys_periph_sysid.control_slave</name>
|
|
<baseAddress>65536</baseAddress>
|
|
<span>8</span>
|
|
</memoryBlock>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_led_pio</moduleName>
|
|
<slaveName>s1</slaveName>
|
|
<name>subsys_periph_led_pio.s1</name>
|
|
<baseAddress>65664</baseAddress>
|
|
<span>16</span>
|
|
</memoryBlock>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_dipsw_pio</moduleName>
|
|
<slaveName>s1</slaveName>
|
|
<name>subsys_periph_dipsw_pio.s1</name>
|
|
<baseAddress>65648</baseAddress>
|
|
<span>16</span>
|
|
</memoryBlock>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_button_pio</moduleName>
|
|
<slaveName>s1</slaveName>
|
|
<name>subsys_periph_button_pio.s1</name>
|
|
<baseAddress>65632</baseAddress>
|
|
<span>16</span>
|
|
</memoryBlock>
|
|
</interface>
|
|
<interface name="h2f_warm_reset_handshake" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_req</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>reset_req</role>
|
|
</port>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_ack</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset_ack</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="hps_io" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>hps_io_hps_osc_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>hps_osc_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data0</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_data0</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data1</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_data1</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cclk</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_cclk</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data2</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_data2</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data3</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_data3</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cmd</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_cmd</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>usb0_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_stp</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>usb0_stp</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_dir</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>usb0_dir</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data0</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data0</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data1</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data1</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_nxt</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>usb0_nxt</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data2</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data2</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data3</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data3</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data4</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data4</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data5</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data5</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data6</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data6</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data7</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data7</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_clk</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_tx_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_ctl</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_tx_ctl</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rx_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_ctl</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rx_ctl</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd0</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_txd0</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd1</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_txd1</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd0</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rxd0</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd1</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rxd1</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd2</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_txd2</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd3</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_txd3</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd2</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rxd2</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd3</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rxd3</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdio</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>mdio0_mdio</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdc</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mdio0_mdc</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_tx</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>uart1_tx</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_rx</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>uart1_rx</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_sda</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>i2c1_sda</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_scl</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>i2c1_scl</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio28</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>gpio28</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio34</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>gpio34</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio40</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>gpio40</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio41</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>gpio41</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="f2h_irq1_in" kind="interrupt_receiver" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedAddressablePoint">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqMap">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqScheme">
|
|
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>interrupt</type>
|
|
<span>0</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>f2h_irq1_in_irq</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>irq</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="f2h_irq0_in" kind="interrupt_receiver" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedAddressablePoint">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqMap">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqScheme">
|
|
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>interrupt</type>
|
|
<span>0</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>f2h_irq0_in_irq</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>irq</role>
|
|
</port>
|
|
<interrupt>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_button_pio</moduleName>
|
|
<slaveName>irq</slaveName>
|
|
<name>subsys_periph_button_pio.irq</name>
|
|
<interruptNumber>1</interruptNumber>
|
|
</interrupt>
|
|
<interrupt>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_dipsw_pio</moduleName>
|
|
<slaveName>irq</slaveName>
|
|
<name>subsys_periph_dipsw_pio.irq</name>
|
|
<interruptNumber>0</interruptNumber>
|
|
</interrupt>
|
|
</interface>
|
|
<interface name="f2sdram_clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>java.lang.Boolean</type>
|
|
<value>true</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>f2sdram_clk_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="f2sdram_rst" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>f2sdram_rst_reset</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="f2sdram" kind="altera_axi4_slave" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>f2sdram_clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>f2sdram_rst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="optionalAssociatedReset">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="trustzoneAware">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wakeupSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="uniqueIdSupport">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="poison">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="traceSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isTranslator">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingReads">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingWrites">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingTransactions">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dataCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="securityAttribute">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="userData">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readAcceptanceCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeAcceptanceCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="combinedAcceptanceCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readDataReorderingDepth">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToMaster">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureGuid">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhGroupId">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterId">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterName">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterVersion">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterData">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterDataLength">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMajorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMinorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureId">
|
|
<type>java.lang.Integer</type>
|
|
<value>35</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureType">
|
|
<type>java.lang.Integer</type>
|
|
<value>3</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="noNarrowTransfer">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>4294967296</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>axi4</type>
|
|
<span>4294967296</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>f2sdram_araddr</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>araddr</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arburst</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>arburst</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arcache</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>arcache</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arid</name>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<role>arid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlen</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>arlen</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlock</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>arlock</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arprot</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>arprot</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arqos</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>arqos</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>arready</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arsize</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>arsize</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>arvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awaddr</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>awaddr</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awburst</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>awburst</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awcache</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>awcache</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awid</name>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<role>awid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlen</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>awlen</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlock</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>awlock</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awprot</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>awprot</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awqos</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>awqos</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>awready</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awsize</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>awsize</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>awvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bid</name>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<role>bid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>bready</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bresp</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>bresp</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>bvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rdata</name>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<role>rdata</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rid</name>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<role>rid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rlast</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>rlast</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>rready</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rresp</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>rresp</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>rvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wdata</name>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<role>wdata</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wlast</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>wlast</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>wready</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wstrb</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>wstrb</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>wvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_aruser</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>aruser</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awuser</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>awuser</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wuser</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>wuser</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_buser</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>buser</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arregion</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>arregion</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_ruser</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>ruser</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awregion</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>awregion</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="emif_hps_emif_mem_0" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>emif_hps_emif_mem_0_mem_cs</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mem_cs</role>
|
|
</port>
|
|
<port>
|
|
<name>emif_hps_emif_mem_0_mem_ca</name>
|
|
<direction>Output</direction>
|
|
<width>6</width>
|
|
<role>mem_ca</role>
|
|
</port>
|
|
<port>
|
|
<name>emif_hps_emif_mem_0_mem_cke</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mem_cke</role>
|
|
</port>
|
|
<port>
|
|
<name>emif_hps_emif_mem_0_mem_dq</name>
|
|
<direction>Bidir</direction>
|
|
<width>32</width>
|
|
<role>mem_dq</role>
|
|
</port>
|
|
<port>
|
|
<name>emif_hps_emif_mem_0_mem_dqs_t</name>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<role>mem_dqs_t</role>
|
|
</port>
|
|
<port>
|
|
<name>emif_hps_emif_mem_0_mem_dqs_c</name>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<role>mem_dqs_c</role>
|
|
</port>
|
|
<port>
|
|
<name>emif_hps_emif_mem_0_mem_dmi</name>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<role>mem_dmi</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="emif_hps_emif_mem_ck_0" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>emif_hps_emif_mem_ck_0_mem_ck_t</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mem_ck_t</role>
|
|
</port>
|
|
<port>
|
|
<name>emif_hps_emif_mem_ck_0_mem_ck_c</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mem_ck_c</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="emif_hps_emif_mem_reset_n" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>emif_hps_emif_mem_reset_n_mem_reset_n</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mem_reset_n</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="emif_hps_emif_oct_0" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>emif_hps_emif_oct_0_oct_rzqin</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>oct_rzqin</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="emif_hps_emif_ref_clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>emif_hps_emif_ref_clk_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="subsys_hps_agilex_hps"
|
|
kind="intel_agilex_5_soc"
|
|
version="13.0.0"
|
|
path="subsys_hps.agilex_hps"
|
|
className="altera_generic_component">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.CPU_FREQ</name>
|
|
<value>50000000u</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.cpuArchitecture</name>
|
|
<value>sm_hps</value>
|
|
</assignment>
|
|
<parameter name="componentDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
|
|
<value><![CDATA[<componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>h2f_reset</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>h2f_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>none</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps2fpga_axi_clock</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps2fpga_axi_clock_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps2fpga_axi_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps2fpga_axi_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps2fpga</name>
|
|
<type>axi4</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps2fpga_awid</name>
|
|
<role>awid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awaddr</name>
|
|
<role>awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>38</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awlen</name>
|
|
<role>awlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awsize</name>
|
|
<role>awsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awburst</name>
|
|
<role>awburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awlock</name>
|
|
<role>awlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awcache</name>
|
|
<role>awcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awprot</name>
|
|
<role>awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awvalid</name>
|
|
<role>awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awready</name>
|
|
<role>awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Output</direction>
|
|
<width>128</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wstrb</name>
|
|
<role>wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>16</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wlast</name>
|
|
<role>wlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wvalid</name>
|
|
<role>wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wready</name>
|
|
<role>wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bid</name>
|
|
<role>bid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bready</name>
|
|
<role>bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arid</name>
|
|
<role>arid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Output</direction>
|
|
<width>38</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arready</name>
|
|
<role>arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rid</name>
|
|
<role>rid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Input</direction>
|
|
<width>128</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rready</name>
|
|
<role>rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>hps2fpga_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>hps2fpga_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noRepeatedIdsBetweenSubordinates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesINCRBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesWRAPBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesFIXEDBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga_axi_clock</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_axi_clock_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga_axi_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_axi_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga</name>
|
|
<type>axi4</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_awid</name>
|
|
<role>awid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awaddr</name>
|
|
<role>awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlen</name>
|
|
<role>awlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awsize</name>
|
|
<role>awsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awburst</name>
|
|
<role>awburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlock</name>
|
|
<role>awlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awcache</name>
|
|
<role>awcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awprot</name>
|
|
<role>awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awvalid</name>
|
|
<role>awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awready</name>
|
|
<role>awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wstrb</name>
|
|
<role>wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wlast</name>
|
|
<role>wlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wvalid</name>
|
|
<role>wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wready</name>
|
|
<role>wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bid</name>
|
|
<role>bid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bready</name>
|
|
<role>bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arid</name>
|
|
<role>arid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arready</name>
|
|
<role>arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rid</name>
|
|
<role>rid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rready</name>
|
|
<role>rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>lwhps2fpga_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>lwhps2fpga_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noRepeatedIdsBetweenSubordinates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesINCRBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesWRAPBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesFIXEDBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>emac0_app_rst</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>emac0_app_rst_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>none</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>h2f_warm_reset_handshake</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_req</name>
|
|
<role>reset_req</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_ack</name>
|
|
<role>reset_ack</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps_io</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps_io_hps_osc_clk</name>
|
|
<role>hps_osc_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data0</name>
|
|
<role>sdmmc_data0</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data1</name>
|
|
<role>sdmmc_data1</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cclk</name>
|
|
<role>sdmmc_cclk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data2</name>
|
|
<role>sdmmc_data2</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data3</name>
|
|
<role>sdmmc_data3</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cmd</name>
|
|
<role>sdmmc_cmd</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_clk</name>
|
|
<role>usb0_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_stp</name>
|
|
<role>usb0_stp</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_dir</name>
|
|
<role>usb0_dir</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data0</name>
|
|
<role>usb0_data0</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data1</name>
|
|
<role>usb0_data1</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_nxt</name>
|
|
<role>usb0_nxt</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data2</name>
|
|
<role>usb0_data2</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data3</name>
|
|
<role>usb0_data3</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data4</name>
|
|
<role>usb0_data4</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data5</name>
|
|
<role>usb0_data5</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data6</name>
|
|
<role>usb0_data6</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data7</name>
|
|
<role>usb0_data7</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_clk</name>
|
|
<role>emac0_tx_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_ctl</name>
|
|
<role>emac0_tx_ctl</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_clk</name>
|
|
<role>emac0_rx_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_ctl</name>
|
|
<role>emac0_rx_ctl</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd0</name>
|
|
<role>emac0_txd0</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd1</name>
|
|
<role>emac0_txd1</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd0</name>
|
|
<role>emac0_rxd0</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd1</name>
|
|
<role>emac0_rxd1</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd2</name>
|
|
<role>emac0_txd2</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd3</name>
|
|
<role>emac0_txd3</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd2</name>
|
|
<role>emac0_rxd2</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd3</name>
|
|
<role>emac0_rxd3</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdio</name>
|
|
<role>mdio0_mdio</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdc</name>
|
|
<role>mdio0_mdc</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_tx</name>
|
|
<role>uart1_tx</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_rx</name>
|
|
<role>uart1_rx</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_sda</name>
|
|
<role>i2c1_sda</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_scl</name>
|
|
<role>i2c1_scl</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio28</name>
|
|
<role>gpio28</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio34</name>
|
|
<role>gpio34</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio40</name>
|
|
<role>gpio40</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio41</name>
|
|
<role>gpio41</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>fpga2hps_interrupt_irq1</name>
|
|
<type>interrupt</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>fpga2hps_interrupt_irq1_irq</name>
|
|
<role>irq</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value></value>
|
|
</entry>
|
|
<entry>
|
|
<key>irqMap</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>fpga2hps_interrupt_irq0</name>
|
|
<type>interrupt</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>fpga2hps_interrupt_irq0_irq</name>
|
|
<role>irq</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value></value>
|
|
</entry>
|
|
<entry>
|
|
<key>irqMap</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram_axi_clock</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_axi_clock_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram_axi_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_axi_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram</name>
|
|
<type>axi4</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arid</name>
|
|
<role>arid</role>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arqos</name>
|
|
<role>arqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arready</name>
|
|
<role>arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awaddr</name>
|
|
<role>awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awburst</name>
|
|
<role>awburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awcache</name>
|
|
<role>awcache</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awid</name>
|
|
<role>awid</role>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlen</name>
|
|
<role>awlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlock</name>
|
|
<role>awlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awprot</name>
|
|
<role>awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awqos</name>
|
|
<role>awqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awready</name>
|
|
<role>awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awsize</name>
|
|
<role>awsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awvalid</name>
|
|
<role>awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bid</name>
|
|
<role>bid</role>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bready</name>
|
|
<role>bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rid</name>
|
|
<role>rid</role>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rready</name>
|
|
<role>rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wlast</name>
|
|
<role>wlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wready</name>
|
|
<role>wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wstrb</name>
|
|
<role>wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wvalid</name>
|
|
<role>wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_aruser</name>
|
|
<role>aruser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awuser</name>
|
|
<role>awuser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wuser</name>
|
|
<role>wuser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_buser</name>
|
|
<role>buser</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arregion</name>
|
|
<role>arregion</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_ruser</name>
|
|
<role>ruser</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awregion</name>
|
|
<role>awregion</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>f2sdram_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>f2sdram_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readDataReorderingDepth</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noNarrowTransfer</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>io96b0_to_hps</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_clk</name>
|
|
<role>ch0_axil_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_reset_n</name>
|
|
<role>ch0_axil_reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arready</name>
|
|
<role>ch0_axil_arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awready</name>
|
|
<role>ch0_axil_awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bresp</name>
|
|
<role>ch0_axil_bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bvalid</name>
|
|
<role>ch0_axil_bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rdata</name>
|
|
<role>ch0_axil_rdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rresp</name>
|
|
<role>ch0_axil_rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rvalid</name>
|
|
<role>ch0_axil_rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wready</name>
|
|
<role>ch0_axil_wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_araddr</name>
|
|
<role>ch0_axil_araddr</role>
|
|
<direction>Output</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arvalid</name>
|
|
<role>ch0_axil_arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awaddr</name>
|
|
<role>ch0_axil_awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awvalid</name>
|
|
<role>ch0_axil_awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bready</name>
|
|
<role>ch0_axil_bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rready</name>
|
|
<role>ch0_axil_rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wdata</name>
|
|
<role>ch0_axil_wdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wstrb</name>
|
|
<role>ch0_axil_wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wvalid</name>
|
|
<role>ch0_axil_wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arprot</name>
|
|
<role>ch0_axil_arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awprot</name>
|
|
<role>ch0_axil_awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_clk</name>
|
|
<role>axi4_ch0_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_reset_n</name>
|
|
<role>axi4_ch0_reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arready</name>
|
|
<role>axi4_ch0_arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awready</name>
|
|
<role>axi4_ch0_awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bid</name>
|
|
<role>axi4_ch0_bid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bresp</name>
|
|
<role>axi4_ch0_bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bvalid</name>
|
|
<role>axi4_ch0_bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rdata</name>
|
|
<role>axi4_ch0_rdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rid</name>
|
|
<role>axi4_ch0_rid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rlast</name>
|
|
<role>axi4_ch0_rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rresp</name>
|
|
<role>axi4_ch0_rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_ruser</name>
|
|
<role>axi4_ch0_ruser</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rvalid</name>
|
|
<role>axi4_ch0_rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wready</name>
|
|
<role>axi4_ch0_wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_araddr</name>
|
|
<role>axi4_ch0_araddr</role>
|
|
<direction>Output</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arburst</name>
|
|
<role>axi4_ch0_arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arid</name>
|
|
<role>axi4_ch0_arid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arlen</name>
|
|
<role>axi4_ch0_arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arlock</name>
|
|
<role>axi4_ch0_arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arqos</name>
|
|
<role>axi4_ch0_arqos</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arsize</name>
|
|
<role>axi4_ch0_arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_aruser</name>
|
|
<role>axi4_ch0_aruser</role>
|
|
<direction>Output</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arvalid</name>
|
|
<role>axi4_ch0_arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awaddr</name>
|
|
<role>axi4_ch0_awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awburst</name>
|
|
<role>axi4_ch0_awburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awid</name>
|
|
<role>axi4_ch0_awid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awlen</name>
|
|
<role>axi4_ch0_awlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awlock</name>
|
|
<role>axi4_ch0_awlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awqos</name>
|
|
<role>axi4_ch0_awqos</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awsize</name>
|
|
<role>axi4_ch0_awsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awuser</name>
|
|
<role>axi4_ch0_awuser</role>
|
|
<direction>Output</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awvalid</name>
|
|
<role>axi4_ch0_awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bready</name>
|
|
<role>axi4_ch0_bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rready</name>
|
|
<role>axi4_ch0_rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wdata</name>
|
|
<role>axi4_ch0_wdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wlast</name>
|
|
<role>axi4_ch0_wlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wstrb</name>
|
|
<role>axi4_ch0_wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wuser</name>
|
|
<role>axi4_ch0_wuser</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wvalid</name>
|
|
<role>axi4_ch0_wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arprot</name>
|
|
<role>axi4_ch0_arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awprot</name>
|
|
<role>axi4_ch0_awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>intel_agilex_5_soc</className>
|
|
<version>13.0.0</version>
|
|
<displayName>Hard Processor System IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>AUTO_BOARD</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>BOARD</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>device_family</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_FAMILY</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>device_name</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>device_trait_iobank_rev</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>DEVICE_IOBANK_REVISION</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>f2sdram</key>
|
|
<value>
|
|
<connectionPointName>f2sdram</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
<value><address-map><slave name='f2sdram' start='0x0' end='0x100000000' datawidth='256' /></address-map></value>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>32</value>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
<value>256</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generationInfoDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
|
|
<value><![CDATA[<generationInfoDefinition>
|
|
<hdlLibraryName>agilex_hps</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>agilex_hps</fileSetName>
|
|
<fileSetFixedName>agilex_hps</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>agilex_hps</fileSetName>
|
|
<fileSetFixedName>agilex_hps</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>agilex_hps</fileSetName>
|
|
<fileSetFixedName>agilex_hps</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>agilex_hps</fileSetName>
|
|
<fileSetFixedName>agilex_hps</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>agilex_hps</fileSetName>
|
|
<fileSetFixedName>agilex_hps</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hlsFile">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="logicalView">
|
|
<type>java.lang.String</type>
|
|
<value>ip/hps_subsys/agilex_hps.ip</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultBoundary">
|
|
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
|
<value><![CDATA[<boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>h2f_reset</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>h2f_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>none</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps2fpga_axi_clock</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps2fpga_axi_clock_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps2fpga_axi_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps2fpga_axi_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps2fpga</name>
|
|
<type>axi4</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps2fpga_awid</name>
|
|
<role>awid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awaddr</name>
|
|
<role>awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>38</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awlen</name>
|
|
<role>awlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awsize</name>
|
|
<role>awsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awburst</name>
|
|
<role>awburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awlock</name>
|
|
<role>awlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awcache</name>
|
|
<role>awcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awprot</name>
|
|
<role>awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awvalid</name>
|
|
<role>awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awready</name>
|
|
<role>awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Output</direction>
|
|
<width>128</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wstrb</name>
|
|
<role>wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>16</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wlast</name>
|
|
<role>wlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wvalid</name>
|
|
<role>wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wready</name>
|
|
<role>wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bid</name>
|
|
<role>bid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bready</name>
|
|
<role>bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arid</name>
|
|
<role>arid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Output</direction>
|
|
<width>38</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arready</name>
|
|
<role>arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rid</name>
|
|
<role>rid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Input</direction>
|
|
<width>128</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rready</name>
|
|
<role>rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>hps2fpga_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>hps2fpga_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noRepeatedIdsBetweenSubordinates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesINCRBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesWRAPBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesFIXEDBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga_axi_clock</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_axi_clock_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga_axi_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_axi_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga</name>
|
|
<type>axi4</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_awid</name>
|
|
<role>awid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awaddr</name>
|
|
<role>awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlen</name>
|
|
<role>awlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awsize</name>
|
|
<role>awsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awburst</name>
|
|
<role>awburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlock</name>
|
|
<role>awlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awcache</name>
|
|
<role>awcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awprot</name>
|
|
<role>awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awvalid</name>
|
|
<role>awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awready</name>
|
|
<role>awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wstrb</name>
|
|
<role>wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wlast</name>
|
|
<role>wlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wvalid</name>
|
|
<role>wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wready</name>
|
|
<role>wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bid</name>
|
|
<role>bid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bready</name>
|
|
<role>bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arid</name>
|
|
<role>arid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arready</name>
|
|
<role>arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rid</name>
|
|
<role>rid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rready</name>
|
|
<role>rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>lwhps2fpga_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>lwhps2fpga_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noRepeatedIdsBetweenSubordinates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesINCRBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesWRAPBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesFIXEDBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>emac0_app_rst</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>emac0_app_rst_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>none</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>h2f_warm_reset_handshake</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_req</name>
|
|
<role>reset_req</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_ack</name>
|
|
<role>reset_ack</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps_io</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps_io_hps_osc_clk</name>
|
|
<role>hps_osc_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data0</name>
|
|
<role>sdmmc_data0</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data1</name>
|
|
<role>sdmmc_data1</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cclk</name>
|
|
<role>sdmmc_cclk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data2</name>
|
|
<role>sdmmc_data2</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data3</name>
|
|
<role>sdmmc_data3</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cmd</name>
|
|
<role>sdmmc_cmd</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_clk</name>
|
|
<role>usb0_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_stp</name>
|
|
<role>usb0_stp</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_dir</name>
|
|
<role>usb0_dir</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data0</name>
|
|
<role>usb0_data0</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data1</name>
|
|
<role>usb0_data1</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_nxt</name>
|
|
<role>usb0_nxt</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data2</name>
|
|
<role>usb0_data2</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data3</name>
|
|
<role>usb0_data3</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data4</name>
|
|
<role>usb0_data4</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data5</name>
|
|
<role>usb0_data5</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data6</name>
|
|
<role>usb0_data6</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data7</name>
|
|
<role>usb0_data7</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_clk</name>
|
|
<role>emac0_tx_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_ctl</name>
|
|
<role>emac0_tx_ctl</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_clk</name>
|
|
<role>emac0_rx_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_ctl</name>
|
|
<role>emac0_rx_ctl</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd0</name>
|
|
<role>emac0_txd0</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd1</name>
|
|
<role>emac0_txd1</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd0</name>
|
|
<role>emac0_rxd0</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd1</name>
|
|
<role>emac0_rxd1</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd2</name>
|
|
<role>emac0_txd2</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd3</name>
|
|
<role>emac0_txd3</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd2</name>
|
|
<role>emac0_rxd2</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd3</name>
|
|
<role>emac0_rxd3</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdio</name>
|
|
<role>mdio0_mdio</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdc</name>
|
|
<role>mdio0_mdc</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_tx</name>
|
|
<role>uart1_tx</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_rx</name>
|
|
<role>uart1_rx</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_sda</name>
|
|
<role>i2c1_sda</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_scl</name>
|
|
<role>i2c1_scl</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio28</name>
|
|
<role>gpio28</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio34</name>
|
|
<role>gpio34</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio40</name>
|
|
<role>gpio40</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio41</name>
|
|
<role>gpio41</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>fpga2hps_interrupt_irq1</name>
|
|
<type>interrupt</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>fpga2hps_interrupt_irq1_irq</name>
|
|
<role>irq</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value></value>
|
|
</entry>
|
|
<entry>
|
|
<key>irqMap</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>fpga2hps_interrupt_irq0</name>
|
|
<type>interrupt</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>fpga2hps_interrupt_irq0_irq</name>
|
|
<role>irq</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value></value>
|
|
</entry>
|
|
<entry>
|
|
<key>irqMap</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram_axi_clock</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_axi_clock_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram_axi_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_axi_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram</name>
|
|
<type>axi4</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arid</name>
|
|
<role>arid</role>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arqos</name>
|
|
<role>arqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arready</name>
|
|
<role>arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awaddr</name>
|
|
<role>awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awburst</name>
|
|
<role>awburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awcache</name>
|
|
<role>awcache</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awid</name>
|
|
<role>awid</role>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlen</name>
|
|
<role>awlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlock</name>
|
|
<role>awlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awprot</name>
|
|
<role>awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awqos</name>
|
|
<role>awqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awready</name>
|
|
<role>awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awsize</name>
|
|
<role>awsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awvalid</name>
|
|
<role>awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bid</name>
|
|
<role>bid</role>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bready</name>
|
|
<role>bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rid</name>
|
|
<role>rid</role>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rready</name>
|
|
<role>rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wlast</name>
|
|
<role>wlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wready</name>
|
|
<role>wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wstrb</name>
|
|
<role>wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wvalid</name>
|
|
<role>wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_aruser</name>
|
|
<role>aruser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awuser</name>
|
|
<role>awuser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wuser</name>
|
|
<role>wuser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_buser</name>
|
|
<role>buser</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arregion</name>
|
|
<role>arregion</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_ruser</name>
|
|
<role>ruser</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awregion</name>
|
|
<role>awregion</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>f2sdram_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>f2sdram_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readDataReorderingDepth</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noNarrowTransfer</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>io96b0_to_hps</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_clk</name>
|
|
<role>ch0_axil_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_reset_n</name>
|
|
<role>ch0_axil_reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arready</name>
|
|
<role>ch0_axil_arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awready</name>
|
|
<role>ch0_axil_awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bresp</name>
|
|
<role>ch0_axil_bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bvalid</name>
|
|
<role>ch0_axil_bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rdata</name>
|
|
<role>ch0_axil_rdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rresp</name>
|
|
<role>ch0_axil_rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rvalid</name>
|
|
<role>ch0_axil_rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wready</name>
|
|
<role>ch0_axil_wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_araddr</name>
|
|
<role>ch0_axil_araddr</role>
|
|
<direction>Output</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arvalid</name>
|
|
<role>ch0_axil_arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awaddr</name>
|
|
<role>ch0_axil_awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awvalid</name>
|
|
<role>ch0_axil_awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bready</name>
|
|
<role>ch0_axil_bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rready</name>
|
|
<role>ch0_axil_rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wdata</name>
|
|
<role>ch0_axil_wdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wstrb</name>
|
|
<role>ch0_axil_wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wvalid</name>
|
|
<role>ch0_axil_wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arprot</name>
|
|
<role>ch0_axil_arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awprot</name>
|
|
<role>ch0_axil_awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_clk</name>
|
|
<role>axi4_ch0_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_reset_n</name>
|
|
<role>axi4_ch0_reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arready</name>
|
|
<role>axi4_ch0_arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awready</name>
|
|
<role>axi4_ch0_awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bid</name>
|
|
<role>axi4_ch0_bid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bresp</name>
|
|
<role>axi4_ch0_bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bvalid</name>
|
|
<role>axi4_ch0_bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rdata</name>
|
|
<role>axi4_ch0_rdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rid</name>
|
|
<role>axi4_ch0_rid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rlast</name>
|
|
<role>axi4_ch0_rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rresp</name>
|
|
<role>axi4_ch0_rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_ruser</name>
|
|
<role>axi4_ch0_ruser</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rvalid</name>
|
|
<role>axi4_ch0_rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wready</name>
|
|
<role>axi4_ch0_wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_araddr</name>
|
|
<role>axi4_ch0_araddr</role>
|
|
<direction>Output</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arburst</name>
|
|
<role>axi4_ch0_arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arid</name>
|
|
<role>axi4_ch0_arid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arlen</name>
|
|
<role>axi4_ch0_arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arlock</name>
|
|
<role>axi4_ch0_arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arqos</name>
|
|
<role>axi4_ch0_arqos</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arsize</name>
|
|
<role>axi4_ch0_arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_aruser</name>
|
|
<role>axi4_ch0_aruser</role>
|
|
<direction>Output</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arvalid</name>
|
|
<role>axi4_ch0_arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awaddr</name>
|
|
<role>axi4_ch0_awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awburst</name>
|
|
<role>axi4_ch0_awburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awid</name>
|
|
<role>axi4_ch0_awid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awlen</name>
|
|
<role>axi4_ch0_awlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awlock</name>
|
|
<role>axi4_ch0_awlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awqos</name>
|
|
<role>axi4_ch0_awqos</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awsize</name>
|
|
<role>axi4_ch0_awsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awuser</name>
|
|
<role>axi4_ch0_awuser</role>
|
|
<direction>Output</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awvalid</name>
|
|
<role>axi4_ch0_awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bready</name>
|
|
<role>axi4_ch0_bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rready</name>
|
|
<role>axi4_ch0_rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wdata</name>
|
|
<role>axi4_ch0_wdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wlast</name>
|
|
<role>axi4_ch0_wlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wstrb</name>
|
|
<role>axi4_ch0_wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wuser</name>
|
|
<role>axi4_ch0_wuser</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wvalid</name>
|
|
<role>axi4_ch0_wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arprot</name>
|
|
<role>axi4_ch0_arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awprot</name>
|
|
<role>axi4_ch0_awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
|
|
<value><![CDATA[<assignmentDefinition>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.CPU_FREQ</key>
|
|
<value>50000000u</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.cpuArchitecture</key>
|
|
<value>sm_hps</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignmentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<transformParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value>intel_agilex_5_soc_inst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="AUTO_BOARD">
|
|
<type>java.lang.String</type>
|
|
<value>default</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>BOARD</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
|
<type>java.lang.String</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="device_family">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="device_name">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="device_trait_iobank_rev">
|
|
<type>java.lang.String</type>
|
|
<value>IO96B_REVB1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>PART_TRAIT</sysinfo_type>
|
|
<sysinfo_arg>DEVICE_IOBANK_REVISION</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="h2f_reset" kind="reset_source" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedDirectReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedResetSinks">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value>none</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>h2f_reset_reset</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>reset</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="hps2fpga_axi_clock" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>hps2fpga_axi_clock_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="hps2fpga_axi_reset" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>hps2fpga_axi_reset_reset</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="hps2fpga" kind="altera_axi4_master" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>hps2fpga_axi_clock</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>hps2fpga_axi_reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="optionalAssociatedReset">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="trustzoneAware">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wakeupSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="uniqueIdSupport">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="poison">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="traceSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isTranslator">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingReads">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingWrites">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingTransactions">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dataCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="securityAttribute">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="userData">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="combinedIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="enableConcurrentSubordinateAccess">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="noRepeatedIdsBetweenSubordinates">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesINCRBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesWRAPBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesFIXEDBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>axi4</type>
|
|
<span>274877906944</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>hps2fpga_awid</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>awid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awaddr</name>
|
|
<direction>Output</direction>
|
|
<width>38</width>
|
|
<role>awaddr</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awlen</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>awlen</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awsize</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>awsize</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awburst</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>awburst</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awlock</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>awlock</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awcache</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>awcache</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>awprot</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>awvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>awready</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wdata</name>
|
|
<direction>Output</direction>
|
|
<width>128</width>
|
|
<role>wdata</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wstrb</name>
|
|
<direction>Output</direction>
|
|
<width>16</width>
|
|
<role>wstrb</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wlast</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>wlast</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>wvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>wready</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bid</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>bid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>bresp</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>bvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>bready</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arid</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>arid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_araddr</name>
|
|
<direction>Output</direction>
|
|
<width>38</width>
|
|
<role>araddr</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlen</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>arlen</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arsize</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>arsize</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arburst</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>arburst</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlock</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>arlock</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arcache</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>arcache</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>arprot</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>arvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>arready</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rid</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>rid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rdata</name>
|
|
<direction>Input</direction>
|
|
<width>128</width>
|
|
<role>rdata</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>rresp</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rlast</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>rlast</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>rvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>rready</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="lwhps2fpga_axi_clock" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>lwhps2fpga_axi_clock_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="lwhps2fpga_axi_reset" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>lwhps2fpga_axi_reset_reset</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="lwhps2fpga" kind="altera_axi4_master" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>lwhps2fpga_axi_clock</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>lwhps2fpga_axi_reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="optionalAssociatedReset">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="trustzoneAware">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wakeupSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="uniqueIdSupport">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="poison">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="traceSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isTranslator">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingReads">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingWrites">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingTransactions">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dataCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="securityAttribute">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="userData">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="combinedIssuingCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="enableConcurrentSubordinateAccess">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="noRepeatedIdsBetweenSubordinates">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesINCRBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesWRAPBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="issuesFIXEDBursts">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>axi4</type>
|
|
<span>536870912</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>lwhps2fpga_awid</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>awid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awaddr</name>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<role>awaddr</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlen</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>awlen</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awsize</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>awsize</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awburst</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>awburst</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlock</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>awlock</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awcache</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>awcache</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>awprot</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>awvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>awready</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wdata</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>wdata</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wstrb</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>wstrb</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wlast</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>wlast</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>wvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>wready</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bid</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>bid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>bresp</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>bvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>bready</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arid</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>arid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_araddr</name>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<role>araddr</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlen</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>arlen</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arsize</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>arsize</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arburst</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>arburst</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlock</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>arlock</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arcache</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>arcache</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>arprot</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>arvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>arready</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rid</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>rid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rdata</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>rdata</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>rresp</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rlast</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>rlast</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>rvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>rready</role>
|
|
</port>
|
|
<memoryBlock>
|
|
<isBridge>true</isBridge>
|
|
<moduleName>subsys_periph_pb_cpu_0</moduleName>
|
|
<slaveName>s0</slaveName>
|
|
<name>subsys_periph_pb_cpu_0.s0</name>
|
|
<baseAddress>0</baseAddress>
|
|
<span>131072</span>
|
|
</memoryBlock>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_sysid</moduleName>
|
|
<slaveName>control_slave</slaveName>
|
|
<name>subsys_periph_sysid.control_slave</name>
|
|
<baseAddress>65536</baseAddress>
|
|
<span>8</span>
|
|
</memoryBlock>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_led_pio</moduleName>
|
|
<slaveName>s1</slaveName>
|
|
<name>subsys_periph_led_pio.s1</name>
|
|
<baseAddress>65664</baseAddress>
|
|
<span>16</span>
|
|
</memoryBlock>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_dipsw_pio</moduleName>
|
|
<slaveName>s1</slaveName>
|
|
<name>subsys_periph_dipsw_pio.s1</name>
|
|
<baseAddress>65648</baseAddress>
|
|
<span>16</span>
|
|
</memoryBlock>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_button_pio</moduleName>
|
|
<slaveName>s1</slaveName>
|
|
<name>subsys_periph_button_pio.s1</name>
|
|
<baseAddress>65632</baseAddress>
|
|
<span>16</span>
|
|
</memoryBlock>
|
|
</interface>
|
|
<interface name="emac0_app_rst" kind="reset_source" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedDirectReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedResetSinks">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value>none</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>emac0_app_rst_reset_n</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>reset_n</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="h2f_warm_reset_handshake" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_req</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>reset_req</role>
|
|
</port>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_ack</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset_ack</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="hps_io" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>hps_io_hps_osc_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>hps_osc_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data0</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_data0</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data1</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_data1</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cclk</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_cclk</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data2</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_data2</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data3</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_data3</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cmd</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>sdmmc_cmd</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>usb0_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_stp</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>usb0_stp</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_dir</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>usb0_dir</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data0</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data0</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data1</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data1</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_nxt</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>usb0_nxt</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data2</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data2</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data3</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data3</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data4</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data4</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data5</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data5</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data6</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data6</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data7</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>usb0_data7</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_clk</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_tx_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_ctl</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_tx_ctl</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rx_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_ctl</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rx_ctl</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd0</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_txd0</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd1</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_txd1</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd0</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rxd0</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd1</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rxd1</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd2</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_txd2</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd3</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>emac0_txd3</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd2</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rxd2</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd3</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>emac0_rxd3</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdio</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>mdio0_mdio</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdc</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mdio0_mdc</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_tx</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>uart1_tx</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_rx</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>uart1_rx</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_sda</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>i2c1_sda</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_scl</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>i2c1_scl</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio28</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>gpio28</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio34</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>gpio34</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio40</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>gpio40</role>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio41</name>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<role>gpio41</role>
|
|
</port>
|
|
</interface>
|
|
<interface
|
|
name="fpga2hps_interrupt_irq1"
|
|
kind="interrupt_receiver"
|
|
version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedAddressablePoint">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqMap">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqScheme">
|
|
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>interrupt</type>
|
|
<span>0</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>fpga2hps_interrupt_irq1_irq</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>irq</role>
|
|
</port>
|
|
</interface>
|
|
<interface
|
|
name="fpga2hps_interrupt_irq0"
|
|
kind="interrupt_receiver"
|
|
version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedAddressablePoint">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqMap">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqScheme">
|
|
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>interrupt</type>
|
|
<span>0</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>fpga2hps_interrupt_irq0_irq</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>irq</role>
|
|
</port>
|
|
<interrupt>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_button_pio</moduleName>
|
|
<slaveName>irq</slaveName>
|
|
<name>subsys_periph_button_pio.irq</name>
|
|
<interruptNumber>1</interruptNumber>
|
|
</interrupt>
|
|
<interrupt>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_dipsw_pio</moduleName>
|
|
<slaveName>irq</slaveName>
|
|
<name>subsys_periph_dipsw_pio.irq</name>
|
|
<interruptNumber>0</interruptNumber>
|
|
</interrupt>
|
|
</interface>
|
|
<interface name="f2sdram_axi_clock" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>f2sdram_axi_clock_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="f2sdram_axi_reset" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>f2sdram_axi_reset_reset</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="f2sdram" kind="altera_axi4_slave" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>f2sdram_axi_clock</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>f2sdram_axi_reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="optionalAssociatedReset">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="trustzoneAware">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wakeupSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="uniqueIdSupport">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="poison">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="traceSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isTranslator">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingReads">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingWrites">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumOutstandingTransactions">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dataCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressCheck">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="securityAttribute">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="userData">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readAcceptanceCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeAcceptanceCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="combinedAcceptanceCapability">
|
|
<type>java.lang.Integer</type>
|
|
<value>16</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readDataReorderingDepth">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToMaster">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureGuid">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhGroupId">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterId">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterName">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterVersion">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterData">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterDataLength">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMajorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMinorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureId">
|
|
<type>java.lang.Integer</type>
|
|
<value>35</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureType">
|
|
<type>java.lang.Integer</type>
|
|
<value>3</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="noNarrowTransfer">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>4294967296</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>axi4</type>
|
|
<span>4294967296</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>f2sdram_araddr</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>araddr</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arburst</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>arburst</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arcache</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>arcache</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arid</name>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<role>arid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlen</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>arlen</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlock</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>arlock</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arprot</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>arprot</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arqos</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>arqos</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>arready</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arsize</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>arsize</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>arvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awaddr</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>awaddr</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awburst</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>awburst</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awcache</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>awcache</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awid</name>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<role>awid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlen</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>awlen</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlock</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>awlock</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awprot</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>awprot</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awqos</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>awqos</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>awready</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awsize</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>awsize</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>awvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bid</name>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<role>bid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>bready</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bresp</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>bresp</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>bvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rdata</name>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<role>rdata</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rid</name>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<role>rid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rlast</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>rlast</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>rready</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rresp</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>rresp</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>rvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wdata</name>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<role>wdata</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wlast</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>wlast</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>wready</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wstrb</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>wstrb</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>wvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_aruser</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>aruser</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awuser</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>awuser</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wuser</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>wuser</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_buser</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>buser</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arregion</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>arregion</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_ruser</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>ruser</role>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awregion</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>awregion</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="io96b0_to_hps" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_reset_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_reset_n</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_arready</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_awready</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>ch0_axil_bresp</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_bvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rdata</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>ch0_axil_rdata</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>ch0_axil_rresp</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_rvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_wready</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_araddr</name>
|
|
<direction>Output</direction>
|
|
<width>27</width>
|
|
<role>ch0_axil_araddr</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_arvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awaddr</name>
|
|
<direction>Output</direction>
|
|
<width>27</width>
|
|
<role>ch0_axil_awaddr</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_awvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_bready</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_rready</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wdata</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>ch0_axil_wdata</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wstrb</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>ch0_axil_wstrb</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_wvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>ch0_axil_arprot</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>ch0_axil_awprot</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_reset_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_reset_n</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_arready</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_awready</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bid</name>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<role>axi4_ch0_bid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>axi4_ch0_bresp</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_bvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rdata</name>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<role>axi4_ch0_rdata</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rid</name>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<role>axi4_ch0_rid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rlast</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_rlast</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rresp</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>axi4_ch0_rresp</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_ruser</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>axi4_ch0_ruser</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_rvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_wready</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_araddr</name>
|
|
<direction>Output</direction>
|
|
<width>40</width>
|
|
<role>axi4_ch0_araddr</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arburst</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>axi4_ch0_arburst</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arid</name>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<role>axi4_ch0_arid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arlen</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>axi4_ch0_arlen</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arlock</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_arlock</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arqos</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>axi4_ch0_arqos</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arsize</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>axi4_ch0_arsize</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_aruser</name>
|
|
<direction>Output</direction>
|
|
<width>14</width>
|
|
<role>axi4_ch0_aruser</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_arvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awaddr</name>
|
|
<direction>Output</direction>
|
|
<width>40</width>
|
|
<role>axi4_ch0_awaddr</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awburst</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>axi4_ch0_awburst</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awid</name>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<role>axi4_ch0_awid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awlen</name>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<role>axi4_ch0_awlen</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awlock</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_awlock</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awqos</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>axi4_ch0_awqos</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awsize</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>axi4_ch0_awsize</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awuser</name>
|
|
<direction>Output</direction>
|
|
<width>14</width>
|
|
<role>axi4_ch0_awuser</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_awvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_bready</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_rready</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wdata</name>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<role>axi4_ch0_wdata</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wlast</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_wlast</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wstrb</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>axi4_ch0_wstrb</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wuser</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>axi4_ch0_wuser</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_wvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>axi4_ch0_arprot</role>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awprot</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>axi4_ch0_awprot</role>
|
|
</port>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="subsys_hps_emif_hps"
|
|
kind="emif_io96b_hps"
|
|
version="4.0.0"
|
|
path="subsys_hps.emif_hps"
|
|
className="altera_generic_component">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<parameter name="componentDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
|
|
<value><![CDATA[<componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>io96b0_to_hps</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>s0_noc_axi4lite_clock</name>
|
|
<role>ch0_axil_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_reset_n</name>
|
|
<role>ch0_axil_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awaddr</name>
|
|
<role>ch0_axil_awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awvalid</name>
|
|
<role>ch0_axil_awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awready</name>
|
|
<role>ch0_axil_awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_araddr</name>
|
|
<role>ch0_axil_araddr</role>
|
|
<direction>Input</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arvalid</name>
|
|
<role>ch0_axil_arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arready</name>
|
|
<role>ch0_axil_arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wdata</name>
|
|
<role>ch0_axil_wdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wvalid</name>
|
|
<role>ch0_axil_wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wready</name>
|
|
<role>ch0_axil_wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rresp</name>
|
|
<role>ch0_axil_rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rdata</name>
|
|
<role>ch0_axil_rdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rvalid</name>
|
|
<role>ch0_axil_rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rready</name>
|
|
<role>ch0_axil_rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bresp</name>
|
|
<role>ch0_axil_bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bvalid</name>
|
|
<role>ch0_axil_bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bready</name>
|
|
<role>ch0_axil_bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awprot</name>
|
|
<role>ch0_axil_awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arprot</name>
|
|
<role>ch0_axil_arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wstrb</name>
|
|
<role>ch0_axil_wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awaddr</name>
|
|
<role>axi4_ch0_awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awburst</name>
|
|
<role>axi4_ch0_awburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awid</name>
|
|
<role>axi4_ch0_awid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awlen</name>
|
|
<role>axi4_ch0_awlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awlock</name>
|
|
<role>axi4_ch0_awlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awqos</name>
|
|
<role>axi4_ch0_awqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awsize</name>
|
|
<role>axi4_ch0_awsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awvalid</name>
|
|
<role>axi4_ch0_awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awuser</name>
|
|
<role>axi4_ch0_awuser</role>
|
|
<direction>Input</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awprot</name>
|
|
<role>axi4_ch0_awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awready</name>
|
|
<role>axi4_ch0_awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_araddr</name>
|
|
<role>axi4_ch0_araddr</role>
|
|
<direction>Input</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arburst</name>
|
|
<role>axi4_ch0_arburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arid</name>
|
|
<role>axi4_ch0_arid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arlen</name>
|
|
<role>axi4_ch0_arlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arlock</name>
|
|
<role>axi4_ch0_arlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arqos</name>
|
|
<role>axi4_ch0_arqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arsize</name>
|
|
<role>axi4_ch0_arsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arvalid</name>
|
|
<role>axi4_ch0_arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_aruser</name>
|
|
<role>axi4_ch0_aruser</role>
|
|
<direction>Input</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arprot</name>
|
|
<role>axi4_ch0_arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arready</name>
|
|
<role>axi4_ch0_arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wdata</name>
|
|
<role>axi4_ch0_wdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wstrb</name>
|
|
<role>axi4_ch0_wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wlast</name>
|
|
<role>axi4_ch0_wlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wvalid</name>
|
|
<role>axi4_ch0_wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wready</name>
|
|
<role>axi4_ch0_wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bready</name>
|
|
<role>axi4_ch0_bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bid</name>
|
|
<role>axi4_ch0_bid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bresp</name>
|
|
<role>axi4_ch0_bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bvalid</name>
|
|
<role>axi4_ch0_bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rready</name>
|
|
<role>axi4_ch0_rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rdata</name>
|
|
<role>axi4_ch0_rdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rid</name>
|
|
<role>axi4_ch0_rid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rlast</name>
|
|
<role>axi4_ch0_rlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rresp</name>
|
|
<role>axi4_ch0_rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rvalid</name>
|
|
<role>axi4_ch0_rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>noc_aclk_0</name>
|
|
<role>axi4_ch0_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>noc_rst_n_0</name>
|
|
<role>axi4_ch0_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wuser</name>
|
|
<role>axi4_ch0_wuser</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_ruser</name>
|
|
<role>axi4_ch0_ruser</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_cs</name>
|
|
<role>mem_cs</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_ca</name>
|
|
<role>mem_ca</role>
|
|
<direction>Output</direction>
|
|
<width>6</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_cke</name>
|
|
<role>mem_cke</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dq</name>
|
|
<role>mem_dq</role>
|
|
<direction>Bidir</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dqs_t</name>
|
|
<role>mem_dqs_t</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dqs_c</name>
|
|
<role>mem_dqs_c</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dmi</name>
|
|
<role>mem_dmi</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_ck_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_ck_t</name>
|
|
<role>mem_ck_t</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_ck_c</name>
|
|
<role>mem_ck_c</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_reset_n</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_reset_n</name>
|
|
<role>mem_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>oct_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>oct_rzqin_0</name>
|
|
<role>oct_rzqin</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>ref_clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>ref_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>emif_io96b_hps</className>
|
|
<version>4.0.0</version>
|
|
<displayName>External Memory Interfaces for HPS IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_BOARD</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>BOARD</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_BOARD_TRAIT</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>BOARD_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_BASE_DIE</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>BASE_DEVICE</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_DIE_REVISIONS</parameterName>
|
|
<parameterType>[Ljava.lang.String;</parameterType>
|
|
<systemInfotype>DEVICE_DIE_REVISIONS</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_FAMILY</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_FAMILY</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_GROUP</parameterName>
|
|
<parameterType>[Ljava.lang.String;</parameterType>
|
|
<systemInfoArgs>DEVICE_GROUP</systemInfoArgs>
|
|
<systemInfotype>DEVICE_INFO</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_IOBANK_REVISION</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>DEVICE_IOBANK_REVISION</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_POWER_MODEL</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>DEVICE_POWER_MODEL</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_SPEEDGRADE</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_TEMPERATURE_GRADE</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>DEVICE_TEMPERATURE_GRADE</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_SUPPORTS_VID</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>SUPPORTS_VID</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos/>
|
|
</systemInfos>
|
|
</componentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generationInfoDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
|
|
<value><![CDATA[<generationInfoDefinition>
|
|
<hdlLibraryName>emif_io96b_hps</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>emif_io96b_hps</fileSetName>
|
|
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>emif_io96b_hps</fileSetName>
|
|
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>emif_io96b_hps</fileSetName>
|
|
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>emif_io96b_hps</fileSetName>
|
|
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>emif_io96b_hps</fileSetName>
|
|
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hlsFile">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="logicalView">
|
|
<type>java.lang.String</type>
|
|
<value>ip/qsys_top/emif_io96b_hps.ip</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultBoundary">
|
|
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
|
<value><![CDATA[<boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>io96b0_to_hps</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>s0_noc_axi4lite_clock</name>
|
|
<role>ch0_axil_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_reset_n</name>
|
|
<role>ch0_axil_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awaddr</name>
|
|
<role>ch0_axil_awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awvalid</name>
|
|
<role>ch0_axil_awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awready</name>
|
|
<role>ch0_axil_awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_araddr</name>
|
|
<role>ch0_axil_araddr</role>
|
|
<direction>Input</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arvalid</name>
|
|
<role>ch0_axil_arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arready</name>
|
|
<role>ch0_axil_arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wdata</name>
|
|
<role>ch0_axil_wdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wvalid</name>
|
|
<role>ch0_axil_wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wready</name>
|
|
<role>ch0_axil_wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rresp</name>
|
|
<role>ch0_axil_rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rdata</name>
|
|
<role>ch0_axil_rdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rvalid</name>
|
|
<role>ch0_axil_rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rready</name>
|
|
<role>ch0_axil_rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bresp</name>
|
|
<role>ch0_axil_bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bvalid</name>
|
|
<role>ch0_axil_bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bready</name>
|
|
<role>ch0_axil_bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awprot</name>
|
|
<role>ch0_axil_awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arprot</name>
|
|
<role>ch0_axil_arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wstrb</name>
|
|
<role>ch0_axil_wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awaddr</name>
|
|
<role>axi4_ch0_awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awburst</name>
|
|
<role>axi4_ch0_awburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awid</name>
|
|
<role>axi4_ch0_awid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awlen</name>
|
|
<role>axi4_ch0_awlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awlock</name>
|
|
<role>axi4_ch0_awlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awqos</name>
|
|
<role>axi4_ch0_awqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awsize</name>
|
|
<role>axi4_ch0_awsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awvalid</name>
|
|
<role>axi4_ch0_awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awuser</name>
|
|
<role>axi4_ch0_awuser</role>
|
|
<direction>Input</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awprot</name>
|
|
<role>axi4_ch0_awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awready</name>
|
|
<role>axi4_ch0_awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_araddr</name>
|
|
<role>axi4_ch0_araddr</role>
|
|
<direction>Input</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arburst</name>
|
|
<role>axi4_ch0_arburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arid</name>
|
|
<role>axi4_ch0_arid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arlen</name>
|
|
<role>axi4_ch0_arlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arlock</name>
|
|
<role>axi4_ch0_arlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arqos</name>
|
|
<role>axi4_ch0_arqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arsize</name>
|
|
<role>axi4_ch0_arsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arvalid</name>
|
|
<role>axi4_ch0_arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_aruser</name>
|
|
<role>axi4_ch0_aruser</role>
|
|
<direction>Input</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arprot</name>
|
|
<role>axi4_ch0_arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arready</name>
|
|
<role>axi4_ch0_arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wdata</name>
|
|
<role>axi4_ch0_wdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wstrb</name>
|
|
<role>axi4_ch0_wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wlast</name>
|
|
<role>axi4_ch0_wlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wvalid</name>
|
|
<role>axi4_ch0_wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wready</name>
|
|
<role>axi4_ch0_wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bready</name>
|
|
<role>axi4_ch0_bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bid</name>
|
|
<role>axi4_ch0_bid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bresp</name>
|
|
<role>axi4_ch0_bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bvalid</name>
|
|
<role>axi4_ch0_bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rready</name>
|
|
<role>axi4_ch0_rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rdata</name>
|
|
<role>axi4_ch0_rdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rid</name>
|
|
<role>axi4_ch0_rid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rlast</name>
|
|
<role>axi4_ch0_rlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rresp</name>
|
|
<role>axi4_ch0_rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rvalid</name>
|
|
<role>axi4_ch0_rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>noc_aclk_0</name>
|
|
<role>axi4_ch0_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>noc_rst_n_0</name>
|
|
<role>axi4_ch0_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wuser</name>
|
|
<role>axi4_ch0_wuser</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_ruser</name>
|
|
<role>axi4_ch0_ruser</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_cs</name>
|
|
<role>mem_cs</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_ca</name>
|
|
<role>mem_ca</role>
|
|
<direction>Output</direction>
|
|
<width>6</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_cke</name>
|
|
<role>mem_cke</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dq</name>
|
|
<role>mem_dq</role>
|
|
<direction>Bidir</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dqs_t</name>
|
|
<role>mem_dqs_t</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dqs_c</name>
|
|
<role>mem_dqs_c</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dmi</name>
|
|
<role>mem_dmi</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_ck_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_ck_t</name>
|
|
<role>mem_ck_t</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_ck_c</name>
|
|
<role>mem_ck_c</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_reset_n</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_reset_n</name>
|
|
<role>mem_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>oct_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>oct_rzqin_0</name>
|
|
<role>oct_rzqin</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>ref_clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>ref_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<transformParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value><![CDATA[<cpuInfoDefinition>
|
|
<version>1</version>
|
|
<cpuGroups/>
|
|
<exportedModules/>
|
|
<systemInformation>
|
|
<name>emif_io96b_hps</name>
|
|
<deviceFamily>Agilex 5</deviceFamily>
|
|
<generateLegacySim>false</generateLegacySim>
|
|
</systemInformation>
|
|
</cpuInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="SYSINFO_BOARD">
|
|
<type>java.lang.String</type>
|
|
<value>default</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>BOARD</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="SYSINFO_BOARD_TRAIT">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>BOARD_TRAIT</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="SYSINFO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="SYSINFO_DEVICE_BASE_DIE">
|
|
<type>java.lang.String</type>
|
|
<value>SM4REVB</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>PART_TRAIT</sysinfo_type>
|
|
<sysinfo_arg>BASE_DEVICE</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="SYSINFO_DEVICE_DIE_REVISIONS">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value>MAIN_SM4_REVB</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_DIE_REVISIONS</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="SYSINFO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="SYSINFO_DEVICE_GROUP">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value>B</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_INFO</sysinfo_type>
|
|
<sysinfo_arg>DEVICE_GROUP</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="SYSINFO_DEVICE_IOBANK_REVISION">
|
|
<type>java.lang.String</type>
|
|
<value>IO96B_REVB1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>PART_TRAIT</sysinfo_type>
|
|
<sysinfo_arg>DEVICE_IOBANK_REVISION</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="SYSINFO_DEVICE_POWER_MODEL">
|
|
<type>java.lang.String</type>
|
|
<value>STANDARD_POWER_FIXED</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>PART_TRAIT</sysinfo_type>
|
|
<sysinfo_arg>DEVICE_POWER_MODEL</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="SYSINFO_DEVICE_SPEEDGRADE">
|
|
<type>java.lang.String</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="SYSINFO_DEVICE_TEMPERATURE_GRADE">
|
|
<type>java.lang.String</type>
|
|
<value>EXTENDED</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>PART_TRAIT</sysinfo_type>
|
|
<sysinfo_arg>DEVICE_TEMPERATURE_GRADE</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="SYSINFO_SUPPORTS_VID">
|
|
<type>java.lang.String</type>
|
|
<value>0</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>PART_TRAIT</sysinfo_type>
|
|
<sysinfo_arg>SUPPORTS_VID</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="io96b0_to_hps" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>s0_noc_axi4lite_clock</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_reset_n</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_reset_n</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awaddr</name>
|
|
<direction>Input</direction>
|
|
<width>27</width>
|
|
<role>ch0_axil_awaddr</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_awvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_awready</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_araddr</name>
|
|
<direction>Input</direction>
|
|
<width>27</width>
|
|
<role>ch0_axil_araddr</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_arvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_arready</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wdata</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>ch0_axil_wdata</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_wvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_wready</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rresp</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>ch0_axil_rresp</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rdata</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>ch0_axil_rdata</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_rvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_rready</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bresp</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>ch0_axil_bresp</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_bvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>ch0_axil_bready</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awprot</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>ch0_axil_awprot</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arprot</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>ch0_axil_arprot</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wstrb</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>ch0_axil_wstrb</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awaddr</name>
|
|
<direction>Input</direction>
|
|
<width>40</width>
|
|
<role>axi4_ch0_awaddr</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awburst</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>axi4_ch0_awburst</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awid</name>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<role>axi4_ch0_awid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awlen</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>axi4_ch0_awlen</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awlock</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_awlock</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awqos</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>axi4_ch0_awqos</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awsize</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>axi4_ch0_awsize</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_awvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awuser</name>
|
|
<direction>Input</direction>
|
|
<width>14</width>
|
|
<role>axi4_ch0_awuser</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awprot</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>axi4_ch0_awprot</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_awready</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_araddr</name>
|
|
<direction>Input</direction>
|
|
<width>40</width>
|
|
<role>axi4_ch0_araddr</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arburst</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>axi4_ch0_arburst</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arid</name>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<role>axi4_ch0_arid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arlen</name>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<role>axi4_ch0_arlen</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arlock</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_arlock</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arqos</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>axi4_ch0_arqos</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arsize</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>axi4_ch0_arsize</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_arvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_aruser</name>
|
|
<direction>Input</direction>
|
|
<width>14</width>
|
|
<role>axi4_ch0_aruser</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arprot</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>axi4_ch0_arprot</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_arready</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wdata</name>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<role>axi4_ch0_wdata</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wstrb</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>axi4_ch0_wstrb</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wlast</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_wlast</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wvalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_wvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wready</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_wready</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_bready</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bid</name>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<role>axi4_ch0_bid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bresp</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>axi4_ch0_bresp</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_bvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rready</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_rready</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rdata</name>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<role>axi4_ch0_rdata</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rid</name>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<role>axi4_ch0_rid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rlast</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_rlast</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rresp</name>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<role>axi4_ch0_rresp</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rvalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_rvalid</role>
|
|
</port>
|
|
<port>
|
|
<name>noc_aclk_0</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_clk</role>
|
|
</port>
|
|
<port>
|
|
<name>noc_rst_n_0</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>axi4_ch0_reset_n</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wuser</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>axi4_ch0_wuser</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_ruser</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>axi4_ch0_ruser</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="mem_0" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>mem_0_cs</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mem_cs</role>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_ca</name>
|
|
<direction>Output</direction>
|
|
<width>6</width>
|
|
<role>mem_ca</role>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_cke</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mem_cke</role>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dq</name>
|
|
<direction>Bidir</direction>
|
|
<width>32</width>
|
|
<role>mem_dq</role>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dqs_t</name>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<role>mem_dqs_t</role>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dqs_c</name>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<role>mem_dqs_c</role>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dmi</name>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<role>mem_dmi</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="mem_ck_0" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>mem_0_ck_t</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mem_ck_t</role>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_ck_c</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mem_ck_c</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="mem_reset_n" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>mem_0_reset_n</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>mem_reset_n</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="oct_0" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>oct_rzqin_0</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>oct_rzqin</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="ref_clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>ref_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="subsys_periph"
|
|
kind="peripheral_subsys"
|
|
version="1.0"
|
|
entity="peripheral_subsys"
|
|
library="qsys_top"
|
|
path="subsys_periph"
|
|
hpath="subsys_periph"
|
|
className="peripheral_subsys">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<parameter name="AUTO_GENERATION_ID">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_UNIQUE_ID">
|
|
<type>java.lang.String</type>
|
|
<value>qsys_top_subsys_periph</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
|
<type>java.lang.String</type>
|
|
<value>4</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_BOARD">
|
|
<type>java.lang.String</type>
|
|
<value>default</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>BOARD</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_PB_CPU_0_S0_CPU_INFO_ID">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CPU_INFO_ID</sysinfo_type>
|
|
<sysinfo_arg>pb_cpu_0_s0</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_CLK_CLOCK_RATE">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_CLK_CLOCK_DOMAIN">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
<sysinfo_arg>clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_CLK_RESET_DOMAIN">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
<sysinfo_arg>clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface
|
|
name="button_pio_external_connection"
|
|
kind="conduit_end"
|
|
version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>button_pio_external_connection_export</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>export</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="button_pio_irq" kind="interrupt_sender" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<assignment>
|
|
<name>embeddedsw.dts.irq.tx_type</name>
|
|
<value>RISING_EDGE</value>
|
|
</assignment>
|
|
<parameter name="associatedAddressablePoint">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value>subsys_periph.pb_cpu_0_s0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgedReceiverOffset">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToReceiver">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqScheme">
|
|
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>interrupt</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>button_pio_irq_irq</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>irq</role>
|
|
</port>
|
|
</interface>
|
|
<interface
|
|
name="dipsw_pio_external_connection"
|
|
kind="conduit_end"
|
|
version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>dipsw_pio_external_connection_export</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>export</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="dipsw_pio_irq" kind="interrupt_sender" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<assignment>
|
|
<name>embeddedsw.dts.irq.tx_type</name>
|
|
<value>RISING_EDGE</value>
|
|
</assignment>
|
|
<parameter name="associatedAddressablePoint">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value>subsys_periph.pb_cpu_0_s0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgedReceiverOffset">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToReceiver">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqScheme">
|
|
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>interrupt</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>dipsw_pio_irq_irq</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>irq</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="led_pio_external_connection" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>led_pio_external_connection_in_port</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>in_port</role>
|
|
</port>
|
|
<port>
|
|
<name>led_pio_external_connection_out_port</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>out_port</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="pb_cpu_0_s0" kind="avalon_slave" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isFlash</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isMemoryDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isNonVolatileStorage</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isPrintableDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<parameter name="addressAlignment">
|
|
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
|
|
<value>DYNAMIC</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressGroup">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>131072</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>SYMBOLS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="alwaysBurstMaxBurst">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bitsPerSymbol">
|
|
<type>int</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgedAddressOffset">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToMaster">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstOnBurstBoundariesOnly">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstcountUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>WORDS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="constantBurstBehavior">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="explicitAddressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="holdTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="interleaveBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isBigEndian">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isFlash">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isMemoryDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isNonVolatileStorage">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="linewrapBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingReadTransactions">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingWriteTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumReadLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumResponseLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumUninterruptedRunLength">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="printableDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitStates">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerIncomingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerOutgoingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="setupTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="timingUnits">
|
|
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
|
|
<value>Cycles</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transparentBridge">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestAllowance">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestTimeout">
|
|
<type>int</type>
|
|
<value>1024</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wellBehavedWaitrequest">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitStates">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureGuid">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhGroupId">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterId">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterName">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterVersion">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterData">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterDataLength">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMajorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMinorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureId">
|
|
<type>java.lang.Integer</type>
|
|
<value>35</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureType">
|
|
<type>java.lang.Integer</type>
|
|
<value>3</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>avalon</type>
|
|
<span>131072</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>pb_cpu_0_s0_waitrequest</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>waitrequest</role>
|
|
</port>
|
|
<port>
|
|
<name>pb_cpu_0_s0_readdata</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>readdata</role>
|
|
</port>
|
|
<port>
|
|
<name>pb_cpu_0_s0_readdatavalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>readdatavalid</role>
|
|
</port>
|
|
<port>
|
|
<name>pb_cpu_0_s0_burstcount</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>burstcount</role>
|
|
</port>
|
|
<port>
|
|
<name>pb_cpu_0_s0_writedata</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>writedata</role>
|
|
</port>
|
|
<port>
|
|
<name>pb_cpu_0_s0_address</name>
|
|
<direction>Input</direction>
|
|
<width>17</width>
|
|
<role>address</role>
|
|
</port>
|
|
<port>
|
|
<name>pb_cpu_0_s0_write</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>write</role>
|
|
</port>
|
|
<port>
|
|
<name>pb_cpu_0_s0_read</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>read</role>
|
|
</port>
|
|
<port>
|
|
<name>pb_cpu_0_s0_byteenable</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>byteenable</role>
|
|
</port>
|
|
<port>
|
|
<name>pb_cpu_0_s0_debugaccess</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>debugaccess</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>java.lang.Boolean</type>
|
|
<value>true</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>clk_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="reset" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>reset_reset_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset_n</role>
|
|
</port>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="subsys_periph_button_pio"
|
|
kind="altera_avalon_pio"
|
|
version="19.2.3"
|
|
path="subsys_periph.button_pio"
|
|
className="altera_generic_component">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</name>
|
|
<value>1</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.CAPTURE</name>
|
|
<value>1</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.DATA_WIDTH</name>
|
|
<value>4</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.DRIVEN_SIM_VALUE</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.EDGE_TYPE</name>
|
|
<value>FALLING</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.FREQ</name>
|
|
<value>100000000</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.HAS_IN</name>
|
|
<value>1</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.HAS_OUT</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.HAS_TRI</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.IRQ_TYPE</name>
|
|
<value>EDGE</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.RESET_VALUE</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.compatible</name>
|
|
<value>altr,pio-1.0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.group</name>
|
|
<value>gpio</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.name</name>
|
|
<value>pio</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.altr,gpio-bank-width</name>
|
|
<value>4</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.altr,interrupt-type</name>
|
|
<value>2</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.altr,interrupt_type</name>
|
|
<value>2</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.edge_type</name>
|
|
<value>1</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.level_trigger</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.resetvalue</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.vendor</name>
|
|
<value>altr</value>
|
|
</assignment>
|
|
<parameter name="componentDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
|
|
<value><![CDATA[<componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s1</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<role>write_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<role>chipselect</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>export</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>irq</name>
|
|
<type>interrupt</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>irq</name>
|
|
<role>irq</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.dts.irq.tx_type</key>
|
|
<value>RISING_EDGE</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
<value>button_pio.s1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedReceiverOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToReceiver</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_avalon_pio</className>
|
|
<version>19.2.3</version>
|
|
<displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>DEVICE_FAMILY</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_FAMILY</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue>0</parameterDefaultValue>
|
|
<parameterName>clockRate</parameterName>
|
|
<parameterType>java.lang.Long</parameterType>
|
|
<systemInfoArgs>clk</systemInfoArgs>
|
|
<systemInfotype>CLOCK_RATE</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>clk</key>
|
|
<value>
|
|
<connectionPointName>clk</connectionPointName>
|
|
<suppliedSystemInfos/>
|
|
<consumedSystemInfos>
|
|
<entry>
|
|
<key>CLOCK_RATE</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
</consumedSystemInfos>
|
|
</value>
|
|
</entry>
|
|
<entry>
|
|
<key>s1</key>
|
|
<value>
|
|
<connectionPointName>s1</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
<value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
<value>32</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generationInfoDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
|
|
<value><![CDATA[<generationInfoDefinition>
|
|
<hdlLibraryName>button_pio</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>button_pio</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>button_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>button_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>button_pio</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>button_pio</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hlsFile">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="logicalView">
|
|
<type>java.lang.String</type>
|
|
<value>ip/peripheral_subsys/button_pio.ip</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultBoundary">
|
|
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
|
<value><![CDATA[<boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s1</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<role>write_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<role>chipselect</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
<cmsisInfo>
|
|
<cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
|
|
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
|
|
<peripherals>
|
|
<peripheral>
|
|
<name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>32</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>Data</displayName>
|
|
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>data</name>
|
|
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRECTION</name>
|
|
<displayName>Direction</displayName>
|
|
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>direction</name>
|
|
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_MASK</name>
|
|
<displayName>Interrupt mask</displayName>
|
|
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>interruptmask</name>
|
|
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EDGE_CAP</name>
|
|
<displayName>Edge capture</displayName>
|
|
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
|
<addressOffset>0xc</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>edgecapture</name>
|
|
<description>Edge detection for each input port.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_BIT</name>
|
|
<displayName>Outset</displayName>
|
|
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>outset</name>
|
|
<description>Specifies which bit of the output port to set.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLEAR_BITS</name>
|
|
<displayName>Outclear</displayName>
|
|
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>outclear</name>
|
|
<description>Specifies which output bit to clear.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device> </cmsisSrcFileContents>
|
|
<addressGroup></addressGroup>
|
|
<cmsisVars/>
|
|
</cmsisInfo>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>export</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>irq</name>
|
|
<type>interrupt</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>irq</name>
|
|
<role>irq</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.dts.irq.tx_type</key>
|
|
<value>RISING_EDGE</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
<value>button_pio.s1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedReceiverOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToReceiver</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
|
|
<value><![CDATA[<assignmentDefinition>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.CAPTURE</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DATA_WIDTH</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.EDGE_TYPE</key>
|
|
<value>FALLING</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.FREQ</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_IN</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_OUT</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_TRI</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.IRQ_TYPE</key>
|
|
<value>EDGE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.RESET_VALUE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.compatible</key>
|
|
<value>altr,pio-1.0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.group</key>
|
|
<value>gpio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.name</key>
|
|
<value>pio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,gpio-bank-width</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,interrupt-type</key>
|
|
<value>2</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,interrupt_type</key>
|
|
<value>2</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.edge_type</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.level_trigger</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.resetvalue</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.vendor</key>
|
|
<value>altr</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignmentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value>altera_avalon_pio_inst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>java.lang.Boolean</type>
|
|
<value>true</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="reset" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>DEASSERT</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset_n</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="s1" kind="avalon_slave" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isFlash</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isMemoryDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isNonVolatileStorage</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isPrintableDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<parameter name="addressAlignment">
|
|
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
|
|
<value>NATIVE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressGroup">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>WORDS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="alwaysBurstMaxBurst">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bitsPerSymbol">
|
|
<type>int</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgedAddressOffset">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToMaster">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstOnBurstBoundariesOnly">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstcountUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>WORDS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="constantBurstBehavior">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="explicitAddressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="holdTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="interleaveBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isBigEndian">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isFlash">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isMemoryDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isNonVolatileStorage">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="linewrapBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingReadTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingWriteTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumReadLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumResponseLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumUninterruptedRunLength">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="printableDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitStates">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitTime">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerIncomingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerOutgoingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="setupTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="timingUnits">
|
|
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
|
|
<value>Cycles</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transparentBridge">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestAllowance">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestTimeout">
|
|
<type>int</type>
|
|
<value>1024</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wellBehavedWaitrequest">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitStates">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureGuid">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhGroupId">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterId">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterName">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterVersion">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterData">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterDataLength">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMajorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMinorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureId">
|
|
<type>java.lang.Integer</type>
|
|
<value>35</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureType">
|
|
<type>java.lang.Integer</type>
|
|
<value>3</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>avalon</type>
|
|
<span>16</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>address</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>address</role>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>write_n</role>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>writedata</role>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>chipselect</role>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>readdata</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="external_connection" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>in_port</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>export</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="irq" kind="interrupt_sender" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<assignment>
|
|
<name>embeddedsw.dts.irq.tx_type</name>
|
|
<value>RISING_EDGE</value>
|
|
</assignment>
|
|
<parameter name="associatedAddressablePoint">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value>button_pio.s1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgedReceiverOffset">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToReceiver">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqScheme">
|
|
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>interrupt</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>irq</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>irq</role>
|
|
</port>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="subsys_periph_dipsw_pio"
|
|
kind="altera_avalon_pio"
|
|
version="19.2.3"
|
|
path="subsys_periph.dipsw_pio"
|
|
className="altera_generic_component">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</name>
|
|
<value>1</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.CAPTURE</name>
|
|
<value>1</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.DATA_WIDTH</name>
|
|
<value>4</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.DRIVEN_SIM_VALUE</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.EDGE_TYPE</name>
|
|
<value>FALLING</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.FREQ</name>
|
|
<value>100000000</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.HAS_IN</name>
|
|
<value>1</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.HAS_OUT</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.HAS_TRI</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.IRQ_TYPE</name>
|
|
<value>EDGE</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.RESET_VALUE</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.compatible</name>
|
|
<value>altr,pio-1.0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.group</name>
|
|
<value>gpio</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.name</name>
|
|
<value>pio</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.altr,gpio-bank-width</name>
|
|
<value>4</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.altr,interrupt-type</name>
|
|
<value>2</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.altr,interrupt_type</name>
|
|
<value>2</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.edge_type</name>
|
|
<value>1</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.level_trigger</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.resetvalue</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.vendor</name>
|
|
<value>altr</value>
|
|
</assignment>
|
|
<parameter name="componentDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
|
|
<value><![CDATA[<componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s1</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<role>write_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<role>chipselect</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>export</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>irq</name>
|
|
<type>interrupt</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>irq</name>
|
|
<role>irq</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.dts.irq.tx_type</key>
|
|
<value>RISING_EDGE</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
<value>dipsw_pio.s1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedReceiverOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToReceiver</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_avalon_pio</className>
|
|
<version>19.2.3</version>
|
|
<displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>DEVICE_FAMILY</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_FAMILY</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue>0</parameterDefaultValue>
|
|
<parameterName>clockRate</parameterName>
|
|
<parameterType>java.lang.Long</parameterType>
|
|
<systemInfoArgs>clk</systemInfoArgs>
|
|
<systemInfotype>CLOCK_RATE</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>clk</key>
|
|
<value>
|
|
<connectionPointName>clk</connectionPointName>
|
|
<suppliedSystemInfos/>
|
|
<consumedSystemInfos>
|
|
<entry>
|
|
<key>CLOCK_RATE</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
</consumedSystemInfos>
|
|
</value>
|
|
</entry>
|
|
<entry>
|
|
<key>s1</key>
|
|
<value>
|
|
<connectionPointName>s1</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
<value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
<value>32</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generationInfoDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
|
|
<value><![CDATA[<generationInfoDefinition>
|
|
<hdlLibraryName>dipsw_pio</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>dipsw_pio</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>dipsw_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>dipsw_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>dipsw_pio</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>dipsw_pio</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hlsFile">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="logicalView">
|
|
<type>java.lang.String</type>
|
|
<value>ip/peripheral_subsys/dipsw_pio.ip</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultBoundary">
|
|
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
|
<value><![CDATA[<boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s1</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<role>write_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<role>chipselect</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
<cmsisInfo>
|
|
<cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
|
|
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
|
|
<peripherals>
|
|
<peripheral>
|
|
<name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>32</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>Data</displayName>
|
|
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>data</name>
|
|
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRECTION</name>
|
|
<displayName>Direction</displayName>
|
|
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>direction</name>
|
|
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_MASK</name>
|
|
<displayName>Interrupt mask</displayName>
|
|
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>interruptmask</name>
|
|
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EDGE_CAP</name>
|
|
<displayName>Edge capture</displayName>
|
|
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
|
<addressOffset>0xc</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>edgecapture</name>
|
|
<description>Edge detection for each input port.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_BIT</name>
|
|
<displayName>Outset</displayName>
|
|
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>outset</name>
|
|
<description>Specifies which bit of the output port to set.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLEAR_BITS</name>
|
|
<displayName>Outclear</displayName>
|
|
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>outclear</name>
|
|
<description>Specifies which output bit to clear.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device> </cmsisSrcFileContents>
|
|
<addressGroup></addressGroup>
|
|
<cmsisVars/>
|
|
</cmsisInfo>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>export</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>irq</name>
|
|
<type>interrupt</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>irq</name>
|
|
<role>irq</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.dts.irq.tx_type</key>
|
|
<value>RISING_EDGE</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
<value>dipsw_pio.s1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedReceiverOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToReceiver</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
|
|
<value><![CDATA[<assignmentDefinition>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.CAPTURE</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DATA_WIDTH</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.EDGE_TYPE</key>
|
|
<value>FALLING</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.FREQ</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_IN</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_OUT</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_TRI</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.IRQ_TYPE</key>
|
|
<value>EDGE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.RESET_VALUE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.compatible</key>
|
|
<value>altr,pio-1.0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.group</key>
|
|
<value>gpio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.name</key>
|
|
<value>pio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,gpio-bank-width</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,interrupt-type</key>
|
|
<value>2</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,interrupt_type</key>
|
|
<value>2</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.edge_type</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.level_trigger</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.resetvalue</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.vendor</key>
|
|
<value>altr</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignmentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value>altera_avalon_pio_inst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>java.lang.Boolean</type>
|
|
<value>true</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="reset" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>DEASSERT</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset_n</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="s1" kind="avalon_slave" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isFlash</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isMemoryDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isNonVolatileStorage</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isPrintableDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<parameter name="addressAlignment">
|
|
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
|
|
<value>NATIVE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressGroup">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>WORDS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="alwaysBurstMaxBurst">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bitsPerSymbol">
|
|
<type>int</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgedAddressOffset">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToMaster">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstOnBurstBoundariesOnly">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstcountUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>WORDS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="constantBurstBehavior">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="explicitAddressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="holdTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="interleaveBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isBigEndian">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isFlash">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isMemoryDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isNonVolatileStorage">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="linewrapBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingReadTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingWriteTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumReadLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumResponseLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumUninterruptedRunLength">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="printableDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitStates">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitTime">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerIncomingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerOutgoingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="setupTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="timingUnits">
|
|
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
|
|
<value>Cycles</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transparentBridge">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestAllowance">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestTimeout">
|
|
<type>int</type>
|
|
<value>1024</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wellBehavedWaitrequest">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitStates">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureGuid">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhGroupId">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterId">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterName">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterVersion">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterData">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterDataLength">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMajorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMinorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureId">
|
|
<type>java.lang.Integer</type>
|
|
<value>35</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureType">
|
|
<type>java.lang.Integer</type>
|
|
<value>3</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>avalon</type>
|
|
<span>16</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>address</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>address</role>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>write_n</role>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>writedata</role>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>chipselect</role>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>readdata</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="external_connection" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>in_port</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>export</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="irq" kind="interrupt_sender" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<assignment>
|
|
<name>embeddedsw.dts.irq.tx_type</name>
|
|
<value>RISING_EDGE</value>
|
|
</assignment>
|
|
<parameter name="associatedAddressablePoint">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value>dipsw_pio.s1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgedReceiverOffset">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToReceiver">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="irqScheme">
|
|
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>interrupt</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>irq</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>irq</role>
|
|
</port>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="subsys_periph_led_pio"
|
|
kind="altera_avalon_pio"
|
|
version="19.2.3"
|
|
path="subsys_periph.led_pio"
|
|
className="altera_generic_component">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.CAPTURE</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.DATA_WIDTH</name>
|
|
<value>3</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.DRIVEN_SIM_VALUE</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.EDGE_TYPE</name>
|
|
<value>NONE</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.FREQ</name>
|
|
<value>100000000</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.HAS_IN</name>
|
|
<value>1</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.HAS_OUT</name>
|
|
<value>1</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.HAS_TRI</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.IRQ_TYPE</name>
|
|
<value>NONE</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.RESET_VALUE</name>
|
|
<value>7</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.compatible</name>
|
|
<value>altr,pio-1.0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.group</name>
|
|
<value>gpio</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.name</name>
|
|
<value>pio</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.altr,gpio-bank-width</name>
|
|
<value>3</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.resetvalue</name>
|
|
<value>7</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.vendor</name>
|
|
<value>altr</value>
|
|
</assignment>
|
|
<parameter name="componentDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
|
|
<value><![CDATA[<componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s1</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<role>write_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<role>chipselect</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>in_port</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>out_port</name>
|
|
<role>out_port</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_avalon_pio</className>
|
|
<version>19.2.3</version>
|
|
<displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>DEVICE_FAMILY</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_FAMILY</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue>0</parameterDefaultValue>
|
|
<parameterName>clockRate</parameterName>
|
|
<parameterType>java.lang.Long</parameterType>
|
|
<systemInfoArgs>clk</systemInfoArgs>
|
|
<systemInfotype>CLOCK_RATE</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>clk</key>
|
|
<value>
|
|
<connectionPointName>clk</connectionPointName>
|
|
<suppliedSystemInfos/>
|
|
<consumedSystemInfos>
|
|
<entry>
|
|
<key>CLOCK_RATE</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
</consumedSystemInfos>
|
|
</value>
|
|
</entry>
|
|
<entry>
|
|
<key>s1</key>
|
|
<value>
|
|
<connectionPointName>s1</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
<value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
<value>32</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generationInfoDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
|
|
<value><![CDATA[<generationInfoDefinition>
|
|
<hdlLibraryName>led_pio</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>led_pio</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>led_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>led_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>led_pio</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>led_pio</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hlsFile">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="logicalView">
|
|
<type>java.lang.String</type>
|
|
<value>ip/peripheral_subsys/led_pio.ip</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultBoundary">
|
|
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
|
<value><![CDATA[<boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s1</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<role>write_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<role>chipselect</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
<cmsisInfo>
|
|
<cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
|
|
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
|
|
<peripherals>
|
|
<peripheral>
|
|
<name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>32</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>Data</displayName>
|
|
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>data</name>
|
|
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRECTION</name>
|
|
<displayName>Direction</displayName>
|
|
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>direction</name>
|
|
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_MASK</name>
|
|
<displayName>Interrupt mask</displayName>
|
|
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>interruptmask</name>
|
|
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EDGE_CAP</name>
|
|
<displayName>Edge capture</displayName>
|
|
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
|
<addressOffset>0xc</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>edgecapture</name>
|
|
<description>Edge detection for each input port.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_BIT</name>
|
|
<displayName>Outset</displayName>
|
|
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>outset</name>
|
|
<description>Specifies which bit of the output port to set.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLEAR_BITS</name>
|
|
<displayName>Outclear</displayName>
|
|
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>outclear</name>
|
|
<description>Specifies which output bit to clear.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device> </cmsisSrcFileContents>
|
|
<addressGroup></addressGroup>
|
|
<cmsisVars/>
|
|
</cmsisInfo>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>in_port</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>out_port</name>
|
|
<role>out_port</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
|
|
<value><![CDATA[<assignmentDefinition>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.CAPTURE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DATA_WIDTH</key>
|
|
<value>3</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.EDGE_TYPE</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.FREQ</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_IN</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_OUT</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_TRI</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.IRQ_TYPE</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.RESET_VALUE</key>
|
|
<value>7</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.compatible</key>
|
|
<value>altr,pio-1.0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.group</key>
|
|
<value>gpio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.name</key>
|
|
<value>pio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,gpio-bank-width</key>
|
|
<value>3</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.resetvalue</key>
|
|
<value>7</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.vendor</key>
|
|
<value>altr</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignmentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value>altera_avalon_pio_inst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>java.lang.Boolean</type>
|
|
<value>true</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="reset" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>DEASSERT</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset_n</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="s1" kind="avalon_slave" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isFlash</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isMemoryDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isNonVolatileStorage</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isPrintableDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<parameter name="addressAlignment">
|
|
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
|
|
<value>NATIVE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressGroup">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>WORDS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="alwaysBurstMaxBurst">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bitsPerSymbol">
|
|
<type>int</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgedAddressOffset">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToMaster">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstOnBurstBoundariesOnly">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstcountUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>WORDS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="constantBurstBehavior">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="explicitAddressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="holdTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="interleaveBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isBigEndian">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isFlash">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isMemoryDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isNonVolatileStorage">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="linewrapBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingReadTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingWriteTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumReadLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumResponseLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumUninterruptedRunLength">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="printableDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitStates">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitTime">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerIncomingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerOutgoingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="setupTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="timingUnits">
|
|
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
|
|
<value>Cycles</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transparentBridge">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestAllowance">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestTimeout">
|
|
<type>int</type>
|
|
<value>1024</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wellBehavedWaitrequest">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitStates">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureGuid">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhGroupId">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterId">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterName">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterVersion">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterData">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterDataLength">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMajorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMinorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureId">
|
|
<type>java.lang.Integer</type>
|
|
<value>35</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureType">
|
|
<type>java.lang.Integer</type>
|
|
<value>3</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>avalon</type>
|
|
<span>16</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>address</name>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<role>address</role>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>write_n</role>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>writedata</role>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>chipselect</role>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>readdata</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="external_connection" kind="conduit_end" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>conduit</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>in_port</name>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<role>in_port</role>
|
|
</port>
|
|
<port>
|
|
<name>out_port</name>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<role>out_port</role>
|
|
</port>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="subsys_periph_pb_cpu_0"
|
|
kind="altera_avalon_mm_bridge"
|
|
version="20.1.0"
|
|
path="subsys_periph.pb_cpu_0"
|
|
className="altera_generic_component">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<parameter name="componentDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
|
|
<value><![CDATA[<componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s0</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>s0_waitrequest</name>
|
|
<role>waitrequest</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_readdatavalid</name>
|
|
<role>readdatavalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_burstcount</name>
|
|
<role>burstcount</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>17</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_write</name>
|
|
<role>write</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_read</name>
|
|
<role>read</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_byteenable</name>
|
|
<role>byteenable</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_debugaccess</name>
|
|
<role>debugaccess</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>DYNAMIC</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>131072</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>SYMBOLS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
<value>pb_cpu_0.m0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>m0</name>
|
|
<type>avalon</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>m0_waitrequest</name>
|
|
<role>waitrequest</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_readdatavalid</name>
|
|
<role>readdatavalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_burstcount</name>
|
|
<role>burstcount</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_address</name>
|
|
<role>address</role>
|
|
<direction>Output</direction>
|
|
<width>17</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_write</name>
|
|
<role>write</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_read</name>
|
|
<role>read</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_byteenable</name>
|
|
<role>byteenable</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_debugaccess</name>
|
|
<role>debugaccess</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>adaptsTo</key>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>SYMBOLS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dBSBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>doStreamReads</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>doStreamWrites</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isAsynchronous</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isReadable</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isWriteable</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maxAddressWidth</key>
|
|
<value>32</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optimizedReadsWithBE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_avalon_mm_bridge</className>
|
|
<version>20.1.0</version>
|
|
<displayName>Avalon Memory Mapped Pipeline Bridge Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue>10</parameterDefaultValue>
|
|
<parameterName>SYSINFO_ADDR_WIDTH</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<systemInfoArgs>m0</systemInfoArgs>
|
|
<systemInfotype>ADDRESS_WIDTH</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>m0</key>
|
|
<value>
|
|
<connectionPointName>m0</connectionPointName>
|
|
<suppliedSystemInfos/>
|
|
<consumedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>17</value>
|
|
</entry>
|
|
</consumedSystemInfos>
|
|
</value>
|
|
</entry>
|
|
<entry>
|
|
<key>s0</key>
|
|
<value>
|
|
<connectionPointName>s0</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generationInfoDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
|
|
<value><![CDATA[<generationInfoDefinition>
|
|
<hdlLibraryName>pb_cpu_0</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hlsFile">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="logicalView">
|
|
<type>java.lang.String</type>
|
|
<value>ip/peripheral_subsys/pb_cpu_0.ip</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultBoundary">
|
|
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
|
<value><![CDATA[<boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s0</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>s0_waitrequest</name>
|
|
<role>waitrequest</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_readdatavalid</name>
|
|
<role>readdatavalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_burstcount</name>
|
|
<role>burstcount</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>17</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_write</name>
|
|
<role>write</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_read</name>
|
|
<role>read</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_byteenable</name>
|
|
<role>byteenable</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_debugaccess</name>
|
|
<role>debugaccess</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>DYNAMIC</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>131072</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>SYMBOLS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
<value>pb_cpu_0.m0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>m0</name>
|
|
<type>avalon</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>m0_waitrequest</name>
|
|
<role>waitrequest</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_readdatavalid</name>
|
|
<role>readdatavalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_burstcount</name>
|
|
<role>burstcount</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_address</name>
|
|
<role>address</role>
|
|
<direction>Output</direction>
|
|
<width>17</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_write</name>
|
|
<role>write</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_read</name>
|
|
<role>read</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_byteenable</name>
|
|
<role>byteenable</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_debugaccess</name>
|
|
<role>debugaccess</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>adaptsTo</key>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>SYMBOLS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dBSBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>doStreamReads</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>doStreamWrites</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isAsynchronous</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isReadable</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isWriteable</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maxAddressWidth</key>
|
|
<value>32</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
|
|
<value><![CDATA[<assignmentDefinition>
|
|
<assignmentValueMap/>
|
|
</assignmentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>Bridge data width</description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>DATA_WIDTH</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>32</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>Symbol (byte) width</description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>SYMBOL_WIDTH</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>8</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>HDL_ADDR_WIDTH</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>17</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>Bridge burstcount width</description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>BURSTCOUNT_WIDTH</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>1</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>When enabled, the command (or response) networks are pipelined, potentially increasing the frequency at the expense of increase logic and latency.</description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>PIPELINE_COMMAND</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>1</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>When enabled, the command (or response) networks are pipelined, potentially increasing the frequency at the expense of increase logic and latency.</description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>PIPELINE_RESPONSE</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>1</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>0 means allows asynchronous resets, 1 means internal reset synchronization </description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>SYNC_RESET</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>0</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>0 means writeresponsvalid is disabled, 1 means writeresponsevalid is enabled </description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>USE_WRITERESPONSE</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>0</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>S0_WAITREQUEST_ALLOWANCE</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>0</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>M0_WAITREQUEST_ALLOWANCE</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>0</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
</hdlParameterDescriptorDefinitionList>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value>altera_avalon_mm_bridge_inst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="SYSINFO_ADDR_WIDTH">
|
|
<type>java.lang.Integer</type>
|
|
<value>17</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
|
|
<sysinfo_arg>m0</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="reset" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>DEASSERT</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>reset</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="s0" kind="avalon_slave" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isFlash</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isMemoryDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isNonVolatileStorage</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isPrintableDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<parameter name="addressAlignment">
|
|
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
|
|
<value>DYNAMIC</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressGroup">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>131072</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>SYMBOLS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="alwaysBurstMaxBurst">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bitsPerSymbol">
|
|
<type>int</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgedAddressOffset">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToMaster">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value>pb_cpu_0.m0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstOnBurstBoundariesOnly">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstcountUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>WORDS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="constantBurstBehavior">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="explicitAddressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="holdTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="interleaveBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isBigEndian">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isFlash">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isMemoryDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isNonVolatileStorage">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="linewrapBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingReadTransactions">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingWriteTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumReadLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumResponseLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumUninterruptedRunLength">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="printableDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitStates">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerIncomingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerOutgoingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="setupTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="timingUnits">
|
|
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
|
|
<value>Cycles</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transparentBridge">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestAllowance">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestTimeout">
|
|
<type>int</type>
|
|
<value>1024</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wellBehavedWaitrequest">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitStates">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureGuid">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhGroupId">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterId">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterName">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterVersion">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterData">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterDataLength">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMajorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMinorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureId">
|
|
<type>java.lang.Integer</type>
|
|
<value>35</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureType">
|
|
<type>java.lang.Integer</type>
|
|
<value>3</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>avalon</type>
|
|
<span>131072</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>s0_waitrequest</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>waitrequest</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_readdata</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>readdata</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_readdatavalid</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>readdatavalid</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_burstcount</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>burstcount</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_writedata</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>writedata</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_address</name>
|
|
<direction>Input</direction>
|
|
<width>17</width>
|
|
<role>address</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_write</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>write</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_read</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>read</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_byteenable</name>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<role>byteenable</role>
|
|
</port>
|
|
<port>
|
|
<name>s0_debugaccess</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>debugaccess</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="m0" kind="avalon_master" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="adaptsTo">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressGroup">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>SYMBOLS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="alwaysBurstMaxBurst">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bitsPerSymbol">
|
|
<type>int</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstOnBurstBoundariesOnly">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstcountUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>WORDS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="constantBurstBehavior">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dBSBigEndian">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="doStreamReads">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="doStreamWrites">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="holdTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="interleaveBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isAsynchronous">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isBigEndian">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isReadable">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isWriteable">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="linewrapBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maxAddressWidth">
|
|
<type>int</type>
|
|
<value>32</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingReadTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingWriteTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumReadLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumResponseLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitTime">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerIncomingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerOutgoingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="setupTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="timingUnits">
|
|
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
|
|
<value>Cycles</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestAllowance">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestTimeout">
|
|
<type>int</type>
|
|
<value>1024</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="enableConcurrentSubordinateAccess">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="optimizedReadsWithBE">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>avalon</type>
|
|
<span>131072</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>m0_waitrequest</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>waitrequest</role>
|
|
</port>
|
|
<port>
|
|
<name>m0_readdata</name>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<role>readdata</role>
|
|
</port>
|
|
<port>
|
|
<name>m0_readdatavalid</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>readdatavalid</role>
|
|
</port>
|
|
<port>
|
|
<name>m0_burstcount</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>burstcount</role>
|
|
</port>
|
|
<port>
|
|
<name>m0_writedata</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>writedata</role>
|
|
</port>
|
|
<port>
|
|
<name>m0_address</name>
|
|
<direction>Output</direction>
|
|
<width>17</width>
|
|
<role>address</role>
|
|
</port>
|
|
<port>
|
|
<name>m0_write</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>write</role>
|
|
</port>
|
|
<port>
|
|
<name>m0_read</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>read</role>
|
|
</port>
|
|
<port>
|
|
<name>m0_byteenable</name>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<role>byteenable</role>
|
|
</port>
|
|
<port>
|
|
<name>m0_debugaccess</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>debugaccess</role>
|
|
</port>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_sysid</moduleName>
|
|
<slaveName>control_slave</slaveName>
|
|
<name>subsys_periph_sysid.control_slave</name>
|
|
<baseAddress>65536</baseAddress>
|
|
<span>8</span>
|
|
</memoryBlock>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_led_pio</moduleName>
|
|
<slaveName>s1</slaveName>
|
|
<name>subsys_periph_led_pio.s1</name>
|
|
<baseAddress>65664</baseAddress>
|
|
<span>16</span>
|
|
</memoryBlock>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_dipsw_pio</moduleName>
|
|
<slaveName>s1</slaveName>
|
|
<name>subsys_periph_dipsw_pio.s1</name>
|
|
<baseAddress>65648</baseAddress>
|
|
<span>16</span>
|
|
</memoryBlock>
|
|
<memoryBlock>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_button_pio</moduleName>
|
|
<slaveName>s1</slaveName>
|
|
<name>subsys_periph_button_pio.s1</name>
|
|
<baseAddress>65632</baseAddress>
|
|
<span>16</span>
|
|
</memoryBlock>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="subsys_periph_periph_clk"
|
|
kind="altera_clock_bridge"
|
|
version="19.2.0"
|
|
path="subsys_periph.periph_clk"
|
|
className="altera_generic_component">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<parameter name="componentDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
|
|
<value><![CDATA[<componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>in_clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>out_clk</name>
|
|
<type>clock</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>out_clk</name>
|
|
<role>clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedDirectClock</key>
|
|
<value>in_clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
<entry>
|
|
<key>clockRateKnown</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_clock_bridge</className>
|
|
<version>19.2.0</version>
|
|
<displayName>Clock Bridge Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue>0</parameterDefaultValue>
|
|
<parameterName>DERIVED_CLOCK_RATE</parameterName>
|
|
<parameterType>java.lang.Long</parameterType>
|
|
<systemInfoArgs>in_clk</systemInfoArgs>
|
|
<systemInfotype>CLOCK_RATE</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>in_clk</key>
|
|
<value>
|
|
<connectionPointName>in_clk</connectionPointName>
|
|
<suppliedSystemInfos/>
|
|
<consumedSystemInfos>
|
|
<entry>
|
|
<key>CLOCK_RATE</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
</consumedSystemInfos>
|
|
</value>
|
|
</entry>
|
|
<entry>
|
|
<key>out_clk</key>
|
|
<value>
|
|
<connectionPointName>out_clk</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>CLOCK_RATE</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generationInfoDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
|
|
<value><![CDATA[<generationInfoDefinition>
|
|
<hdlLibraryName>periph_clk</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>periph_clk</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>periph_clk</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>periph_clk</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>periph_clk</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>periph_clk</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hlsFile">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="logicalView">
|
|
<type>java.lang.String</type>
|
|
<value>ip/peripheral_subsys/periph_clk.ip</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultBoundary">
|
|
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
|
<value><![CDATA[<boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>in_clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>out_clk</name>
|
|
<type>clock</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>out_clk</name>
|
|
<role>clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedDirectClock</key>
|
|
<value>in_clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
<entry>
|
|
<key>clockRateKnown</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
|
|
<value><![CDATA[<assignmentDefinition>
|
|
<assignmentValueMap/>
|
|
</assignmentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value>altera_clock_bridge_inst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="DERIVED_CLOCK_RATE">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>in_clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="in_clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>java.lang.Boolean</type>
|
|
<value>true</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>in_clk</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="out_clk" kind="clock_source" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedDirectClock">
|
|
<type>java.lang.String</type>
|
|
<value>in_clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRate">
|
|
<type>long</type>
|
|
<value>100000000</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="clockRateKnown">
|
|
<type>boolean</type>
|
|
<value>true</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>out_clk</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_sysid</moduleName>
|
|
<slaveName>clk</slaveName>
|
|
<name>subsys_periph_sysid.clk</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_pb_cpu_0</moduleName>
|
|
<slaveName>clk</slaveName>
|
|
<name>subsys_periph_pb_cpu_0.clk</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_led_pio</moduleName>
|
|
<slaveName>clk</slaveName>
|
|
<name>subsys_periph_led_pio.clk</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_dipsw_pio</moduleName>
|
|
<slaveName>clk</slaveName>
|
|
<name>subsys_periph_dipsw_pio.clk</name>
|
|
</clockDomainMember>
|
|
<clockDomainMember>
|
|
<isBridge>false</isBridge>
|
|
<moduleName>subsys_periph_button_pio</moduleName>
|
|
<slaveName>clk</slaveName>
|
|
<name>subsys_periph_button_pio.clk</name>
|
|
</clockDomainMember>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="subsys_periph_periph_rst_in"
|
|
kind="altera_reset_bridge"
|
|
version="19.2.0"
|
|
path="subsys_periph.periph_rst_in"
|
|
className="altera_generic_component">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<parameter name="componentDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
|
|
<value><![CDATA[<componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>in_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>out_reset</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>out_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_reset_bridge</className>
|
|
<version>19.2.0</version>
|
|
<displayName>Reset Bridge Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue>-1</parameterDefaultValue>
|
|
<parameterName>AUTO_CLK_CLOCK_RATE</parameterName>
|
|
<parameterType>java.lang.Long</parameterType>
|
|
<systemInfoArgs>clk</systemInfoArgs>
|
|
<systemInfotype>CLOCK_RATE</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos/>
|
|
</systemInfos>
|
|
</componentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generationInfoDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
|
|
<value><![CDATA[<generationInfoDefinition>
|
|
<hdlLibraryName>periph_rst_in</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>periph_rst_in</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>periph_rst_in</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>periph_rst_in</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>periph_rst_in</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>periph_rst_in</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hlsFile">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="logicalView">
|
|
<type>java.lang.String</type>
|
|
<value>ip/peripheral_subsys/periph_rst_in.ip</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultBoundary">
|
|
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
|
<value><![CDATA[<boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>in_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>out_reset</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>out_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
|
|
<value><![CDATA[<assignmentDefinition>
|
|
<assignmentValueMap/>
|
|
</assignmentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value>altera_reset_bridge_inst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="AUTO_CLK_CLOCK_RATE">
|
|
<type>java.lang.Long</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
<sysinfo_arg>clk</sysinfo_arg>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="in_reset" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>in_reset_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset_n</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="out_reset" kind="reset_source" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedDirectReset">
|
|
<type>java.lang.String</type>
|
|
<value>in_reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedResetSinks">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value>in_reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>NONE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>true</isStart>
|
|
<port>
|
|
<name>out_reset_n</name>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<role>reset_n</role>
|
|
</port>
|
|
</interface>
|
|
</module>
|
|
<module
|
|
name="subsys_periph_sysid"
|
|
kind="altera_avalon_sysid_qsys"
|
|
version="19.1.7"
|
|
path="subsys_periph.sysid"
|
|
className="altera_generic_component">
|
|
<!-- Describes a single module. Module parameters are
|
|
the requested settings for a module instance. -->
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.ID</name>
|
|
<value>-1395275010</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.CMacro.TIMESTAMP</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.compatible</name>
|
|
<value>altr,sysid-1.0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.group</name>
|
|
<value>sysid</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.name</name>
|
|
<value>sysid</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.id</name>
|
|
<value>-1395275010</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.params.timestamp</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.dts.vendor</name>
|
|
<value>altr</value>
|
|
</assignment>
|
|
<parameter name="componentDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
|
|
<value><![CDATA[<componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clock</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>control_slave</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>DYNAMIC</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_avalon_sysid_qsys</className>
|
|
<version>19.1.7</version>
|
|
<displayName>System ID Peripheral Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue>0</parameterDefaultValue>
|
|
<parameterName>TIMESTAMP</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<systemInfotype>GENERATION_ID</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>control_slave</key>
|
|
<value>
|
|
<connectionPointName>control_slave</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
<value><address-map><slave name='control_slave' start='0x0' end='0x8' datawidth='32' /></address-map></value>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>3</value>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
<value>32</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generationInfoDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
|
|
<value><![CDATA[<generationInfoDefinition>
|
|
<hdlLibraryName>sysid</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>sysid</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>sysid</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>sysid</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>sysid</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>sysid</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hlsFile">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="logicalView">
|
|
<type>java.lang.String</type>
|
|
<value>ip/peripheral_subsys/sysid.ip</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultBoundary">
|
|
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
|
<value><![CDATA[<boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clock</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>control_slave</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>DYNAMIC</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
<cmsisInfo>
|
|
<cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
|
|
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
|
|
<peripherals>
|
|
<peripheral>
|
|
<name>altera_avalon_sysid</name><baseAddress>0x00000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ID</name>
|
|
<displayName>System ID</displayName>
|
|
<description>A unique 32-bit value that is based on the contents of the QSys system. The id is similar to a check-sum value; QSys systems with different components, different configuration options, or both, produce different id values.</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>${sysid_id_value}</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>id</name>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMESTAMP</name>
|
|
<displayName>Time stamp</displayName>
|
|
<description>A unique 32-bit value that is based on the system generation time. The value is equivalent to the number of seconds after Jan. 1, 1970.</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>${sysid_timestamp_value}</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>timestamp</name>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device> </cmsisSrcFileContents>
|
|
<addressGroup></addressGroup>
|
|
<cmsisVars>
|
|
<entry>
|
|
<key>sysid_timestamp_value</key>
|
|
<value>0x0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>sysid_id_value</key>
|
|
<value>0xacd5cafe</value>
|
|
</entry>
|
|
</cmsisVars>
|
|
</cmsisInfo>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="moduleAssignmentDefinition">
|
|
<type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
|
|
<value><![CDATA[<assignmentDefinition>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.ID</key>
|
|
<value>-1395275010</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.TIMESTAMP</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.compatible</key>
|
|
<value>altr,sysid-1.0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.group</key>
|
|
<value>sysid</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.name</key>
|
|
<value>sysid</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.id</key>
|
|
<value>-1395275010</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.timestamp</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.vendor</key>
|
|
<value>altr</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignmentDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="svInterfaceDefinition">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="hdlParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
|
|
<value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transformParameters">
|
|
<type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuInfo">
|
|
<type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bspCpu">
|
|
<type>java.lang.Boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="liveModuleName">
|
|
<type>java.lang.String</type>
|
|
<value>altera_avalon_sysid_qsys_inst</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="cpuHashInfo">
|
|
<type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
|
|
<value><![CDATA[<cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition>]]></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="TIMESTAMP">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE_FAMILY">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="AUTO_DEVICE">
|
|
<type>java.lang.String</type>
|
|
<value>A5EB013BB23BE4SCS</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>Agilex 5</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<interface name="clk" kind="clock_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="externallyDriven">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="ptfSchematicName">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>clock</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>clock</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>clk</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="reset" kind="reset_sink" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="synchronousEdges">
|
|
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
|
<value>DEASSERT</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>reset</type>
|
|
<span>0</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>reset_n</role>
|
|
</port>
|
|
</interface>
|
|
<interface name="control_slave" kind="avalon_slave" version="26.1">
|
|
<!-- The connection points exposed by a module instance for the
|
|
particular module parameters. Connection points and their
|
|
parameters are a RESULT of the module parameters. -->
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isFlash</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isMemoryDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isNonVolatileStorage</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<assignment>
|
|
<name>embeddedsw.configuration.isPrintableDevice</name>
|
|
<value>0</value>
|
|
</assignment>
|
|
<parameter name="addressAlignment">
|
|
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
|
|
<value>DYNAMIC</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressGroup">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>8</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="addressUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>WORDS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="alwaysBurstMaxBurst">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedClock">
|
|
<type>java.lang.String</type>
|
|
<value>clk</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="associatedReset">
|
|
<type>java.lang.String</type>
|
|
<value>reset</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bitsPerSymbol">
|
|
<type>int</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgedAddressOffset">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="bridgesToMaster">
|
|
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstOnBurstBoundariesOnly">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="burstcountUnits">
|
|
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
|
<value>WORDS</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="constantBurstBehavior">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="explicitAddressSpan">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="holdTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="interleaveBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isBigEndian">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isFlash">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isMemoryDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="isNonVolatileStorage">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="linewrapBursts">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingReadTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="maximumPendingWriteTransactions">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumReadLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumResponseLatency">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="minimumUninterruptedRunLength">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="prSafe">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="printableDevice">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitStates">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="readWaitTime">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerIncomingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="registerOutgoingSignals">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="setupTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="timingUnits">
|
|
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
|
|
<value>Cycles</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="transparentBridge">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestAllowance">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>false</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="waitrequestTimeout">
|
|
<type>int</type>
|
|
<value>1024</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="wellBehavedWaitrequest">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeLatency">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitStates">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="writeWaitTime">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureGuid">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhGroupId">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterId">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterName">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterVersion">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterData">
|
|
<type>[Ljava.lang.String;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhParameterDataLength">
|
|
<type>[Ljava.lang.Integer;</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMajorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureMinorVersion">
|
|
<type>java.lang.Integer</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureId">
|
|
<type>java.lang.Integer</type>
|
|
<value>35</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="dfhFeatureType">
|
|
<type>java.lang.Integer</type>
|
|
<value>3</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<type>avalon</type>
|
|
<span>8</span>
|
|
<isStart>false</isStart>
|
|
<port>
|
|
<name>readdata</name>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<role>readdata</role>
|
|
</port>
|
|
<port>
|
|
<name>address</name>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<role>address</role>
|
|
</port>
|
|
</interface>
|
|
</module>
|
|
<connection
|
|
name="subsys_hps_emif_hps.io96b0_to_hps/subsys_hps_agilex_hps.io96b0_to_hps"
|
|
kind="conduit"
|
|
version="26.1"
|
|
start="subsys_hps_emif_hps.io96b0_to_hps"
|
|
end="subsys_hps_agilex_hps.io96b0_to_hps">
|
|
<parameter name="endPort">
|
|
<type>com.altera.entityinterfaces.IPort</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="endPortLSB">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="startPort">
|
|
<type>com.altera.entityinterfaces.IPort</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="startPortLSB">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="width">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_hps_emif_hps</startModule>
|
|
<startConnectionPoint>io96b0_to_hps</startConnectionPoint>
|
|
<endModule>subsys_hps_agilex_hps</endModule>
|
|
<endConnectionPoint>io96b0_to_hps</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_pb_cpu_0.m0/subsys_periph_sysid.control_slave"
|
|
kind="avalon"
|
|
version="26.1"
|
|
start="subsys_periph_pb_cpu_0.m0"
|
|
end="subsys_periph_sysid.control_slave">
|
|
<parameter name="arbitrationPriority">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="baseAddress">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0x00010000</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultConnection">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="domainAlias">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="slaveDataWidthSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>MAX_SLAVE_DATA_WIDTH</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="addressMapSysInfo">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressMap</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_MAP</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="addressWidthSysInfo">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
|
|
<value>17</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="cpuInfoIdSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CPU_INFO_ID</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="qsys_mm.piplineType">
|
|
<type>java.lang.String</type>
|
|
<value>PIPELINE_STAGE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableAllPipelines">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.maxAdditionalLatency">
|
|
<type>java.lang.String</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.clockCrossingAdapter">
|
|
<type>java.lang.String</type>
|
|
<value>AUTO</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.fifoDepth">
|
|
<type>java.lang.String</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.insertDefaultSlave">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableInstrumentation">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.interconnectResetSource">
|
|
<type>java.lang.String</type>
|
|
<value>DEFAULT</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.burstAdapterImplementation">
|
|
<type>java.lang.String</type>
|
|
<value>GENERIC_CONVERTER</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.widthAdapterImplementation">
|
|
<type>java.lang.String</type>
|
|
<value>GENERIC_CONVERTER</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableEccProtection">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.interconnectType">
|
|
<type>java.lang.String</type>
|
|
<value>STANDARD</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.syncResets">
|
|
<type>java.lang.String</type>
|
|
<value>TRUE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.optimizeRdFifoSize">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.responseFifoType">
|
|
<type>java.lang.String</type>
|
|
<value>REGISTER_BASED</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableOutOfOrderSupport">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.splitCommandsFor4KBoundary">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_pb_cpu_0</startModule>
|
|
<startConnectionPoint>m0</startConnectionPoint>
|
|
<endModule>subsys_periph_sysid</endModule>
|
|
<endConnectionPoint>control_slave</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_pb_cpu_0.m0/subsys_periph_led_pio.s1"
|
|
kind="avalon"
|
|
version="26.1"
|
|
start="subsys_periph_pb_cpu_0.m0"
|
|
end="subsys_periph_led_pio.s1">
|
|
<parameter name="arbitrationPriority">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="baseAddress">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0x00010080</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultConnection">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="domainAlias">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="slaveDataWidthSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>MAX_SLAVE_DATA_WIDTH</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="addressMapSysInfo">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressMap</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_MAP</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="addressWidthSysInfo">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
|
|
<value>17</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="cpuInfoIdSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CPU_INFO_ID</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="qsys_mm.piplineType">
|
|
<type>java.lang.String</type>
|
|
<value>PIPELINE_STAGE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableAllPipelines">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.maxAdditionalLatency">
|
|
<type>java.lang.String</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.clockCrossingAdapter">
|
|
<type>java.lang.String</type>
|
|
<value>AUTO</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.fifoDepth">
|
|
<type>java.lang.String</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.insertDefaultSlave">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableInstrumentation">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.interconnectResetSource">
|
|
<type>java.lang.String</type>
|
|
<value>DEFAULT</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.burstAdapterImplementation">
|
|
<type>java.lang.String</type>
|
|
<value>GENERIC_CONVERTER</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.widthAdapterImplementation">
|
|
<type>java.lang.String</type>
|
|
<value>GENERIC_CONVERTER</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableEccProtection">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.interconnectType">
|
|
<type>java.lang.String</type>
|
|
<value>STANDARD</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.syncResets">
|
|
<type>java.lang.String</type>
|
|
<value>TRUE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.optimizeRdFifoSize">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.responseFifoType">
|
|
<type>java.lang.String</type>
|
|
<value>REGISTER_BASED</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableOutOfOrderSupport">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.splitCommandsFor4KBoundary">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_pb_cpu_0</startModule>
|
|
<startConnectionPoint>m0</startConnectionPoint>
|
|
<endModule>subsys_periph_led_pio</endModule>
|
|
<endConnectionPoint>s1</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_pb_cpu_0.m0/subsys_periph_dipsw_pio.s1"
|
|
kind="avalon"
|
|
version="26.1"
|
|
start="subsys_periph_pb_cpu_0.m0"
|
|
end="subsys_periph_dipsw_pio.s1">
|
|
<parameter name="arbitrationPriority">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="baseAddress">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0x00010070</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultConnection">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="domainAlias">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="slaveDataWidthSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>MAX_SLAVE_DATA_WIDTH</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="addressMapSysInfo">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressMap</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_MAP</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="addressWidthSysInfo">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
|
|
<value>17</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="cpuInfoIdSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CPU_INFO_ID</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="qsys_mm.piplineType">
|
|
<type>java.lang.String</type>
|
|
<value>PIPELINE_STAGE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableAllPipelines">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.maxAdditionalLatency">
|
|
<type>java.lang.String</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.clockCrossingAdapter">
|
|
<type>java.lang.String</type>
|
|
<value>AUTO</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.fifoDepth">
|
|
<type>java.lang.String</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.insertDefaultSlave">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableInstrumentation">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.interconnectResetSource">
|
|
<type>java.lang.String</type>
|
|
<value>DEFAULT</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.burstAdapterImplementation">
|
|
<type>java.lang.String</type>
|
|
<value>GENERIC_CONVERTER</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.widthAdapterImplementation">
|
|
<type>java.lang.String</type>
|
|
<value>GENERIC_CONVERTER</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableEccProtection">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.interconnectType">
|
|
<type>java.lang.String</type>
|
|
<value>STANDARD</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.syncResets">
|
|
<type>java.lang.String</type>
|
|
<value>TRUE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.optimizeRdFifoSize">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.responseFifoType">
|
|
<type>java.lang.String</type>
|
|
<value>REGISTER_BASED</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableOutOfOrderSupport">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.splitCommandsFor4KBoundary">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_pb_cpu_0</startModule>
|
|
<startConnectionPoint>m0</startConnectionPoint>
|
|
<endModule>subsys_periph_dipsw_pio</endModule>
|
|
<endConnectionPoint>s1</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_pb_cpu_0.m0/subsys_periph_button_pio.s1"
|
|
kind="avalon"
|
|
version="26.1"
|
|
start="subsys_periph_pb_cpu_0.m0"
|
|
end="subsys_periph_button_pio.s1">
|
|
<parameter name="arbitrationPriority">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="baseAddress">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0x00010060</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultConnection">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="domainAlias">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="slaveDataWidthSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>MAX_SLAVE_DATA_WIDTH</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="addressMapSysInfo">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressMap</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_MAP</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="addressWidthSysInfo">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
|
|
<value>17</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="cpuInfoIdSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CPU_INFO_ID</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="qsys_mm.piplineType">
|
|
<type>java.lang.String</type>
|
|
<value>PIPELINE_STAGE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableAllPipelines">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.maxAdditionalLatency">
|
|
<type>java.lang.String</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.clockCrossingAdapter">
|
|
<type>java.lang.String</type>
|
|
<value>AUTO</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.fifoDepth">
|
|
<type>java.lang.String</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.insertDefaultSlave">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableInstrumentation">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.interconnectResetSource">
|
|
<type>java.lang.String</type>
|
|
<value>DEFAULT</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.burstAdapterImplementation">
|
|
<type>java.lang.String</type>
|
|
<value>GENERIC_CONVERTER</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.widthAdapterImplementation">
|
|
<type>java.lang.String</type>
|
|
<value>GENERIC_CONVERTER</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableEccProtection">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.interconnectType">
|
|
<type>java.lang.String</type>
|
|
<value>STANDARD</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.syncResets">
|
|
<type>java.lang.String</type>
|
|
<value>TRUE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.optimizeRdFifoSize">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.responseFifoType">
|
|
<type>java.lang.String</type>
|
|
<value>REGISTER_BASED</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableOutOfOrderSupport">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.splitCommandsFor4KBoundary">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_pb_cpu_0</startModule>
|
|
<startConnectionPoint>m0</startConnectionPoint>
|
|
<endModule>subsys_periph_button_pio</endModule>
|
|
<endConnectionPoint>s1</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_periph_clk.out_clk/subsys_periph_sysid.clk"
|
|
kind="clock"
|
|
version="26.1"
|
|
start="subsys_periph_periph_clk.out_clk"
|
|
end="subsys_periph_sysid.clk">
|
|
<parameter name="clockRateSysInfo">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_periph_clk</startModule>
|
|
<startConnectionPoint>out_clk</startConnectionPoint>
|
|
<endModule>subsys_periph_sysid</endModule>
|
|
<endConnectionPoint>clk</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_periph_clk.out_clk/subsys_periph_pb_cpu_0.clk"
|
|
kind="clock"
|
|
version="26.1"
|
|
start="subsys_periph_periph_clk.out_clk"
|
|
end="subsys_periph_pb_cpu_0.clk">
|
|
<parameter name="clockRateSysInfo">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_periph_clk</startModule>
|
|
<startConnectionPoint>out_clk</startConnectionPoint>
|
|
<endModule>subsys_periph_pb_cpu_0</endModule>
|
|
<endConnectionPoint>clk</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_periph_clk.out_clk/subsys_periph_led_pio.clk"
|
|
kind="clock"
|
|
version="26.1"
|
|
start="subsys_periph_periph_clk.out_clk"
|
|
end="subsys_periph_led_pio.clk">
|
|
<parameter name="clockRateSysInfo">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_periph_clk</startModule>
|
|
<startConnectionPoint>out_clk</startConnectionPoint>
|
|
<endModule>subsys_periph_led_pio</endModule>
|
|
<endConnectionPoint>clk</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_periph_clk.out_clk/subsys_periph_dipsw_pio.clk"
|
|
kind="clock"
|
|
version="26.1"
|
|
start="subsys_periph_periph_clk.out_clk"
|
|
end="subsys_periph_dipsw_pio.clk">
|
|
<parameter name="clockRateSysInfo">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_periph_clk</startModule>
|
|
<startConnectionPoint>out_clk</startConnectionPoint>
|
|
<endModule>subsys_periph_dipsw_pio</endModule>
|
|
<endConnectionPoint>clk</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_periph_clk.out_clk/subsys_periph_button_pio.clk"
|
|
kind="clock"
|
|
version="26.1"
|
|
start="subsys_periph_periph_clk.out_clk"
|
|
end="subsys_periph_button_pio.clk">
|
|
<parameter name="clockRateSysInfo">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_periph_clk</startModule>
|
|
<startConnectionPoint>out_clk</startConnectionPoint>
|
|
<endModule>subsys_periph_button_pio</endModule>
|
|
<endConnectionPoint>clk</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_periph_rst_in.out_reset/subsys_periph_sysid.reset"
|
|
kind="reset"
|
|
version="26.1"
|
|
start="subsys_periph_periph_rst_in.out_reset"
|
|
end="subsys_periph_sysid.reset">
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_periph_rst_in</startModule>
|
|
<startConnectionPoint>out_reset</startConnectionPoint>
|
|
<endModule>subsys_periph_sysid</endModule>
|
|
<endConnectionPoint>reset</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_periph_rst_in.out_reset/subsys_periph_led_pio.reset"
|
|
kind="reset"
|
|
version="26.1"
|
|
start="subsys_periph_periph_rst_in.out_reset"
|
|
end="subsys_periph_led_pio.reset">
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_periph_rst_in</startModule>
|
|
<startConnectionPoint>out_reset</startConnectionPoint>
|
|
<endModule>subsys_periph_led_pio</endModule>
|
|
<endConnectionPoint>reset</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_periph_rst_in.out_reset/subsys_periph_dipsw_pio.reset"
|
|
kind="reset"
|
|
version="26.1"
|
|
start="subsys_periph_periph_rst_in.out_reset"
|
|
end="subsys_periph_dipsw_pio.reset">
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_periph_rst_in</startModule>
|
|
<startConnectionPoint>out_reset</startConnectionPoint>
|
|
<endModule>subsys_periph_dipsw_pio</endModule>
|
|
<endConnectionPoint>reset</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_periph_rst_in.out_reset/subsys_periph_button_pio.reset"
|
|
kind="reset"
|
|
version="26.1"
|
|
start="subsys_periph_periph_rst_in.out_reset"
|
|
end="subsys_periph_button_pio.reset">
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_periph_rst_in</startModule>
|
|
<startConnectionPoint>out_reset</startConnectionPoint>
|
|
<endModule>subsys_periph_button_pio</endModule>
|
|
<endConnectionPoint>reset</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_periph_periph_rst_in.out_reset/subsys_periph_pb_cpu_0.reset"
|
|
kind="reset"
|
|
version="26.1"
|
|
start="subsys_periph_periph_rst_in.out_reset"
|
|
end="subsys_periph_pb_cpu_0.reset">
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_periph_periph_rst_in</startModule>
|
|
<startConnectionPoint>out_reset</startConnectionPoint>
|
|
<endModule>subsys_periph_pb_cpu_0</endModule>
|
|
<endConnectionPoint>reset</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_hps_agilex_hps.lwhps2fpga/subsys_periph_pb_cpu_0.s0"
|
|
kind="avalon"
|
|
version="26.1"
|
|
start="subsys_hps_agilex_hps.lwhps2fpga"
|
|
end="subsys_periph_pb_cpu_0.s0">
|
|
<parameter name="arbitrationPriority">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="baseAddress">
|
|
<type>java.math.BigInteger</type>
|
|
<value>0x0000</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="defaultConnection">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="domainAlias">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="slaveDataWidthSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>-1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>MAX_SLAVE_DATA_WIDTH</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="addressMapSysInfo">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressMap</type>
|
|
<value><![CDATA[<address-map><slave name='subsys_periph.sysid.control_slave' start='0x10000' end='0x10008' datawidth='32' /><slave name='subsys_periph.button_pio.s1' start='0x10060' end='0x10070' datawidth='32' /><slave name='subsys_periph.dipsw_pio.s1' start='0x10070' end='0x10080' datawidth='32' /><slave name='subsys_periph.led_pio.s1' start='0x10080' end='0x10090' datawidth='32' /></address-map>]]></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_MAP</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="addressWidthSysInfo">
|
|
<type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
|
|
<value>17</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="cpuInfoIdSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CPU_INFO_ID</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="qsys_mm.piplineType">
|
|
<type>java.lang.String</type>
|
|
<value>PIPELINE_STAGE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableAllPipelines">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.maxAdditionalLatency">
|
|
<type>java.lang.String</type>
|
|
<value>4</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.clockCrossingAdapter">
|
|
<type>java.lang.String</type>
|
|
<value>AUTO</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.fifoDepth">
|
|
<type>java.lang.String</type>
|
|
<value>8</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.insertDefaultSlave">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableInstrumentation">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.interconnectResetSource">
|
|
<type>java.lang.String</type>
|
|
<value>DEFAULT</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.burstAdapterImplementation">
|
|
<type>java.lang.String</type>
|
|
<value>PER_BURST_TYPE_CONVERTER</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.widthAdapterImplementation">
|
|
<type>java.lang.String</type>
|
|
<value>GENERIC_CONVERTER</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableEccProtection">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.interconnectType">
|
|
<type>java.lang.String</type>
|
|
<value>STANDARD</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.syncResets">
|
|
<type>java.lang.String</type>
|
|
<value>TRUE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.optimizeRdFifoSize">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.responseFifoType">
|
|
<type>java.lang.String</type>
|
|
<value>REGISTER_BASED</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.enableOutOfOrderSupport">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="qsys_mm.splitCommandsFor4KBoundary">
|
|
<type>java.lang.String</type>
|
|
<value>FALSE</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_hps_agilex_hps</startModule>
|
|
<startConnectionPoint>lwhps2fpga</startConnectionPoint>
|
|
<endModule>subsys_periph_pb_cpu_0</endModule>
|
|
<endConnectionPoint>s0</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="clk_100.out_clk/subsys_periph_periph_clk.in_clk"
|
|
kind="clock"
|
|
version="26.1"
|
|
start="clk_100.out_clk"
|
|
end="subsys_periph_periph_clk.in_clk">
|
|
<parameter name="clockRateSysInfo">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>clk_100</startModule>
|
|
<startConnectionPoint>out_clk</startConnectionPoint>
|
|
<endModule>subsys_periph_periph_clk</endModule>
|
|
<endConnectionPoint>in_clk</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="clk_100.out_clk/subsys_hps_agilex_hps.f2sdram_axi_clock"
|
|
kind="clock"
|
|
version="26.1"
|
|
start="clk_100.out_clk"
|
|
end="subsys_hps_agilex_hps.f2sdram_axi_clock">
|
|
<parameter name="clockRateSysInfo">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>clk_100</startModule>
|
|
<startConnectionPoint>out_clk</startConnectionPoint>
|
|
<endModule>subsys_hps_agilex_hps</endModule>
|
|
<endConnectionPoint>f2sdram_axi_clock</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="clk_100.out_clk/subsys_hps_agilex_hps.hps2fpga_axi_clock"
|
|
kind="clock"
|
|
version="26.1"
|
|
start="clk_100.out_clk"
|
|
end="subsys_hps_agilex_hps.hps2fpga_axi_clock">
|
|
<parameter name="clockRateSysInfo">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>clk_100</startModule>
|
|
<startConnectionPoint>out_clk</startConnectionPoint>
|
|
<endModule>subsys_hps_agilex_hps</endModule>
|
|
<endConnectionPoint>hps2fpga_axi_clock</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="clk_100.out_clk/subsys_hps_agilex_hps.lwhps2fpga_axi_clock"
|
|
kind="clock"
|
|
version="26.1"
|
|
start="clk_100.out_clk"
|
|
end="subsys_hps_agilex_hps.lwhps2fpga_axi_clock">
|
|
<parameter name="clockRateSysInfo">
|
|
<type>java.lang.Long</type>
|
|
<value>100000000</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>1</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>clk_100</startModule>
|
|
<startConnectionPoint>out_clk</startConnectionPoint>
|
|
<endModule>subsys_hps_agilex_hps</endModule>
|
|
<endConnectionPoint>lwhps2fpga_axi_clock</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_hps_agilex_hps.fpga2hps_interrupt_irq0/subsys_periph_button_pio.irq"
|
|
kind="interrupt"
|
|
version="26.1"
|
|
start="subsys_hps_agilex_hps.fpga2hps_interrupt_irq0"
|
|
end="subsys_periph_button_pio.irq">
|
|
<parameter name="irqNumber">
|
|
<type>int</type>
|
|
<value>1</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="interruptsUsedSysInfo">
|
|
<type>java.math.BigInteger</type>
|
|
<value>3</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>INTERRUPTS_USED</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_hps_agilex_hps</startModule>
|
|
<startConnectionPoint>fpga2hps_interrupt_irq0</startConnectionPoint>
|
|
<endModule>subsys_periph_button_pio</endModule>
|
|
<endConnectionPoint>irq</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="subsys_hps_agilex_hps.fpga2hps_interrupt_irq0/subsys_periph_dipsw_pio.irq"
|
|
kind="interrupt"
|
|
version="26.1"
|
|
start="subsys_hps_agilex_hps.fpga2hps_interrupt_irq0"
|
|
end="subsys_periph_dipsw_pio.irq">
|
|
<parameter name="irqNumber">
|
|
<type>int</type>
|
|
<value>0</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="interruptsUsedSysInfo">
|
|
<type>java.math.BigInteger</type>
|
|
<value>3</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>INTERRUPTS_USED</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>subsys_hps_agilex_hps</startModule>
|
|
<startConnectionPoint>fpga2hps_interrupt_irq0</startConnectionPoint>
|
|
<endModule>subsys_periph_dipsw_pio</endModule>
|
|
<endConnectionPoint>irq</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="rst_in.out_reset/subsys_hps_agilex_hps.f2sdram_axi_reset"
|
|
kind="reset"
|
|
version="26.1"
|
|
start="rst_in.out_reset"
|
|
end="subsys_hps_agilex_hps.f2sdram_axi_reset">
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>rst_in</startModule>
|
|
<startConnectionPoint>out_reset</startConnectionPoint>
|
|
<endModule>subsys_hps_agilex_hps</endModule>
|
|
<endConnectionPoint>f2sdram_axi_reset</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="rst_in.out_reset/subsys_hps_agilex_hps.hps2fpga_axi_reset"
|
|
kind="reset"
|
|
version="26.1"
|
|
start="rst_in.out_reset"
|
|
end="subsys_hps_agilex_hps.hps2fpga_axi_reset">
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>rst_in</startModule>
|
|
<startConnectionPoint>out_reset</startConnectionPoint>
|
|
<endModule>subsys_hps_agilex_hps</endModule>
|
|
<endConnectionPoint>hps2fpga_axi_reset</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="rst_in.out_reset/subsys_hps_agilex_hps.lwhps2fpga_axi_reset"
|
|
kind="reset"
|
|
version="26.1"
|
|
start="rst_in.out_reset"
|
|
end="subsys_hps_agilex_hps.lwhps2fpga_axi_reset">
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>rst_in</startModule>
|
|
<startConnectionPoint>out_reset</startConnectionPoint>
|
|
<endModule>subsys_hps_agilex_hps</endModule>
|
|
<endConnectionPoint>lwhps2fpga_axi_reset</endConnectionPoint>
|
|
</connection>
|
|
<connection
|
|
name="rst_in.out_reset/subsys_periph_periph_rst_in.in_reset"
|
|
kind="reset"
|
|
version="26.1"
|
|
start="rst_in.out_reset"
|
|
end="subsys_periph_periph_rst_in.in_reset">
|
|
<parameter name="resetDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockDomainSysInfo">
|
|
<type>java.lang.Integer</type>
|
|
<value>4</value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="clockResetSysInfo">
|
|
<type>java.lang.String</type>
|
|
<value></value>
|
|
<derived>true</derived>
|
|
<enabled>true</enabled>
|
|
<visible>false</visible>
|
|
<valid>true</valid>
|
|
<sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
|
|
</parameter>
|
|
<parameter name="deviceFamily">
|
|
<type>java.lang.String</type>
|
|
<value>UNKNOWN</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<parameter name="generateLegacySim">
|
|
<type>boolean</type>
|
|
<value>false</value>
|
|
<derived>false</derived>
|
|
<enabled>true</enabled>
|
|
<visible>true</visible>
|
|
<valid>true</valid>
|
|
</parameter>
|
|
<startModule>rst_in</startModule>
|
|
<startConnectionPoint>out_reset</startConnectionPoint>
|
|
<endModule>subsys_periph_periph_rst_in</endModule>
|
|
<endConnectionPoint>in_reset</endConnectionPoint>
|
|
</connection>
|
|
<plugin>
|
|
<instanceCount>12</instanceCount>
|
|
<name>altera_generic_component</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype></subtype>
|
|
<displayName>Generic Component</displayName>
|
|
<version>1.0</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>16</instanceCount>
|
|
<name>clock_sink</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
|
<displayName>Clock Input</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>2</instanceCount>
|
|
<name>clock_source</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
|
<displayName>Clock Output</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>14</instanceCount>
|
|
<name>reset_sink</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
|
<displayName>Reset Input</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>5</instanceCount>
|
|
<name>reset_source</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
|
<displayName>Reset Output</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>21</instanceCount>
|
|
<name>conduit_end</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
|
<displayName>Conduit</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>1</instanceCount>
|
|
<name>hps_subsys</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
|
<displayName>hps_subsys</displayName>
|
|
<version>1.0</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>4</instanceCount>
|
|
<name>altera_axi4_master</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
|
<displayName>AXI4 Manager</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>4</instanceCount>
|
|
<name>interrupt_receiver</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
|
<displayName>Interrupt Receiver</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>2</instanceCount>
|
|
<name>altera_axi4_slave</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
|
<displayName>AXI4 Subordinate</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>1</instanceCount>
|
|
<name>peripheral_subsys</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
|
<displayName>peripheral_subsys</displayName>
|
|
<version>1.0</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>4</instanceCount>
|
|
<name>interrupt_sender</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
|
<displayName>Interrupt Sender</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>6</instanceCount>
|
|
<name>avalon_slave</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
|
<displayName>Avalon Memory Mapped Agent</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>1</instanceCount>
|
|
<name>avalon_master</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
|
<displayName>Avalon Memory Mapped Host</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>1</instanceCount>
|
|
<name>conduit</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
|
<displayName>Conduit Connection</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>5</instanceCount>
|
|
<name>avalon</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
|
<displayName>Avalon Memory Mapped Connection</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>9</instanceCount>
|
|
<name>clock</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
|
<displayName>Clock Connection</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>9</instanceCount>
|
|
<name>reset</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
|
<displayName>Reset Connection</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<plugin>
|
|
<instanceCount>2</instanceCount>
|
|
<name>interrupt</name>
|
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
|
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
|
<displayName>Interrupt Connection</displayName>
|
|
<version>26.1</version>
|
|
</plugin>
|
|
<reportVersion>26.1 110</reportVersion>
|
|
<uniqueIdentifier></uniqueIdentifier>
|
|
</EnsembleReport>
|