java.lang.Integer 0 false true false true GENERATION_ID java.lang.String false true false true UNIQUE_ID java.lang.String Agilex 5 false true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS false true false true DEVICE java.lang.String 4 false true false true DEVICE_SPEEDGRADE java.lang.String default false true false true BOARD java.lang.Long -1 false true false true CLOCK_RATE clk_100 java.lang.Integer -1 false true false true CLOCK_DOMAIN clk_100 java.lang.Integer -1 false true false true RESET_DOMAIN clk_100 com.altera.entityinterfaces.moduleext.AddressMap false true false true ADDRESS_MAP subsys_hps_hps2fpga com.altera.entityinterfaces.moduleext.AddressWidthType -1 false true false true ADDRESS_WIDTH subsys_hps_hps2fpga java.math.BigInteger -1 false true false true INTERRUPTS_USED f2h_irq1_in java.lang.String false true false true CPU_INFO_ID f2sdram java.lang.Long -1 false true false true CLOCK_RATE emif_hps_emif_ref_clk_0 java.lang.Integer -1 false true false true CLOCK_DOMAIN emif_hps_emif_ref_clk_0 java.lang.Integer -1 false true false true RESET_DOMAIN emif_hps_emif_ref_clk_0 java.lang.String Agilex 5 false true false true DEVICE_FAMILY boolean false false true true true com.altera.qsys.blackboxmodule.definitions.ComponentDefinition in_clk clock false in_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName out_clk clock true out_clk clk Output 1 0 STD_LOGIC 0 associatedDirectClock in_clk clockRate 100000000 clockRateKnown true externallyDriven false ptfSchematicName altera_clock_bridge 19.2.0 Clock Bridge IP 0 DERIVED_CLOCK_RATE java.lang.Long in_clk CLOCK_RATE in_clk in_clk CLOCK_RATE 0 out_clk out_clk CLOCK_RATE 100000000 ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition clk_100 clk_100 clk_100 QUARTUS_SYNTH clk_100 clk_100 SIM_VERILOG clk_100 clk_100 SIM_VHDL clk_100 clk_100 CDC clk_100 clk_100 CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/qsys_top/clk_100.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition in_clk clock false in_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName out_clk clock true out_clk clk Output 1 0 STD_LOGIC 0 associatedDirectClock in_clk clockRate 100000000 clockRateKnown true externallyDriven false ptfSchematicName ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition ]]> false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList ]]> false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition false true false true java.lang.Boolean false false true false true java.lang.String altera_clock_bridge_inst false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.Long 0 true true false true CLOCK_RATE in_clk java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean false true true false true java.lang.Long 0 true true false true clock 0 false in_clk Input 1 clk java.lang.String in_clk false true true true long 100000000 false true false true boolean true false true false true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock 0 true out_clk Output 1 clk true subsys_periph_periph_clk in_clk subsys_periph_periph_clk.in_clk false subsys_periph_sysid clk subsys_periph_sysid.clk false subsys_periph_pb_cpu_0 clk subsys_periph_pb_cpu_0.clk false subsys_periph_led_pio clk subsys_periph_led_pio.clk false subsys_periph_dipsw_pio clk subsys_periph_dipsw_pio.clk false subsys_periph_button_pio clk subsys_periph_button_pio.clk false subsys_hps_agilex_hps f2sdram_axi_clock subsys_hps_agilex_hps.f2sdram_axi_clock false subsys_hps_agilex_hps hps2fpga_axi_clock subsys_hps_agilex_hps.hps2fpga_axi_clock false subsys_hps_agilex_hps lwhps2fpga_axi_clock subsys_hps_agilex_hps.lwhps2fpga_axi_clock com.altera.qsys.blackboxmodule.definitions.ComponentDefinition in_reset reset false in_reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock synchronousEdges NONE out_reset reset true out_reset_n reset_n Output 1 0 STD_LOGIC 0 associatedClock associatedDirectReset in_reset associatedResetSinks in_reset synchronousEdges NONE altera_reset_bridge 19.2.0 Reset Bridge IP -1 AUTO_CLK_CLOCK_RATE java.lang.Long clk CLOCK_RATE ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition rst_in rst_in rst_in QUARTUS_SYNTH rst_in rst_in SIM_VERILOG rst_in rst_in SIM_VHDL rst_in rst_in CDC rst_in rst_in CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/qsys_top/rst_in.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition in_reset reset false in_reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock synchronousEdges NONE out_reset reset true out_reset_n reset_n Output 1 0 STD_LOGIC 0 associatedClock associatedDirectReset in_reset associatedResetSinks in_reset synchronousEdges NONE ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition ]]> false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList ]]> false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition false true false true java.lang.Boolean false false true false true java.lang.String altera_reset_bridge_inst false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.Long -1 true true false true CLOCK_RATE clk java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true java.lang.String false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false in_reset_n Input 1 reset_n java.lang.String false true true true java.lang.String in_reset false true true true [Ljava.lang.String; in_reset false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 true out_reset_n Output 1 reset_n com.altera.qsys.blackboxmodule.definitions.ComponentDefinition ninit_done conduit false ninit_done ninit_done Output 1 0 STD_LOGIC 0 associatedClock associatedReset prSafe false intel_user_rst_clkgate 1.0.1 Reset Release IP DEVICE_FAMILY java.lang.String DEVICE_FAMILY ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition user_rst_clkgate_0 user_rst_clkgate_0 user_rst_clkgate_0 QUARTUS_SYNTH user_rst_clkgate_0 user_rst_clkgate_0 SIM_VERILOG user_rst_clkgate_0 user_rst_clkgate_0 SIM_VHDL user_rst_clkgate_0 user_rst_clkgate_0 CDC user_rst_clkgate_0 user_rst_clkgate_0 CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/qsys_top/user_rst_clkgate_0.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition ninit_done conduit false ninit_done ninit_done Output 1 0 STD_LOGIC 0 associatedClock associatedReset prSafe false ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition ]]> false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList ]]> false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition false true false true java.lang.Boolean false false true false true java.lang.String intel_user_rst_clkgate_inst false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false ninit_done Output 1 ninit_done java.lang.Integer 0 false true false true GENERATION_ID java.lang.String qsys_top_subsys_hps false true false true UNIQUE_ID java.lang.String Agilex 5 false true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS false true false true DEVICE java.lang.String 4 false true false true DEVICE_SPEEDGRADE java.lang.String default false true false true BOARD java.lang.Long 100000000 false true false true CLOCK_RATE hps2fpga_clk java.lang.Integer 1 false true false true CLOCK_DOMAIN hps2fpga_clk java.lang.Integer 1 false true false true RESET_DOMAIN hps2fpga_clk com.altera.entityinterfaces.moduleext.AddressMap false true false true ADDRESS_MAP hps2fpga com.altera.entityinterfaces.moduleext.AddressWidthType -1 false true false true ADDRESS_WIDTH hps2fpga java.lang.Long 100000000 false true false true CLOCK_RATE lwhps2fpga_clk java.lang.Integer 1 false true false true CLOCK_DOMAIN lwhps2fpga_clk java.lang.Integer 1 false true false true RESET_DOMAIN lwhps2fpga_clk com.altera.entityinterfaces.moduleext.AddressMap ]]> false true false true ADDRESS_MAP lwhps2fpga com.altera.entityinterfaces.moduleext.AddressWidthType 17 false true false true ADDRESS_WIDTH lwhps2fpga java.math.BigInteger -1 false true false true INTERRUPTS_USED f2h_irq1_in java.math.BigInteger 3 false true false true INTERRUPTS_USED f2h_irq0_in java.lang.Long 100000000 false true false true CLOCK_RATE f2sdram_clk java.lang.Integer 1 false true false true CLOCK_DOMAIN f2sdram_clk java.lang.Integer 1 false true false true RESET_DOMAIN f2sdram_clk java.lang.String false true false true CPU_INFO_ID f2sdram java.lang.Long -1 false true false true CLOCK_RATE emif_hps_emif_ref_clk java.lang.Integer 2 false true false true CLOCK_DOMAIN emif_hps_emif_ref_clk java.lang.Integer 2 false true false true RESET_DOMAIN emif_hps_emif_ref_clk java.lang.String Agilex 5 false true false true DEVICE_FAMILY boolean false false true true true java.lang.String false true true true java.lang.String false true true true [Ljava.lang.String; none false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 true h2f_reset_reset Output 1 reset boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 100000000 true true false true clock 0 false hps2fpga_clk_clk Input 1 clk java.lang.String false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false hps2fpga_rst_reset Input 1 reset java.lang.String hps2fpga_clk false true true true java.lang.String hps2fpga_rst false true true true boolean false false true true true boolean true false true false true boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true false true boolean false false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true boolean true false true true true boolean true false true true true boolean true false true true true java.lang.String UNKNOWN false true true true boolean false false true true true axi4 274877906944 true hps2fpga_awid Output 4 awid hps2fpga_awaddr Output 38 awaddr hps2fpga_awlen Output 8 awlen hps2fpga_awsize Output 3 awsize hps2fpga_awburst Output 2 awburst hps2fpga_awlock Output 1 awlock hps2fpga_awcache Output 4 awcache hps2fpga_awprot Output 3 awprot hps2fpga_awvalid Output 1 awvalid hps2fpga_awready Input 1 awready hps2fpga_wdata Output 128 wdata hps2fpga_wstrb Output 16 wstrb hps2fpga_wlast Output 1 wlast hps2fpga_wvalid Output 1 wvalid hps2fpga_wready Input 1 wready hps2fpga_bid Input 4 bid hps2fpga_bresp Input 2 bresp hps2fpga_bvalid Input 1 bvalid hps2fpga_bready Output 1 bready hps2fpga_arid Output 4 arid hps2fpga_araddr Output 38 araddr hps2fpga_arlen Output 8 arlen hps2fpga_arsize Output 3 arsize hps2fpga_arburst Output 2 arburst hps2fpga_arlock Output 1 arlock hps2fpga_arcache Output 4 arcache hps2fpga_arprot Output 3 arprot hps2fpga_arvalid Output 1 arvalid hps2fpga_arready Input 1 arready hps2fpga_rid Input 4 rid hps2fpga_rdata Input 128 rdata hps2fpga_rresp Input 2 rresp hps2fpga_rlast Input 1 rlast hps2fpga_rvalid Input 1 rvalid hps2fpga_rready Output 1 rready boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 100000000 true true false true clock 0 false lwhps2fpga_clk_clk Input 1 clk java.lang.String false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false lwhps2fpga_rst_reset Input 1 reset java.lang.String lwhps2fpga_clk false true true true java.lang.String lwhps2fpga_rst false true true true boolean false false true true true boolean true false true false true boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true false true boolean false false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true boolean true false true true true boolean true false true true true boolean true false true true true java.lang.String UNKNOWN false true true true boolean false false true true true axi4 536870912 true lwhps2fpga_awid Output 4 awid lwhps2fpga_awaddr Output 29 awaddr lwhps2fpga_awlen Output 8 awlen lwhps2fpga_awsize Output 3 awsize lwhps2fpga_awburst Output 2 awburst lwhps2fpga_awlock Output 1 awlock lwhps2fpga_awcache Output 4 awcache lwhps2fpga_awprot Output 3 awprot lwhps2fpga_awvalid Output 1 awvalid lwhps2fpga_awready Input 1 awready lwhps2fpga_wdata Output 32 wdata lwhps2fpga_wstrb Output 4 wstrb lwhps2fpga_wlast Output 1 wlast lwhps2fpga_wvalid Output 1 wvalid lwhps2fpga_wready Input 1 wready lwhps2fpga_bid Input 4 bid lwhps2fpga_bresp Input 2 bresp lwhps2fpga_bvalid Input 1 bvalid lwhps2fpga_bready Output 1 bready lwhps2fpga_arid Output 4 arid lwhps2fpga_araddr Output 29 araddr lwhps2fpga_arlen Output 8 arlen lwhps2fpga_arsize Output 3 arsize lwhps2fpga_arburst Output 2 arburst lwhps2fpga_arlock Output 1 arlock lwhps2fpga_arcache Output 4 arcache lwhps2fpga_arprot Output 3 arprot lwhps2fpga_arvalid Output 1 arvalid lwhps2fpga_arready Input 1 arready lwhps2fpga_rid Input 4 rid lwhps2fpga_rdata Input 32 rdata lwhps2fpga_rresp Input 2 rresp lwhps2fpga_rlast Input 1 rlast lwhps2fpga_rvalid Input 1 rvalid lwhps2fpga_rready Output 1 rready true subsys_periph_pb_cpu_0 s0 subsys_periph_pb_cpu_0.s0 0 131072 false subsys_periph_sysid control_slave subsys_periph_sysid.control_slave 65536 8 false subsys_periph_led_pio s1 subsys_periph_led_pio.s1 65664 16 false subsys_periph_dipsw_pio s1 subsys_periph_dipsw_pio.s1 65648 16 false subsys_periph_button_pio s1 subsys_periph_button_pio.s1 65632 16 java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false h2f_warm_reset_handshake_reset_req Output 1 reset_req h2f_warm_reset_handshake_reset_ack Input 1 reset_ack java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false hps_io_hps_osc_clk Input 1 hps_osc_clk hps_io_sdmmc_data0 Bidir 1 sdmmc_data0 hps_io_sdmmc_data1 Bidir 1 sdmmc_data1 hps_io_sdmmc_cclk Output 1 sdmmc_cclk hps_io_sdmmc_data2 Bidir 1 sdmmc_data2 hps_io_sdmmc_data3 Bidir 1 sdmmc_data3 hps_io_sdmmc_cmd Bidir 1 sdmmc_cmd hps_io_usb0_clk Input 1 usb0_clk hps_io_usb0_stp Output 1 usb0_stp hps_io_usb0_dir Input 1 usb0_dir hps_io_usb0_data0 Bidir 1 usb0_data0 hps_io_usb0_data1 Bidir 1 usb0_data1 hps_io_usb0_nxt Input 1 usb0_nxt hps_io_usb0_data2 Bidir 1 usb0_data2 hps_io_usb0_data3 Bidir 1 usb0_data3 hps_io_usb0_data4 Bidir 1 usb0_data4 hps_io_usb0_data5 Bidir 1 usb0_data5 hps_io_usb0_data6 Bidir 1 usb0_data6 hps_io_usb0_data7 Bidir 1 usb0_data7 hps_io_emac0_tx_clk Output 1 emac0_tx_clk hps_io_emac0_tx_ctl Output 1 emac0_tx_ctl hps_io_emac0_rx_clk Input 1 emac0_rx_clk hps_io_emac0_rx_ctl Input 1 emac0_rx_ctl hps_io_emac0_txd0 Output 1 emac0_txd0 hps_io_emac0_txd1 Output 1 emac0_txd1 hps_io_emac0_rxd0 Input 1 emac0_rxd0 hps_io_emac0_rxd1 Input 1 emac0_rxd1 hps_io_emac0_txd2 Output 1 emac0_txd2 hps_io_emac0_txd3 Output 1 emac0_txd3 hps_io_emac0_rxd2 Input 1 emac0_rxd2 hps_io_emac0_rxd3 Input 1 emac0_rxd3 hps_io_mdio0_mdio Bidir 1 mdio0_mdio hps_io_mdio0_mdc Output 1 mdio0_mdc hps_io_uart1_tx Output 1 uart1_tx hps_io_uart1_rx Input 1 uart1_rx hps_io_i2c1_sda Bidir 1 i2c1_sda hps_io_i2c1_scl Bidir 1 i2c1_scl hps_io_gpio28 Bidir 1 gpio28 hps_io_gpio34 Bidir 1 gpio34 hps_io_gpio40 Bidir 1 gpio40 hps_io_gpio41 Bidir 1 gpio41 com.altera.entityinterfaces.IConnectionPoint false true false true java.lang.String false true false true java.lang.String false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt 0 true f2h_irq1_in_irq Input 32 irq com.altera.entityinterfaces.IConnectionPoint false true false true java.lang.String false true false true java.lang.String false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt 0 true f2h_irq0_in_irq Input 32 irq false subsys_periph_button_pio irq subsys_periph_button_pio.irq 1 false subsys_periph_dipsw_pio irq subsys_periph_dipsw_pio.irq 0 boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 100000000 true true false true clock 0 false f2sdram_clk_clk Input 1 clk java.lang.String false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false f2sdram_rst_reset Input 1 reset java.lang.String f2sdram_clk false true true true java.lang.String f2sdram_rst false true true true boolean false false true true true boolean true false true false true boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true false true boolean false false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.math.BigInteger 0 false true true true java.lang.Integer 0 false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true java.lang.Integer 35 false true true true java.lang.Integer 3 false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4294967296 true true false true axi4 4294967296 false f2sdram_araddr Input 32 araddr f2sdram_arburst Input 2 arburst f2sdram_arcache Input 4 arcache f2sdram_arid Input 5 arid f2sdram_arlen Input 8 arlen f2sdram_arlock Input 1 arlock f2sdram_arprot Input 3 arprot f2sdram_arqos Input 4 arqos f2sdram_arready Output 1 arready f2sdram_arsize Input 3 arsize f2sdram_arvalid Input 1 arvalid f2sdram_awaddr Input 32 awaddr f2sdram_awburst Input 2 awburst f2sdram_awcache Input 4 awcache f2sdram_awid Input 5 awid f2sdram_awlen Input 8 awlen f2sdram_awlock Input 1 awlock f2sdram_awprot Input 3 awprot f2sdram_awqos Input 4 awqos f2sdram_awready Output 1 awready f2sdram_awsize Input 3 awsize f2sdram_awvalid Input 1 awvalid f2sdram_bid Output 5 bid f2sdram_bready Input 1 bready f2sdram_bresp Output 2 bresp f2sdram_bvalid Output 1 bvalid f2sdram_rdata Output 256 rdata f2sdram_rid Output 5 rid f2sdram_rlast Output 1 rlast f2sdram_rready Input 1 rready f2sdram_rresp Output 2 rresp f2sdram_rvalid Output 1 rvalid f2sdram_wdata Input 256 wdata f2sdram_wlast Input 1 wlast f2sdram_wready Output 1 wready f2sdram_wstrb Input 32 wstrb f2sdram_wvalid Input 1 wvalid f2sdram_aruser Input 8 aruser f2sdram_awuser Input 8 awuser f2sdram_wuser Input 8 wuser f2sdram_buser Output 8 buser f2sdram_arregion Input 4 arregion f2sdram_ruser Output 8 ruser f2sdram_awregion Input 4 awregion java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false emif_hps_emif_mem_0_mem_cs Output 1 mem_cs emif_hps_emif_mem_0_mem_ca Output 6 mem_ca emif_hps_emif_mem_0_mem_cke Output 1 mem_cke emif_hps_emif_mem_0_mem_dq Bidir 32 mem_dq emif_hps_emif_mem_0_mem_dqs_t Bidir 4 mem_dqs_t emif_hps_emif_mem_0_mem_dqs_c Bidir 4 mem_dqs_c emif_hps_emif_mem_0_mem_dmi Bidir 4 mem_dmi java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false emif_hps_emif_mem_ck_0_mem_ck_t Output 1 mem_ck_t emif_hps_emif_mem_ck_0_mem_ck_c Output 1 mem_ck_c java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false emif_hps_emif_mem_reset_n_mem_reset_n Output 1 mem_reset_n java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false emif_hps_emif_oct_0_oct_rzqin Input 1 oct_rzqin boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean false true true false true java.lang.Long -1 true true false true clock 0 false emif_hps_emif_ref_clk_clk Input 1 clk embeddedsw.CMacro.CPU_FREQ 50000000u embeddedsw.configuration.cpuArchitecture sm_hps com.altera.qsys.blackboxmodule.definitions.ComponentDefinition h2f_reset reset true h2f_reset_reset reset Output 1 0 STD_LOGIC 0 associatedClock associatedDirectReset associatedResetSinks none synchronousEdges NONE hps2fpga_axi_clock clock false hps2fpga_axi_clock_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName hps2fpga_axi_reset reset false hps2fpga_axi_reset_reset reset Input 1 0 STD_LOGIC 0 associatedClock synchronousEdges NONE hps2fpga axi4 true hps2fpga_awid awid Output 4 0 STD_LOGIC_VECTOR 0 hps2fpga_awaddr awaddr Output 38 0 STD_LOGIC_VECTOR 0 hps2fpga_awlen awlen Output 8 0 STD_LOGIC_VECTOR 0 hps2fpga_awsize awsize Output 3 0 STD_LOGIC_VECTOR 0 hps2fpga_awburst awburst Output 2 0 STD_LOGIC_VECTOR 0 hps2fpga_awlock awlock Output 1 0 STD_LOGIC 0 hps2fpga_awcache awcache Output 4 0 STD_LOGIC_VECTOR 0 hps2fpga_awprot awprot Output 3 0 STD_LOGIC_VECTOR 0 hps2fpga_awvalid awvalid Output 1 0 STD_LOGIC 0 hps2fpga_awready awready Input 1 0 STD_LOGIC 0 hps2fpga_wdata wdata Output 128 0 STD_LOGIC_VECTOR 0 hps2fpga_wstrb wstrb Output 16 0 STD_LOGIC_VECTOR 0 hps2fpga_wlast wlast Output 1 0 STD_LOGIC 0 hps2fpga_wvalid wvalid Output 1 0 STD_LOGIC 0 hps2fpga_wready wready Input 1 0 STD_LOGIC 0 hps2fpga_bid bid Input 4 0 STD_LOGIC_VECTOR 0 hps2fpga_bresp bresp Input 2 0 STD_LOGIC_VECTOR 0 hps2fpga_bvalid bvalid Input 1 0 STD_LOGIC 0 hps2fpga_bready bready Output 1 0 STD_LOGIC 0 hps2fpga_arid arid Output 4 0 STD_LOGIC_VECTOR 0 hps2fpga_araddr araddr Output 38 0 STD_LOGIC_VECTOR 0 hps2fpga_arlen arlen Output 8 0 STD_LOGIC_VECTOR 0 hps2fpga_arsize arsize Output 3 0 STD_LOGIC_VECTOR 0 hps2fpga_arburst arburst Output 2 0 STD_LOGIC_VECTOR 0 hps2fpga_arlock arlock Output 1 0 STD_LOGIC 0 hps2fpga_arcache arcache Output 4 0 STD_LOGIC_VECTOR 0 hps2fpga_arprot arprot Output 3 0 STD_LOGIC_VECTOR 0 hps2fpga_arvalid arvalid Output 1 0 STD_LOGIC 0 hps2fpga_arready arready Input 1 0 STD_LOGIC 0 hps2fpga_rid rid Input 4 0 STD_LOGIC_VECTOR 0 hps2fpga_rdata rdata Input 128 0 STD_LOGIC_VECTOR 0 hps2fpga_rresp rresp Input 2 0 STD_LOGIC_VECTOR 0 hps2fpga_rlast rlast Input 1 0 STD_LOGIC 0 hps2fpga_rvalid rvalid Input 1 0 STD_LOGIC 0 hps2fpga_rready rready Output 1 0 STD_LOGIC 0 associatedClock hps2fpga_axi_clock associatedReset hps2fpga_axi_reset optionalAssociatedReset false trustzoneAware true wakeupSignals false uniqueIdSupport false poison false traceSignals false isTranslator false maximumOutstandingReads 1 maximumOutstandingWrites 1 maximumOutstandingTransactions 1 dataCheck false addressCheck false securityAttribute false userData false readIssuingCapability 16 writeIssuingCapability 16 combinedIssuingCapability 16 enableConcurrentSubordinateAccess 0 noRepeatedIdsBetweenSubordinates 0 issuesINCRBursts true issuesWRAPBursts true issuesFIXEDBursts true lwhps2fpga_axi_clock clock false lwhps2fpga_axi_clock_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName lwhps2fpga_axi_reset reset false lwhps2fpga_axi_reset_reset reset Input 1 0 STD_LOGIC 0 associatedClock synchronousEdges NONE lwhps2fpga axi4 true lwhps2fpga_awid awid Output 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awaddr awaddr Output 29 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awlen awlen Output 8 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awsize awsize Output 3 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awburst awburst Output 2 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awlock awlock Output 1 0 STD_LOGIC 0 lwhps2fpga_awcache awcache Output 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awprot awprot Output 3 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awvalid awvalid Output 1 0 STD_LOGIC 0 lwhps2fpga_awready awready Input 1 0 STD_LOGIC 0 lwhps2fpga_wdata wdata Output 32 0 STD_LOGIC_VECTOR 0 lwhps2fpga_wstrb wstrb Output 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_wlast wlast Output 1 0 STD_LOGIC 0 lwhps2fpga_wvalid wvalid Output 1 0 STD_LOGIC 0 lwhps2fpga_wready wready Input 1 0 STD_LOGIC 0 lwhps2fpga_bid bid Input 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_bresp bresp Input 2 0 STD_LOGIC_VECTOR 0 lwhps2fpga_bvalid bvalid Input 1 0 STD_LOGIC 0 lwhps2fpga_bready bready Output 1 0 STD_LOGIC 0 lwhps2fpga_arid arid Output 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_araddr araddr Output 29 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arlen arlen Output 8 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arsize arsize Output 3 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arburst arburst Output 2 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arlock arlock Output 1 0 STD_LOGIC 0 lwhps2fpga_arcache arcache Output 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arprot arprot Output 3 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arvalid arvalid Output 1 0 STD_LOGIC 0 lwhps2fpga_arready arready Input 1 0 STD_LOGIC 0 lwhps2fpga_rid rid Input 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_rdata rdata Input 32 0 STD_LOGIC_VECTOR 0 lwhps2fpga_rresp rresp Input 2 0 STD_LOGIC_VECTOR 0 lwhps2fpga_rlast rlast Input 1 0 STD_LOGIC 0 lwhps2fpga_rvalid rvalid Input 1 0 STD_LOGIC 0 lwhps2fpga_rready rready Output 1 0 STD_LOGIC 0 associatedClock lwhps2fpga_axi_clock associatedReset lwhps2fpga_axi_reset optionalAssociatedReset false trustzoneAware true wakeupSignals false uniqueIdSupport false poison false traceSignals false isTranslator false maximumOutstandingReads 1 maximumOutstandingWrites 1 maximumOutstandingTransactions 1 dataCheck false addressCheck false securityAttribute false userData false readIssuingCapability 16 writeIssuingCapability 16 combinedIssuingCapability 16 enableConcurrentSubordinateAccess 0 noRepeatedIdsBetweenSubordinates 0 issuesINCRBursts true issuesWRAPBursts true issuesFIXEDBursts true emac0_app_rst reset true emac0_app_rst_reset_n reset_n Output 1 0 STD_LOGIC 0 associatedClock associatedDirectReset associatedResetSinks none synchronousEdges NONE h2f_warm_reset_handshake conduit false h2f_warm_reset_handshake_reset_req reset_req Output 1 0 STD_LOGIC 0 h2f_warm_reset_handshake_reset_ack reset_ack Input 1 0 STD_LOGIC 0 associatedClock associatedReset prSafe false hps_io conduit false hps_io_hps_osc_clk hps_osc_clk Input 1 0 STD_LOGIC 0 hps_io_sdmmc_data0 sdmmc_data0 Bidir 1 0 STD_LOGIC 0 hps_io_sdmmc_data1 sdmmc_data1 Bidir 1 0 STD_LOGIC 0 hps_io_sdmmc_cclk sdmmc_cclk Output 1 0 STD_LOGIC 0 hps_io_sdmmc_data2 sdmmc_data2 Bidir 1 0 STD_LOGIC 0 hps_io_sdmmc_data3 sdmmc_data3 Bidir 1 0 STD_LOGIC 0 hps_io_sdmmc_cmd sdmmc_cmd Bidir 1 0 STD_LOGIC 0 hps_io_usb0_clk usb0_clk Input 1 0 STD_LOGIC 0 hps_io_usb0_stp usb0_stp Output 1 0 STD_LOGIC 0 hps_io_usb0_dir usb0_dir Input 1 0 STD_LOGIC 0 hps_io_usb0_data0 usb0_data0 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data1 usb0_data1 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_nxt usb0_nxt Input 1 0 STD_LOGIC 0 hps_io_usb0_data2 usb0_data2 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data3 usb0_data3 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data4 usb0_data4 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data5 usb0_data5 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data6 usb0_data6 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data7 usb0_data7 Bidir 1 0 STD_LOGIC 0 hps_io_emac0_tx_clk emac0_tx_clk Output 1 0 STD_LOGIC 0 hps_io_emac0_tx_ctl emac0_tx_ctl Output 1 0 STD_LOGIC 0 hps_io_emac0_rx_clk emac0_rx_clk Input 1 0 STD_LOGIC 0 hps_io_emac0_rx_ctl emac0_rx_ctl Input 1 0 STD_LOGIC 0 hps_io_emac0_txd0 emac0_txd0 Output 1 0 STD_LOGIC 0 hps_io_emac0_txd1 emac0_txd1 Output 1 0 STD_LOGIC 0 hps_io_emac0_rxd0 emac0_rxd0 Input 1 0 STD_LOGIC 0 hps_io_emac0_rxd1 emac0_rxd1 Input 1 0 STD_LOGIC 0 hps_io_emac0_txd2 emac0_txd2 Output 1 0 STD_LOGIC 0 hps_io_emac0_txd3 emac0_txd3 Output 1 0 STD_LOGIC 0 hps_io_emac0_rxd2 emac0_rxd2 Input 1 0 STD_LOGIC 0 hps_io_emac0_rxd3 emac0_rxd3 Input 1 0 STD_LOGIC 0 hps_io_mdio0_mdio mdio0_mdio Bidir 1 0 STD_LOGIC 0 hps_io_mdio0_mdc mdio0_mdc Output 1 0 STD_LOGIC 0 hps_io_uart1_tx uart1_tx Output 1 0 STD_LOGIC 0 hps_io_uart1_rx uart1_rx Input 1 0 STD_LOGIC 0 hps_io_i2c1_sda i2c1_sda Bidir 1 0 STD_LOGIC 0 hps_io_i2c1_scl i2c1_scl Bidir 1 0 STD_LOGIC 0 hps_io_gpio28 gpio28 Bidir 1 0 STD_LOGIC 0 hps_io_gpio34 gpio34 Bidir 1 0 STD_LOGIC 0 hps_io_gpio40 gpio40 Bidir 1 0 STD_LOGIC 0 hps_io_gpio41 gpio41 Bidir 1 0 STD_LOGIC 0 associatedClock associatedReset prSafe false fpga2hps_interrupt_irq1 interrupt true fpga2hps_interrupt_irq1_irq irq Input 32 0 STD_LOGIC_VECTOR 0 associatedAddressablePoint associatedClock associatedReset irqMap irqScheme INDIVIDUAL_REQUESTS fpga2hps_interrupt_irq0 interrupt true fpga2hps_interrupt_irq0_irq irq Input 32 0 STD_LOGIC_VECTOR 0 associatedAddressablePoint associatedClock associatedReset irqMap irqScheme INDIVIDUAL_REQUESTS f2sdram_axi_clock clock false f2sdram_axi_clock_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName f2sdram_axi_reset reset false f2sdram_axi_reset_reset reset Input 1 0 STD_LOGIC 0 associatedClock synchronousEdges NONE f2sdram axi4 false f2sdram_araddr araddr Input 32 0 STD_LOGIC_VECTOR 0 f2sdram_arburst arburst Input 2 0 STD_LOGIC_VECTOR 0 f2sdram_arcache arcache Input 4 0 STD_LOGIC_VECTOR 0 f2sdram_arid arid Input 5 0 STD_LOGIC_VECTOR 0 f2sdram_arlen arlen Input 8 0 STD_LOGIC_VECTOR 0 f2sdram_arlock arlock Input 1 0 STD_LOGIC 0 f2sdram_arprot arprot Input 3 0 STD_LOGIC_VECTOR 0 f2sdram_arqos arqos Input 4 0 STD_LOGIC_VECTOR 0 f2sdram_arready arready Output 1 0 STD_LOGIC 0 f2sdram_arsize arsize Input 3 0 STD_LOGIC_VECTOR 0 f2sdram_arvalid arvalid Input 1 0 STD_LOGIC 0 f2sdram_awaddr awaddr Input 32 0 STD_LOGIC_VECTOR 0 f2sdram_awburst awburst Input 2 0 STD_LOGIC_VECTOR 0 f2sdram_awcache awcache Input 4 0 STD_LOGIC_VECTOR 0 f2sdram_awid awid Input 5 0 STD_LOGIC_VECTOR 0 f2sdram_awlen awlen Input 8 0 STD_LOGIC_VECTOR 0 f2sdram_awlock awlock Input 1 0 STD_LOGIC 0 f2sdram_awprot awprot Input 3 0 STD_LOGIC_VECTOR 0 f2sdram_awqos awqos Input 4 0 STD_LOGIC_VECTOR 0 f2sdram_awready awready Output 1 0 STD_LOGIC 0 f2sdram_awsize awsize Input 3 0 STD_LOGIC_VECTOR 0 f2sdram_awvalid awvalid Input 1 0 STD_LOGIC 0 f2sdram_bid bid Output 5 0 STD_LOGIC_VECTOR 0 f2sdram_bready bready Input 1 0 STD_LOGIC 0 f2sdram_bresp bresp Output 2 0 STD_LOGIC_VECTOR 0 f2sdram_bvalid bvalid Output 1 0 STD_LOGIC 0 f2sdram_rdata rdata Output 256 0 STD_LOGIC_VECTOR 0 f2sdram_rid rid Output 5 0 STD_LOGIC_VECTOR 0 f2sdram_rlast rlast Output 1 0 STD_LOGIC 0 f2sdram_rready rready Input 1 0 STD_LOGIC 0 f2sdram_rresp rresp Output 2 0 STD_LOGIC_VECTOR 0 f2sdram_rvalid rvalid Output 1 0 STD_LOGIC 0 f2sdram_wdata wdata Input 256 0 STD_LOGIC_VECTOR 0 f2sdram_wlast wlast Input 1 0 STD_LOGIC 0 f2sdram_wready wready Output 1 0 STD_LOGIC 0 f2sdram_wstrb wstrb Input 32 0 STD_LOGIC_VECTOR 0 f2sdram_wvalid wvalid Input 1 0 STD_LOGIC 0 f2sdram_aruser aruser Input 8 0 STD_LOGIC_VECTOR 0 f2sdram_awuser awuser Input 8 0 STD_LOGIC_VECTOR 0 f2sdram_wuser wuser Input 8 0 STD_LOGIC_VECTOR 0 f2sdram_buser buser Output 8 0 STD_LOGIC_VECTOR 0 f2sdram_arregion arregion Input 4 0 STD_LOGIC_VECTOR 0 f2sdram_ruser ruser Output 8 0 STD_LOGIC_VECTOR 0 f2sdram_awregion awregion Input 4 0 STD_LOGIC_VECTOR 0 associatedClock f2sdram_axi_clock associatedReset f2sdram_axi_reset optionalAssociatedReset false trustzoneAware true wakeupSignals false uniqueIdSupport false poison false traceSignals false isTranslator false maximumOutstandingReads 1 maximumOutstandingWrites 1 maximumOutstandingTransactions 1 dataCheck false addressCheck false securityAttribute false userData false readAcceptanceCapability 16 writeAcceptanceCapability 16 combinedAcceptanceCapability 16 readDataReorderingDepth 1 bridgesToMaster dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 noNarrowTransfer false io96b0_to_hps conduit false io96b0_to_hps_ch0_axil_clk ch0_axil_clk Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_reset_n ch0_axil_reset_n Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_arready ch0_axil_arready Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_awready ch0_axil_awready Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_bresp ch0_axil_bresp Input 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_bvalid ch0_axil_bvalid Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_rdata ch0_axil_rdata Input 32 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_rresp ch0_axil_rresp Input 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_rvalid ch0_axil_rvalid Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_wready ch0_axil_wready Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_araddr ch0_axil_araddr Output 27 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_arvalid ch0_axil_arvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_awaddr ch0_axil_awaddr Output 27 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_awvalid ch0_axil_awvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_bready ch0_axil_bready Output 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_rready ch0_axil_rready Output 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_wdata ch0_axil_wdata Output 32 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_wstrb ch0_axil_wstrb Output 4 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_wvalid ch0_axil_wvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_arprot ch0_axil_arprot Output 3 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_awprot ch0_axil_awprot Output 3 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_clk axi4_ch0_clk Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_reset_n axi4_ch0_reset_n Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_arready axi4_ch0_arready Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_awready axi4_ch0_awready Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_bid axi4_ch0_bid Input 7 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_bresp axi4_ch0_bresp Input 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_bvalid axi4_ch0_bvalid Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_rdata axi4_ch0_rdata Input 256 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_rid axi4_ch0_rid Input 7 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_rlast axi4_ch0_rlast Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_rresp axi4_ch0_rresp Input 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_ruser axi4_ch0_ruser Input 32 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_rvalid axi4_ch0_rvalid Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_wready axi4_ch0_wready Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_araddr axi4_ch0_araddr Output 40 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arburst axi4_ch0_arburst Output 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arid axi4_ch0_arid Output 7 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arlen axi4_ch0_arlen Output 8 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arlock axi4_ch0_arlock Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_arqos axi4_ch0_arqos Output 4 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arsize axi4_ch0_arsize Output 3 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_aruser axi4_ch0_aruser Output 14 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arvalid axi4_ch0_arvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_awaddr axi4_ch0_awaddr Output 40 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awburst axi4_ch0_awburst Output 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awid axi4_ch0_awid Output 7 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awlen axi4_ch0_awlen Output 8 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awlock axi4_ch0_awlock Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_awqos axi4_ch0_awqos Output 4 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awsize axi4_ch0_awsize Output 3 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awuser axi4_ch0_awuser Output 14 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awvalid axi4_ch0_awvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_bready axi4_ch0_bready Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_rready axi4_ch0_rready Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_wdata axi4_ch0_wdata Output 256 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_wlast axi4_ch0_wlast Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_wstrb axi4_ch0_wstrb Output 32 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_wuser axi4_ch0_wuser Output 32 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_wvalid axi4_ch0_wvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_arprot axi4_ch0_arprot Output 3 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awprot axi4_ch0_awprot Output 3 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false intel_agilex_5_soc 13.0.0 Hard Processor System IP AUTO_BOARD java.lang.String BOARD AUTO_DEVICE_SPEEDGRADE java.lang.String DEVICE_SPEEDGRADE device_family java.lang.String DEVICE_FAMILY device_name java.lang.String DEVICE device_trait_iobank_rev java.lang.String DEVICE_IOBANK_REVISION PART_TRAIT f2sdram f2sdram ADDRESS_MAP <address-map><slave name='f2sdram' start='0x0' end='0x100000000' datawidth='256' /></address-map> ADDRESS_WIDTH 32 MAX_SLAVE_DATA_WIDTH 256 ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition agilex_hps agilex_hps agilex_hps QUARTUS_SYNTH agilex_hps agilex_hps SIM_VERILOG agilex_hps agilex_hps SIM_VHDL agilex_hps agilex_hps CDC agilex_hps agilex_hps CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/hps_subsys/agilex_hps.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition h2f_reset reset true h2f_reset_reset reset Output 1 0 STD_LOGIC 0 associatedClock associatedDirectReset associatedResetSinks none synchronousEdges NONE hps2fpga_axi_clock clock false hps2fpga_axi_clock_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName hps2fpga_axi_reset reset false hps2fpga_axi_reset_reset reset Input 1 0 STD_LOGIC 0 associatedClock synchronousEdges NONE hps2fpga axi4 true hps2fpga_awid awid Output 4 0 STD_LOGIC_VECTOR 0 hps2fpga_awaddr awaddr Output 38 0 STD_LOGIC_VECTOR 0 hps2fpga_awlen awlen Output 8 0 STD_LOGIC_VECTOR 0 hps2fpga_awsize awsize Output 3 0 STD_LOGIC_VECTOR 0 hps2fpga_awburst awburst Output 2 0 STD_LOGIC_VECTOR 0 hps2fpga_awlock awlock Output 1 0 STD_LOGIC 0 hps2fpga_awcache awcache Output 4 0 STD_LOGIC_VECTOR 0 hps2fpga_awprot awprot Output 3 0 STD_LOGIC_VECTOR 0 hps2fpga_awvalid awvalid Output 1 0 STD_LOGIC 0 hps2fpga_awready awready Input 1 0 STD_LOGIC 0 hps2fpga_wdata wdata Output 128 0 STD_LOGIC_VECTOR 0 hps2fpga_wstrb wstrb Output 16 0 STD_LOGIC_VECTOR 0 hps2fpga_wlast wlast Output 1 0 STD_LOGIC 0 hps2fpga_wvalid wvalid Output 1 0 STD_LOGIC 0 hps2fpga_wready wready Input 1 0 STD_LOGIC 0 hps2fpga_bid bid Input 4 0 STD_LOGIC_VECTOR 0 hps2fpga_bresp bresp Input 2 0 STD_LOGIC_VECTOR 0 hps2fpga_bvalid bvalid Input 1 0 STD_LOGIC 0 hps2fpga_bready bready Output 1 0 STD_LOGIC 0 hps2fpga_arid arid Output 4 0 STD_LOGIC_VECTOR 0 hps2fpga_araddr araddr Output 38 0 STD_LOGIC_VECTOR 0 hps2fpga_arlen arlen Output 8 0 STD_LOGIC_VECTOR 0 hps2fpga_arsize arsize Output 3 0 STD_LOGIC_VECTOR 0 hps2fpga_arburst arburst Output 2 0 STD_LOGIC_VECTOR 0 hps2fpga_arlock arlock Output 1 0 STD_LOGIC 0 hps2fpga_arcache arcache Output 4 0 STD_LOGIC_VECTOR 0 hps2fpga_arprot arprot Output 3 0 STD_LOGIC_VECTOR 0 hps2fpga_arvalid arvalid Output 1 0 STD_LOGIC 0 hps2fpga_arready arready Input 1 0 STD_LOGIC 0 hps2fpga_rid rid Input 4 0 STD_LOGIC_VECTOR 0 hps2fpga_rdata rdata Input 128 0 STD_LOGIC_VECTOR 0 hps2fpga_rresp rresp Input 2 0 STD_LOGIC_VECTOR 0 hps2fpga_rlast rlast Input 1 0 STD_LOGIC 0 hps2fpga_rvalid rvalid Input 1 0 STD_LOGIC 0 hps2fpga_rready rready Output 1 0 STD_LOGIC 0 associatedClock hps2fpga_axi_clock associatedReset hps2fpga_axi_reset optionalAssociatedReset false trustzoneAware true wakeupSignals false uniqueIdSupport false poison false traceSignals false isTranslator false maximumOutstandingReads 1 maximumOutstandingWrites 1 maximumOutstandingTransactions 1 dataCheck false addressCheck false securityAttribute false userData false readIssuingCapability 16 writeIssuingCapability 16 combinedIssuingCapability 16 enableConcurrentSubordinateAccess 0 noRepeatedIdsBetweenSubordinates 0 issuesINCRBursts true issuesWRAPBursts true issuesFIXEDBursts true lwhps2fpga_axi_clock clock false lwhps2fpga_axi_clock_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName lwhps2fpga_axi_reset reset false lwhps2fpga_axi_reset_reset reset Input 1 0 STD_LOGIC 0 associatedClock synchronousEdges NONE lwhps2fpga axi4 true lwhps2fpga_awid awid Output 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awaddr awaddr Output 29 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awlen awlen Output 8 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awsize awsize Output 3 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awburst awburst Output 2 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awlock awlock Output 1 0 STD_LOGIC 0 lwhps2fpga_awcache awcache Output 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awprot awprot Output 3 0 STD_LOGIC_VECTOR 0 lwhps2fpga_awvalid awvalid Output 1 0 STD_LOGIC 0 lwhps2fpga_awready awready Input 1 0 STD_LOGIC 0 lwhps2fpga_wdata wdata Output 32 0 STD_LOGIC_VECTOR 0 lwhps2fpga_wstrb wstrb Output 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_wlast wlast Output 1 0 STD_LOGIC 0 lwhps2fpga_wvalid wvalid Output 1 0 STD_LOGIC 0 lwhps2fpga_wready wready Input 1 0 STD_LOGIC 0 lwhps2fpga_bid bid Input 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_bresp bresp Input 2 0 STD_LOGIC_VECTOR 0 lwhps2fpga_bvalid bvalid Input 1 0 STD_LOGIC 0 lwhps2fpga_bready bready Output 1 0 STD_LOGIC 0 lwhps2fpga_arid arid Output 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_araddr araddr Output 29 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arlen arlen Output 8 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arsize arsize Output 3 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arburst arburst Output 2 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arlock arlock Output 1 0 STD_LOGIC 0 lwhps2fpga_arcache arcache Output 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arprot arprot Output 3 0 STD_LOGIC_VECTOR 0 lwhps2fpga_arvalid arvalid Output 1 0 STD_LOGIC 0 lwhps2fpga_arready arready Input 1 0 STD_LOGIC 0 lwhps2fpga_rid rid Input 4 0 STD_LOGIC_VECTOR 0 lwhps2fpga_rdata rdata Input 32 0 STD_LOGIC_VECTOR 0 lwhps2fpga_rresp rresp Input 2 0 STD_LOGIC_VECTOR 0 lwhps2fpga_rlast rlast Input 1 0 STD_LOGIC 0 lwhps2fpga_rvalid rvalid Input 1 0 STD_LOGIC 0 lwhps2fpga_rready rready Output 1 0 STD_LOGIC 0 associatedClock lwhps2fpga_axi_clock associatedReset lwhps2fpga_axi_reset optionalAssociatedReset false trustzoneAware true wakeupSignals false uniqueIdSupport false poison false traceSignals false isTranslator false maximumOutstandingReads 1 maximumOutstandingWrites 1 maximumOutstandingTransactions 1 dataCheck false addressCheck false securityAttribute false userData false readIssuingCapability 16 writeIssuingCapability 16 combinedIssuingCapability 16 enableConcurrentSubordinateAccess 0 noRepeatedIdsBetweenSubordinates 0 issuesINCRBursts true issuesWRAPBursts true issuesFIXEDBursts true emac0_app_rst reset true emac0_app_rst_reset_n reset_n Output 1 0 STD_LOGIC 0 associatedClock associatedDirectReset associatedResetSinks none synchronousEdges NONE h2f_warm_reset_handshake conduit false h2f_warm_reset_handshake_reset_req reset_req Output 1 0 STD_LOGIC 0 h2f_warm_reset_handshake_reset_ack reset_ack Input 1 0 STD_LOGIC 0 associatedClock associatedReset prSafe false hps_io conduit false hps_io_hps_osc_clk hps_osc_clk Input 1 0 STD_LOGIC 0 hps_io_sdmmc_data0 sdmmc_data0 Bidir 1 0 STD_LOGIC 0 hps_io_sdmmc_data1 sdmmc_data1 Bidir 1 0 STD_LOGIC 0 hps_io_sdmmc_cclk sdmmc_cclk Output 1 0 STD_LOGIC 0 hps_io_sdmmc_data2 sdmmc_data2 Bidir 1 0 STD_LOGIC 0 hps_io_sdmmc_data3 sdmmc_data3 Bidir 1 0 STD_LOGIC 0 hps_io_sdmmc_cmd sdmmc_cmd Bidir 1 0 STD_LOGIC 0 hps_io_usb0_clk usb0_clk Input 1 0 STD_LOGIC 0 hps_io_usb0_stp usb0_stp Output 1 0 STD_LOGIC 0 hps_io_usb0_dir usb0_dir Input 1 0 STD_LOGIC 0 hps_io_usb0_data0 usb0_data0 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data1 usb0_data1 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_nxt usb0_nxt Input 1 0 STD_LOGIC 0 hps_io_usb0_data2 usb0_data2 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data3 usb0_data3 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data4 usb0_data4 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data5 usb0_data5 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data6 usb0_data6 Bidir 1 0 STD_LOGIC 0 hps_io_usb0_data7 usb0_data7 Bidir 1 0 STD_LOGIC 0 hps_io_emac0_tx_clk emac0_tx_clk Output 1 0 STD_LOGIC 0 hps_io_emac0_tx_ctl emac0_tx_ctl Output 1 0 STD_LOGIC 0 hps_io_emac0_rx_clk emac0_rx_clk Input 1 0 STD_LOGIC 0 hps_io_emac0_rx_ctl emac0_rx_ctl Input 1 0 STD_LOGIC 0 hps_io_emac0_txd0 emac0_txd0 Output 1 0 STD_LOGIC 0 hps_io_emac0_txd1 emac0_txd1 Output 1 0 STD_LOGIC 0 hps_io_emac0_rxd0 emac0_rxd0 Input 1 0 STD_LOGIC 0 hps_io_emac0_rxd1 emac0_rxd1 Input 1 0 STD_LOGIC 0 hps_io_emac0_txd2 emac0_txd2 Output 1 0 STD_LOGIC 0 hps_io_emac0_txd3 emac0_txd3 Output 1 0 STD_LOGIC 0 hps_io_emac0_rxd2 emac0_rxd2 Input 1 0 STD_LOGIC 0 hps_io_emac0_rxd3 emac0_rxd3 Input 1 0 STD_LOGIC 0 hps_io_mdio0_mdio mdio0_mdio Bidir 1 0 STD_LOGIC 0 hps_io_mdio0_mdc mdio0_mdc Output 1 0 STD_LOGIC 0 hps_io_uart1_tx uart1_tx Output 1 0 STD_LOGIC 0 hps_io_uart1_rx uart1_rx Input 1 0 STD_LOGIC 0 hps_io_i2c1_sda i2c1_sda Bidir 1 0 STD_LOGIC 0 hps_io_i2c1_scl i2c1_scl Bidir 1 0 STD_LOGIC 0 hps_io_gpio28 gpio28 Bidir 1 0 STD_LOGIC 0 hps_io_gpio34 gpio34 Bidir 1 0 STD_LOGIC 0 hps_io_gpio40 gpio40 Bidir 1 0 STD_LOGIC 0 hps_io_gpio41 gpio41 Bidir 1 0 STD_LOGIC 0 associatedClock associatedReset prSafe false fpga2hps_interrupt_irq1 interrupt true fpga2hps_interrupt_irq1_irq irq Input 32 0 STD_LOGIC_VECTOR 0 associatedAddressablePoint associatedClock associatedReset irqMap irqScheme INDIVIDUAL_REQUESTS fpga2hps_interrupt_irq0 interrupt true fpga2hps_interrupt_irq0_irq irq Input 32 0 STD_LOGIC_VECTOR 0 associatedAddressablePoint associatedClock associatedReset irqMap irqScheme INDIVIDUAL_REQUESTS f2sdram_axi_clock clock false f2sdram_axi_clock_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName f2sdram_axi_reset reset false f2sdram_axi_reset_reset reset Input 1 0 STD_LOGIC 0 associatedClock synchronousEdges NONE f2sdram axi4 false f2sdram_araddr araddr Input 32 0 STD_LOGIC_VECTOR 0 f2sdram_arburst arburst Input 2 0 STD_LOGIC_VECTOR 0 f2sdram_arcache arcache Input 4 0 STD_LOGIC_VECTOR 0 f2sdram_arid arid Input 5 0 STD_LOGIC_VECTOR 0 f2sdram_arlen arlen Input 8 0 STD_LOGIC_VECTOR 0 f2sdram_arlock arlock Input 1 0 STD_LOGIC 0 f2sdram_arprot arprot Input 3 0 STD_LOGIC_VECTOR 0 f2sdram_arqos arqos Input 4 0 STD_LOGIC_VECTOR 0 f2sdram_arready arready Output 1 0 STD_LOGIC 0 f2sdram_arsize arsize Input 3 0 STD_LOGIC_VECTOR 0 f2sdram_arvalid arvalid Input 1 0 STD_LOGIC 0 f2sdram_awaddr awaddr Input 32 0 STD_LOGIC_VECTOR 0 f2sdram_awburst awburst Input 2 0 STD_LOGIC_VECTOR 0 f2sdram_awcache awcache Input 4 0 STD_LOGIC_VECTOR 0 f2sdram_awid awid Input 5 0 STD_LOGIC_VECTOR 0 f2sdram_awlen awlen Input 8 0 STD_LOGIC_VECTOR 0 f2sdram_awlock awlock Input 1 0 STD_LOGIC 0 f2sdram_awprot awprot Input 3 0 STD_LOGIC_VECTOR 0 f2sdram_awqos awqos Input 4 0 STD_LOGIC_VECTOR 0 f2sdram_awready awready Output 1 0 STD_LOGIC 0 f2sdram_awsize awsize Input 3 0 STD_LOGIC_VECTOR 0 f2sdram_awvalid awvalid Input 1 0 STD_LOGIC 0 f2sdram_bid bid Output 5 0 STD_LOGIC_VECTOR 0 f2sdram_bready bready Input 1 0 STD_LOGIC 0 f2sdram_bresp bresp Output 2 0 STD_LOGIC_VECTOR 0 f2sdram_bvalid bvalid Output 1 0 STD_LOGIC 0 f2sdram_rdata rdata Output 256 0 STD_LOGIC_VECTOR 0 f2sdram_rid rid Output 5 0 STD_LOGIC_VECTOR 0 f2sdram_rlast rlast Output 1 0 STD_LOGIC 0 f2sdram_rready rready Input 1 0 STD_LOGIC 0 f2sdram_rresp rresp Output 2 0 STD_LOGIC_VECTOR 0 f2sdram_rvalid rvalid Output 1 0 STD_LOGIC 0 f2sdram_wdata wdata Input 256 0 STD_LOGIC_VECTOR 0 f2sdram_wlast wlast Input 1 0 STD_LOGIC 0 f2sdram_wready wready Output 1 0 STD_LOGIC 0 f2sdram_wstrb wstrb Input 32 0 STD_LOGIC_VECTOR 0 f2sdram_wvalid wvalid Input 1 0 STD_LOGIC 0 f2sdram_aruser aruser Input 8 0 STD_LOGIC_VECTOR 0 f2sdram_awuser awuser Input 8 0 STD_LOGIC_VECTOR 0 f2sdram_wuser wuser Input 8 0 STD_LOGIC_VECTOR 0 f2sdram_buser buser Output 8 0 STD_LOGIC_VECTOR 0 f2sdram_arregion arregion Input 4 0 STD_LOGIC_VECTOR 0 f2sdram_ruser ruser Output 8 0 STD_LOGIC_VECTOR 0 f2sdram_awregion awregion Input 4 0 STD_LOGIC_VECTOR 0 associatedClock f2sdram_axi_clock associatedReset f2sdram_axi_reset optionalAssociatedReset false trustzoneAware true wakeupSignals false uniqueIdSupport false poison false traceSignals false isTranslator false maximumOutstandingReads 1 maximumOutstandingWrites 1 maximumOutstandingTransactions 1 dataCheck false addressCheck false securityAttribute false userData false readAcceptanceCapability 16 writeAcceptanceCapability 16 combinedAcceptanceCapability 16 readDataReorderingDepth 1 bridgesToMaster dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 noNarrowTransfer false io96b0_to_hps conduit false io96b0_to_hps_ch0_axil_clk ch0_axil_clk Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_reset_n ch0_axil_reset_n Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_arready ch0_axil_arready Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_awready ch0_axil_awready Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_bresp ch0_axil_bresp Input 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_bvalid ch0_axil_bvalid Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_rdata ch0_axil_rdata Input 32 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_rresp ch0_axil_rresp Input 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_rvalid ch0_axil_rvalid Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_wready ch0_axil_wready Input 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_araddr ch0_axil_araddr Output 27 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_arvalid ch0_axil_arvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_awaddr ch0_axil_awaddr Output 27 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_awvalid ch0_axil_awvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_bready ch0_axil_bready Output 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_rready ch0_axil_rready Output 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_wdata ch0_axil_wdata Output 32 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_wstrb ch0_axil_wstrb Output 4 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_wvalid ch0_axil_wvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_ch0_axil_arprot ch0_axil_arprot Output 3 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_ch0_axil_awprot ch0_axil_awprot Output 3 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_clk axi4_ch0_clk Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_reset_n axi4_ch0_reset_n Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_arready axi4_ch0_arready Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_awready axi4_ch0_awready Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_bid axi4_ch0_bid Input 7 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_bresp axi4_ch0_bresp Input 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_bvalid axi4_ch0_bvalid Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_rdata axi4_ch0_rdata Input 256 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_rid axi4_ch0_rid Input 7 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_rlast axi4_ch0_rlast Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_rresp axi4_ch0_rresp Input 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_ruser axi4_ch0_ruser Input 32 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_rvalid axi4_ch0_rvalid Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_wready axi4_ch0_wready Input 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_araddr axi4_ch0_araddr Output 40 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arburst axi4_ch0_arburst Output 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arid axi4_ch0_arid Output 7 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arlen axi4_ch0_arlen Output 8 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arlock axi4_ch0_arlock Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_arqos axi4_ch0_arqos Output 4 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arsize axi4_ch0_arsize Output 3 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_aruser axi4_ch0_aruser Output 14 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_arvalid axi4_ch0_arvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_awaddr axi4_ch0_awaddr Output 40 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awburst axi4_ch0_awburst Output 2 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awid axi4_ch0_awid Output 7 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awlen axi4_ch0_awlen Output 8 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awlock axi4_ch0_awlock Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_awqos axi4_ch0_awqos Output 4 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awsize axi4_ch0_awsize Output 3 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awuser axi4_ch0_awuser Output 14 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awvalid axi4_ch0_awvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_bready axi4_ch0_bready Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_rready axi4_ch0_rready Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_wdata axi4_ch0_wdata Output 256 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_wlast axi4_ch0_wlast Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_wstrb axi4_ch0_wstrb Output 32 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_wuser axi4_ch0_wuser Output 32 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_wvalid axi4_ch0_wvalid Output 1 0 STD_LOGIC 0 io96b0_to_hps_axi4_ch0_arprot axi4_ch0_arprot Output 3 0 STD_LOGIC_VECTOR 0 io96b0_to_hps_axi4_ch0_awprot axi4_ch0_awprot Output 3 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition embeddedsw.CMacro.CPU_FREQ 50000000u embeddedsw.configuration.cpuArchitecture sm_hps ]]> false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList ]]> false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition false true false true java.lang.Boolean true false true false true java.lang.String intel_agilex_5_soc_inst false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.String default true true false true BOARD java.lang.String 4 true true false true DEVICE_SPEEDGRADE java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String IO96B_REVB1 true true false true PART_TRAIT DEVICE_IOBANK_REVISION java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true java.lang.String false true true true java.lang.String false true true true [Ljava.lang.String; none false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 true h2f_reset_reset Output 1 reset boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock 0 false hps2fpga_axi_clock_clk Input 1 clk java.lang.String false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false hps2fpga_axi_reset_reset Input 1 reset java.lang.String hps2fpga_axi_clock false true true true java.lang.String hps2fpga_axi_reset false true true true boolean false false true true true boolean true false true false true boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true false true boolean false false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true boolean true false true true true boolean true false true true true boolean true false true true true java.lang.String UNKNOWN false true true true boolean false false true true true axi4 274877906944 true hps2fpga_awid Output 4 awid hps2fpga_awaddr Output 38 awaddr hps2fpga_awlen Output 8 awlen hps2fpga_awsize Output 3 awsize hps2fpga_awburst Output 2 awburst hps2fpga_awlock Output 1 awlock hps2fpga_awcache Output 4 awcache hps2fpga_awprot Output 3 awprot hps2fpga_awvalid Output 1 awvalid hps2fpga_awready Input 1 awready hps2fpga_wdata Output 128 wdata hps2fpga_wstrb Output 16 wstrb hps2fpga_wlast Output 1 wlast hps2fpga_wvalid Output 1 wvalid hps2fpga_wready Input 1 wready hps2fpga_bid Input 4 bid hps2fpga_bresp Input 2 bresp hps2fpga_bvalid Input 1 bvalid hps2fpga_bready Output 1 bready hps2fpga_arid Output 4 arid hps2fpga_araddr Output 38 araddr hps2fpga_arlen Output 8 arlen hps2fpga_arsize Output 3 arsize hps2fpga_arburst Output 2 arburst hps2fpga_arlock Output 1 arlock hps2fpga_arcache Output 4 arcache hps2fpga_arprot Output 3 arprot hps2fpga_arvalid Output 1 arvalid hps2fpga_arready Input 1 arready hps2fpga_rid Input 4 rid hps2fpga_rdata Input 128 rdata hps2fpga_rresp Input 2 rresp hps2fpga_rlast Input 1 rlast hps2fpga_rvalid Input 1 rvalid hps2fpga_rready Output 1 rready boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock 0 false lwhps2fpga_axi_clock_clk Input 1 clk java.lang.String false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false lwhps2fpga_axi_reset_reset Input 1 reset java.lang.String lwhps2fpga_axi_clock false true true true java.lang.String lwhps2fpga_axi_reset false true true true boolean false false true true true boolean true false true false true boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true false true boolean false false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true boolean true false true true true boolean true false true true true boolean true false true true true java.lang.String UNKNOWN false true true true boolean false false true true true axi4 536870912 true lwhps2fpga_awid Output 4 awid lwhps2fpga_awaddr Output 29 awaddr lwhps2fpga_awlen Output 8 awlen lwhps2fpga_awsize Output 3 awsize lwhps2fpga_awburst Output 2 awburst lwhps2fpga_awlock Output 1 awlock lwhps2fpga_awcache Output 4 awcache lwhps2fpga_awprot Output 3 awprot lwhps2fpga_awvalid Output 1 awvalid lwhps2fpga_awready Input 1 awready lwhps2fpga_wdata Output 32 wdata lwhps2fpga_wstrb Output 4 wstrb lwhps2fpga_wlast Output 1 wlast lwhps2fpga_wvalid Output 1 wvalid lwhps2fpga_wready Input 1 wready lwhps2fpga_bid Input 4 bid lwhps2fpga_bresp Input 2 bresp lwhps2fpga_bvalid Input 1 bvalid lwhps2fpga_bready Output 1 bready lwhps2fpga_arid Output 4 arid lwhps2fpga_araddr Output 29 araddr lwhps2fpga_arlen Output 8 arlen lwhps2fpga_arsize Output 3 arsize lwhps2fpga_arburst Output 2 arburst lwhps2fpga_arlock Output 1 arlock lwhps2fpga_arcache Output 4 arcache lwhps2fpga_arprot Output 3 arprot lwhps2fpga_arvalid Output 1 arvalid lwhps2fpga_arready Input 1 arready lwhps2fpga_rid Input 4 rid lwhps2fpga_rdata Input 32 rdata lwhps2fpga_rresp Input 2 rresp lwhps2fpga_rlast Input 1 rlast lwhps2fpga_rvalid Input 1 rvalid lwhps2fpga_rready Output 1 rready true subsys_periph_pb_cpu_0 s0 subsys_periph_pb_cpu_0.s0 0 131072 false subsys_periph_sysid control_slave subsys_periph_sysid.control_slave 65536 8 false subsys_periph_led_pio s1 subsys_periph_led_pio.s1 65664 16 false subsys_periph_dipsw_pio s1 subsys_periph_dipsw_pio.s1 65648 16 false subsys_periph_button_pio s1 subsys_periph_button_pio.s1 65632 16 java.lang.String false true true true java.lang.String false true true true [Ljava.lang.String; none false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 true emac0_app_rst_reset_n Output 1 reset_n java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false h2f_warm_reset_handshake_reset_req Output 1 reset_req h2f_warm_reset_handshake_reset_ack Input 1 reset_ack java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false hps_io_hps_osc_clk Input 1 hps_osc_clk hps_io_sdmmc_data0 Bidir 1 sdmmc_data0 hps_io_sdmmc_data1 Bidir 1 sdmmc_data1 hps_io_sdmmc_cclk Output 1 sdmmc_cclk hps_io_sdmmc_data2 Bidir 1 sdmmc_data2 hps_io_sdmmc_data3 Bidir 1 sdmmc_data3 hps_io_sdmmc_cmd Bidir 1 sdmmc_cmd hps_io_usb0_clk Input 1 usb0_clk hps_io_usb0_stp Output 1 usb0_stp hps_io_usb0_dir Input 1 usb0_dir hps_io_usb0_data0 Bidir 1 usb0_data0 hps_io_usb0_data1 Bidir 1 usb0_data1 hps_io_usb0_nxt Input 1 usb0_nxt hps_io_usb0_data2 Bidir 1 usb0_data2 hps_io_usb0_data3 Bidir 1 usb0_data3 hps_io_usb0_data4 Bidir 1 usb0_data4 hps_io_usb0_data5 Bidir 1 usb0_data5 hps_io_usb0_data6 Bidir 1 usb0_data6 hps_io_usb0_data7 Bidir 1 usb0_data7 hps_io_emac0_tx_clk Output 1 emac0_tx_clk hps_io_emac0_tx_ctl Output 1 emac0_tx_ctl hps_io_emac0_rx_clk Input 1 emac0_rx_clk hps_io_emac0_rx_ctl Input 1 emac0_rx_ctl hps_io_emac0_txd0 Output 1 emac0_txd0 hps_io_emac0_txd1 Output 1 emac0_txd1 hps_io_emac0_rxd0 Input 1 emac0_rxd0 hps_io_emac0_rxd1 Input 1 emac0_rxd1 hps_io_emac0_txd2 Output 1 emac0_txd2 hps_io_emac0_txd3 Output 1 emac0_txd3 hps_io_emac0_rxd2 Input 1 emac0_rxd2 hps_io_emac0_rxd3 Input 1 emac0_rxd3 hps_io_mdio0_mdio Bidir 1 mdio0_mdio hps_io_mdio0_mdc Output 1 mdio0_mdc hps_io_uart1_tx Output 1 uart1_tx hps_io_uart1_rx Input 1 uart1_rx hps_io_i2c1_sda Bidir 1 i2c1_sda hps_io_i2c1_scl Bidir 1 i2c1_scl hps_io_gpio28 Bidir 1 gpio28 hps_io_gpio34 Bidir 1 gpio34 hps_io_gpio40 Bidir 1 gpio40 hps_io_gpio41 Bidir 1 gpio41 com.altera.entityinterfaces.IConnectionPoint false true false true java.lang.String false true false true java.lang.String false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt 0 true fpga2hps_interrupt_irq1_irq Input 32 irq com.altera.entityinterfaces.IConnectionPoint false true false true java.lang.String false true false true java.lang.String false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt 0 true fpga2hps_interrupt_irq0_irq Input 32 irq false subsys_periph_button_pio irq subsys_periph_button_pio.irq 1 false subsys_periph_dipsw_pio irq subsys_periph_dipsw_pio.irq 0 boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock 0 false f2sdram_axi_clock_clk Input 1 clk java.lang.String false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false f2sdram_axi_reset_reset Input 1 reset java.lang.String f2sdram_axi_clock false true true true java.lang.String f2sdram_axi_reset false true true true boolean false false true true true boolean true false true false true boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true false true boolean false false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 16 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.math.BigInteger 0 false true true true java.lang.Integer 0 false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true java.lang.Integer 35 false true true true java.lang.Integer 3 false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4294967296 true true false true axi4 4294967296 false f2sdram_araddr Input 32 araddr f2sdram_arburst Input 2 arburst f2sdram_arcache Input 4 arcache f2sdram_arid Input 5 arid f2sdram_arlen Input 8 arlen f2sdram_arlock Input 1 arlock f2sdram_arprot Input 3 arprot f2sdram_arqos Input 4 arqos f2sdram_arready Output 1 arready f2sdram_arsize Input 3 arsize f2sdram_arvalid Input 1 arvalid f2sdram_awaddr Input 32 awaddr f2sdram_awburst Input 2 awburst f2sdram_awcache Input 4 awcache f2sdram_awid Input 5 awid f2sdram_awlen Input 8 awlen f2sdram_awlock Input 1 awlock f2sdram_awprot Input 3 awprot f2sdram_awqos Input 4 awqos f2sdram_awready Output 1 awready f2sdram_awsize Input 3 awsize f2sdram_awvalid Input 1 awvalid f2sdram_bid Output 5 bid f2sdram_bready Input 1 bready f2sdram_bresp Output 2 bresp f2sdram_bvalid Output 1 bvalid f2sdram_rdata Output 256 rdata f2sdram_rid Output 5 rid f2sdram_rlast Output 1 rlast f2sdram_rready Input 1 rready f2sdram_rresp Output 2 rresp f2sdram_rvalid Output 1 rvalid f2sdram_wdata Input 256 wdata f2sdram_wlast Input 1 wlast f2sdram_wready Output 1 wready f2sdram_wstrb Input 32 wstrb f2sdram_wvalid Input 1 wvalid f2sdram_aruser Input 8 aruser f2sdram_awuser Input 8 awuser f2sdram_wuser Input 8 wuser f2sdram_buser Output 8 buser f2sdram_arregion Input 4 arregion f2sdram_ruser Output 8 ruser f2sdram_awregion Input 4 awregion java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false io96b0_to_hps_ch0_axil_clk Input 1 ch0_axil_clk io96b0_to_hps_ch0_axil_reset_n Input 1 ch0_axil_reset_n io96b0_to_hps_ch0_axil_arready Input 1 ch0_axil_arready io96b0_to_hps_ch0_axil_awready Input 1 ch0_axil_awready io96b0_to_hps_ch0_axil_bresp Input 2 ch0_axil_bresp io96b0_to_hps_ch0_axil_bvalid Input 1 ch0_axil_bvalid io96b0_to_hps_ch0_axil_rdata Input 32 ch0_axil_rdata io96b0_to_hps_ch0_axil_rresp Input 2 ch0_axil_rresp io96b0_to_hps_ch0_axil_rvalid Input 1 ch0_axil_rvalid io96b0_to_hps_ch0_axil_wready Input 1 ch0_axil_wready io96b0_to_hps_ch0_axil_araddr Output 27 ch0_axil_araddr io96b0_to_hps_ch0_axil_arvalid Output 1 ch0_axil_arvalid io96b0_to_hps_ch0_axil_awaddr Output 27 ch0_axil_awaddr io96b0_to_hps_ch0_axil_awvalid Output 1 ch0_axil_awvalid io96b0_to_hps_ch0_axil_bready Output 1 ch0_axil_bready io96b0_to_hps_ch0_axil_rready Output 1 ch0_axil_rready io96b0_to_hps_ch0_axil_wdata Output 32 ch0_axil_wdata io96b0_to_hps_ch0_axil_wstrb Output 4 ch0_axil_wstrb io96b0_to_hps_ch0_axil_wvalid Output 1 ch0_axil_wvalid io96b0_to_hps_ch0_axil_arprot Output 3 ch0_axil_arprot io96b0_to_hps_ch0_axil_awprot Output 3 ch0_axil_awprot io96b0_to_hps_axi4_ch0_clk Input 1 axi4_ch0_clk io96b0_to_hps_axi4_ch0_reset_n Input 1 axi4_ch0_reset_n io96b0_to_hps_axi4_ch0_arready Input 1 axi4_ch0_arready io96b0_to_hps_axi4_ch0_awready Input 1 axi4_ch0_awready io96b0_to_hps_axi4_ch0_bid Input 7 axi4_ch0_bid io96b0_to_hps_axi4_ch0_bresp Input 2 axi4_ch0_bresp io96b0_to_hps_axi4_ch0_bvalid Input 1 axi4_ch0_bvalid io96b0_to_hps_axi4_ch0_rdata Input 256 axi4_ch0_rdata io96b0_to_hps_axi4_ch0_rid Input 7 axi4_ch0_rid io96b0_to_hps_axi4_ch0_rlast Input 1 axi4_ch0_rlast io96b0_to_hps_axi4_ch0_rresp Input 2 axi4_ch0_rresp io96b0_to_hps_axi4_ch0_ruser Input 32 axi4_ch0_ruser io96b0_to_hps_axi4_ch0_rvalid Input 1 axi4_ch0_rvalid io96b0_to_hps_axi4_ch0_wready Input 1 axi4_ch0_wready io96b0_to_hps_axi4_ch0_araddr Output 40 axi4_ch0_araddr io96b0_to_hps_axi4_ch0_arburst Output 2 axi4_ch0_arburst io96b0_to_hps_axi4_ch0_arid Output 7 axi4_ch0_arid io96b0_to_hps_axi4_ch0_arlen Output 8 axi4_ch0_arlen io96b0_to_hps_axi4_ch0_arlock Output 1 axi4_ch0_arlock io96b0_to_hps_axi4_ch0_arqos Output 4 axi4_ch0_arqos io96b0_to_hps_axi4_ch0_arsize Output 3 axi4_ch0_arsize io96b0_to_hps_axi4_ch0_aruser Output 14 axi4_ch0_aruser io96b0_to_hps_axi4_ch0_arvalid Output 1 axi4_ch0_arvalid io96b0_to_hps_axi4_ch0_awaddr Output 40 axi4_ch0_awaddr io96b0_to_hps_axi4_ch0_awburst Output 2 axi4_ch0_awburst io96b0_to_hps_axi4_ch0_awid Output 7 axi4_ch0_awid io96b0_to_hps_axi4_ch0_awlen Output 8 axi4_ch0_awlen io96b0_to_hps_axi4_ch0_awlock Output 1 axi4_ch0_awlock io96b0_to_hps_axi4_ch0_awqos Output 4 axi4_ch0_awqos io96b0_to_hps_axi4_ch0_awsize Output 3 axi4_ch0_awsize io96b0_to_hps_axi4_ch0_awuser Output 14 axi4_ch0_awuser io96b0_to_hps_axi4_ch0_awvalid Output 1 axi4_ch0_awvalid io96b0_to_hps_axi4_ch0_bready Output 1 axi4_ch0_bready io96b0_to_hps_axi4_ch0_rready Output 1 axi4_ch0_rready io96b0_to_hps_axi4_ch0_wdata Output 256 axi4_ch0_wdata io96b0_to_hps_axi4_ch0_wlast Output 1 axi4_ch0_wlast io96b0_to_hps_axi4_ch0_wstrb Output 32 axi4_ch0_wstrb io96b0_to_hps_axi4_ch0_wuser Output 32 axi4_ch0_wuser io96b0_to_hps_axi4_ch0_wvalid Output 1 axi4_ch0_wvalid io96b0_to_hps_axi4_ch0_arprot Output 3 axi4_ch0_arprot io96b0_to_hps_axi4_ch0_awprot Output 3 axi4_ch0_awprot com.altera.qsys.blackboxmodule.definitions.ComponentDefinition io96b0_to_hps conduit false s0_noc_axi4lite_clock ch0_axil_clk Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_reset_n ch0_axil_reset_n Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_awaddr ch0_axil_awaddr Input 27 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_awvalid ch0_axil_awvalid Input 1 0 STD_LOGIC 0 s0_noc_axi4lite_awready ch0_axil_awready Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_araddr ch0_axil_araddr Input 27 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_arvalid ch0_axil_arvalid Input 1 0 STD_LOGIC 0 s0_noc_axi4lite_arready ch0_axil_arready Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_wdata ch0_axil_wdata Input 32 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_wvalid ch0_axil_wvalid Input 1 0 STD_LOGIC 0 s0_noc_axi4lite_wready ch0_axil_wready Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_rresp ch0_axil_rresp Output 2 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_rdata ch0_axil_rdata Output 32 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_rvalid ch0_axil_rvalid Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_rready ch0_axil_rready Input 1 0 STD_LOGIC 0 s0_noc_axi4lite_bresp ch0_axil_bresp Output 2 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_bvalid ch0_axil_bvalid Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_bready ch0_axil_bready Input 1 0 STD_LOGIC 0 s0_noc_axi4lite_awprot ch0_axil_awprot Input 3 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_arprot ch0_axil_arprot Input 3 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_wstrb ch0_axil_wstrb Input 4 0 STD_LOGIC_VECTOR 0 s0_axi4_awaddr axi4_ch0_awaddr Input 40 0 STD_LOGIC_VECTOR 0 s0_axi4_awburst axi4_ch0_awburst Input 2 0 STD_LOGIC_VECTOR 0 s0_axi4_awid axi4_ch0_awid Input 7 0 STD_LOGIC_VECTOR 0 s0_axi4_awlen axi4_ch0_awlen Input 8 0 STD_LOGIC_VECTOR 0 s0_axi4_awlock axi4_ch0_awlock Input 1 0 STD_LOGIC 0 s0_axi4_awqos axi4_ch0_awqos Input 4 0 STD_LOGIC_VECTOR 0 s0_axi4_awsize axi4_ch0_awsize Input 3 0 STD_LOGIC_VECTOR 0 s0_axi4_awvalid axi4_ch0_awvalid Input 1 0 STD_LOGIC 0 s0_axi4_awuser axi4_ch0_awuser Input 14 0 STD_LOGIC_VECTOR 0 s0_axi4_awprot axi4_ch0_awprot Input 3 0 STD_LOGIC_VECTOR 0 s0_axi4_awready axi4_ch0_awready Output 1 0 STD_LOGIC 0 s0_axi4_araddr axi4_ch0_araddr Input 40 0 STD_LOGIC_VECTOR 0 s0_axi4_arburst axi4_ch0_arburst Input 2 0 STD_LOGIC_VECTOR 0 s0_axi4_arid axi4_ch0_arid Input 7 0 STD_LOGIC_VECTOR 0 s0_axi4_arlen axi4_ch0_arlen Input 8 0 STD_LOGIC_VECTOR 0 s0_axi4_arlock axi4_ch0_arlock Input 1 0 STD_LOGIC 0 s0_axi4_arqos axi4_ch0_arqos Input 4 0 STD_LOGIC_VECTOR 0 s0_axi4_arsize axi4_ch0_arsize Input 3 0 STD_LOGIC_VECTOR 0 s0_axi4_arvalid axi4_ch0_arvalid Input 1 0 STD_LOGIC 0 s0_axi4_aruser axi4_ch0_aruser Input 14 0 STD_LOGIC_VECTOR 0 s0_axi4_arprot axi4_ch0_arprot Input 3 0 STD_LOGIC_VECTOR 0 s0_axi4_arready axi4_ch0_arready Output 1 0 STD_LOGIC 0 s0_axi4_wdata axi4_ch0_wdata Input 256 0 STD_LOGIC_VECTOR 0 s0_axi4_wstrb axi4_ch0_wstrb Input 32 0 STD_LOGIC_VECTOR 0 s0_axi4_wlast axi4_ch0_wlast Input 1 0 STD_LOGIC 0 s0_axi4_wvalid axi4_ch0_wvalid Input 1 0 STD_LOGIC 0 s0_axi4_wready axi4_ch0_wready Output 1 0 STD_LOGIC 0 s0_axi4_bready axi4_ch0_bready Input 1 0 STD_LOGIC 0 s0_axi4_bid axi4_ch0_bid Output 7 0 STD_LOGIC_VECTOR 0 s0_axi4_bresp axi4_ch0_bresp Output 2 0 STD_LOGIC_VECTOR 0 s0_axi4_bvalid axi4_ch0_bvalid Output 1 0 STD_LOGIC 0 s0_axi4_rready axi4_ch0_rready Input 1 0 STD_LOGIC 0 s0_axi4_rdata axi4_ch0_rdata Output 256 0 STD_LOGIC_VECTOR 0 s0_axi4_rid axi4_ch0_rid Output 7 0 STD_LOGIC_VECTOR 0 s0_axi4_rlast axi4_ch0_rlast Output 1 0 STD_LOGIC 0 s0_axi4_rresp axi4_ch0_rresp Output 2 0 STD_LOGIC_VECTOR 0 s0_axi4_rvalid axi4_ch0_rvalid Output 1 0 STD_LOGIC 0 noc_aclk_0 axi4_ch0_clk Output 1 0 STD_LOGIC 0 noc_rst_n_0 axi4_ch0_reset_n Output 1 0 STD_LOGIC 0 s0_axi4_wuser axi4_ch0_wuser Input 32 0 STD_LOGIC_VECTOR 0 s0_axi4_ruser axi4_ch0_ruser Output 32 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false mem_0 conduit false mem_0_cs mem_cs Output 1 0 STD_LOGIC_VECTOR 0 mem_0_ca mem_ca Output 6 0 STD_LOGIC_VECTOR 0 mem_0_cke mem_cke Output 1 0 STD_LOGIC_VECTOR 0 mem_0_dq mem_dq Bidir 32 0 STD_LOGIC_VECTOR 0 mem_0_dqs_t mem_dqs_t Bidir 4 0 STD_LOGIC_VECTOR 0 mem_0_dqs_c mem_dqs_c Bidir 4 0 STD_LOGIC_VECTOR 0 mem_0_dmi mem_dmi Bidir 4 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false mem_ck_0 conduit false mem_0_ck_t mem_ck_t Output 1 0 STD_LOGIC_VECTOR 0 mem_0_ck_c mem_ck_c Output 1 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false mem_reset_n conduit false mem_0_reset_n mem_reset_n Output 1 0 STD_LOGIC 0 associatedClock associatedReset prSafe false oct_0 conduit false oct_rzqin_0 oct_rzqin Input 1 0 STD_LOGIC 0 associatedClock associatedReset prSafe false ref_clk clock false ref_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName emif_io96b_hps 4.0.0 External Memory Interfaces for HPS IP SYSINFO_BOARD java.lang.String BOARD SYSINFO_BOARD_TRAIT java.lang.String BOARD_TRAIT SYSINFO_DEVICE java.lang.String DEVICE SYSINFO_DEVICE_BASE_DIE java.lang.String BASE_DEVICE PART_TRAIT SYSINFO_DEVICE_DIE_REVISIONS [Ljava.lang.String; DEVICE_DIE_REVISIONS SYSINFO_DEVICE_FAMILY java.lang.String DEVICE_FAMILY SYSINFO_DEVICE_GROUP [Ljava.lang.String; DEVICE_GROUP DEVICE_INFO SYSINFO_DEVICE_IOBANK_REVISION java.lang.String DEVICE_IOBANK_REVISION PART_TRAIT SYSINFO_DEVICE_POWER_MODEL java.lang.String DEVICE_POWER_MODEL PART_TRAIT SYSINFO_DEVICE_SPEEDGRADE java.lang.String DEVICE_SPEEDGRADE SYSINFO_DEVICE_TEMPERATURE_GRADE java.lang.String DEVICE_TEMPERATURE_GRADE PART_TRAIT SYSINFO_SUPPORTS_VID java.lang.String SUPPORTS_VID PART_TRAIT ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition emif_io96b_hps emif_io96b_hps emif_io96b_hps QUARTUS_SYNTH emif_io96b_hps emif_io96b_hps SIM_VERILOG emif_io96b_hps emif_io96b_hps SIM_VHDL emif_io96b_hps emif_io96b_hps CDC emif_io96b_hps emif_io96b_hps CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/qsys_top/emif_io96b_hps.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition io96b0_to_hps conduit false s0_noc_axi4lite_clock ch0_axil_clk Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_reset_n ch0_axil_reset_n Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_awaddr ch0_axil_awaddr Input 27 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_awvalid ch0_axil_awvalid Input 1 0 STD_LOGIC 0 s0_noc_axi4lite_awready ch0_axil_awready Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_araddr ch0_axil_araddr Input 27 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_arvalid ch0_axil_arvalid Input 1 0 STD_LOGIC 0 s0_noc_axi4lite_arready ch0_axil_arready Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_wdata ch0_axil_wdata Input 32 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_wvalid ch0_axil_wvalid Input 1 0 STD_LOGIC 0 s0_noc_axi4lite_wready ch0_axil_wready Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_rresp ch0_axil_rresp Output 2 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_rdata ch0_axil_rdata Output 32 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_rvalid ch0_axil_rvalid Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_rready ch0_axil_rready Input 1 0 STD_LOGIC 0 s0_noc_axi4lite_bresp ch0_axil_bresp Output 2 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_bvalid ch0_axil_bvalid Output 1 0 STD_LOGIC 0 s0_noc_axi4lite_bready ch0_axil_bready Input 1 0 STD_LOGIC 0 s0_noc_axi4lite_awprot ch0_axil_awprot Input 3 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_arprot ch0_axil_arprot Input 3 0 STD_LOGIC_VECTOR 0 s0_noc_axi4lite_wstrb ch0_axil_wstrb Input 4 0 STD_LOGIC_VECTOR 0 s0_axi4_awaddr axi4_ch0_awaddr Input 40 0 STD_LOGIC_VECTOR 0 s0_axi4_awburst axi4_ch0_awburst Input 2 0 STD_LOGIC_VECTOR 0 s0_axi4_awid axi4_ch0_awid Input 7 0 STD_LOGIC_VECTOR 0 s0_axi4_awlen axi4_ch0_awlen Input 8 0 STD_LOGIC_VECTOR 0 s0_axi4_awlock axi4_ch0_awlock Input 1 0 STD_LOGIC 0 s0_axi4_awqos axi4_ch0_awqos Input 4 0 STD_LOGIC_VECTOR 0 s0_axi4_awsize axi4_ch0_awsize Input 3 0 STD_LOGIC_VECTOR 0 s0_axi4_awvalid axi4_ch0_awvalid Input 1 0 STD_LOGIC 0 s0_axi4_awuser axi4_ch0_awuser Input 14 0 STD_LOGIC_VECTOR 0 s0_axi4_awprot axi4_ch0_awprot Input 3 0 STD_LOGIC_VECTOR 0 s0_axi4_awready axi4_ch0_awready Output 1 0 STD_LOGIC 0 s0_axi4_araddr axi4_ch0_araddr Input 40 0 STD_LOGIC_VECTOR 0 s0_axi4_arburst axi4_ch0_arburst Input 2 0 STD_LOGIC_VECTOR 0 s0_axi4_arid axi4_ch0_arid Input 7 0 STD_LOGIC_VECTOR 0 s0_axi4_arlen axi4_ch0_arlen Input 8 0 STD_LOGIC_VECTOR 0 s0_axi4_arlock axi4_ch0_arlock Input 1 0 STD_LOGIC 0 s0_axi4_arqos axi4_ch0_arqos Input 4 0 STD_LOGIC_VECTOR 0 s0_axi4_arsize axi4_ch0_arsize Input 3 0 STD_LOGIC_VECTOR 0 s0_axi4_arvalid axi4_ch0_arvalid Input 1 0 STD_LOGIC 0 s0_axi4_aruser axi4_ch0_aruser Input 14 0 STD_LOGIC_VECTOR 0 s0_axi4_arprot axi4_ch0_arprot Input 3 0 STD_LOGIC_VECTOR 0 s0_axi4_arready axi4_ch0_arready Output 1 0 STD_LOGIC 0 s0_axi4_wdata axi4_ch0_wdata Input 256 0 STD_LOGIC_VECTOR 0 s0_axi4_wstrb axi4_ch0_wstrb Input 32 0 STD_LOGIC_VECTOR 0 s0_axi4_wlast axi4_ch0_wlast Input 1 0 STD_LOGIC 0 s0_axi4_wvalid axi4_ch0_wvalid Input 1 0 STD_LOGIC 0 s0_axi4_wready axi4_ch0_wready Output 1 0 STD_LOGIC 0 s0_axi4_bready axi4_ch0_bready Input 1 0 STD_LOGIC 0 s0_axi4_bid axi4_ch0_bid Output 7 0 STD_LOGIC_VECTOR 0 s0_axi4_bresp axi4_ch0_bresp Output 2 0 STD_LOGIC_VECTOR 0 s0_axi4_bvalid axi4_ch0_bvalid Output 1 0 STD_LOGIC 0 s0_axi4_rready axi4_ch0_rready Input 1 0 STD_LOGIC 0 s0_axi4_rdata axi4_ch0_rdata Output 256 0 STD_LOGIC_VECTOR 0 s0_axi4_rid axi4_ch0_rid Output 7 0 STD_LOGIC_VECTOR 0 s0_axi4_rlast axi4_ch0_rlast Output 1 0 STD_LOGIC 0 s0_axi4_rresp axi4_ch0_rresp Output 2 0 STD_LOGIC_VECTOR 0 s0_axi4_rvalid axi4_ch0_rvalid Output 1 0 STD_LOGIC 0 noc_aclk_0 axi4_ch0_clk Output 1 0 STD_LOGIC 0 noc_rst_n_0 axi4_ch0_reset_n Output 1 0 STD_LOGIC 0 s0_axi4_wuser axi4_ch0_wuser Input 32 0 STD_LOGIC_VECTOR 0 s0_axi4_ruser axi4_ch0_ruser Output 32 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false mem_0 conduit false mem_0_cs mem_cs Output 1 0 STD_LOGIC_VECTOR 0 mem_0_ca mem_ca Output 6 0 STD_LOGIC_VECTOR 0 mem_0_cke mem_cke Output 1 0 STD_LOGIC_VECTOR 0 mem_0_dq mem_dq Bidir 32 0 STD_LOGIC_VECTOR 0 mem_0_dqs_t mem_dqs_t Bidir 4 0 STD_LOGIC_VECTOR 0 mem_0_dqs_c mem_dqs_c Bidir 4 0 STD_LOGIC_VECTOR 0 mem_0_dmi mem_dmi Bidir 4 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false mem_ck_0 conduit false mem_0_ck_t mem_ck_t Output 1 0 STD_LOGIC_VECTOR 0 mem_0_ck_c mem_ck_c Output 1 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false mem_reset_n conduit false mem_0_reset_n mem_reset_n Output 1 0 STD_LOGIC 0 associatedClock associatedReset prSafe false oct_0 conduit false oct_rzqin_0 oct_rzqin Input 1 0 STD_LOGIC 0 associatedClock associatedReset prSafe false ref_clk clock false ref_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList ]]> false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition 1 emif_io96b_hps Agilex 5 false ]]> false true false true java.lang.Boolean false true false true java.lang.String false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.String default true true false true BOARD java.lang.String true true false true BOARD_TRAIT java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String SM4REVB true true false true PART_TRAIT BASE_DEVICE [Ljava.lang.String; MAIN_SM4_REVB true true false true DEVICE_DIE_REVISIONS java.lang.String Agilex 5 true true false true DEVICE_FAMILY [Ljava.lang.String; B true true false true DEVICE_INFO DEVICE_GROUP java.lang.String IO96B_REVB1 true true false true PART_TRAIT DEVICE_IOBANK_REVISION java.lang.String STANDARD_POWER_FIXED true true false true PART_TRAIT DEVICE_POWER_MODEL java.lang.String 4 true true false true DEVICE_SPEEDGRADE java.lang.String EXTENDED true true false true PART_TRAIT DEVICE_TEMPERATURE_GRADE java.lang.String 0 true true false true PART_TRAIT SUPPORTS_VID java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false s0_noc_axi4lite_clock Output 1 ch0_axil_clk s0_noc_axi4lite_reset_n Output 1 ch0_axil_reset_n s0_noc_axi4lite_awaddr Input 27 ch0_axil_awaddr s0_noc_axi4lite_awvalid Input 1 ch0_axil_awvalid s0_noc_axi4lite_awready Output 1 ch0_axil_awready s0_noc_axi4lite_araddr Input 27 ch0_axil_araddr s0_noc_axi4lite_arvalid Input 1 ch0_axil_arvalid s0_noc_axi4lite_arready Output 1 ch0_axil_arready s0_noc_axi4lite_wdata Input 32 ch0_axil_wdata s0_noc_axi4lite_wvalid Input 1 ch0_axil_wvalid s0_noc_axi4lite_wready Output 1 ch0_axil_wready s0_noc_axi4lite_rresp Output 2 ch0_axil_rresp s0_noc_axi4lite_rdata Output 32 ch0_axil_rdata s0_noc_axi4lite_rvalid Output 1 ch0_axil_rvalid s0_noc_axi4lite_rready Input 1 ch0_axil_rready s0_noc_axi4lite_bresp Output 2 ch0_axil_bresp s0_noc_axi4lite_bvalid Output 1 ch0_axil_bvalid s0_noc_axi4lite_bready Input 1 ch0_axil_bready s0_noc_axi4lite_awprot Input 3 ch0_axil_awprot s0_noc_axi4lite_arprot Input 3 ch0_axil_arprot s0_noc_axi4lite_wstrb Input 4 ch0_axil_wstrb s0_axi4_awaddr Input 40 axi4_ch0_awaddr s0_axi4_awburst Input 2 axi4_ch0_awburst s0_axi4_awid Input 7 axi4_ch0_awid s0_axi4_awlen Input 8 axi4_ch0_awlen s0_axi4_awlock Input 1 axi4_ch0_awlock s0_axi4_awqos Input 4 axi4_ch0_awqos s0_axi4_awsize Input 3 axi4_ch0_awsize s0_axi4_awvalid Input 1 axi4_ch0_awvalid s0_axi4_awuser Input 14 axi4_ch0_awuser s0_axi4_awprot Input 3 axi4_ch0_awprot s0_axi4_awready Output 1 axi4_ch0_awready s0_axi4_araddr Input 40 axi4_ch0_araddr s0_axi4_arburst Input 2 axi4_ch0_arburst s0_axi4_arid Input 7 axi4_ch0_arid s0_axi4_arlen Input 8 axi4_ch0_arlen s0_axi4_arlock Input 1 axi4_ch0_arlock s0_axi4_arqos Input 4 axi4_ch0_arqos s0_axi4_arsize Input 3 axi4_ch0_arsize s0_axi4_arvalid Input 1 axi4_ch0_arvalid s0_axi4_aruser Input 14 axi4_ch0_aruser s0_axi4_arprot Input 3 axi4_ch0_arprot s0_axi4_arready Output 1 axi4_ch0_arready s0_axi4_wdata Input 256 axi4_ch0_wdata s0_axi4_wstrb Input 32 axi4_ch0_wstrb s0_axi4_wlast Input 1 axi4_ch0_wlast s0_axi4_wvalid Input 1 axi4_ch0_wvalid s0_axi4_wready Output 1 axi4_ch0_wready s0_axi4_bready Input 1 axi4_ch0_bready s0_axi4_bid Output 7 axi4_ch0_bid s0_axi4_bresp Output 2 axi4_ch0_bresp s0_axi4_bvalid Output 1 axi4_ch0_bvalid s0_axi4_rready Input 1 axi4_ch0_rready s0_axi4_rdata Output 256 axi4_ch0_rdata s0_axi4_rid Output 7 axi4_ch0_rid s0_axi4_rlast Output 1 axi4_ch0_rlast s0_axi4_rresp Output 2 axi4_ch0_rresp s0_axi4_rvalid Output 1 axi4_ch0_rvalid noc_aclk_0 Output 1 axi4_ch0_clk noc_rst_n_0 Output 1 axi4_ch0_reset_n s0_axi4_wuser Input 32 axi4_ch0_wuser s0_axi4_ruser Output 32 axi4_ch0_ruser java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false mem_0_cs Output 1 mem_cs mem_0_ca Output 6 mem_ca mem_0_cke Output 1 mem_cke mem_0_dq Bidir 32 mem_dq mem_0_dqs_t Bidir 4 mem_dqs_t mem_0_dqs_c Bidir 4 mem_dqs_c mem_0_dmi Bidir 4 mem_dmi java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false mem_0_ck_t Output 1 mem_ck_t mem_0_ck_c Output 1 mem_ck_c java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false mem_0_reset_n Output 1 mem_reset_n java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false oct_rzqin_0 Input 1 oct_rzqin boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock 0 false ref_clk Input 1 clk java.lang.Integer 0 false true false true GENERATION_ID java.lang.String qsys_top_subsys_periph false true false true UNIQUE_ID java.lang.String Agilex 5 false true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS false true false true DEVICE java.lang.String 4 false true false true DEVICE_SPEEDGRADE java.lang.String default false true false true BOARD java.lang.String false true false true CPU_INFO_ID pb_cpu_0_s0 java.lang.Long 100000000 false true false true CLOCK_RATE clk java.lang.Integer 1 false true false true CLOCK_DOMAIN clk java.lang.Integer 1 false true false true RESET_DOMAIN clk java.lang.String Agilex 5 false true false true DEVICE_FAMILY boolean false false true true true java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false button_pio_external_connection_export Input 4 export embeddedsw.dts.irq.tx_type RISING_EDGE com.altera.entityinterfaces.IConnectionPoint subsys_periph.pb_cpu_0_s0 false true false true java.lang.String clk false true false true java.lang.String reset false true false true java.lang.Integer 0 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt 0 false button_pio_irq_irq Output 1 irq java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false dipsw_pio_external_connection_export Input 4 export embeddedsw.dts.irq.tx_type RISING_EDGE com.altera.entityinterfaces.IConnectionPoint subsys_periph.pb_cpu_0_s0 false true false true java.lang.String clk false true false true java.lang.String reset false true false true java.lang.Integer 0 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt 0 false dipsw_pio_irq_irq Output 1 irq java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false led_pio_external_connection_in_port Input 3 in_port led_pio_external_connection_out_port Output 3 out_port embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment DYNAMIC false true false true int 0 false true true true java.math.BigInteger 131072 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits SYMBOLS false true true true boolean false false true false true java.lang.String clk false true true true java.lang.String reset false true true true int 8 false true true true java.math.BigInteger 0 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false false true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 1 false true true true int 0 false false true true int 1 false true false true int 1 false true true true int 1 false true false true boolean false false true false true boolean false false true false true int 0 false false true true int 0 false true false true int 0 false false true true boolean false false true false true boolean false false true false true int 0 false false true true com.altera.sopcmodel.avalon.TimingUnits Cycles false false true true boolean false false true true true int 0 false true true true int 1024 false false false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false false true true java.math.BigInteger 0 false true true true java.lang.Integer 0 false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true java.lang.Integer 35 false true true true java.lang.Integer 3 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon 131072 false pb_cpu_0_s0_waitrequest Output 1 waitrequest pb_cpu_0_s0_readdata Output 32 readdata pb_cpu_0_s0_readdatavalid Output 1 readdatavalid pb_cpu_0_s0_burstcount Input 1 burstcount pb_cpu_0_s0_writedata Input 32 writedata pb_cpu_0_s0_address Input 17 address pb_cpu_0_s0_write Input 1 write pb_cpu_0_s0_read Input 1 read pb_cpu_0_s0_byteenable Input 4 byteenable pb_cpu_0_s0_debugaccess Input 1 debugaccess boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 100000000 true true false true clock 0 false clk_clk Input 1 clk java.lang.String false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false reset_reset_n Input 1 reset_n embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER 1 embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER 0 embeddedsw.CMacro.CAPTURE 1 embeddedsw.CMacro.DATA_WIDTH 4 embeddedsw.CMacro.DO_TEST_BENCH_WIRING 0 embeddedsw.CMacro.DRIVEN_SIM_VALUE 0 embeddedsw.CMacro.EDGE_TYPE FALLING embeddedsw.CMacro.FREQ 100000000 embeddedsw.CMacro.HAS_IN 1 embeddedsw.CMacro.HAS_OUT 0 embeddedsw.CMacro.HAS_TRI 0 embeddedsw.CMacro.IRQ_TYPE EDGE embeddedsw.CMacro.RESET_VALUE 0 embeddedsw.dts.compatible altr,pio-1.0 embeddedsw.dts.group gpio embeddedsw.dts.name pio embeddedsw.dts.params.altr,gpio-bank-width 4 embeddedsw.dts.params.altr,interrupt-type 2 embeddedsw.dts.params.altr,interrupt_type 2 embeddedsw.dts.params.edge_type 1 embeddedsw.dts.params.level_trigger 0 embeddedsw.dts.params.resetvalue 0 embeddedsw.dts.vendor altr com.altera.qsys.blackboxmodule.definitions.ComponentDefinition clk clock false clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName reset reset false reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock clk synchronousEdges DEASSERT s1 avalon false address address Input 2 0 STD_LOGIC_VECTOR 0 write_n write_n Input 1 0 STD_LOGIC 0 writedata writedata Input 32 0 STD_LOGIC_VECTOR 0 chipselect chipselect Input 1 0 STD_LOGIC 0 readdata readdata Output 32 0 STD_LOGIC_VECTOR 0 embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 addressAlignment NATIVE addressGroup 0 addressSpan 4 addressUnits WORDS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 bridgedAddressOffset 0 bridgesToMaster burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false explicitAddressSpan 0 holdTime 0 interleaveBursts false isBigEndian false isFlash false isMemoryDevice false isNonVolatileStorage false linewrapBursts false maximumPendingReadTransactions 0 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 minimumUninterruptedRunLength 1 prSafe false printableDevice false readLatency 0 readWaitStates 1 readWaitTime 1 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles transparentBridge false waitrequestAllowance 0 waitrequestTimeout 1024 wellBehavedWaitrequest false writeLatency 0 writeWaitStates 0 writeWaitTime 0 dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 external_connection conduit false in_port export Input 4 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false irq interrupt false irq irq Output 1 0 STD_LOGIC 0 embeddedsw.dts.irq.tx_type RISING_EDGE associatedAddressablePoint button_pio.s1 associatedClock clk associatedReset reset bridgedReceiverOffset 0 bridgesToReceiver irqScheme NONE altera_avalon_pio 19.2.3 PIO (Parallel I/O) Intel FPGA IP DEVICE_FAMILY java.lang.String DEVICE_FAMILY 0 clockRate java.lang.Long clk CLOCK_RATE clk clk CLOCK_RATE 100000000 s1 s1 ADDRESS_MAP <address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map> ADDRESS_WIDTH 4 MAX_SLAVE_DATA_WIDTH 32 ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition button_pio QUARTUS_SYNTH button_pio QUARTUS_SYNTH SIM_VERILOG button_pio SIM_VERILOG SIM_VHDL button_pio SIM_VHDL CDC button_pio CDC CDC_VHDL button_pio CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/peripheral_subsys/button_pio.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition clk clock false clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName reset reset false reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock clk synchronousEdges DEASSERT s1 avalon false address address Input 2 0 STD_LOGIC_VECTOR 0 write_n write_n Input 1 0 STD_LOGIC 0 writedata writedata Input 32 0 STD_LOGIC_VECTOR 0 chipselect chipselect Input 1 0 STD_LOGIC 0 readdata readdata Output 32 0 STD_LOGIC_VECTOR 0 embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 addressAlignment NATIVE addressGroup 0 addressSpan 4 addressUnits WORDS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 bridgedAddressOffset 0 bridgesToMaster burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false explicitAddressSpan 0 holdTime 0 interleaveBursts false isBigEndian false isFlash false isMemoryDevice false isNonVolatileStorage false linewrapBursts false maximumPendingReadTransactions 0 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 minimumUninterruptedRunLength 1 prSafe false printableDevice false readLatency 0 readWaitStates 1 readWaitTime 1 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles transparentBridge false waitrequestAllowance 0 waitrequestTimeout 1024 wellBehavedWaitrequest false writeLatency 0 writeWaitStates 0 writeWaitTime 0 dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 <?xml version="1.0" encoding="utf-8"?> <device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > <peripherals> <peripheral> <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress> <addressBlock> <offset>0x0</offset> <size>32</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>DATA</name> <displayName>Data</displayName> <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description> <addressOffset>0x0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>data</name> <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DIRECTION</name> <displayName>Direction</displayName> <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description> <addressOffset>0x4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>direction</name> <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>IRQ_MASK</name> <displayName>Interrupt mask</displayName> <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description> <addressOffset>0x8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>interruptmask</name> <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>EDGE_CAP</name> <displayName>Edge capture</displayName> <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description> <addressOffset>0xc</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>edgecapture</name> <description>Edge detection for each input port.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>SET_BIT</name> <displayName>Outset</displayName> <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> <addressOffset>0x10</addressOffset> <size>32</size> <access>write-only</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>outset</name> <description>Specifies which bit of the output port to set.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>write-only</access> </field> </fields> </register> <register> <name>CLEAR_BITS</name> <displayName>Outclear</displayName> <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> <addressOffset>0x14</addressOffset> <size>32</size> <access>write-only</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>outclear</name> <description>Specifies which output bit to clear.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>write-only</access> </field> </fields> </register> </registers> </peripheral> </peripherals> </device> external_connection conduit false in_port export Input 4 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false irq interrupt false irq irq Output 1 0 STD_LOGIC 0 embeddedsw.dts.irq.tx_type RISING_EDGE associatedAddressablePoint button_pio.s1 associatedClock clk associatedReset reset bridgedReceiverOffset 0 bridgesToReceiver irqScheme NONE ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER 1 embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER 0 embeddedsw.CMacro.CAPTURE 1 embeddedsw.CMacro.DATA_WIDTH 4 embeddedsw.CMacro.DO_TEST_BENCH_WIRING 0 embeddedsw.CMacro.DRIVEN_SIM_VALUE 0 embeddedsw.CMacro.EDGE_TYPE FALLING embeddedsw.CMacro.FREQ 100000000 embeddedsw.CMacro.HAS_IN 1 embeddedsw.CMacro.HAS_OUT 0 embeddedsw.CMacro.HAS_TRI 0 embeddedsw.CMacro.IRQ_TYPE EDGE embeddedsw.CMacro.RESET_VALUE 0 embeddedsw.dts.compatible altr,pio-1.0 embeddedsw.dts.group gpio embeddedsw.dts.name pio embeddedsw.dts.params.altr,gpio-bank-width 4 embeddedsw.dts.params.altr,interrupt-type 2 embeddedsw.dts.params.altr,interrupt_type 2 embeddedsw.dts.params.edge_type 1 embeddedsw.dts.params.level_trigger 0 embeddedsw.dts.params.resetvalue 0 embeddedsw.dts.vendor altr ]]> false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition false true false true java.lang.Boolean false false true false true java.lang.String altera_avalon_pio_inst false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.Long 100000000 true true false true CLOCK_RATE clk java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 100000000 true true false true clock 0 false clk Input 1 clk java.lang.String clk false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false reset_n Input 1 reset_n embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment NATIVE false true false true int 0 false true true true java.math.BigInteger 4 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.lang.String clk false true true true java.lang.String reset false true true true int 8 false true true true java.math.BigInteger 0 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 0 false false true true int 0 false false true true int 1 false true false true int 1 false false true true int 1 false true false true boolean false false true false true boolean false false true false true int 0 false true true true int 1 false true false true int 1 false true true true boolean false false true false true boolean false false true false true int 0 false true true true com.altera.sopcmodel.avalon.TimingUnits Cycles false true true true boolean false false true true true int 0 false false true true int 1024 false true false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false true true true java.math.BigInteger 0 false true true true java.lang.Integer 0 false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true java.lang.Integer 35 false true true true java.lang.Integer 3 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon 16 false address Input 2 address write_n Input 1 write_n writedata Input 32 writedata chipselect Input 1 chipselect readdata Output 32 readdata java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false in_port Input 4 export embeddedsw.dts.irq.tx_type RISING_EDGE com.altera.entityinterfaces.IConnectionPoint button_pio.s1 false true false true java.lang.String clk false true false true java.lang.String reset false true false true java.lang.Integer 0 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt 0 false irq Output 1 irq embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER 1 embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER 0 embeddedsw.CMacro.CAPTURE 1 embeddedsw.CMacro.DATA_WIDTH 4 embeddedsw.CMacro.DO_TEST_BENCH_WIRING 0 embeddedsw.CMacro.DRIVEN_SIM_VALUE 0 embeddedsw.CMacro.EDGE_TYPE FALLING embeddedsw.CMacro.FREQ 100000000 embeddedsw.CMacro.HAS_IN 1 embeddedsw.CMacro.HAS_OUT 0 embeddedsw.CMacro.HAS_TRI 0 embeddedsw.CMacro.IRQ_TYPE EDGE embeddedsw.CMacro.RESET_VALUE 0 embeddedsw.dts.compatible altr,pio-1.0 embeddedsw.dts.group gpio embeddedsw.dts.name pio embeddedsw.dts.params.altr,gpio-bank-width 4 embeddedsw.dts.params.altr,interrupt-type 2 embeddedsw.dts.params.altr,interrupt_type 2 embeddedsw.dts.params.edge_type 1 embeddedsw.dts.params.level_trigger 0 embeddedsw.dts.params.resetvalue 0 embeddedsw.dts.vendor altr com.altera.qsys.blackboxmodule.definitions.ComponentDefinition clk clock false clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName reset reset false reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock clk synchronousEdges DEASSERT s1 avalon false address address Input 2 0 STD_LOGIC_VECTOR 0 write_n write_n Input 1 0 STD_LOGIC 0 writedata writedata Input 32 0 STD_LOGIC_VECTOR 0 chipselect chipselect Input 1 0 STD_LOGIC 0 readdata readdata Output 32 0 STD_LOGIC_VECTOR 0 embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 addressAlignment NATIVE addressGroup 0 addressSpan 4 addressUnits WORDS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 bridgedAddressOffset 0 bridgesToMaster burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false explicitAddressSpan 0 holdTime 0 interleaveBursts false isBigEndian false isFlash false isMemoryDevice false isNonVolatileStorage false linewrapBursts false maximumPendingReadTransactions 0 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 minimumUninterruptedRunLength 1 prSafe false printableDevice false readLatency 0 readWaitStates 1 readWaitTime 1 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles transparentBridge false waitrequestAllowance 0 waitrequestTimeout 1024 wellBehavedWaitrequest false writeLatency 0 writeWaitStates 0 writeWaitTime 0 dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 external_connection conduit false in_port export Input 4 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false irq interrupt false irq irq Output 1 0 STD_LOGIC 0 embeddedsw.dts.irq.tx_type RISING_EDGE associatedAddressablePoint dipsw_pio.s1 associatedClock clk associatedReset reset bridgedReceiverOffset 0 bridgesToReceiver irqScheme NONE altera_avalon_pio 19.2.3 PIO (Parallel I/O) Intel FPGA IP DEVICE_FAMILY java.lang.String DEVICE_FAMILY 0 clockRate java.lang.Long clk CLOCK_RATE clk clk CLOCK_RATE 100000000 s1 s1 ADDRESS_MAP <address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map> ADDRESS_WIDTH 4 MAX_SLAVE_DATA_WIDTH 32 ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition dipsw_pio QUARTUS_SYNTH dipsw_pio QUARTUS_SYNTH SIM_VERILOG dipsw_pio SIM_VERILOG SIM_VHDL dipsw_pio SIM_VHDL CDC dipsw_pio CDC CDC_VHDL dipsw_pio CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/peripheral_subsys/dipsw_pio.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition clk clock false clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName reset reset false reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock clk synchronousEdges DEASSERT s1 avalon false address address Input 2 0 STD_LOGIC_VECTOR 0 write_n write_n Input 1 0 STD_LOGIC 0 writedata writedata Input 32 0 STD_LOGIC_VECTOR 0 chipselect chipselect Input 1 0 STD_LOGIC 0 readdata readdata Output 32 0 STD_LOGIC_VECTOR 0 embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 addressAlignment NATIVE addressGroup 0 addressSpan 4 addressUnits WORDS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 bridgedAddressOffset 0 bridgesToMaster burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false explicitAddressSpan 0 holdTime 0 interleaveBursts false isBigEndian false isFlash false isMemoryDevice false isNonVolatileStorage false linewrapBursts false maximumPendingReadTransactions 0 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 minimumUninterruptedRunLength 1 prSafe false printableDevice false readLatency 0 readWaitStates 1 readWaitTime 1 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles transparentBridge false waitrequestAllowance 0 waitrequestTimeout 1024 wellBehavedWaitrequest false writeLatency 0 writeWaitStates 0 writeWaitTime 0 dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 <?xml version="1.0" encoding="utf-8"?> <device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > <peripherals> <peripheral> <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress> <addressBlock> <offset>0x0</offset> <size>32</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>DATA</name> <displayName>Data</displayName> <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description> <addressOffset>0x0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>data</name> <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DIRECTION</name> <displayName>Direction</displayName> <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description> <addressOffset>0x4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>direction</name> <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>IRQ_MASK</name> <displayName>Interrupt mask</displayName> <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description> <addressOffset>0x8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>interruptmask</name> <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>EDGE_CAP</name> <displayName>Edge capture</displayName> <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description> <addressOffset>0xc</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>edgecapture</name> <description>Edge detection for each input port.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>SET_BIT</name> <displayName>Outset</displayName> <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> <addressOffset>0x10</addressOffset> <size>32</size> <access>write-only</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>outset</name> <description>Specifies which bit of the output port to set.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>write-only</access> </field> </fields> </register> <register> <name>CLEAR_BITS</name> <displayName>Outclear</displayName> <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> <addressOffset>0x14</addressOffset> <size>32</size> <access>write-only</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>outclear</name> <description>Specifies which output bit to clear.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>write-only</access> </field> </fields> </register> </registers> </peripheral> </peripherals> </device> external_connection conduit false in_port export Input 4 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false irq interrupt false irq irq Output 1 0 STD_LOGIC 0 embeddedsw.dts.irq.tx_type RISING_EDGE associatedAddressablePoint dipsw_pio.s1 associatedClock clk associatedReset reset bridgedReceiverOffset 0 bridgesToReceiver irqScheme NONE ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER 1 embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER 0 embeddedsw.CMacro.CAPTURE 1 embeddedsw.CMacro.DATA_WIDTH 4 embeddedsw.CMacro.DO_TEST_BENCH_WIRING 0 embeddedsw.CMacro.DRIVEN_SIM_VALUE 0 embeddedsw.CMacro.EDGE_TYPE FALLING embeddedsw.CMacro.FREQ 100000000 embeddedsw.CMacro.HAS_IN 1 embeddedsw.CMacro.HAS_OUT 0 embeddedsw.CMacro.HAS_TRI 0 embeddedsw.CMacro.IRQ_TYPE EDGE embeddedsw.CMacro.RESET_VALUE 0 embeddedsw.dts.compatible altr,pio-1.0 embeddedsw.dts.group gpio embeddedsw.dts.name pio embeddedsw.dts.params.altr,gpio-bank-width 4 embeddedsw.dts.params.altr,interrupt-type 2 embeddedsw.dts.params.altr,interrupt_type 2 embeddedsw.dts.params.edge_type 1 embeddedsw.dts.params.level_trigger 0 embeddedsw.dts.params.resetvalue 0 embeddedsw.dts.vendor altr ]]> false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition false true false true java.lang.Boolean false false true false true java.lang.String altera_avalon_pio_inst false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.Long 100000000 true true false true CLOCK_RATE clk java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 100000000 true true false true clock 0 false clk Input 1 clk java.lang.String clk false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false reset_n Input 1 reset_n embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment NATIVE false true false true int 0 false true true true java.math.BigInteger 4 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.lang.String clk false true true true java.lang.String reset false true true true int 8 false true true true java.math.BigInteger 0 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 0 false false true true int 0 false false true true int 1 false true false true int 1 false false true true int 1 false true false true boolean false false true false true boolean false false true false true int 0 false true true true int 1 false true false true int 1 false true true true boolean false false true false true boolean false false true false true int 0 false true true true com.altera.sopcmodel.avalon.TimingUnits Cycles false true true true boolean false false true true true int 0 false false true true int 1024 false true false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false true true true java.math.BigInteger 0 false true true true java.lang.Integer 0 false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true java.lang.Integer 35 false true true true java.lang.Integer 3 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon 16 false address Input 2 address write_n Input 1 write_n writedata Input 32 writedata chipselect Input 1 chipselect readdata Output 32 readdata java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false in_port Input 4 export embeddedsw.dts.irq.tx_type RISING_EDGE com.altera.entityinterfaces.IConnectionPoint dipsw_pio.s1 false true false true java.lang.String clk false true false true java.lang.String reset false true false true java.lang.Integer 0 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt 0 false irq Output 1 irq embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER 0 embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER 0 embeddedsw.CMacro.CAPTURE 0 embeddedsw.CMacro.DATA_WIDTH 3 embeddedsw.CMacro.DO_TEST_BENCH_WIRING 0 embeddedsw.CMacro.DRIVEN_SIM_VALUE 0 embeddedsw.CMacro.EDGE_TYPE NONE embeddedsw.CMacro.FREQ 100000000 embeddedsw.CMacro.HAS_IN 1 embeddedsw.CMacro.HAS_OUT 1 embeddedsw.CMacro.HAS_TRI 0 embeddedsw.CMacro.IRQ_TYPE NONE embeddedsw.CMacro.RESET_VALUE 7 embeddedsw.dts.compatible altr,pio-1.0 embeddedsw.dts.group gpio embeddedsw.dts.name pio embeddedsw.dts.params.altr,gpio-bank-width 3 embeddedsw.dts.params.resetvalue 7 embeddedsw.dts.vendor altr com.altera.qsys.blackboxmodule.definitions.ComponentDefinition clk clock false clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName reset reset false reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock clk synchronousEdges DEASSERT s1 avalon false address address Input 2 0 STD_LOGIC_VECTOR 0 write_n write_n Input 1 0 STD_LOGIC 0 writedata writedata Input 32 0 STD_LOGIC_VECTOR 0 chipselect chipselect Input 1 0 STD_LOGIC 0 readdata readdata Output 32 0 STD_LOGIC_VECTOR 0 embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 addressAlignment NATIVE addressGroup 0 addressSpan 4 addressUnits WORDS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 bridgedAddressOffset 0 bridgesToMaster burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false explicitAddressSpan 0 holdTime 0 interleaveBursts false isBigEndian false isFlash false isMemoryDevice false isNonVolatileStorage false linewrapBursts false maximumPendingReadTransactions 0 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 minimumUninterruptedRunLength 1 prSafe false printableDevice false readLatency 0 readWaitStates 1 readWaitTime 1 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles transparentBridge false waitrequestAllowance 0 waitrequestTimeout 1024 wellBehavedWaitrequest false writeLatency 0 writeWaitStates 0 writeWaitTime 0 dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 external_connection conduit false in_port in_port Input 3 0 STD_LOGIC_VECTOR 0 out_port out_port Output 3 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false altera_avalon_pio 19.2.3 PIO (Parallel I/O) Intel FPGA IP DEVICE_FAMILY java.lang.String DEVICE_FAMILY 0 clockRate java.lang.Long clk CLOCK_RATE clk clk CLOCK_RATE 100000000 s1 s1 ADDRESS_MAP <address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map> ADDRESS_WIDTH 4 MAX_SLAVE_DATA_WIDTH 32 ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition led_pio QUARTUS_SYNTH led_pio QUARTUS_SYNTH SIM_VERILOG led_pio SIM_VERILOG SIM_VHDL led_pio SIM_VHDL CDC led_pio CDC CDC_VHDL led_pio CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/peripheral_subsys/led_pio.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition clk clock false clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName reset reset false reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock clk synchronousEdges DEASSERT s1 avalon false address address Input 2 0 STD_LOGIC_VECTOR 0 write_n write_n Input 1 0 STD_LOGIC 0 writedata writedata Input 32 0 STD_LOGIC_VECTOR 0 chipselect chipselect Input 1 0 STD_LOGIC 0 readdata readdata Output 32 0 STD_LOGIC_VECTOR 0 embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 addressAlignment NATIVE addressGroup 0 addressSpan 4 addressUnits WORDS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 bridgedAddressOffset 0 bridgesToMaster burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false explicitAddressSpan 0 holdTime 0 interleaveBursts false isBigEndian false isFlash false isMemoryDevice false isNonVolatileStorage false linewrapBursts false maximumPendingReadTransactions 0 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 minimumUninterruptedRunLength 1 prSafe false printableDevice false readLatency 0 readWaitStates 1 readWaitTime 1 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles transparentBridge false waitrequestAllowance 0 waitrequestTimeout 1024 wellBehavedWaitrequest false writeLatency 0 writeWaitStates 0 writeWaitTime 0 dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 <?xml version="1.0" encoding="utf-8"?> <device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > <peripherals> <peripheral> <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress> <addressBlock> <offset>0x0</offset> <size>32</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>DATA</name> <displayName>Data</displayName> <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description> <addressOffset>0x0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>data</name> <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DIRECTION</name> <displayName>Direction</displayName> <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description> <addressOffset>0x4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>direction</name> <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>IRQ_MASK</name> <displayName>Interrupt mask</displayName> <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description> <addressOffset>0x8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>interruptmask</name> <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>EDGE_CAP</name> <displayName>Edge capture</displayName> <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description> <addressOffset>0xc</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>edgecapture</name> <description>Edge detection for each input port.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>SET_BIT</name> <displayName>Outset</displayName> <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> <addressOffset>0x10</addressOffset> <size>32</size> <access>write-only</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>outset</name> <description>Specifies which bit of the output port to set.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>write-only</access> </field> </fields> </register> <register> <name>CLEAR_BITS</name> <displayName>Outclear</displayName> <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> <addressOffset>0x14</addressOffset> <size>32</size> <access>write-only</access> <resetValue>0x0</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>outclear</name> <description>Specifies which output bit to clear.</description> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>write-only</access> </field> </fields> </register> </registers> </peripheral> </peripherals> </device> external_connection conduit false in_port in_port Input 3 0 STD_LOGIC_VECTOR 0 out_port out_port Output 3 0 STD_LOGIC_VECTOR 0 associatedClock associatedReset prSafe false ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER 0 embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER 0 embeddedsw.CMacro.CAPTURE 0 embeddedsw.CMacro.DATA_WIDTH 3 embeddedsw.CMacro.DO_TEST_BENCH_WIRING 0 embeddedsw.CMacro.DRIVEN_SIM_VALUE 0 embeddedsw.CMacro.EDGE_TYPE NONE embeddedsw.CMacro.FREQ 100000000 embeddedsw.CMacro.HAS_IN 1 embeddedsw.CMacro.HAS_OUT 1 embeddedsw.CMacro.HAS_TRI 0 embeddedsw.CMacro.IRQ_TYPE NONE embeddedsw.CMacro.RESET_VALUE 7 embeddedsw.dts.compatible altr,pio-1.0 embeddedsw.dts.group gpio embeddedsw.dts.name pio embeddedsw.dts.params.altr,gpio-bank-width 3 embeddedsw.dts.params.resetvalue 7 embeddedsw.dts.vendor altr ]]> false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition false true false true java.lang.Boolean false false true false true java.lang.String altera_avalon_pio_inst false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.Long 100000000 true true false true CLOCK_RATE clk java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 100000000 true true false true clock 0 false clk Input 1 clk java.lang.String clk false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false reset_n Input 1 reset_n embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment NATIVE false true false true int 0 false true true true java.math.BigInteger 4 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.lang.String clk false true true true java.lang.String reset false true true true int 8 false true true true java.math.BigInteger 0 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 0 false false true true int 0 false false true true int 1 false true false true int 1 false false true true int 1 false true false true boolean false false true false true boolean false false true false true int 0 false true true true int 1 false true false true int 1 false true true true boolean false false true false true boolean false false true false true int 0 false true true true com.altera.sopcmodel.avalon.TimingUnits Cycles false true true true boolean false false true true true int 0 false false true true int 1024 false true false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false true true true java.math.BigInteger 0 false true true true java.lang.Integer 0 false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true java.lang.Integer 35 false true true true java.lang.Integer 3 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon 16 false address Input 2 address write_n Input 1 write_n writedata Input 32 writedata chipselect Input 1 chipselect readdata Output 32 readdata java.lang.String false true true true java.lang.String false true true true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true conduit 0 false in_port Input 3 in_port out_port Output 3 out_port com.altera.qsys.blackboxmodule.definitions.ComponentDefinition clk clock false clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName reset reset false reset reset Input 1 0 STD_LOGIC 0 associatedClock clk synchronousEdges DEASSERT s0 avalon false s0_waitrequest waitrequest Output 1 0 STD_LOGIC 0 s0_readdata readdata Output 32 0 STD_LOGIC_VECTOR 0 s0_readdatavalid readdatavalid Output 1 0 STD_LOGIC 0 s0_burstcount burstcount Input 1 0 STD_LOGIC_VECTOR 0 s0_writedata writedata Input 32 0 STD_LOGIC_VECTOR 0 s0_address address Input 17 0 STD_LOGIC_VECTOR 0 s0_write write Input 1 0 STD_LOGIC 0 s0_read read Input 1 0 STD_LOGIC 0 s0_byteenable byteenable Input 4 0 STD_LOGIC_VECTOR 0 s0_debugaccess debugaccess Input 1 0 STD_LOGIC 0 embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 addressAlignment DYNAMIC addressGroup 0 addressSpan 131072 addressUnits SYMBOLS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 bridgedAddressOffset 0 bridgesToMaster pb_cpu_0.m0 burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false explicitAddressSpan 0 holdTime 0 interleaveBursts false isBigEndian false isFlash false isMemoryDevice false isNonVolatileStorage false linewrapBursts false maximumPendingReadTransactions 1 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 minimumUninterruptedRunLength 1 prSafe false printableDevice false readLatency 0 readWaitStates 0 readWaitTime 0 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles transparentBridge false waitrequestAllowance 0 waitrequestTimeout 1024 wellBehavedWaitrequest false writeLatency 0 writeWaitStates 0 writeWaitTime 0 dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 m0 avalon true m0_waitrequest waitrequest Input 1 0 STD_LOGIC 0 m0_readdata readdata Input 32 0 STD_LOGIC_VECTOR 0 m0_readdatavalid readdatavalid Input 1 0 STD_LOGIC 0 m0_burstcount burstcount Output 1 0 STD_LOGIC_VECTOR 0 m0_writedata writedata Output 32 0 STD_LOGIC_VECTOR 0 m0_address address Output 17 0 STD_LOGIC_VECTOR 0 m0_write write Output 1 0 STD_LOGIC 0 m0_read read Output 1 0 STD_LOGIC 0 m0_byteenable byteenable Output 4 0 STD_LOGIC_VECTOR 0 m0_debugaccess debugaccess Output 1 0 STD_LOGIC 0 adaptsTo addressGroup 0 addressUnits SYMBOLS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false dBSBigEndian false doStreamReads false doStreamWrites false holdTime 0 interleaveBursts false isAsynchronous false isBigEndian false isReadable false isWriteable false linewrapBursts false maxAddressWidth 32 maximumPendingReadTransactions 0 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 prSafe false readLatency 0 readWaitTime 1 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles waitrequestAllowance 0 waitrequestTimeout 1024 writeWaitTime 0 enableConcurrentSubordinateAccess 0 optimizedReadsWithBE 0 altera_avalon_mm_bridge 20.1.0 Avalon Memory Mapped Pipeline Bridge Intel FPGA IP 10 SYSINFO_ADDR_WIDTH java.lang.Integer m0 ADDRESS_WIDTH m0 m0 ADDRESS_WIDTH 17 s0 s0 ADDRESS_MAP ADDRESS_WIDTH MAX_SLAVE_DATA_WIDTH ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition pb_cpu_0 QUARTUS_SYNTH pb_cpu_0 QUARTUS_SYNTH SIM_VERILOG pb_cpu_0 SIM_VERILOG SIM_VHDL pb_cpu_0 SIM_VHDL CDC pb_cpu_0 CDC CDC_VHDL pb_cpu_0 CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/peripheral_subsys/pb_cpu_0.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition clk clock false clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName reset reset false reset reset Input 1 0 STD_LOGIC 0 associatedClock clk synchronousEdges DEASSERT s0 avalon false s0_waitrequest waitrequest Output 1 0 STD_LOGIC 0 s0_readdata readdata Output 32 0 STD_LOGIC_VECTOR 0 s0_readdatavalid readdatavalid Output 1 0 STD_LOGIC 0 s0_burstcount burstcount Input 1 0 STD_LOGIC_VECTOR 0 s0_writedata writedata Input 32 0 STD_LOGIC_VECTOR 0 s0_address address Input 17 0 STD_LOGIC_VECTOR 0 s0_write write Input 1 0 STD_LOGIC 0 s0_read read Input 1 0 STD_LOGIC 0 s0_byteenable byteenable Input 4 0 STD_LOGIC_VECTOR 0 s0_debugaccess debugaccess Input 1 0 STD_LOGIC 0 embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 addressAlignment DYNAMIC addressGroup 0 addressSpan 131072 addressUnits SYMBOLS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 bridgedAddressOffset 0 bridgesToMaster pb_cpu_0.m0 burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false explicitAddressSpan 0 holdTime 0 interleaveBursts false isBigEndian false isFlash false isMemoryDevice false isNonVolatileStorage false linewrapBursts false maximumPendingReadTransactions 1 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 minimumUninterruptedRunLength 1 prSafe false printableDevice false readLatency 0 readWaitStates 0 readWaitTime 0 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles transparentBridge false waitrequestAllowance 0 waitrequestTimeout 1024 wellBehavedWaitrequest false writeLatency 0 writeWaitStates 0 writeWaitTime 0 dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 m0 avalon true m0_waitrequest waitrequest Input 1 0 STD_LOGIC 0 m0_readdata readdata Input 32 0 STD_LOGIC_VECTOR 0 m0_readdatavalid readdatavalid Input 1 0 STD_LOGIC 0 m0_burstcount burstcount Output 1 0 STD_LOGIC_VECTOR 0 m0_writedata writedata Output 32 0 STD_LOGIC_VECTOR 0 m0_address address Output 17 0 STD_LOGIC_VECTOR 0 m0_write write Output 1 0 STD_LOGIC 0 m0_read read Output 1 0 STD_LOGIC 0 m0_byteenable byteenable Output 4 0 STD_LOGIC_VECTOR 0 m0_debugaccess debugaccess Output 1 0 STD_LOGIC 0 adaptsTo addressGroup 0 addressUnits SYMBOLS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false dBSBigEndian false doStreamReads false doStreamWrites false holdTime 0 interleaveBursts false isAsynchronous false isBigEndian false isReadable false isWriteable false linewrapBursts false maxAddressWidth 32 maximumPendingReadTransactions 0 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 prSafe false readLatency 0 readWaitTime 1 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles waitrequestAllowance 0 waitrequestTimeout 1024 writeWaitTime 0 enableConcurrentSubordinateAccess 0 ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition ]]> false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList Bridge data width true false INTEGER DATA_WIDTH java.lang.Integer 32 Symbol (byte) width true false INTEGER SYMBOL_WIDTH java.lang.Integer 8 true false INTEGER HDL_ADDR_WIDTH java.lang.Integer 17 Bridge burstcount width true false INTEGER BURSTCOUNT_WIDTH java.lang.Integer 1 When enabled, the command (or response) networks are pipelined, potentially increasing the frequency at the expense of increase logic and latency. true false INTEGER PIPELINE_COMMAND java.lang.Integer 1 When enabled, the command (or response) networks are pipelined, potentially increasing the frequency at the expense of increase logic and latency. true false INTEGER PIPELINE_RESPONSE java.lang.Integer 1 0 means allows asynchronous resets, 1 means internal reset synchronization true false INTEGER SYNC_RESET java.lang.Integer 0 0 means writeresponsvalid is disabled, 1 means writeresponsevalid is enabled true false INTEGER USE_WRITERESPONSE java.lang.Integer 0 true false INTEGER S0_WAITREQUEST_ALLOWANCE java.lang.Integer 0 true false INTEGER M0_WAITREQUEST_ALLOWANCE java.lang.Integer 0 ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition false true false true java.lang.Boolean false false true false true java.lang.String altera_avalon_mm_bridge_inst false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.Integer 17 true true false true ADDRESS_WIDTH m0 java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock 0 false clk Input 1 clk java.lang.String clk false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false reset Input 1 reset embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment DYNAMIC false true false true int 0 false true true true java.math.BigInteger 131072 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits SYMBOLS false true true true boolean false false true false true java.lang.String clk false true true true java.lang.String reset false true true true int 8 false true true true java.math.BigInteger 0 false true true true com.altera.entityinterfaces.IConnectionPoint pb_cpu_0.m0 false true true true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false false true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 1 false true true true int 0 false false true true int 1 false true false true int 1 false true true true int 1 false true false true boolean false false true false true boolean false false true false true int 0 false false true true int 0 false true false true int 0 false false true true boolean false false true false true boolean false false true false true int 0 false false true true com.altera.sopcmodel.avalon.TimingUnits Cycles false false true true boolean false false true true true int 0 false true true true int 1024 false false false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false false true true java.math.BigInteger 0 false true true true java.lang.Integer 0 false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true java.lang.Integer 35 false true true true java.lang.Integer 3 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon 131072 false s0_waitrequest Output 1 waitrequest s0_readdata Output 32 readdata s0_readdatavalid Output 1 readdatavalid s0_burstcount Input 1 burstcount s0_writedata Input 32 writedata s0_address Input 17 address s0_write Input 1 write s0_read Input 1 read s0_byteenable Input 4 byteenable s0_debugaccess Input 1 debugaccess com.altera.entityinterfaces.IConnectionPoint false true false true int 0 false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits SYMBOLS false true true true boolean false false true false true java.lang.String clk false true true true java.lang.String reset false true true true int 8 false true true true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true true true int 0 false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 32 false true false true int 0 false true true true int 0 false true true true int 1 false true false true int 1 false true true true boolean false false true false true int 0 false true true true int 1 false true true true boolean false false true false true boolean false false true false true int 0 false true true true com.altera.sopcmodel.avalon.TimingUnits Cycles false true true true int 0 false true true true int 1024 false true true true int 0 false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon 131072 true m0_waitrequest Input 1 waitrequest m0_readdata Input 32 readdata m0_readdatavalid Input 1 readdatavalid m0_burstcount Output 1 burstcount m0_writedata Output 32 writedata m0_address Output 17 address m0_write Output 1 write m0_read Output 1 read m0_byteenable Output 4 byteenable m0_debugaccess Output 1 debugaccess false subsys_periph_sysid control_slave subsys_periph_sysid.control_slave 65536 8 false subsys_periph_led_pio s1 subsys_periph_led_pio.s1 65664 16 false subsys_periph_dipsw_pio s1 subsys_periph_dipsw_pio.s1 65648 16 false subsys_periph_button_pio s1 subsys_periph_button_pio.s1 65632 16 com.altera.qsys.blackboxmodule.definitions.ComponentDefinition in_clk clock false in_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName out_clk clock true out_clk clk Output 1 0 STD_LOGIC 0 associatedDirectClock in_clk clockRate 100000000 clockRateKnown true externallyDriven false ptfSchematicName altera_clock_bridge 19.2.0 Clock Bridge Intel FPGA IP 0 DERIVED_CLOCK_RATE java.lang.Long in_clk CLOCK_RATE in_clk in_clk CLOCK_RATE 100000000 out_clk out_clk CLOCK_RATE 100000000 ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition periph_clk QUARTUS_SYNTH periph_clk QUARTUS_SYNTH SIM_VERILOG periph_clk SIM_VERILOG SIM_VHDL periph_clk SIM_VHDL CDC periph_clk CDC CDC_VHDL periph_clk CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/peripheral_subsys/periph_clk.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition in_clk clock false in_clk clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName out_clk clock true out_clk clk Output 1 0 STD_LOGIC 0 associatedDirectClock in_clk clockRate 100000000 clockRateKnown true externallyDriven false ptfSchematicName ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition ]]> false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition false true false true java.lang.Boolean false false true false true java.lang.String altera_clock_bridge_inst false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.Long 100000000 true true false true CLOCK_RATE in_clk java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 100000000 true true false true clock 0 false in_clk Input 1 clk java.lang.String in_clk false true true true long 100000000 false true false true boolean true false true false true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock 0 true out_clk Output 1 clk false subsys_periph_sysid clk subsys_periph_sysid.clk false subsys_periph_pb_cpu_0 clk subsys_periph_pb_cpu_0.clk false subsys_periph_led_pio clk subsys_periph_led_pio.clk false subsys_periph_dipsw_pio clk subsys_periph_dipsw_pio.clk false subsys_periph_button_pio clk subsys_periph_button_pio.clk com.altera.qsys.blackboxmodule.definitions.ComponentDefinition in_reset reset false in_reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock synchronousEdges NONE out_reset reset true out_reset_n reset_n Output 1 0 STD_LOGIC 0 associatedClock associatedDirectReset in_reset associatedResetSinks in_reset synchronousEdges NONE altera_reset_bridge 19.2.0 Reset Bridge Intel FPGA IP -1 AUTO_CLK_CLOCK_RATE java.lang.Long clk CLOCK_RATE ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition periph_rst_in QUARTUS_SYNTH periph_rst_in QUARTUS_SYNTH SIM_VERILOG periph_rst_in SIM_VERILOG SIM_VHDL periph_rst_in SIM_VHDL CDC periph_rst_in CDC CDC_VHDL periph_rst_in CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/peripheral_subsys/periph_rst_in.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition in_reset reset false in_reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock synchronousEdges NONE out_reset reset true out_reset_n reset_n Output 1 0 STD_LOGIC 0 associatedClock associatedDirectReset in_reset associatedResetSinks in_reset synchronousEdges NONE ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition ]]> false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition false true false true java.lang.Boolean false false true false true java.lang.String altera_reset_bridge_inst false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.Long -1 true true false true CLOCK_RATE clk java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true java.lang.String false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false in_reset_n Input 1 reset_n java.lang.String false true true true java.lang.String in_reset false true true true [Ljava.lang.String; in_reset false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 true out_reset_n Output 1 reset_n embeddedsw.CMacro.ID -1395275010 embeddedsw.CMacro.TIMESTAMP 0 embeddedsw.dts.compatible altr,sysid-1.0 embeddedsw.dts.group sysid embeddedsw.dts.name sysid embeddedsw.dts.params.id -1395275010 embeddedsw.dts.params.timestamp 0 embeddedsw.dts.vendor altr com.altera.qsys.blackboxmodule.definitions.ComponentDefinition clk clock false clock clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName reset reset false reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock clk synchronousEdges DEASSERT control_slave avalon false readdata readdata Output 32 0 STD_LOGIC_VECTOR 0 address address Input 1 0 STD_LOGIC 0 embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 addressAlignment DYNAMIC addressGroup 0 addressSpan 8 addressUnits WORDS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 bridgedAddressOffset 0 bridgesToMaster burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false explicitAddressSpan 0 holdTime 0 interleaveBursts false isBigEndian false isFlash false isMemoryDevice false isNonVolatileStorage false linewrapBursts false maximumPendingReadTransactions 0 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 minimumUninterruptedRunLength 1 prSafe false printableDevice false readLatency 0 readWaitStates 1 readWaitTime 1 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles transparentBridge false waitrequestAllowance 0 waitrequestTimeout 1024 wellBehavedWaitrequest false writeLatency 0 writeWaitStates 0 writeWaitTime 0 dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 altera_avalon_sysid_qsys 19.1.7 System ID Peripheral Intel FPGA IP 0 TIMESTAMP java.lang.Integer GENERATION_ID control_slave control_slave ADDRESS_MAP <address-map><slave name='control_slave' start='0x0' end='0x8' datawidth='32' /></address-map> ADDRESS_WIDTH 3 MAX_SLAVE_DATA_WIDTH 32 ]]> false true false true com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition sysid QUARTUS_SYNTH sysid QUARTUS_SYNTH SIM_VERILOG sysid SIM_VERILOG SIM_VHDL sysid SIM_VHDL CDC sysid CDC CDC_VHDL sysid CDC_VHDL ]]> false true false true java.lang.String false true false true java.lang.String ip/peripheral_subsys/sysid.ip false true false true com.altera.sopcmodel.definition.BoundaryDefinition clk clock false clock clk Input 1 0 STD_LOGIC 0 clockRate 0 externallyDriven false ptfSchematicName reset reset false reset_n reset_n Input 1 0 STD_LOGIC 0 associatedClock clk synchronousEdges DEASSERT control_slave avalon false readdata readdata Output 32 0 STD_LOGIC_VECTOR 0 address address Input 1 0 STD_LOGIC 0 embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 addressAlignment DYNAMIC addressGroup 0 addressSpan 8 addressUnits WORDS alwaysBurstMaxBurst false associatedClock clk associatedReset reset bitsPerSymbol 8 bridgedAddressOffset 0 bridgesToMaster burstOnBurstBoundariesOnly false burstcountUnits WORDS constantBurstBehavior false explicitAddressSpan 0 holdTime 0 interleaveBursts false isBigEndian false isFlash false isMemoryDevice false isNonVolatileStorage false linewrapBursts false maximumPendingReadTransactions 0 maximumPendingWriteTransactions 0 minimumReadLatency 1 minimumResponseLatency 1 minimumUninterruptedRunLength 1 prSafe false printableDevice false readLatency 0 readWaitStates 1 readWaitTime 1 registerIncomingSignals false registerOutgoingSignals false setupTime 0 timingUnits Cycles transparentBridge false waitrequestAllowance 0 waitrequestTimeout 1024 wellBehavedWaitrequest false writeLatency 0 writeWaitStates 0 writeWaitTime 0 dfhFeatureGuid 0 dfhGroupId 0 dfhParameterId dfhParameterName dfhParameterVersion dfhParameterData dfhParameterDataLength dfhFeatureMajorVersion 0 dfhFeatureMinorVersion 0 dfhFeatureId 35 dfhFeatureType 3 <?xml version="1.0" encoding="utf-8"?> <device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > <peripherals> <peripheral> <name>altera_avalon_sysid</name><baseAddress>0x00000000</baseAddress> <addressBlock> <offset>0x0</offset> <size>8</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>ID</name> <displayName>System ID</displayName> <description>A unique 32-bit value that is based on the contents of the QSys system. The id is similar to a check-sum value; QSys systems with different components, different configuration options, or both, produce different id values.</description> <addressOffset>0x0</addressOffset> <size>32</size> <access>read-only</access> <resetValue>${sysid_id_value}</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>id</name> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>TIMESTAMP</name> <displayName>Time stamp</displayName> <description>A unique 32-bit value that is based on the system generation time. The value is equivalent to the number of seconds after Jan. 1, 1970.</description> <addressOffset>0x4</addressOffset> <size>32</size> <access>read-only</access> <resetValue>${sysid_timestamp_value}</resetValue> <resetMask>0xffffffff</resetMask> <fields> <field><name>timestamp</name> <bitOffset>0x0</bitOffset> <bitWidth>32</bitWidth> <access>read-only</access> </field> </fields> </register> </registers> </peripheral> </peripherals> </device> sysid_timestamp_value 0x0 sysid_id_value 0xacd5cafe ]]> false true false true com.altera.sopcmodel.definition.AssignmentDefinition embeddedsw.CMacro.ID -1395275010 embeddedsw.CMacro.TIMESTAMP 0 embeddedsw.dts.compatible altr,sysid-1.0 embeddedsw.dts.group sysid embeddedsw.dts.name sysid embeddedsw.dts.params.id -1395275010 embeddedsw.dts.params.timestamp 0 embeddedsw.dts.vendor altr ]]> false true false true com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition false true false true com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList ]]> false true false true com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList false true false true com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition false true false true java.lang.Boolean false false true false true java.lang.String altera_avalon_sysid_qsys_inst false true false true com.altera.sopcmodel.definition.CpuHashInfoDefinition ]]> false true false true java.lang.Integer 0 true true false true GENERATION_ID java.lang.String Agilex 5 true true false true DEVICE_FAMILY java.lang.String A5EB013BB23BE4SCS true true false true DEVICE java.lang.String Agilex 5 true true false true DEVICE_FAMILY boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock 0 false clock Input 1 clk java.lang.String clk false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset 0 false reset_n Input 1 reset_n embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment DYNAMIC false true false true int 0 false true true true java.math.BigInteger 8 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.lang.String clk false true true true java.lang.String reset false true true true int 8 false true true true java.math.BigInteger 0 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 0 false false true true int 0 false false true true int 1 false true false true int 1 false false true true int 1 false true false true boolean false false true false true boolean false false true false true int 0 false true true true int 1 false true false true int 1 false true true true boolean false false true false true boolean false false true false true int 0 false true true true com.altera.sopcmodel.avalon.TimingUnits Cycles false true true true boolean false false true true true int 0 false false true true int 1024 false true false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false true true true java.math.BigInteger 0 false true true true java.lang.Integer 0 false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true [Ljava.lang.String; false true true true [Ljava.lang.Integer; false true true true java.lang.Integer 0 false true true true java.lang.Integer 0 false true true true java.lang.Integer 35 false true true true java.lang.Integer 3 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon 8 false readdata Output 32 readdata address Input 1 address com.altera.entityinterfaces.IPort false true true true int 0 false true true true com.altera.entityinterfaces.IPort false true true true int 0 false true true true int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true subsys_hps_emif_hps io96b0_to_hps subsys_hps_agilex_hps io96b0_to_hps int 1 false true true true java.math.BigInteger 0x00010000 false true true true boolean false false true true true java.lang.String false true true true java.lang.Integer -1 true true false true MAX_SLAVE_DATA_WIDTH com.altera.entityinterfaces.moduleext.AddressMap true true false true ADDRESS_MAP com.altera.entityinterfaces.moduleext.AddressWidthType 17 true true false true ADDRESS_WIDTH java.lang.String true true false true CPU_INFO_ID java.lang.String PIPELINE_STAGE false true true true java.lang.String FALSE false true true true java.lang.String 1 false true true true java.lang.String AUTO false true true true java.lang.String 8 false true true true java.lang.String FALSE false true true true java.lang.String FALSE false true true true java.lang.String DEFAULT false true true true java.lang.String GENERIC_CONVERTER false true true true java.lang.String GENERIC_CONVERTER false true true true java.lang.String FALSE false true true true java.lang.String STANDARD false true true true java.lang.String TRUE false true true true java.lang.String FALSE false true true true java.lang.String REGISTER_BASED false true true true java.lang.String FALSE false true true true java.lang.String FALSE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_pb_cpu_0 m0 subsys_periph_sysid control_slave int 1 false true true true java.math.BigInteger 0x00010080 false true true true boolean false false true true true java.lang.String false true true true java.lang.Integer -1 true true false true MAX_SLAVE_DATA_WIDTH com.altera.entityinterfaces.moduleext.AddressMap true true false true ADDRESS_MAP com.altera.entityinterfaces.moduleext.AddressWidthType 17 true true false true ADDRESS_WIDTH java.lang.String true true false true CPU_INFO_ID java.lang.String PIPELINE_STAGE false true true true java.lang.String FALSE false true true true java.lang.String 1 false true true true java.lang.String AUTO false true true true java.lang.String 8 false true true true java.lang.String FALSE false true true true java.lang.String FALSE false true true true java.lang.String DEFAULT false true true true java.lang.String GENERIC_CONVERTER false true true true java.lang.String GENERIC_CONVERTER false true true true java.lang.String FALSE false true true true java.lang.String STANDARD false true true true java.lang.String TRUE false true true true java.lang.String FALSE false true true true java.lang.String REGISTER_BASED false true true true java.lang.String FALSE false true true true java.lang.String FALSE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_pb_cpu_0 m0 subsys_periph_led_pio s1 int 1 false true true true java.math.BigInteger 0x00010070 false true true true boolean false false true true true java.lang.String false true true true java.lang.Integer -1 true true false true MAX_SLAVE_DATA_WIDTH com.altera.entityinterfaces.moduleext.AddressMap true true false true ADDRESS_MAP com.altera.entityinterfaces.moduleext.AddressWidthType 17 true true false true ADDRESS_WIDTH java.lang.String true true false true CPU_INFO_ID java.lang.String PIPELINE_STAGE false true true true java.lang.String FALSE false true true true java.lang.String 1 false true true true java.lang.String AUTO false true true true java.lang.String 8 false true true true java.lang.String FALSE false true true true java.lang.String FALSE false true true true java.lang.String DEFAULT false true true true java.lang.String GENERIC_CONVERTER false true true true java.lang.String GENERIC_CONVERTER false true true true java.lang.String FALSE false true true true java.lang.String STANDARD false true true true java.lang.String TRUE false true true true java.lang.String FALSE false true true true java.lang.String REGISTER_BASED false true true true java.lang.String FALSE false true true true java.lang.String FALSE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_pb_cpu_0 m0 subsys_periph_dipsw_pio s1 int 1 false true true true java.math.BigInteger 0x00010060 false true true true boolean false false true true true java.lang.String false true true true java.lang.Integer -1 true true false true MAX_SLAVE_DATA_WIDTH com.altera.entityinterfaces.moduleext.AddressMap true true false true ADDRESS_MAP com.altera.entityinterfaces.moduleext.AddressWidthType 17 true true false true ADDRESS_WIDTH java.lang.String true true false true CPU_INFO_ID java.lang.String PIPELINE_STAGE false true true true java.lang.String FALSE false true true true java.lang.String 1 false true true true java.lang.String AUTO false true true true java.lang.String 8 false true true true java.lang.String FALSE false true true true java.lang.String FALSE false true true true java.lang.String DEFAULT false true true true java.lang.String GENERIC_CONVERTER false true true true java.lang.String GENERIC_CONVERTER false true true true java.lang.String FALSE false true true true java.lang.String STANDARD false true true true java.lang.String TRUE false true true true java.lang.String FALSE false true true true java.lang.String REGISTER_BASED false true true true java.lang.String FALSE false true true true java.lang.String FALSE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_pb_cpu_0 m0 subsys_periph_button_pio s1 java.lang.Long 100000000 true true false true CLOCK_RATE java.lang.Integer -1 true true false true CLOCK_DOMAIN java.lang.Integer -1 true true false true RESET_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_periph_clk out_clk subsys_periph_sysid clk java.lang.Long 100000000 true true false true CLOCK_RATE java.lang.Integer -1 true true false true CLOCK_DOMAIN java.lang.Integer -1 true true false true RESET_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_periph_clk out_clk subsys_periph_pb_cpu_0 clk java.lang.Long 100000000 true true false true CLOCK_RATE java.lang.Integer -1 true true false true CLOCK_DOMAIN java.lang.Integer -1 true true false true RESET_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_periph_clk out_clk subsys_periph_led_pio clk java.lang.Long 100000000 true true false true CLOCK_RATE java.lang.Integer -1 true true false true CLOCK_DOMAIN java.lang.Integer -1 true true false true RESET_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_periph_clk out_clk subsys_periph_dipsw_pio clk java.lang.Long 100000000 true true false true CLOCK_RATE java.lang.Integer -1 true true false true CLOCK_DOMAIN java.lang.Integer -1 true true false true RESET_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_periph_clk out_clk subsys_periph_button_pio clk java.lang.Integer -1 true true false true RESET_DOMAIN java.lang.Integer -1 true true false true CLOCK_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_periph_rst_in out_reset subsys_periph_sysid reset java.lang.Integer -1 true true false true RESET_DOMAIN java.lang.Integer -1 true true false true CLOCK_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_periph_rst_in out_reset subsys_periph_led_pio reset java.lang.Integer -1 true true false true RESET_DOMAIN java.lang.Integer -1 true true false true CLOCK_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_periph_rst_in out_reset subsys_periph_dipsw_pio reset java.lang.Integer -1 true true false true RESET_DOMAIN java.lang.Integer -1 true true false true CLOCK_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_periph_rst_in out_reset subsys_periph_button_pio reset java.lang.Integer -1 true true false true RESET_DOMAIN java.lang.Integer -1 true true false true CLOCK_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true subsys_periph_periph_rst_in out_reset subsys_periph_pb_cpu_0 reset int 1 false true true true java.math.BigInteger 0x0000 false true true true boolean false false true true true java.lang.String false true true true java.lang.Integer -1 true true false true MAX_SLAVE_DATA_WIDTH com.altera.entityinterfaces.moduleext.AddressMap ]]> true true false true ADDRESS_MAP com.altera.entityinterfaces.moduleext.AddressWidthType 17 true true false true ADDRESS_WIDTH java.lang.String true true false true CPU_INFO_ID java.lang.String PIPELINE_STAGE false true true true java.lang.String FALSE false true true true java.lang.String 4 false true true true java.lang.String AUTO false true true true java.lang.String 8 false true true true java.lang.String FALSE false true true true java.lang.String FALSE false true true true java.lang.String DEFAULT false true true true java.lang.String PER_BURST_TYPE_CONVERTER false true true true java.lang.String GENERIC_CONVERTER false true true true java.lang.String FALSE false true true true java.lang.String STANDARD false true true true java.lang.String TRUE false true true true java.lang.String FALSE false true true true java.lang.String REGISTER_BASED false true true true java.lang.String FALSE false true true true java.lang.String FALSE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true subsys_hps_agilex_hps lwhps2fpga subsys_periph_pb_cpu_0 s0 java.lang.Long 100000000 true true false true CLOCK_RATE java.lang.Integer 1 true true false true CLOCK_DOMAIN java.lang.Integer 1 true true false true RESET_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true clk_100 out_clk subsys_periph_periph_clk in_clk java.lang.Long 100000000 true true false true CLOCK_RATE java.lang.Integer 1 true true false true CLOCK_DOMAIN java.lang.Integer 1 true true false true RESET_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true clk_100 out_clk subsys_hps_agilex_hps f2sdram_axi_clock java.lang.Long 100000000 true true false true CLOCK_RATE java.lang.Integer 1 true true false true CLOCK_DOMAIN java.lang.Integer 1 true true false true RESET_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true clk_100 out_clk subsys_hps_agilex_hps hps2fpga_axi_clock java.lang.Long 100000000 true true false true CLOCK_RATE java.lang.Integer 1 true true false true CLOCK_DOMAIN java.lang.Integer 1 true true false true RESET_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true clk_100 out_clk subsys_hps_agilex_hps lwhps2fpga_axi_clock int 1 false true true true java.math.BigInteger 3 true true false true INTERRUPTS_USED java.lang.String UNKNOWN false true true true boolean false false true true true subsys_hps_agilex_hps fpga2hps_interrupt_irq0 subsys_periph_button_pio irq int 0 false true true true java.math.BigInteger 3 true true false true INTERRUPTS_USED java.lang.String UNKNOWN false true true true boolean false false true true true subsys_hps_agilex_hps fpga2hps_interrupt_irq0 subsys_periph_dipsw_pio irq java.lang.Integer 4 true true false true RESET_DOMAIN java.lang.Integer 4 true true false true CLOCK_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true rst_in out_reset subsys_hps_agilex_hps f2sdram_axi_reset java.lang.Integer 4 true true false true RESET_DOMAIN java.lang.Integer 4 true true false true CLOCK_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true rst_in out_reset subsys_hps_agilex_hps hps2fpga_axi_reset java.lang.Integer 4 true true false true RESET_DOMAIN java.lang.Integer 4 true true false true CLOCK_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true rst_in out_reset subsys_hps_agilex_hps lwhps2fpga_axi_reset java.lang.Integer 4 true true false true RESET_DOMAIN java.lang.Integer 4 true true false true CLOCK_DOMAIN java.lang.String true true false true CLOCK_RESET_INFO java.lang.String UNKNOWN false true true true boolean false false true true true rst_in out_reset subsys_periph_periph_rst_in in_reset 12 altera_generic_component com.altera.entityinterfaces.IElementClass Generic Component 1.0 16 clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Clock Input 26.1 2 clock_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Clock Output 26.1 14 reset_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Input 26.1 5 reset_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Output 26.1 21 conduit_end com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Conduit 26.1 1 hps_subsys com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule hps_subsys 1.0 4 altera_axi4_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint AXI4 Manager 26.1 4 interrupt_receiver com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Interrupt Receiver 26.1 2 altera_axi4_slave com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint AXI4 Subordinate 26.1 1 peripheral_subsys com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule peripheral_subsys 1.0 4 interrupt_sender com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Interrupt Sender 26.1 6 avalon_slave com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Avalon Memory Mapped Agent 26.1 1 avalon_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Avalon Memory Mapped Host 26.1 1 conduit com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Conduit Connection 26.1 5 avalon com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Avalon Memory Mapped Connection 26.1 9 clock com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Clock Connection 26.1 9 reset com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Reset Connection 26.1 2 interrupt com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Interrupt Connection 26.1 26.1 110