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retroDE_ps2/qsys/qsys_top/qsys_top.qgsynthc
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thejayman77 ec82764bef Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5) 
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-06-29 20:10:50 -04:00

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<?xml version="1.0" ?>
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
<instanceKey xsi:type="xs:string">qsys_top</instanceKey>
<instanceData xsi:type="data">
<parameters></parameters>
<interconnectAssignments></interconnectAssignments>
<className>qsys_top</className>
<version>1.0</version>
<name>qsys_top</name>
<uniqueName>qsys_top</uniqueName>
<nonce>0</nonce>
<incidentConnections></incidentConnections>
</instanceData>
<children>
<node>
<instanceKey xsi:type="xs:string">clk_100</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>DERIVED_CLOCK_RATE</name>
<value>0</value>
</parameter>
<parameter>
<name>bspCpu</name>
<value>false</value>
</parameter>
<parameter>
<name>componentDefinition</name>
<value>&lt;componentDefinition&gt;
&lt;boundary&gt;
&lt;interfaces&gt;
&lt;interface&gt;
&lt;name&gt;in_clk&lt;/name&gt;
&lt;type&gt;clock&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;in_clk&lt;/name&gt;
&lt;role&gt;clk&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;terminationValue&gt;0&lt;/terminationValue&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;clockRate&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;externallyDriven&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;ptfSchematicName&lt;/key&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;out_clk&lt;/name&gt;
&lt;type&gt;clock&lt;/type&gt;
&lt;isStart&gt;true&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;out_clk&lt;/name&gt;
&lt;role&gt;clk&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;terminationValue&gt;0&lt;/terminationValue&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedDirectClock&lt;/key&gt;
&lt;value&gt;in_clk&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;clockRate&lt;/key&gt;
&lt;value&gt;100000000&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;clockRateKnown&lt;/key&gt;
&lt;value&gt;true&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;externallyDriven&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;ptfSchematicName&lt;/key&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;/interfaces&gt;
&lt;/boundary&gt;
&lt;originalModuleInfo&gt;
&lt;className&gt;altera_clock_bridge&lt;/className&gt;
&lt;version&gt;19.2.0&lt;/version&gt;
&lt;displayName&gt;Clock Bridge IP&lt;/displayName&gt;
&lt;/originalModuleInfo&gt;
&lt;systemInfoParameterDescriptors&gt;
&lt;descriptors&gt;
&lt;descriptor&gt;
&lt;parameterDefaultValue&gt;0&lt;/parameterDefaultValue&gt;
&lt;parameterName&gt;DERIVED_CLOCK_RATE&lt;/parameterName&gt;
&lt;parameterType&gt;java.lang.Long&lt;/parameterType&gt;
&lt;systemInfoArgs&gt;in_clk&lt;/systemInfoArgs&gt;
&lt;systemInfotype&gt;CLOCK_RATE&lt;/systemInfotype&gt;
&lt;/descriptor&gt;
&lt;/descriptors&gt;
&lt;/systemInfoParameterDescriptors&gt;
&lt;systemInfos&gt;
&lt;connPtSystemInfos&gt;
&lt;entry&gt;
&lt;key&gt;in_clk&lt;/key&gt;
&lt;value&gt;
&lt;connectionPointName&gt;in_clk&lt;/connectionPointName&gt;
&lt;suppliedSystemInfos/&gt;
&lt;consumedSystemInfos&gt;
&lt;entry&gt;
&lt;key&gt;CLOCK_RATE&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;/consumedSystemInfos&gt;
&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;out_clk&lt;/key&gt;
&lt;value&gt;
&lt;connectionPointName&gt;out_clk&lt;/connectionPointName&gt;
&lt;suppliedSystemInfos&gt;
&lt;entry&gt;
&lt;key&gt;CLOCK_RATE&lt;/key&gt;
&lt;value&gt;100000000&lt;/value&gt;
&lt;/entry&gt;
&lt;/suppliedSystemInfos&gt;
&lt;consumedSystemInfos/&gt;
&lt;/value&gt;
&lt;/entry&gt;
&lt;/connPtSystemInfos&gt;
&lt;/systemInfos&gt;
&lt;/componentDefinition&gt;</value>
</parameter>
<parameter>
<name>cpuHashInfo</name>
<value>&lt;cpuHashInfoDefinition&gt;
&lt;cpuHashInfoMap/&gt;
&lt;/cpuHashInfoDefinition&gt;</value>
</parameter>
<parameter>
<name>cpuInfo</name>
<value></value>
</parameter>
<parameter>
<name>defaultBoundary</name>
<value>&lt;boundaryDefinition&gt;
&lt;interfaces&gt;
&lt;interface&gt;
&lt;name&gt;in_clk&lt;/name&gt;
&lt;type&gt;clock&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;in_clk&lt;/name&gt;
&lt;role&gt;clk&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;terminationValue&gt;0&lt;/terminationValue&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;clockRate&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;externallyDriven&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;ptfSchematicName&lt;/key&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;out_clk&lt;/name&gt;
&lt;type&gt;clock&lt;/type&gt;
&lt;isStart&gt;true&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;out_clk&lt;/name&gt;
&lt;role&gt;clk&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;terminationValue&gt;0&lt;/terminationValue&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedDirectClock&lt;/key&gt;
&lt;value&gt;in_clk&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;clockRate&lt;/key&gt;
&lt;value&gt;100000000&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;clockRateKnown&lt;/key&gt;
&lt;value&gt;true&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;externallyDriven&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;ptfSchematicName&lt;/key&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;/interfaces&gt;
&lt;/boundaryDefinition&gt;</value>
</parameter>
<parameter>
<name>generationInfoDefinition</name>
<value>&lt;generationInfoDefinition&gt;
&lt;hdlLibraryName&gt;clk_100&lt;/hdlLibraryName&gt;
&lt;fileSets&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;clk_100&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;clk_100&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;QUARTUS_SYNTH&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;clk_100&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;clk_100&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;SIM_VERILOG&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;clk_100&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;clk_100&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;SIM_VHDL&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;clk_100&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;clk_100&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;CDC&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;clk_100&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;clk_100&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;CDC_VHDL&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;/fileSets&gt;
&lt;/generationInfoDefinition&gt;</value>
</parameter>
<parameter>
<name>hdlParameters</name>
<value>&lt;hdlParameterDescriptorDefinitionList/&gt;</value>
</parameter>
<parameter>
<name>hlsFile</name>
<value></value>
</parameter>
<parameter>
<name>liveModuleName</name>
<value>altera_clock_bridge_inst</value>
</parameter>
<parameter>
<name>logicalView</name>
<value>ip/qsys_top/clk_100.ip</value>
</parameter>
<parameter>
<name>moduleAssignmentDefinition</name>
<value>&lt;assignmentDefinition&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignmentDefinition&gt;</value>
</parameter>
<parameter>
<name>svInterfaceDefinition</name>
<value></value>
</parameter>
<parameter>
<name>transformParameters</name>
<value>&lt;transformParameterDescriptorDefinitionList/&gt;</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_generic_component</className>
<version>1.0</version>
<name>clk_100</name>
<uniqueName>clk_100</uniqueName>
<fixedName>clk_100</fixedName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>clockRateSysInfo</name>
<value>-1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>mm_interconnect_0/clk_100_out_clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>clockRateSysInfo</name>
<value>-1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>rst_controller/clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>subsys_hps/f2sdram_clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>subsys_hps/hps2fpga_clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>subsys_hps/lwhps2fpga_clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>subsys_periph/clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.clk_100</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">irq_mapper</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>IRQ_MAP</name>
<value>0:1,1:0</value>
</parameter>
<parameter>
<name>NUM_RCVRS</name>
<value>2</value>
</parameter>
<parameter>
<name>REMOVE_CLK_RST</name>
<value>0</value>
</parameter>
<parameter>
<name>SENDER_IRQ_WIDTH</name>
<value>32</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_irq_mapper</className>
<version>20.0.1</version>
<name>irq_mapper</name>
<uniqueName>qsys_top_altera_irq_mapper_2001_lp4cnei</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>interruptsUsedSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>irqNumber</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>interrupt</className>
<version>26.1</version>
<end>subsys_periph/button_pio_irq</end>
<start>irq_mapper/receiver0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>interruptsUsedSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>irqNumber</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>interrupt</className>
<version>26.1</version>
<end>subsys_periph/dipsw_pio_irq</end>
<start>irq_mapper/receiver1</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>interruptsUsedSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>irqNumber</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>interrupt</className>
<version>26.1</version>
<end>irq_mapper/sender</end>
<start>subsys_hps/f2h_irq0_in</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.irq_mapper</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">mm_interconnect_0</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>COMPOSE_CONTENTS</name>
<value>add_instance {subsys_hps_lwhps2fpga_translator} {altera_merlin_axi_translator};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWREGION} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWREGION} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWLEN} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSIZE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWBURST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWQOS} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWQOS} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WSTRB} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WLAST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WLAST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_BRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARREGION} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARREGION} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARLEN} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARSIZE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARBURST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARQOS} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARQOS} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RLAST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_BUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUSER_ADDRCHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUSER_SAI} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARUSER_ADDRCHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARUSER_SAI} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER_DATACHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER_POISON} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER_DATACHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER_POISON} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER_DATA} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER_DATA} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWAKEUP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_BTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUNIQUE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWAKEUP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUSER_ADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUSER_SAI} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARUSER_ADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARUSER_SAI} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER_DATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER_POISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER_DATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER_DATA} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER_DATA} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER_POISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUNIQUE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWATOP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHNID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHNIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHLPID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHLPIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWATOP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHNID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHNIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHLPID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHLPIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSNOOP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARSNOOP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_ID_WIDTH} {4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {DATA_WIDTH} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_SAI_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_SAI_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USER_DATA_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_USER_ADDRCHK_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_USER_ADDRCHK_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_ID_WIDTH} {4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_ADDR_WIDTH} {29};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_WRITE_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_READ_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_WRITE_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_READ_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_WRITE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_WRITE_RESPONSE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_READ_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_WRITE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_WRITE_RESPONSE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_READ_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_ADDR_WIDTH} {29};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_SID_WIDTH} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_SID_WIDTH} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {WRITE_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {READ_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {COMBINED_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {WRITE_ACCEPTANCE_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {READ_ACCEPTANCE_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {COMBINED_ACCEPTANCE_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {READ_DATA_REORDERING_DEPTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_AXI_VERSION} {AXI4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_AXI_VERSION} {AXI4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ACE_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ACE5_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {SYNC_RESET} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {REGENERATE_ADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ENABLE_AXI5} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {IS_TRANSLATOR} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {TERMINATE_READ_CHANNEL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {TERMINATE_WRITE_CHANNEL} {0};add_instance {subsys_periph_pb_cpu_0_s0_translator} {altera_merlin_slave_translator};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ADDRESS_W} {17};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_DATA_W} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_DATA_W} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_READLATENCY} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READDATA} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READ} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITE} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_ADDRESS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_LOCK} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {WAITREQUEST_ALLOWANCE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {SYNC_RESET} {1};add_instance {subsys_hps_lwhps2fpga_agent} {altera_merlin_axi_master_ni};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ID_WIDTH} {4};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDR_WIDTH} {29};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {RDATA_WIDTH} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {WDATA_WIDTH} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {SAI_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDRCHK_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USER_DATA_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {SID_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_ADDR_USER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_PKT_DATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_PKT_ADDRCHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {AXI_VERSION} {AXI4};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ACE_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ACE5_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {WRITE_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {READ_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_READ_TERMINAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_WRITE_TERMINAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_READ_UNIVERSAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_WRITE_UNIVERSAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_CACHE_H} {113};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_CACHE_L} {110};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_PROTECTION_H} {109};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_PROTECTION_L} {107};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_RESPONSE_STATUS_L} {114};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_RESPONSE_STATUS_H} {115};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURSTWRAP_L} {82};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTE_CNT_H} {81};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_H} {31};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_L} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SRC_ID_H} {101};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SRC_ID_L} {101};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DEST_ID_H} {102};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DEST_ID_L} {102};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_THREAD_ID_H} {106};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_THREAD_ID_L} {103};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_QOS_L} {97};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_QOS_H} {100};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ORI_BURST_SIZE_L} {116};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ORI_BURST_SIZE_H} {118};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DOMAIN_H} {126};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DOMAIN_L} {125};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SNOOP_H} {124};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SNOOP_L} {121};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BARRIER_H} {120};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BARRIER_L} {119};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_WUNIQUE} {127};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_EOP_OOO} {134};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SOP_OOO} {135};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ATRACE} {141};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRACE} {142};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWAKEUP} {143};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_POISON_H} {128};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_POISON_L} {128};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATACHK_H} {129};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATACHK_L} {129};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDRCHK_H} {132};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDRCHK_L} {131};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SAI_H} {133};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SAI_L} {133};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_SEQ_H} {140};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_SEQ_L} {136};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_USER_DATA_H} {130};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_USER_DATA_L} {130};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWATOP_L} {144};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWATOP_H} {149};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHNID_L} {150};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHNID_H} {160};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHNIDEN} {161};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHLPID_L} {162};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHLPID_H} {166};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHLPIDEN} {167};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_MMUSECSID} {169};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_MMUSID_L} {168};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_MMUSID_H} {168};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATALESS} {170};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ST_DATA_W} {171};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDR_MAP} {&lt;?xml version="1.0" encoding="UTF-8"?&gt;
&lt;address_map&gt;
&lt;slave
id="0"
name="subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0"
start="0x0000000000000000"
end="0x00000000000020000"
responds="1"
user_default="0" /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {SYNC_RESET} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_TRACE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_POISON} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ENABLE_AXI5} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {RESP_USER_WIDTH} {8};add_instance {subsys_periph_pb_cpu_0_s0_agent} {altera_merlin_slave_agent};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ORI_BURST_SIZE_H} {118};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ORI_BURST_SIZE_L} {116};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_RESPONSE_STATUS_H} {115};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_RESPONSE_STATUS_L} {114};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_PROTECTION_H} {109};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_PROTECTION_L} {107};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURSTWRAP_L} {82};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTE_CNT_H} {81};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATA_H} {31};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATA_L} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SRC_ID_H} {101};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SRC_ID_L} {101};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DEST_ID_H} {102};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DEST_ID_L} {102};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_POISON_H} {128};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_POISON_L} {128};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATACHK_H} {129};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATACHK_L} {129};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SAI_H} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SAI_L} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDRCHK_H} {132};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDRCHK_L} {131};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_EOP_OOO} {134};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SOP_OOO} {135};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_SEQ_H} {140};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_SEQ_L} {136};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_USER_DATA_H} {130};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_USER_DATA_L} {130};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ATRACE} {141};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRACE} {142};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWAKEUP} {143};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWATOP_H} {149};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWATOP_L} {144};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHNID_H} {160};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHNID_L} {150};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHNIDEN} {161};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHLPID_H} {166};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHLPID_L} {162};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHLPIDEN} {167};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_MMUSECSID} {169};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_MMUSID_H} {168};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_MMUSID_L} {168};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATALESS} {170};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ST_DATA_W} {171};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {MAX_BURSTWRAP} {127};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ID} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ECC_ENABLE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {SYNC_RESET} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_PKT_DATACHK} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ENABLE_AXI5} {0};add_instance {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {BITS_PER_SYMBOL} {172};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {MEM_TYPE} {M20K};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {SYNC_RESET} {1};add_instance {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {MEM_TYPE} {M20K};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {SYNC_RESET} {1};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {0 };set_instance_parameter_value {router} {CHANNEL_ID} {1 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 };set_instance_parameter_value {router} {END_ADDRESS} {0x20000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {64};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {109};set_instance_parameter_value {router} {PKT_PROTECTION_L} {107};set_instance_parameter_value {router} {PKT_DEST_ID_H} {102};set_instance_parameter_value {router} {PKT_DEST_ID_L} {102};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router} {PKT_TRANS_READ} {68};set_instance_parameter_value {router} {ST_DATA_W} {171};set_instance_parameter_value {router} {ST_CHANNEL_W} {2};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};set_instance_parameter_value {router} {HAS_USER_DEFAULT_SLAVE} {0};set_instance_parameter_value {router} {SYNC_RESET} {1};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {1 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x20000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {64};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {109};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {107};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {102};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {102};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_001} {ST_DATA_W} {171};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};set_instance_parameter_value {router_001} {HAS_USER_DEFAULT_SLAVE} {0};set_instance_parameter_value {router_001} {SYNC_RESET} {1};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {write read };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {64};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {109};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {107};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {102};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {102};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_002} {ST_DATA_W} {171};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};set_instance_parameter_value {router_002} {HAS_USER_DEFAULT_SLAVE} {0};set_instance_parameter_value {router_002} {SYNC_RESET} {1};add_instance {subsys_periph_pb_cpu_0_s0_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_ADDR_H} {64};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_ADDR_L} {36};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTE_CNT_H} {81};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURSTWRAP_L} {82};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_SAI_H} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_SAI_L} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ENABLE_AXI5} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_TRANS_READ} {68};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {IN_NARROW_SIZE} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_EOP_OOO} {89};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_SOP_OOO} {90};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ENABLE_OOO} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ST_DATA_W} {171};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_BYTE_CNT_H} {73};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {BURSTWRAP_CONST_MASK} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {BURSTWRAP_CONST_VALUE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ADAPTER_VERSION} {new};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {SYNC_RESET} {1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {171};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cmd_demux} {SYNC_RESET} {1};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {171};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cmd_demux_001} {SYNC_RESET} {1};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {171};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cmd_mux} {SYNC_RESET} {1};set_instance_parameter_value {cmd_mux} {ENABLE_OOO_CHUNKS} {0};set_instance_parameter_value {cmd_mux} {PKT_SOP_OOO} {135};set_instance_parameter_value {cmd_mux} {PKT_EOP_OOO} {134};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {171};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {rsp_demux} {SYNC_RESET} {1};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {171};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {rsp_mux} {SYNC_RESET} {1};set_instance_parameter_value {rsp_mux} {ENABLE_OOO_CHUNKS} {0};set_instance_parameter_value {rsp_mux} {PKT_SOP_OOO} {135};set_instance_parameter_value {rsp_mux} {PKT_EOP_OOO} {134};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {171};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {rsp_mux_001} {SYNC_RESET} {1};set_instance_parameter_value {rsp_mux_001} {ENABLE_OOO_CHUNKS} {0};set_instance_parameter_value {rsp_mux_001} {PKT_SOP_OOO} {135};set_instance_parameter_value {rsp_mux_001} {PKT_EOP_OOO} {134};add_instance {agent_pipeline} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {agent_pipeline} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {agent_pipeline} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {agent_pipeline} {USE_PACKETS} {1};set_instance_parameter_value {agent_pipeline} {USE_EMPTY} {0};set_instance_parameter_value {agent_pipeline} {CHANNEL_WIDTH} {2};set_instance_parameter_value {agent_pipeline} {MAX_CHANNEL} {0};set_instance_parameter_value {agent_pipeline} {ERROR_WIDTH} {0};set_instance_parameter_value {agent_pipeline} {PIPELINE_READY} {1};set_instance_parameter_value {agent_pipeline} {SYNC_RESET} {1};add_instance {agent_pipeline_001} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {agent_pipeline_001} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {agent_pipeline_001} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {agent_pipeline_001} {USE_PACKETS} {1};set_instance_parameter_value {agent_pipeline_001} {USE_EMPTY} {0};set_instance_parameter_value {agent_pipeline_001} {CHANNEL_WIDTH} {0};set_instance_parameter_value {agent_pipeline_001} {MAX_CHANNEL} {0};set_instance_parameter_value {agent_pipeline_001} {ERROR_WIDTH} {0};set_instance_parameter_value {agent_pipeline_001} {PIPELINE_READY} {1};set_instance_parameter_value {agent_pipeline_001} {SYNC_RESET} {1};add_instance {mux_pipeline} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline} {SYNC_RESET} {1};add_instance {mux_pipeline_001} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline_001} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline_001} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline_001} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline_001} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline_001} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline_001} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline_001} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline_001} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline_001} {SYNC_RESET} {1};add_instance {mux_pipeline_002} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline_002} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline_002} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline_002} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline_002} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline_002} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline_002} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline_002} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline_002} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline_002} {SYNC_RESET} {1};add_instance {mux_pipeline_003} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline_003} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline_003} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline_003} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline_003} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline_003} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline_003} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline_003} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline_003} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline_003} {SYNC_RESET} {1};add_instance {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {USE_RESET_REQUEST} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {SYNC_RESET} {1};add_instance {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {USE_RESET_REQUEST} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {SYNC_RESET} {1};add_instance {clk_100_out_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {clk_100_out_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {100000000};set_instance_parameter_value {clk_100_out_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {subsys_hps_lwhps2fpga_translator.m0} {subsys_hps_lwhps2fpga_agent.altera_axi_slave} {avalon};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {arbitrationPriority} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {baseAddress} {0x0000};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {defaultConnection} {false};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {domainAlias} {};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {rsp_mux.src} {subsys_hps_lwhps2fpga_agent.write_rp} {avalon_streaming};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.response};add_connection {rsp_mux_001.src} {subsys_hps_lwhps2fpga_agent.read_rp} {avalon_streaming};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.response};add_connection {subsys_periph_pb_cpu_0_s0_agent.m0} {subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {defaultConnection} {false};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {domainAlias} {};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent.rf_source} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out} {subsys_periph_pb_cpu_0_s0_agent.rf_sink} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src} {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out} {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_hps_lwhps2fpga_agent.write_cp} {router.sink} {avalon_streaming};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {subsys_hps_lwhps2fpga_agent.read_cp} {router_001.sink} {avalon_streaming};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {cmd_mux.src} {subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {avalon_streaming};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.command};add_connection {subsys_periph_pb_cpu_0_s0_burst_adapter.source0} {agent_pipeline.sink0} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.command};add_connection {agent_pipeline.source0} {subsys_periph_pb_cpu_0_s0_agent.cp} {avalon_streaming};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.command};add_connection {subsys_periph_pb_cpu_0_s0_agent.rp} {agent_pipeline_001.sink0} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.response};add_connection {agent_pipeline_001.source0} {router_002.sink} {avalon_streaming};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {agent_pipeline_001.source0/router_002.sink} {qsys_mm.response};add_connection {cmd_demux.src0} {mux_pipeline.sink0} {avalon_streaming};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.command};add_connection {mux_pipeline.source0} {cmd_mux.sink0} {avalon_streaming};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {mux_pipeline_001.sink0} {avalon_streaming};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.command};add_connection {mux_pipeline_001.source0} {cmd_mux.sink1} {avalon_streaming};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.command};add_connection {rsp_demux.src0} {mux_pipeline_002.sink0} {avalon_streaming};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.response};add_connection {mux_pipeline_002.source0} {rsp_mux.sink0} {avalon_streaming};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {mux_pipeline_003.sink0} {avalon_streaming};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.response};add_connection {mux_pipeline_003.source0} {rsp_mux_001.sink0} {avalon_streaming};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.response};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_hps_lwhps2fpga_translator.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_translator.reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_hps_lwhps2fpga_agent.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_agent.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_burst_adapter.cr0_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {agent_pipeline.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {agent_pipeline_001.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline_001.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline_002.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline_003.cr0_reset} {reset};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_hps_lwhps2fpga_translator.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_translator.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_hps_lwhps2fpga_agent.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_burst_adapter.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {agent_pipeline.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {agent_pipeline_001.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline_001.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline_002.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline_003.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.clk} {clock};add_interface {subsys_hps_lwhps2fpga} {axi4} {slave};set_interface_property {subsys_hps_lwhps2fpga} {EXPORT_OF} {subsys_hps_lwhps2fpga_translator.s0};add_interface {subsys_periph_pb_cpu_0_s0} {avalon} {master};set_interface_property {subsys_periph_pb_cpu_0_s0} {EXPORT_OF} {subsys_periph_pb_cpu_0_s0_translator.avalon_anti_slave_0};add_interface {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset} {EXPORT_OF} {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.in_reset};add_interface {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset} {EXPORT_OF} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.in_reset};add_interface {clk_100_out_clk} {clock} {slave};set_interface_property {clk_100_out_clk} {EXPORT_OF} {clk_100_out_clk_clock_bridge.in_clk};set_module_assignment {interconnect_id.subsys_hps.lwhps2fpga} {0};set_module_assignment {interconnect_id.subsys_periph.pb_cpu_0_s0} {0};</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_mm_interconnect</className>
<version>19.2.0</version>
<name>mm_interconnect_0</name>
<uniqueName>qsys_top_altera_mm_interconnect_1920_ykfyxdi</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>clockRateSysInfo</name>
<value>-1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>mm_interconnect_0/clk_100_out_clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>domainAlias</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>addressWidthSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>TRUE</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>slaveDataWidthSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>4</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
<parameter>
<name>defaultConnection</name>
<value>false</value>
</parameter>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>cpuInfoIdSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>baseAddress</name>
<value>0x0000</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>PER_BURST_TYPE_CONVERTER</value>
</parameter>
<parameter>
<name>arbitrationPriority</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>addressMapSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon</className>
<version>26.1</version>
<end>subsys_periph/pb_cpu_0_s0</end>
<start>mm_interconnect_0/subsys_periph_pb_cpu_0_s0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>mm_interconnect_0/subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset</end>
<start>rst_controller/reset_out</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>mm_interconnect_0/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset</end>
<start>rst_controller/reset_out</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>domainAlias</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>addressWidthSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>TRUE</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>slaveDataWidthSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>4</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
<parameter>
<name>defaultConnection</name>
<value>false</value>
</parameter>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>cpuInfoIdSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>baseAddress</name>
<value>0x0000</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>PER_BURST_TYPE_CONVERTER</value>
</parameter>
<parameter>
<name>arbitrationPriority</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>addressMapSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon</className>
<version>26.1</version>
<end>mm_interconnect_0/subsys_hps_lwhps2fpga</end>
<start>subsys_hps/lwhps2fpga</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0</path>
</instanceData>
<children>
<node>
<instanceKey xsi:type="xs:string">agent_pipeline</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>BITS_PER_SYMBOL</name>
<value>171</value>
</parameter>
<parameter>
<name>CHANNEL_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>EMPTY_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>ERROR_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>MAX_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>PACKET_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>PIPELINE_READY</name>
<value>1</value>
</parameter>
<parameter>
<name>SYMBOLS_PER_BEAT</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_EMPTY</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_PACKETS</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_avalon_st_pipeline_stage</className>
<version>19.3.0</version>
<name>agent_pipeline</name>
<uniqueName>qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp</name>
<end>subsys_periph_pb_cpu_0_s0_agent/cp</end>
<start>agent_pipeline/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/agent_pipeline.cr0</name>
<end>agent_pipeline/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/agent_pipeline.cr0_reset</name>
<end>agent_pipeline/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0</name>
<end>agent_pipeline/sink0</end>
<start>subsys_periph_pb_cpu_0_s0_burst_adapter/source0</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.agent_pipeline</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">agent_pipeline_001</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>BITS_PER_SYMBOL</name>
<value>171</value>
</parameter>
<parameter>
<name>CHANNEL_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>EMPTY_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>ERROR_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>MAX_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>PACKET_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>PIPELINE_READY</name>
<value>1</value>
</parameter>
<parameter>
<name>SYMBOLS_PER_BEAT</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_EMPTY</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_PACKETS</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_avalon_st_pipeline_stage</className>
<version>19.3.0</version>
<name>agent_pipeline_001</name>
<uniqueName>qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>agent_pipeline_001.source0/router_002.sink</name>
<end>router_002/sink</end>
<start>agent_pipeline_001/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/agent_pipeline_001.cr0</name>
<end>agent_pipeline_001/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0</name>
<end>agent_pipeline_001/sink0</end>
<start>subsys_periph_pb_cpu_0_s0_agent/rp</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/agent_pipeline_001.cr0_reset</name>
<end>agent_pipeline_001/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.agent_pipeline_001</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">clk_100_out_clk_clock_bridge</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>DERIVED_CLOCK_RATE</name>
<value>0</value>
</parameter>
<parameter>
<name>EXPLICIT_CLOCK_RATE</name>
<value>100000000</value>
</parameter>
<parameter>
<name>NUM_CLOCK_OUTPUTS</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_clock_bridge</className>
<version>19.2.0</version>
<name>clk_100_out_clk_clock_bridge</name>
<uniqueName>qsys_top_altera_clock_bridge_1920_njakcna</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/agent_pipeline.cr0</name>
<end>agent_pipeline/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/agent_pipeline_001.cr0</name>
<end>agent_pipeline_001/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/cmd_demux.clk</name>
<end>cmd_demux/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/cmd_demux_001.clk</name>
<end>cmd_demux_001/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/cmd_mux.clk</name>
<end>cmd_mux/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/mux_pipeline.cr0</name>
<end>mux_pipeline/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_001.cr0</name>
<end>mux_pipeline_001/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_002.cr0</name>
<end>mux_pipeline_002/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_003.cr0</name>
<end>mux_pipeline_003/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/router.clk</name>
<end>router/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/router_001.clk</name>
<end>router_001/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/router_002.clk</name>
<end>router_002/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/rsp_demux.clk</name>
<end>rsp_demux/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/rsp_mux.clk</name>
<end>rsp_mux/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/rsp_mux_001.clk</name>
<end>rsp_mux_001/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_agent.clk</name>
<end>subsys_hps_lwhps2fpga_agent/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_translator.clk</name>
<end>subsys_hps_lwhps2fpga_translator/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.clk</name>
<end>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent.clk</name>
<end>subsys_periph_pb_cpu_0_s0_agent/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.clk</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_burst_adapter.cr0</name>
<end>subsys_periph_pb_cpu_0_s0_burst_adapter/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_translator.clk</name>
<end>subsys_periph_pb_cpu_0_s0_translator/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.clk_100_out_clk_clock_bridge</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">cmd_demux</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>NUM_OUTPUTS</name>
<value>1</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>VALID_WIDTH</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_demultiplexer</className>
<version>19.2.1</version>
<name>cmd_demux</name>
<uniqueName>qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/cmd_demux.clk</name>
<end>cmd_demux/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>cmd_demux.src0/mux_pipeline.sink0</name>
<end>mux_pipeline/sink0</end>
<start>cmd_demux/src0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>router.src/cmd_demux.sink</name>
<end>cmd_demux/sink</end>
<start>router/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_demux.clk_reset</name>
<end>cmd_demux/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.cmd_demux</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">cmd_demux_001</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>NUM_OUTPUTS</name>
<value>1</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>VALID_WIDTH</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_demultiplexer</className>
<version>19.2.1</version>
<name>cmd_demux_001</name>
<uniqueName>qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/cmd_demux_001.clk</name>
<end>cmd_demux_001/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>cmd_demux_001.src0/mux_pipeline_001.sink0</name>
<end>mux_pipeline_001/sink0</end>
<start>cmd_demux_001/src0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>router_001.src/cmd_demux_001.sink</name>
<end>cmd_demux_001/sink</end>
<start>router_001/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_demux_001.clk_reset</name>
<end>cmd_demux_001/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.cmd_demux_001</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">cmd_mux</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>ARBITRATION_SCHEME</name>
<value>round-robin</value>
</parameter>
<parameter>
<name>ARBITRATION_SHARES</name>
<value>1,1</value>
</parameter>
<parameter>
<name>ENABLE_OOO_CHUNKS</name>
<value>0</value>
</parameter>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>NUM_INPUTS</name>
<value>2</value>
</parameter>
<parameter>
<name>PIPELINE_ARB</name>
<value>1</value>
</parameter>
<parameter>
<name>PKT_EOP_OOO</name>
<value>134</value>
</parameter>
<parameter>
<name>PKT_SOP_OOO</name>
<value>135</value>
</parameter>
<parameter>
<name>PKT_TRANS_LOCK</name>
<value>69</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_EXTERNAL_ARB</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_multiplexer</className>
<version>19.2.2</version>
<name>cmd_mux</name>
<uniqueName>qsys_top_altera_merlin_multiplexer_1922_666s25q</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/cmd_mux.clk</name>
<end>cmd_mux/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0</name>
<end>subsys_periph_pb_cpu_0_s0_burst_adapter/sink0</end>
<start>cmd_mux/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>mux_pipeline.source0/cmd_mux.sink0</name>
<end>cmd_mux/sink0</end>
<start>mux_pipeline/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>mux_pipeline_001.source0/cmd_mux.sink1</name>
<end>cmd_mux/sink1</end>
<start>mux_pipeline_001/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_mux.clk_reset</name>
<end>cmd_mux/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.cmd_mux</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">mux_pipeline</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>BITS_PER_SYMBOL</name>
<value>171</value>
</parameter>
<parameter>
<name>CHANNEL_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>EMPTY_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>ERROR_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>MAX_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>PACKET_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>PIPELINE_READY</name>
<value>1</value>
</parameter>
<parameter>
<name>SYMBOLS_PER_BEAT</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_EMPTY</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_PACKETS</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_avalon_st_pipeline_stage</className>
<version>19.3.0</version>
<name>mux_pipeline</name>
<uniqueName>qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/mux_pipeline.cr0</name>
<end>mux_pipeline/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>cmd_demux.src0/mux_pipeline.sink0</name>
<end>mux_pipeline/sink0</end>
<start>cmd_demux/src0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>mux_pipeline.source0/cmd_mux.sink0</name>
<end>cmd_mux/sink0</end>
<start>mux_pipeline/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline.cr0_reset</name>
<end>mux_pipeline/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.mux_pipeline</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">mux_pipeline_001</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>BITS_PER_SYMBOL</name>
<value>171</value>
</parameter>
<parameter>
<name>CHANNEL_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>EMPTY_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>ERROR_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>MAX_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>PACKET_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>PIPELINE_READY</name>
<value>1</value>
</parameter>
<parameter>
<name>SYMBOLS_PER_BEAT</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_EMPTY</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_PACKETS</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_avalon_st_pipeline_stage</className>
<version>19.3.0</version>
<name>mux_pipeline_001</name>
<uniqueName>qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_001.cr0</name>
<end>mux_pipeline_001/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>cmd_demux_001.src0/mux_pipeline_001.sink0</name>
<end>mux_pipeline_001/sink0</end>
<start>cmd_demux_001/src0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>mux_pipeline_001.source0/cmd_mux.sink1</name>
<end>cmd_mux/sink1</end>
<start>mux_pipeline_001/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_001.cr0_reset</name>
<end>mux_pipeline_001/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.mux_pipeline_001</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">mux_pipeline_002</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>BITS_PER_SYMBOL</name>
<value>171</value>
</parameter>
<parameter>
<name>CHANNEL_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>EMPTY_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>ERROR_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>MAX_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>PACKET_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>PIPELINE_READY</name>
<value>1</value>
</parameter>
<parameter>
<name>SYMBOLS_PER_BEAT</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_EMPTY</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_PACKETS</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_avalon_st_pipeline_stage</className>
<version>19.3.0</version>
<name>mux_pipeline_002</name>
<uniqueName>qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_002.cr0</name>
<end>mux_pipeline_002/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>mux_pipeline_002.source0/rsp_mux.sink0</name>
<end>rsp_mux/sink0</end>
<start>mux_pipeline_002/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>rsp_demux.src0/mux_pipeline_002.sink0</name>
<end>mux_pipeline_002/sink0</end>
<start>rsp_demux/src0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_002.cr0_reset</name>
<end>mux_pipeline_002/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.mux_pipeline_002</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">mux_pipeline_003</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>BITS_PER_SYMBOL</name>
<value>171</value>
</parameter>
<parameter>
<name>CHANNEL_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>EMPTY_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>ERROR_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>MAX_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>PACKET_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>PIPELINE_READY</name>
<value>1</value>
</parameter>
<parameter>
<name>SYMBOLS_PER_BEAT</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_EMPTY</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_PACKETS</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_avalon_st_pipeline_stage</className>
<version>19.3.0</version>
<name>mux_pipeline_003</name>
<uniqueName>qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_003.cr0</name>
<end>mux_pipeline_003/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>mux_pipeline_003.source0/rsp_mux_001.sink0</name>
<end>rsp_mux_001/sink0</end>
<start>mux_pipeline_003/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>rsp_demux.src1/mux_pipeline_003.sink0</name>
<end>mux_pipeline_003/sink0</end>
<start>rsp_demux/src1</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_003.cr0_reset</name>
<end>mux_pipeline_003/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.mux_pipeline_003</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">router</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>CHANNEL_ID</name>
<value>1</value>
</parameter>
<parameter>
<name>DECODER_TYPE</name>
<value>0</value>
</parameter>
<parameter>
<name>DEFAULT_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>DEFAULT_DESTID</name>
<value>0</value>
</parameter>
<parameter>
<name>DEFAULT_RD_CHANNEL</name>
<value>-1</value>
</parameter>
<parameter>
<name>DEFAULT_WR_CHANNEL</name>
<value>-1</value>
</parameter>
<parameter>
<name>DESTINATION_ID</name>
<value>0</value>
</parameter>
<parameter>
<name>END_ADDRESS</name>
<value>0x20000</value>
</parameter>
<parameter>
<name>HAS_USER_DEFAULT_SLAVE</name>
<value>0</value>
</parameter>
<parameter>
<name>MEMORY_ALIASING_DECODE</name>
<value>0</value>
</parameter>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>NON_SECURED_TAG</name>
<value>1</value>
</parameter>
<parameter>
<name>PKT_ADDR_H</name>
<value>64</value>
</parameter>
<parameter>
<name>PKT_ADDR_L</name>
<value>36</value>
</parameter>
<parameter>
<name>PKT_DEST_ID_H</name>
<value>102</value>
</parameter>
<parameter>
<name>PKT_DEST_ID_L</name>
<value>102</value>
</parameter>
<parameter>
<name>PKT_PROTECTION_H</name>
<value>109</value>
</parameter>
<parameter>
<name>PKT_PROTECTION_L</name>
<value>107</value>
</parameter>
<parameter>
<name>PKT_TRANS_READ</name>
<value>68</value>
</parameter>
<parameter>
<name>PKT_TRANS_WRITE</name>
<value>67</value>
</parameter>
<parameter>
<name>SECURED_RANGE_LIST</name>
<value>0</value>
</parameter>
<parameter>
<name>SECURED_RANGE_PAIRS</name>
<value>0</value>
</parameter>
<parameter>
<name>SLAVES_INFO</name>
<value>0:1:0x0:0x20000:both:1:0:0:1</value>
</parameter>
<parameter>
<name>SPAN_OFFSET</name>
<value></value>
</parameter>
<parameter>
<name>START_ADDRESS</name>
<value>0x0</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>TYPE_OF_TRANSACTION</name>
<value>both</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_router</className>
<version>19.2.1</version>
<name>router</name>
<uniqueName>qsys_top_altera_merlin_router_1921_ox5xuhq</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/router.clk</name>
<end>router/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>router.src/cmd_demux.sink</name>
<end>cmd_demux/sink</end>
<start>router/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_agent.write_cp/router.sink</name>
<end>router/sink</end>
<start>subsys_hps_lwhps2fpga_agent/write_cp</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router.clk_reset</name>
<end>router/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.router</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">router_001</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>CHANNEL_ID</name>
<value>1</value>
</parameter>
<parameter>
<name>DECODER_TYPE</name>
<value>0</value>
</parameter>
<parameter>
<name>DEFAULT_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>DEFAULT_DESTID</name>
<value>0</value>
</parameter>
<parameter>
<name>DEFAULT_RD_CHANNEL</name>
<value>-1</value>
</parameter>
<parameter>
<name>DEFAULT_WR_CHANNEL</name>
<value>-1</value>
</parameter>
<parameter>
<name>DESTINATION_ID</name>
<value>0</value>
</parameter>
<parameter>
<name>END_ADDRESS</name>
<value>0x20000</value>
</parameter>
<parameter>
<name>HAS_USER_DEFAULT_SLAVE</name>
<value>0</value>
</parameter>
<parameter>
<name>MEMORY_ALIASING_DECODE</name>
<value>0</value>
</parameter>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>NON_SECURED_TAG</name>
<value>1</value>
</parameter>
<parameter>
<name>PKT_ADDR_H</name>
<value>64</value>
</parameter>
<parameter>
<name>PKT_ADDR_L</name>
<value>36</value>
</parameter>
<parameter>
<name>PKT_DEST_ID_H</name>
<value>102</value>
</parameter>
<parameter>
<name>PKT_DEST_ID_L</name>
<value>102</value>
</parameter>
<parameter>
<name>PKT_PROTECTION_H</name>
<value>109</value>
</parameter>
<parameter>
<name>PKT_PROTECTION_L</name>
<value>107</value>
</parameter>
<parameter>
<name>PKT_TRANS_READ</name>
<value>68</value>
</parameter>
<parameter>
<name>PKT_TRANS_WRITE</name>
<value>67</value>
</parameter>
<parameter>
<name>SECURED_RANGE_LIST</name>
<value>0</value>
</parameter>
<parameter>
<name>SECURED_RANGE_PAIRS</name>
<value>0</value>
</parameter>
<parameter>
<name>SLAVES_INFO</name>
<value>0:1:0x0:0x20000:both:1:0:0:1</value>
</parameter>
<parameter>
<name>SPAN_OFFSET</name>
<value></value>
</parameter>
<parameter>
<name>START_ADDRESS</name>
<value>0x0</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>TYPE_OF_TRANSACTION</name>
<value>both</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_router</className>
<version>19.2.1</version>
<name>router_001</name>
<uniqueName>qsys_top_altera_merlin_router_1921_ox5xuhq</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/router_001.clk</name>
<end>router_001/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>router_001.src/cmd_demux_001.sink</name>
<end>cmd_demux_001/sink</end>
<start>router_001/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink</name>
<end>router_001/sink</end>
<start>subsys_hps_lwhps2fpga_agent/read_cp</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router_001.clk_reset</name>
<end>router_001/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.router_001</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">router_002</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>CHANNEL_ID</name>
<value>01,10</value>
</parameter>
<parameter>
<name>DECODER_TYPE</name>
<value>1</value>
</parameter>
<parameter>
<name>DEFAULT_CHANNEL</name>
<value>-1</value>
</parameter>
<parameter>
<name>DEFAULT_DESTID</name>
<value>0</value>
</parameter>
<parameter>
<name>DEFAULT_RD_CHANNEL</name>
<value>1</value>
</parameter>
<parameter>
<name>DEFAULT_WR_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>DESTINATION_ID</name>
<value>0,0</value>
</parameter>
<parameter>
<name>END_ADDRESS</name>
<value>0x0,0x0</value>
</parameter>
<parameter>
<name>HAS_USER_DEFAULT_SLAVE</name>
<value>0</value>
</parameter>
<parameter>
<name>MEMORY_ALIASING_DECODE</name>
<value>0</value>
</parameter>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>NON_SECURED_TAG</name>
<value>1,1</value>
</parameter>
<parameter>
<name>PKT_ADDR_H</name>
<value>64</value>
</parameter>
<parameter>
<name>PKT_ADDR_L</name>
<value>36</value>
</parameter>
<parameter>
<name>PKT_DEST_ID_H</name>
<value>102</value>
</parameter>
<parameter>
<name>PKT_DEST_ID_L</name>
<value>102</value>
</parameter>
<parameter>
<name>PKT_PROTECTION_H</name>
<value>109</value>
</parameter>
<parameter>
<name>PKT_PROTECTION_L</name>
<value>107</value>
</parameter>
<parameter>
<name>PKT_TRANS_READ</name>
<value>68</value>
</parameter>
<parameter>
<name>PKT_TRANS_WRITE</name>
<value>67</value>
</parameter>
<parameter>
<name>SECURED_RANGE_LIST</name>
<value>0,0</value>
</parameter>
<parameter>
<name>SECURED_RANGE_PAIRS</name>
<value>0,0</value>
</parameter>
<parameter>
<name>SLAVES_INFO</name>
<value>0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1</value>
</parameter>
<parameter>
<name>SPAN_OFFSET</name>
<value></value>
</parameter>
<parameter>
<name>START_ADDRESS</name>
<value>0x0,0x0</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>TYPE_OF_TRANSACTION</name>
<value>write,read</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_router</className>
<version>19.2.1</version>
<name>router_002</name>
<uniqueName>qsys_top_altera_merlin_router_1921_sxavatq</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>agent_pipeline_001.source0/router_002.sink</name>
<end>router_002/sink</end>
<start>agent_pipeline_001/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/router_002.clk</name>
<end>router_002/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>router_002.src/rsp_demux.sink</name>
<end>rsp_demux/sink</end>
<start>router_002/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router_002.clk_reset</name>
<end>router_002/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.router_002</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">rsp_demux</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>NUM_OUTPUTS</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>VALID_WIDTH</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_demultiplexer</className>
<version>19.2.1</version>
<name>rsp_demux</name>
<uniqueName>qsys_top_altera_merlin_demultiplexer_1921_qyizksq</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/rsp_demux.clk</name>
<end>rsp_demux/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>router_002.src/rsp_demux.sink</name>
<end>rsp_demux/sink</end>
<start>router_002/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>rsp_demux.src0/mux_pipeline_002.sink0</name>
<end>mux_pipeline_002/sink0</end>
<start>rsp_demux/src0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>rsp_demux.src1/mux_pipeline_003.sink0</name>
<end>mux_pipeline_003/sink0</end>
<start>rsp_demux/src1</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_demux.clk_reset</name>
<end>rsp_demux/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.rsp_demux</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">rsp_mux</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>ARBITRATION_SCHEME</name>
<value>no-arb</value>
</parameter>
<parameter>
<name>ARBITRATION_SHARES</name>
<value>1</value>
</parameter>
<parameter>
<name>ENABLE_OOO_CHUNKS</name>
<value>0</value>
</parameter>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>NUM_INPUTS</name>
<value>1</value>
</parameter>
<parameter>
<name>PIPELINE_ARB</name>
<value>0</value>
</parameter>
<parameter>
<name>PKT_EOP_OOO</name>
<value>134</value>
</parameter>
<parameter>
<name>PKT_SOP_OOO</name>
<value>135</value>
</parameter>
<parameter>
<name>PKT_TRANS_LOCK</name>
<value>69</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_EXTERNAL_ARB</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_multiplexer</className>
<version>19.2.2</version>
<name>rsp_mux</name>
<uniqueName>qsys_top_altera_merlin_multiplexer_1922_yjgptii</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/rsp_mux.clk</name>
<end>rsp_mux/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>mux_pipeline_002.source0/rsp_mux.sink0</name>
<end>rsp_mux/sink0</end>
<start>mux_pipeline_002/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp</name>
<end>subsys_hps_lwhps2fpga_agent/write_rp</end>
<start>rsp_mux/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_mux.clk_reset</name>
<end>rsp_mux/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.rsp_mux</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">rsp_mux_001</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>ARBITRATION_SCHEME</name>
<value>no-arb</value>
</parameter>
<parameter>
<name>ARBITRATION_SHARES</name>
<value>1</value>
</parameter>
<parameter>
<name>ENABLE_OOO_CHUNKS</name>
<value>0</value>
</parameter>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>NUM_INPUTS</name>
<value>1</value>
</parameter>
<parameter>
<name>PIPELINE_ARB</name>
<value>0</value>
</parameter>
<parameter>
<name>PKT_EOP_OOO</name>
<value>134</value>
</parameter>
<parameter>
<name>PKT_SOP_OOO</name>
<value>135</value>
</parameter>
<parameter>
<name>PKT_TRANS_LOCK</name>
<value>69</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_EXTERNAL_ARB</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_multiplexer</className>
<version>19.2.2</version>
<name>rsp_mux_001</name>
<uniqueName>qsys_top_altera_merlin_multiplexer_1922_yjgptii</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/rsp_mux_001.clk</name>
<end>rsp_mux_001/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>mux_pipeline_003.source0/rsp_mux_001.sink0</name>
<end>rsp_mux_001/sink0</end>
<start>mux_pipeline_003/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp</name>
<end>subsys_hps_lwhps2fpga_agent/read_rp</end>
<start>rsp_mux_001/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_mux_001.clk_reset</name>
<end>rsp_mux_001/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.rsp_mux_001</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">subsys_hps_lwhps2fpga_agent</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>ACE5_LITE_SUPPORT</name>
<value>0</value>
</parameter>
<parameter>
<name>ACE_LITE_SUPPORT</name>
<value>0</value>
</parameter>
<parameter>
<name>ADDRCHK_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>ADDR_MAP</name>
<value>&lt;?xml version="1.0" encoding="UTF-8"?&gt;
&lt;address_map&gt;
&lt;slave
id="0"
name="subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0"
start="0x0000000000000000"
end="0x00000000000020000"
responds="1"
user_default="0" /&gt;
&lt;/address_map&gt;
</value>
</parameter>
<parameter>
<name>ADDR_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>ADDR_WIDTH</name>
<value>29</value>
</parameter>
<parameter>
<name>AWSNOOP_WIDTH</name>
<value>3</value>
</parameter>
<parameter>
<name>AXI_BURST_LENGTH_WIDTH</name>
<value>8</value>
</parameter>
<parameter>
<name>AXI_LOCK_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>AXI_VERSION</name>
<value>AXI4</value>
</parameter>
<parameter>
<name>DATA_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>ENABLE_AXI5</name>
<value>0</value>
</parameter>
<parameter>
<name>ID</name>
<value>0</value>
</parameter>
<parameter>
<name>ID_WIDTH</name>
<value>4</value>
</parameter>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>PKT_ADDRCHK_H</name>
<value>132</value>
</parameter>
<parameter>
<name>PKT_ADDRCHK_L</name>
<value>131</value>
</parameter>
<parameter>
<name>PKT_ADDR_H</name>
<value>64</value>
</parameter>
<parameter>
<name>PKT_ADDR_L</name>
<value>36</value>
</parameter>
<parameter>
<name>PKT_ADDR_SIDEBAND_H</name>
<value>94</value>
</parameter>
<parameter>
<name>PKT_ADDR_SIDEBAND_L</name>
<value>94</value>
</parameter>
<parameter>
<name>PKT_ATRACE</name>
<value>141</value>
</parameter>
<parameter>
<name>PKT_AWAKEUP</name>
<value>143</value>
</parameter>
<parameter>
<name>PKT_AWATOP_H</name>
<value>149</value>
</parameter>
<parameter>
<name>PKT_AWATOP_L</name>
<value>144</value>
</parameter>
<parameter>
<name>PKT_AWSTASHLPIDEN</name>
<value>167</value>
</parameter>
<parameter>
<name>PKT_AWSTASHLPID_H</name>
<value>166</value>
</parameter>
<parameter>
<name>PKT_AWSTASHLPID_L</name>
<value>162</value>
</parameter>
<parameter>
<name>PKT_AWSTASHNIDEN</name>
<value>161</value>
</parameter>
<parameter>
<name>PKT_AWSTASHNID_H</name>
<value>160</value>
</parameter>
<parameter>
<name>PKT_AWSTASHNID_L</name>
<value>150</value>
</parameter>
<parameter>
<name>PKT_BARRIER_H</name>
<value>120</value>
</parameter>
<parameter>
<name>PKT_BARRIER_L</name>
<value>119</value>
</parameter>
<parameter>
<name>PKT_BEGIN_BURST</name>
<value>96</value>
</parameter>
<parameter>
<name>PKT_BURSTWRAP_H</name>
<value>88</value>
</parameter>
<parameter>
<name>PKT_BURSTWRAP_L</name>
<value>82</value>
</parameter>
<parameter>
<name>PKT_BURST_SIZE_H</name>
<value>91</value>
</parameter>
<parameter>
<name>PKT_BURST_SIZE_L</name>
<value>89</value>
</parameter>
<parameter>
<name>PKT_BURST_TYPE_H</name>
<value>93</value>
</parameter>
<parameter>
<name>PKT_BURST_TYPE_L</name>
<value>92</value>
</parameter>
<parameter>
<name>PKT_BYTEEN_H</name>
<value>35</value>
</parameter>
<parameter>
<name>PKT_BYTEEN_L</name>
<value>32</value>
</parameter>
<parameter>
<name>PKT_BYTE_CNT_H</name>
<value>81</value>
</parameter>
<parameter>
<name>PKT_BYTE_CNT_L</name>
<value>71</value>
</parameter>
<parameter>
<name>PKT_CACHE_H</name>
<value>113</value>
</parameter>
<parameter>
<name>PKT_CACHE_L</name>
<value>110</value>
</parameter>
<parameter>
<name>PKT_DATACHK_H</name>
<value>129</value>
</parameter>
<parameter>
<name>PKT_DATACHK_L</name>
<value>129</value>
</parameter>
<parameter>
<name>PKT_DATALESS</name>
<value>170</value>
</parameter>
<parameter>
<name>PKT_DATA_H</name>
<value>31</value>
</parameter>
<parameter>
<name>PKT_DATA_L</name>
<value>0</value>
</parameter>
<parameter>
<name>PKT_DATA_SIDEBAND_H</name>
<value>95</value>
</parameter>
<parameter>
<name>PKT_DATA_SIDEBAND_L</name>
<value>95</value>
</parameter>
<parameter>
<name>PKT_DEST_ID_H</name>
<value>102</value>
</parameter>
<parameter>
<name>PKT_DEST_ID_L</name>
<value>102</value>
</parameter>
<parameter>
<name>PKT_DOMAIN_H</name>
<value>126</value>
</parameter>
<parameter>
<name>PKT_DOMAIN_L</name>
<value>125</value>
</parameter>
<parameter>
<name>PKT_EOP_OOO</name>
<value>134</value>
</parameter>
<parameter>
<name>PKT_MMUSECSID</name>
<value>169</value>
</parameter>
<parameter>
<name>PKT_MMUSID_H</name>
<value>168</value>
</parameter>
<parameter>
<name>PKT_MMUSID_L</name>
<value>168</value>
</parameter>
<parameter>
<name>PKT_ORI_BURST_SIZE_H</name>
<value>118</value>
</parameter>
<parameter>
<name>PKT_ORI_BURST_SIZE_L</name>
<value>116</value>
</parameter>
<parameter>
<name>PKT_POISON_H</name>
<value>128</value>
</parameter>
<parameter>
<name>PKT_POISON_L</name>
<value>128</value>
</parameter>
<parameter>
<name>PKT_PROTECTION_H</name>
<value>109</value>
</parameter>
<parameter>
<name>PKT_PROTECTION_L</name>
<value>107</value>
</parameter>
<parameter>
<name>PKT_QOS_H</name>
<value>100</value>
</parameter>
<parameter>
<name>PKT_QOS_L</name>
<value>97</value>
</parameter>
<parameter>
<name>PKT_RESPONSE_STATUS_H</name>
<value>115</value>
</parameter>
<parameter>
<name>PKT_RESPONSE_STATUS_L</name>
<value>114</value>
</parameter>
<parameter>
<name>PKT_SAI_H</name>
<value>133</value>
</parameter>
<parameter>
<name>PKT_SAI_L</name>
<value>133</value>
</parameter>
<parameter>
<name>PKT_SNOOP_H</name>
<value>124</value>
</parameter>
<parameter>
<name>PKT_SNOOP_L</name>
<value>121</value>
</parameter>
<parameter>
<name>PKT_SOP_OOO</name>
<value>135</value>
</parameter>
<parameter>
<name>PKT_SRC_ID_H</name>
<value>101</value>
</parameter>
<parameter>
<name>PKT_SRC_ID_L</name>
<value>101</value>
</parameter>
<parameter>
<name>PKT_THREAD_ID_H</name>
<value>106</value>
</parameter>
<parameter>
<name>PKT_THREAD_ID_L</name>
<value>103</value>
</parameter>
<parameter>
<name>PKT_TRACE</name>
<value>142</value>
</parameter>
<parameter>
<name>PKT_TRANS_COMPRESSED_READ</name>
<value>65</value>
</parameter>
<parameter>
<name>PKT_TRANS_EXCLUSIVE</name>
<value>70</value>
</parameter>
<parameter>
<name>PKT_TRANS_LOCK</name>
<value>69</value>
</parameter>
<parameter>
<name>PKT_TRANS_POSTED</name>
<value>66</value>
</parameter>
<parameter>
<name>PKT_TRANS_READ</name>
<value>68</value>
</parameter>
<parameter>
<name>PKT_TRANS_SEQ_H</name>
<value>140</value>
</parameter>
<parameter>
<name>PKT_TRANS_SEQ_L</name>
<value>136</value>
</parameter>
<parameter>
<name>PKT_TRANS_WRITE</name>
<value>67</value>
</parameter>
<parameter>
<name>PKT_USER_DATA_H</name>
<value>130</value>
</parameter>
<parameter>
<name>PKT_USER_DATA_L</name>
<value>130</value>
</parameter>
<parameter>
<name>PKT_WUNIQUE</name>
<value>127</value>
</parameter>
<parameter>
<name>RDATA_WIDTH</name>
<value>32</value>
</parameter>
<parameter>
<name>READ_ISSUING_CAPABILITY</name>
<value>16</value>
</parameter>
<parameter>
<name>RESP_USER_WIDTH</name>
<value>8</value>
</parameter>
<parameter>
<name>ROLE_BASED_USER</name>
<value>0</value>
</parameter>
<parameter>
<name>SAI_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>SID_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>TERMINATE_READ_TERMINAL</name>
<value>0</value>
</parameter>
<parameter>
<name>TERMINATE_READ_UNIVERSAL</name>
<value>0</value>
</parameter>
<parameter>
<name>TERMINATE_WRITE_TERMINAL</name>
<value>0</value>
</parameter>
<parameter>
<name>TERMINATE_WRITE_UNIVERSAL</name>
<value>0</value>
</parameter>
<parameter>
<name>USER_DATA_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_ADDR_USER</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_PKT_ADDRCHK</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_PKT_DATACHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_POISON</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_TRACE</name>
<value>1</value>
</parameter>
<parameter>
<name>WDATA_WIDTH</name>
<value>32</value>
</parameter>
<parameter>
<name>WRITE_ISSUING_CAPABILITY</name>
<value>16</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_axi_master_ni</className>
<version>19.11.7</version>
<name>subsys_hps_lwhps2fpga_agent</name>
<uniqueName>qsys_top_altera_merlin_axi_master_ni_19117_qautany</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_agent.clk</name>
<end>subsys_hps_lwhps2fpga_agent/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp</name>
<end>subsys_hps_lwhps2fpga_agent/write_rp</end>
<start>rsp_mux/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp</name>
<end>subsys_hps_lwhps2fpga_agent/read_rp</end>
<start>rsp_mux_001/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink</name>
<end>router_001/sink</end>
<start>subsys_hps_lwhps2fpga_agent/read_cp</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_agent.write_cp/router.sink</name>
<end>router/sink</end>
<start>subsys_hps_lwhps2fpga_agent/write_cp</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>domainAlias</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>addressWidthSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>slaveDataWidthSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
<parameter>
<name>defaultConnection</name>
<value>false</value>
</parameter>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>cpuInfoIdSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>baseAddress</name>
<value>0x0000</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>arbitrationPriority</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>addressMapSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave</name>
<end>subsys_hps_lwhps2fpga_agent/altera_axi_slave</end>
<start>subsys_hps_lwhps2fpga_translator/m0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_hps_lwhps2fpga_agent.clk_reset</name>
<end>subsys_hps_lwhps2fpga_agent/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_agent</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">subsys_hps_lwhps2fpga_translator</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>ACE5_LITE_SUPPORT</name>
<value>0</value>
</parameter>
<parameter>
<name>ACE_LITE_SUPPORT</name>
<value>0</value>
</parameter>
<parameter>
<name>COMBINED_ACCEPTANCE_CAPABILITY</name>
<value>16</value>
</parameter>
<parameter>
<name>COMBINED_ISSUING_CAPABILITY</name>
<value>16</value>
</parameter>
<parameter>
<name>DATA_WIDTH</name>
<value>32</value>
</parameter>
<parameter>
<name>ENABLE_AXI5</name>
<value>0</value>
</parameter>
<parameter>
<name>IS_TRANSLATOR</name>
<value>1</value>
</parameter>
<parameter>
<name>M0_ADDR_WIDTH</name>
<value>29</value>
</parameter>
<parameter>
<name>M0_AWSNOOP_WIDTH</name>
<value>3</value>
</parameter>
<parameter>
<name>M0_AXI_VERSION</name>
<value>AXI4</value>
</parameter>
<parameter>
<name>M0_BURST_LENGTH_WIDTH</name>
<value>8</value>
</parameter>
<parameter>
<name>M0_ID_WIDTH</name>
<value>4</value>
</parameter>
<parameter>
<name>M0_LOCK_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>M0_READ_ADDR_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>M0_READ_DATA_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>M0_SAI_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>M0_SID_WIDTH</name>
<value>16</value>
</parameter>
<parameter>
<name>M0_USER_ADDRCHK_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>M0_WRITE_ADDR_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>M0_WRITE_DATA_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>M0_WRITE_RESPONSE_DATA_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>READ_ACCEPTANCE_CAPABILITY</name>
<value>16</value>
</parameter>
<parameter>
<name>READ_DATA_REORDERING_DEPTH</name>
<value>1</value>
</parameter>
<parameter>
<name>READ_ISSUING_CAPABILITY</name>
<value>16</value>
</parameter>
<parameter>
<name>REGENERATE_ADDRCHK</name>
<value>0</value>
</parameter>
<parameter>
<name>ROLE_BASED_USER</name>
<value>0</value>
</parameter>
<parameter>
<name>S0_ADDR_WIDTH</name>
<value>29</value>
</parameter>
<parameter>
<name>S0_AWSNOOP_WIDTH</name>
<value>3</value>
</parameter>
<parameter>
<name>S0_AXI_VERSION</name>
<value>AXI4</value>
</parameter>
<parameter>
<name>S0_BURST_LENGTH_WIDTH</name>
<value>8</value>
</parameter>
<parameter>
<name>S0_ID_WIDTH</name>
<value>4</value>
</parameter>
<parameter>
<name>S0_LOCK_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>S0_READ_ADDR_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>S0_READ_DATA_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>S0_SAI_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>S0_SID_WIDTH</name>
<value>16</value>
</parameter>
<parameter>
<name>S0_USER_ADDRCHK_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>S0_WRITE_ADDR_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>S0_WRITE_DATA_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>S0_WRITE_RESPONSE_DATA_USER_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>TERMINATE_READ_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>TERMINATE_WRITE_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>USER_DATA_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_ARADDRCHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_ARCACHE</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_ARLOCK</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_ARMMUSECSID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_ARMMUSID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_ARPROT</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_ARQOS</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_ARREGION</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_ARTRACE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_ARUSER</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_ARUSER_ADDRCHK</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_ARUSER_SAI</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_AWADDRCHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_AWAKEUP</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_AWATOP</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_AWCACHE</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_AWLOCK</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_AWMMUSECSID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_AWMMUSID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_AWPROT</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_AWQOS</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_AWREGION</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_AWSTASHLPID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_AWSTASHLPIDEN</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_AWSTASHNID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_AWSTASHNIDEN</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_AWTRACE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_AWUNIQUE</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_AWUSER</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_AWUSER_ADDRCHK</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_AWUSER_SAI</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_BRESP</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_BTRACE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_BUSER</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_RDATACHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_RPOISON</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_RRESP</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_RTRACE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_RUSER</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_RUSER_DATA</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_RUSER_DATACHK</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_RUSER_POISON</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_WDATACHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_WLAST</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_WPOISON</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_WTRACE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_M0_WUSER</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_WUSER_DATA</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_WUSER_DATACHK</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_M0_WUSER_POISON</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_ARADDRCHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_ARBURST</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_ARCACHE</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_ARID</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_ARLEN</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_ARLOCK</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_ARMMUSECSID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_ARMMUSID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_ARPROT</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_ARQOS</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_ARREGION</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_ARSIZE</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_ARSNOOP</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_ARTRACE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_ARUSER</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_ARUSER_ADDRCHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_ARUSER_SAI</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWADDRCHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWAKEUP</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWATOP</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWBURST</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_AWCACHE</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_AWID</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_AWLEN</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_AWLOCK</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_AWMMUSECSID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWMMUSID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWPROT</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_AWQOS</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWREGION</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWSIZE</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_AWSNOOP</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_AWSTASHLPID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWSTASHLPIDEN</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWSTASHNID</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWSTASHNIDEN</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWTRACE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWUNIQUE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWUSER</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWUSER_ADDRCHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_AWUSER_SAI</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_BID</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_BRESP</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_BTRACE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_BUSER</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_RDATACHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_RID</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_RLAST</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_RPOISON</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_RRESP</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_RTRACE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_RUSER</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_RUSER_DATA</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_RUSER_DATACHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_RUSER_POISON</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_WDATACHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_WLAST</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_WPOISON</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_WSTRB</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_S0_WTRACE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_WUSER</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_WUSER_DATA</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_WUSER_DATACHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_S0_WUSER_POISON</name>
<value>0</value>
</parameter>
<parameter>
<name>WRITE_ACCEPTANCE_CAPABILITY</name>
<value>16</value>
</parameter>
<parameter>
<name>WRITE_ISSUING_CAPABILITY</name>
<value>16</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_axi_translator</className>
<version>19.8.7</version>
<name>subsys_hps_lwhps2fpga_translator</name>
<uniqueName>qsys_top_altera_merlin_axi_translator_1987_lty7xoq</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_translator.clk</name>
<end>subsys_hps_lwhps2fpga_translator/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>domainAlias</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>addressWidthSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>slaveDataWidthSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
<parameter>
<name>defaultConnection</name>
<value>false</value>
</parameter>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>cpuInfoIdSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>baseAddress</name>
<value>0x0000</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>arbitrationPriority</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>addressMapSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave</name>
<end>subsys_hps_lwhps2fpga_agent/altera_axi_slave</end>
<start>subsys_hps_lwhps2fpga_translator/m0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_hps_lwhps2fpga_translator.clk_reset</name>
<end>subsys_hps_lwhps2fpga_translator/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_translator</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>ACTIVE_LOW_RESET</name>
<value>0</value>
</parameter>
<parameter>
<name>NUM_RESET_OUTPUTS</name>
<value>1</value>
</parameter>
<parameter>
<name>O_SYNCHRONOUS_EDGES</name>
<value>deassert</value>
</parameter>
<parameter>
<name>SYNCHRONOUS_EDGES</name>
<value>deassert</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_reset_bridge</className>
<version>19.2.0</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge</name>
<uniqueName>qsys_top_altera_reset_bridge_1920_xf2264i</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.clk</name>
<end>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_demux.clk_reset</name>
<end>cmd_demux/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_demux_001.clk_reset</name>
<end>cmd_demux_001/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_mux.clk_reset</name>
<end>cmd_mux/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router.clk_reset</name>
<end>router/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router_001.clk_reset</name>
<end>router_001/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router_002.clk_reset</name>
<end>router_002/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_demux.clk_reset</name>
<end>rsp_demux/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_mux.clk_reset</name>
<end>rsp_mux/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_mux_001.clk_reset</name>
<end>rsp_mux_001/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_hps_lwhps2fpga_agent.clk_reset</name>
<end>subsys_hps_lwhps2fpga_agent/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_hps_lwhps2fpga_translator.clk_reset</name>
<end>subsys_hps_lwhps2fpga_translator/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent.clk_reset</name>
<end>subsys_periph_pb_cpu_0_s0_agent/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_burst_adapter.cr0_reset</name>
<end>subsys_periph_pb_cpu_0_s0_burst_adapter/cr0_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_translator.reset</name>
<end>subsys_periph_pb_cpu_0_s0_translator/reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">subsys_periph_pb_cpu_0_s0_agent</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>AVS_BURSTCOUNT_SYMBOLS</name>
<value>0</value>
</parameter>
<parameter>
<name>AVS_BURSTCOUNT_W</name>
<value>3</value>
</parameter>
<parameter>
<name>AV_LINEWRAPBURSTS</name>
<value>0</value>
</parameter>
<parameter>
<name>ECC_ENABLE</name>
<value>0</value>
</parameter>
<parameter>
<name>ENABLE_AXI5</name>
<value>0</value>
</parameter>
<parameter>
<name>ID</name>
<value>0</value>
</parameter>
<parameter>
<name>MAX_BURSTWRAP</name>
<value>127</value>
</parameter>
<parameter>
<name>MAX_BYTE_CNT</name>
<value>4</value>
</parameter>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>PKT_ADDRCHK_H</name>
<value>132</value>
</parameter>
<parameter>
<name>PKT_ADDRCHK_L</name>
<value>131</value>
</parameter>
<parameter>
<name>PKT_ADDR_H</name>
<value>64</value>
</parameter>
<parameter>
<name>PKT_ADDR_L</name>
<value>36</value>
</parameter>
<parameter>
<name>PKT_ATRACE</name>
<value>141</value>
</parameter>
<parameter>
<name>PKT_AWAKEUP</name>
<value>143</value>
</parameter>
<parameter>
<name>PKT_AWATOP_H</name>
<value>149</value>
</parameter>
<parameter>
<name>PKT_AWATOP_L</name>
<value>144</value>
</parameter>
<parameter>
<name>PKT_AWSTASHLPIDEN</name>
<value>167</value>
</parameter>
<parameter>
<name>PKT_AWSTASHLPID_H</name>
<value>166</value>
</parameter>
<parameter>
<name>PKT_AWSTASHLPID_L</name>
<value>162</value>
</parameter>
<parameter>
<name>PKT_AWSTASHNIDEN</name>
<value>161</value>
</parameter>
<parameter>
<name>PKT_AWSTASHNID_H</name>
<value>160</value>
</parameter>
<parameter>
<name>PKT_AWSTASHNID_L</name>
<value>150</value>
</parameter>
<parameter>
<name>PKT_BEGIN_BURST</name>
<value>96</value>
</parameter>
<parameter>
<name>PKT_BURSTWRAP_H</name>
<value>88</value>
</parameter>
<parameter>
<name>PKT_BURSTWRAP_L</name>
<value>82</value>
</parameter>
<parameter>
<name>PKT_BURST_SIZE_H</name>
<value>91</value>
</parameter>
<parameter>
<name>PKT_BURST_SIZE_L</name>
<value>89</value>
</parameter>
<parameter>
<name>PKT_BYTEEN_H</name>
<value>35</value>
</parameter>
<parameter>
<name>PKT_BYTEEN_L</name>
<value>32</value>
</parameter>
<parameter>
<name>PKT_BYTE_CNT_H</name>
<value>81</value>
</parameter>
<parameter>
<name>PKT_BYTE_CNT_L</name>
<value>71</value>
</parameter>
<parameter>
<name>PKT_DATACHK_H</name>
<value>129</value>
</parameter>
<parameter>
<name>PKT_DATACHK_L</name>
<value>129</value>
</parameter>
<parameter>
<name>PKT_DATALESS</name>
<value>170</value>
</parameter>
<parameter>
<name>PKT_DATA_H</name>
<value>31</value>
</parameter>
<parameter>
<name>PKT_DATA_L</name>
<value>0</value>
</parameter>
<parameter>
<name>PKT_DEST_ID_H</name>
<value>102</value>
</parameter>
<parameter>
<name>PKT_DEST_ID_L</name>
<value>102</value>
</parameter>
<parameter>
<name>PKT_EOP_OOO</name>
<value>134</value>
</parameter>
<parameter>
<name>PKT_MMUSECSID</name>
<value>169</value>
</parameter>
<parameter>
<name>PKT_MMUSID_H</name>
<value>168</value>
</parameter>
<parameter>
<name>PKT_MMUSID_L</name>
<value>168</value>
</parameter>
<parameter>
<name>PKT_ORI_BURST_SIZE_H</name>
<value>118</value>
</parameter>
<parameter>
<name>PKT_ORI_BURST_SIZE_L</name>
<value>116</value>
</parameter>
<parameter>
<name>PKT_POISON_H</name>
<value>128</value>
</parameter>
<parameter>
<name>PKT_POISON_L</name>
<value>128</value>
</parameter>
<parameter>
<name>PKT_PROTECTION_H</name>
<value>109</value>
</parameter>
<parameter>
<name>PKT_PROTECTION_L</name>
<value>107</value>
</parameter>
<parameter>
<name>PKT_RESPONSE_STATUS_H</name>
<value>115</value>
</parameter>
<parameter>
<name>PKT_RESPONSE_STATUS_L</name>
<value>114</value>
</parameter>
<parameter>
<name>PKT_SAI_H</name>
<value>133</value>
</parameter>
<parameter>
<name>PKT_SAI_L</name>
<value>133</value>
</parameter>
<parameter>
<name>PKT_SOP_OOO</name>
<value>135</value>
</parameter>
<parameter>
<name>PKT_SRC_ID_H</name>
<value>101</value>
</parameter>
<parameter>
<name>PKT_SRC_ID_L</name>
<value>101</value>
</parameter>
<parameter>
<name>PKT_SYMBOL_W</name>
<value>8</value>
</parameter>
<parameter>
<name>PKT_TRACE</name>
<value>142</value>
</parameter>
<parameter>
<name>PKT_TRANS_COMPRESSED_READ</name>
<value>65</value>
</parameter>
<parameter>
<name>PKT_TRANS_LOCK</name>
<value>69</value>
</parameter>
<parameter>
<name>PKT_TRANS_POSTED</name>
<value>66</value>
</parameter>
<parameter>
<name>PKT_TRANS_READ</name>
<value>68</value>
</parameter>
<parameter>
<name>PKT_TRANS_SEQ_H</name>
<value>140</value>
</parameter>
<parameter>
<name>PKT_TRANS_SEQ_L</name>
<value>136</value>
</parameter>
<parameter>
<name>PKT_TRANS_WRITE</name>
<value>67</value>
</parameter>
<parameter>
<name>PKT_USER_DATA_H</name>
<value>130</value>
</parameter>
<parameter>
<name>PKT_USER_DATA_L</name>
<value>130</value>
</parameter>
<parameter>
<name>PREVENT_FIFO_OVERFLOW</name>
<value>1</value>
</parameter>
<parameter>
<name>ROLE_BASED_USER</name>
<value>0</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SUPPRESS_0_BYTEEN_CMD</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_MEMORY_BLOCKS</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_PKT_DATACHK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_READRESPONSE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_WRITERESPONSE</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_slave_agent</className>
<version>19.3.0</version>
<name>subsys_periph_pb_cpu_0_s0_agent</name>
<uniqueName>qsys_top_altera_merlin_slave_agent_1930_jxauz3i</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp</name>
<end>subsys_periph_pb_cpu_0_s0_agent/cp</end>
<start>agent_pipeline/source0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent.clk</name>
<end>subsys_periph_pb_cpu_0_s0_agent/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent.clk_reset</name>
<end>subsys_periph_pb_cpu_0_s0_agent/clk_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>domainAlias</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>addressWidthSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>slaveDataWidthSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
<parameter>
<name>defaultConnection</name>
<value>false</value>
</parameter>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>cpuInfoIdSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>baseAddress</name>
<value>0x0000</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>arbitrationPriority</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>addressMapSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0</name>
<end>subsys_periph_pb_cpu_0_s0_translator/avalon_universal_slave_0</end>
<start>subsys_periph_pb_cpu_0_s0_agent/m0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/in</end>
<start>subsys_periph_pb_cpu_0_s0_agent/rdata_fifo_src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/in</end>
<start>subsys_periph_pb_cpu_0_s0_agent/rf_source</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0</name>
<end>agent_pipeline_001/sink0</end>
<start>subsys_periph_pb_cpu_0_s0_agent/rp</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink</name>
<end>subsys_periph_pb_cpu_0_s0_agent/rdata_fifo_sink</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/out</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink</name>
<end>subsys_periph_pb_cpu_0_s0_agent/rf_sink</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/out</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">subsys_periph_pb_cpu_0_s0_agent_rdata_fifo</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>BITS_PER_SYMBOL</name>
<value>34</value>
</parameter>
<parameter>
<name>CHANNEL_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>EMPTY_LATENCY</name>
<value>0</value>
</parameter>
<parameter>
<name>EMPTY_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>ENABLE_EXPLICIT_MAXCHANNEL</name>
<value>false</value>
</parameter>
<parameter>
<name>ERROR_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>EXPLICIT_MAXCHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>FIFO_DEPTH</name>
<value>2</value>
</parameter>
<parameter>
<name>MEM_TYPE</name>
<value>M20K</value>
</parameter>
<parameter>
<name>SYMBOLS_PER_BEAT</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_ALMOST_EMPTY_IF</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_ALMOST_FULL_IF</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_FILL_LEVEL</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_MEMORY_BLOCKS</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_PACKETS</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_STORE_FORWARD</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_avalon_sc_fifo</className>
<version>19.3.2</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rdata_fifo</name>
<uniqueName>qsys_top_altera_avalon_sc_fifo_1932_22gxxgi</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/in</end>
<start>subsys_periph_pb_cpu_0_s0_agent/rdata_fifo_src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink</name>
<end>subsys_periph_pb_cpu_0_s0_agent/rdata_fifo_sink</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/out</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk_reset</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/clk_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rdata_fifo</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">subsys_periph_pb_cpu_0_s0_agent_rsp_fifo</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>BITS_PER_SYMBOL</name>
<value>172</value>
</parameter>
<parameter>
<name>CHANNEL_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>EMPTY_LATENCY</name>
<value>1</value>
</parameter>
<parameter>
<name>EMPTY_WIDTH</name>
<value>1</value>
</parameter>
<parameter>
<name>ENABLE_EXPLICIT_MAXCHANNEL</name>
<value>false</value>
</parameter>
<parameter>
<name>ERROR_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>EXPLICIT_MAXCHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>FIFO_DEPTH</name>
<value>2</value>
</parameter>
<parameter>
<name>MEM_TYPE</name>
<value>M20K</value>
</parameter>
<parameter>
<name>SYMBOLS_PER_BEAT</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_ALMOST_EMPTY_IF</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_ALMOST_FULL_IF</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_FILL_LEVEL</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_MEMORY_BLOCKS</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_PACKETS</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_STORE_FORWARD</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_avalon_sc_fifo</className>
<version>19.3.2</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo</name>
<uniqueName>qsys_top_altera_avalon_sc_fifo_1932_22gxxgi</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/in</end>
<start>subsys_periph_pb_cpu_0_s0_agent/rf_source</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink</name>
<end>subsys_periph_pb_cpu_0_s0_agent/rf_sink</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/out</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk_reset</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/clk_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>ACTIVE_LOW_RESET</name>
<value>0</value>
</parameter>
<parameter>
<name>NUM_RESET_OUTPUTS</name>
<value>1</value>
</parameter>
<parameter>
<name>O_SYNCHRONOUS_EDGES</name>
<value>deassert</value>
</parameter>
<parameter>
<name>SYNCHRONOUS_EDGES</name>
<value>deassert</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_reset_bridge</className>
<version>19.2.0</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge</name>
<uniqueName>qsys_top_altera_reset_bridge_1920_xf2264i</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.clk</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/agent_pipeline.cr0_reset</name>
<end>agent_pipeline/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/agent_pipeline_001.cr0_reset</name>
<end>agent_pipeline_001/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline.cr0_reset</name>
<end>mux_pipeline/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_001.cr0_reset</name>
<end>mux_pipeline_001/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_002.cr0_reset</name>
<end>mux_pipeline_002/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_003.cr0_reset</name>
<end>mux_pipeline_003/cr0_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk_reset</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/clk_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk_reset</name>
<end>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/clk_reset</end>
<start>subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">subsys_periph_pb_cpu_0_s0_burst_adapter</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>ADAPTER_VERSION</name>
<value>new</value>
</parameter>
<parameter>
<name>BURSTWRAP_CONST_MASK</name>
<value>0</value>
</parameter>
<parameter>
<name>BURSTWRAP_CONST_VALUE</name>
<value>0</value>
</parameter>
<parameter>
<name>BYTEENABLE_SYNTHESIS</name>
<value>1</value>
</parameter>
<parameter>
<name>COMPRESSED_READ_SUPPORT</name>
<value>1</value>
</parameter>
<parameter>
<name>ENABLE_AXI5</name>
<value>0</value>
</parameter>
<parameter>
<name>ENABLE_OOO</name>
<value>0</value>
</parameter>
<parameter>
<name>INCOMPLETE_WRAP_SUPPORT</name>
<value>0</value>
</parameter>
<parameter>
<name>IN_NARROW_SIZE</name>
<value>1</value>
</parameter>
<parameter>
<name>MERLIN_PACKET_FORMAT</name>
<value>dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)</value>
</parameter>
<parameter>
<name>NO_WRAP_SUPPORT</name>
<value>0</value>
</parameter>
<parameter>
<name>OUT_BURSTWRAP_H</name>
<value>88</value>
</parameter>
<parameter>
<name>OUT_BYTE_CNT_H</name>
<value>73</value>
</parameter>
<parameter>
<name>OUT_COMPLETE_WRAP</name>
<value>0</value>
</parameter>
<parameter>
<name>OUT_FIXED</name>
<value>0</value>
</parameter>
<parameter>
<name>OUT_NARROW_SIZE</name>
<value>0</value>
</parameter>
<parameter>
<name>PIPE_INPUTS</name>
<value>0</value>
</parameter>
<parameter>
<name>PKT_ADDR_H</name>
<value>64</value>
</parameter>
<parameter>
<name>PKT_ADDR_L</name>
<value>36</value>
</parameter>
<parameter>
<name>PKT_BEGIN_BURST</name>
<value>96</value>
</parameter>
<parameter>
<name>PKT_BURSTWRAP_H</name>
<value>88</value>
</parameter>
<parameter>
<name>PKT_BURSTWRAP_L</name>
<value>82</value>
</parameter>
<parameter>
<name>PKT_BURST_SIZE_H</name>
<value>91</value>
</parameter>
<parameter>
<name>PKT_BURST_SIZE_L</name>
<value>89</value>
</parameter>
<parameter>
<name>PKT_BURST_TYPE_H</name>
<value>93</value>
</parameter>
<parameter>
<name>PKT_BURST_TYPE_L</name>
<value>92</value>
</parameter>
<parameter>
<name>PKT_BYTEEN_H</name>
<value>35</value>
</parameter>
<parameter>
<name>PKT_BYTEEN_L</name>
<value>32</value>
</parameter>
<parameter>
<name>PKT_BYTE_CNT_H</name>
<value>81</value>
</parameter>
<parameter>
<name>PKT_BYTE_CNT_L</name>
<value>71</value>
</parameter>
<parameter>
<name>PKT_EOP_OOO</name>
<value>89</value>
</parameter>
<parameter>
<name>PKT_SAI_H</name>
<value>133</value>
</parameter>
<parameter>
<name>PKT_SAI_L</name>
<value>133</value>
</parameter>
<parameter>
<name>PKT_SOP_OOO</name>
<value>90</value>
</parameter>
<parameter>
<name>PKT_TRANS_COMPRESSED_READ</name>
<value>65</value>
</parameter>
<parameter>
<name>PKT_TRANS_READ</name>
<value>68</value>
</parameter>
<parameter>
<name>PKT_TRANS_WRITE</name>
<value>67</value>
</parameter>
<parameter>
<name>ROLE_BASED_USER</name>
<value>0</value>
</parameter>
<parameter>
<name>ST_CHANNEL_W</name>
<value>2</value>
</parameter>
<parameter>
<name>ST_DATA_W</name>
<value>171</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_burst_adapter</className>
<version>19.4.0</version>
<name>subsys_periph_pb_cpu_0_s0_burst_adapter</name>
<uniqueName>qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_burst_adapter.cr0</name>
<end>subsys_periph_pb_cpu_0_s0_burst_adapter/cr0</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0</name>
<end>subsys_periph_pb_cpu_0_s0_burst_adapter/sink0</end>
<start>cmd_mux/src</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_burst_adapter.cr0_reset</name>
<end>subsys_periph_pb_cpu_0_s0_burst_adapter/cr0_reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon_streaming</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0</name>
<end>agent_pipeline/sink0</end>
<start>subsys_periph_pb_cpu_0_s0_burst_adapter/source0</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter</path>
</instanceData>
<children>
<node>
<instanceKey xsi:type="xs:string">my_altera_avalon_st_pipeline_stage</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>BITS_PER_SYMBOL</name>
<value>171</value>
</parameter>
<parameter>
<name>CHANNEL_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>EMPTY_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>ERROR_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>MAX_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>PACKET_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>PIPELINE_READY</name>
<value>1</value>
</parameter>
<parameter>
<name>SYMBOLS_PER_BEAT</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_EMPTY</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_PACKETS</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage</className>
<version>19.4.0</version>
<name>my_altera_avalon_st_pipeline_stage</name>
<uniqueName>qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di</uniqueName>
<nonce>0</nonce>
<incidentConnections></incidentConnections>
<path>qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage</path>
</instanceData>
<children>
<node>
<instanceKey xsi:type="xs:string">my_altera_avalon_st_pipeline_stage</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>BITS_PER_SYMBOL</name>
<value>171</value>
</parameter>
<parameter>
<name>CHANNEL_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>EMPTY_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>ERROR_WIDTH</name>
<value>0</value>
</parameter>
<parameter>
<name>MAX_CHANNEL</name>
<value>0</value>
</parameter>
<parameter>
<name>PACKET_WIDTH</name>
<value>2</value>
</parameter>
<parameter>
<name>PIPELINE_READY</name>
<value>1</value>
</parameter>
<parameter>
<name>SYMBOLS_PER_BEAT</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_EMPTY</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_PACKETS</name>
<value>1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_avalon_st_pipeline_stage</className>
<version>19.3.0</version>
<name>my_altera_avalon_st_pipeline_stage</name>
<uniqueName>qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq</uniqueName>
<nonce>0</nonce>
<incidentConnections></incidentConnections>
<path>qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage.my_altera_avalon_st_pipeline_stage</path>
</instanceData>
<children></children>
</node>
</children>
</node>
</children>
</node>
<node>
<instanceKey xsi:type="xs:string">subsys_periph_pb_cpu_0_s0_translator</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>AV_ADDRESSGROUP</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_ADDRESS_SYMBOLS</name>
<value>1</value>
</parameter>
<parameter>
<name>AV_ADDRESS_W</name>
<value>17</value>
</parameter>
<parameter>
<name>AV_ALWAYSBURSTMAXBURST</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_BITS_PER_SYMBOL</name>
<value>8</value>
</parameter>
<parameter>
<name>AV_BURSTBOUNDARIES</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_BURSTCOUNT_SYMBOLS</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_BURSTCOUNT_W</name>
<value>1</value>
</parameter>
<parameter>
<name>AV_BYTEENABLE_W</name>
<value>4</value>
</parameter>
<parameter>
<name>AV_CONSTANT_BURST_BEHAVIOR</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_DATA_HOLD</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_DATA_HOLD_CYCLES</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_DATA_W</name>
<value>32</value>
</parameter>
<parameter>
<name>AV_INTERLEAVEBURSTS</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_ISBIGENDIAN</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_LINEWRAPBURSTS</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_MAX_PENDING_READ_TRANSACTIONS</name>
<value>1</value>
</parameter>
<parameter>
<name>AV_MAX_PENDING_WRITE_TRANSACTIONS</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_READLATENCY</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_READ_WAIT</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_READ_WAIT_CYCLES</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_REGISTERINCOMINGSIGNALS</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_REGISTEROUTGOINGSIGNALS</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_SETUP_WAIT</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_SETUP_WAIT_CYCLES</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_SYMBOLS_PER_WORD</name>
<value>4</value>
</parameter>
<parameter>
<name>AV_TIMING_UNITS</name>
<value>1</value>
</parameter>
<parameter>
<name>AV_WRITE_WAIT</name>
<value>0</value>
</parameter>
<parameter>
<name>AV_WRITE_WAIT_CYCLES</name>
<value>0</value>
</parameter>
<parameter>
<name>CHIPSELECT_THROUGH_READLATENCY</name>
<value>0</value>
</parameter>
<parameter>
<name>CLOCK_RATE</name>
<value>100000000</value>
</parameter>
<parameter>
<name>SYNC_RESET</name>
<value>1</value>
</parameter>
<parameter>
<name>UAV_ADDRESSGROUP</name>
<value>0</value>
</parameter>
<parameter>
<name>UAV_ADDRESS_W</name>
<value>29</value>
</parameter>
<parameter>
<name>UAV_BURSTCOUNT_W</name>
<value>3</value>
</parameter>
<parameter>
<name>UAV_BYTEENABLE_W</name>
<value>4</value>
</parameter>
<parameter>
<name>UAV_CONSTANT_BURST_BEHAVIOR</name>
<value>0</value>
</parameter>
<parameter>
<name>UAV_DATA_W</name>
<value>32</value>
</parameter>
<parameter>
<name>USE_ADDRESS</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_AV_CLKEN</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_BEGINBURSTTRANSFER</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_BEGINTRANSFER</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_BURSTCOUNT</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_BYTEENABLE</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_CHIPSELECT</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_DEBUGACCESS</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_LOCK</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_OUTPUTENABLE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_READ</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_READDATA</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_READDATAVALID</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_READRESPONSE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_UAV_CLKEN</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_WAITREQUEST</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_WRITE</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_WRITEBYTEENABLE</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_WRITEDATA</name>
<value>1</value>
</parameter>
<parameter>
<name>USE_WRITERESPONSE</name>
<value>0</value>
</parameter>
<parameter>
<name>WAITREQUEST_ALLOWANCE</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_merlin_slave_translator</className>
<version>19.1</version>
<name>subsys_periph_pb_cpu_0_s0_translator</name>
<uniqueName>qsys_top_altera_merlin_slave_translator_191_xg7rzxi</uniqueName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<name>clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_translator.clk</name>
<end>subsys_periph_pb_cpu_0_s0_translator/clk</end>
<start>clk_100_out_clk_clock_bridge/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<name>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_translator.reset</name>
<end>subsys_periph_pb_cpu_0_s0_translator/reset</end>
<start>subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>domainAlias</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>addressWidthSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>slaveDataWidthSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
<parameter>
<name>defaultConnection</name>
<value>false</value>
</parameter>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>cpuInfoIdSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>baseAddress</name>
<value>0x0000</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>arbitrationPriority</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>addressMapSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon</className>
<version>26.1</version>
<name>subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0</name>
<end>subsys_periph_pb_cpu_0_s0_translator/avalon_universal_slave_0</end>
<start>subsys_periph_pb_cpu_0_s0_agent/m0</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_translator</path>
</instanceData>
<children></children>
</node>
</children>
</node>
<node>
<instanceKey xsi:type="xs:string">rst_controller</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>ADAPT_RESET_REQUEST</name>
<value>0</value>
</parameter>
<parameter>
<name>MIN_RST_ASSERTION_TIME</name>
<value>3</value>
</parameter>
<parameter>
<name>NUM_RESET_INPUTS</name>
<value>1</value>
</parameter>
<parameter>
<name>OUTPUT_RESET_SYNC_EDGES</name>
<value>both</value>
</parameter>
<parameter>
<name>RESET_REQUEST_PRESENT</name>
<value>0</value>
</parameter>
<parameter>
<name>RESET_REQ_EARLY_DSRT_TIME</name>
<value>1</value>
</parameter>
<parameter>
<name>RESET_REQ_WAIT_TIME</name>
<value>1</value>
</parameter>
<parameter>
<name>SYNC_DEPTH</name>
<value>2</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN0</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN1</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN10</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN11</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN12</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN13</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN14</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN15</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN2</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN3</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN4</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN5</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN6</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN7</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN8</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_IN9</name>
<value>0</value>
</parameter>
<parameter>
<name>USE_RESET_REQUEST_INPUT</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_reset_controller</className>
<version>19.2.4</version>
<name>rst_controller</name>
<uniqueName>altera_reset_controller</uniqueName>
<fixedName>altera_reset_controller</fixedName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>clockRateSysInfo</name>
<value>-1</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>rst_controller/clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>mm_interconnect_0/subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset</end>
<start>rst_controller/reset_out</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>mm_interconnect_0/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset</end>
<start>rst_controller/reset_out</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>rst_controller/reset_in0</end>
<start>rst_in/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.rst_controller</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">rst_in</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>AUTO_CLK_CLOCK_RATE</name>
<value>-1</value>
</parameter>
<parameter>
<name>bspCpu</name>
<value>false</value>
</parameter>
<parameter>
<name>componentDefinition</name>
<value>&lt;componentDefinition&gt;
&lt;boundary&gt;
&lt;interfaces&gt;
&lt;interface&gt;
&lt;name&gt;in_reset&lt;/name&gt;
&lt;type&gt;reset&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;in_reset_n&lt;/name&gt;
&lt;role&gt;reset_n&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;terminationValue&gt;0&lt;/terminationValue&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;synchronousEdges&lt;/key&gt;
&lt;value&gt;NONE&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;out_reset&lt;/name&gt;
&lt;type&gt;reset&lt;/type&gt;
&lt;isStart&gt;true&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;out_reset_n&lt;/name&gt;
&lt;role&gt;reset_n&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;terminationValue&gt;0&lt;/terminationValue&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedDirectReset&lt;/key&gt;
&lt;value&gt;in_reset&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedResetSinks&lt;/key&gt;
&lt;value&gt;in_reset&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;synchronousEdges&lt;/key&gt;
&lt;value&gt;NONE&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;/interfaces&gt;
&lt;/boundary&gt;
&lt;originalModuleInfo&gt;
&lt;className&gt;altera_reset_bridge&lt;/className&gt;
&lt;version&gt;19.2.0&lt;/version&gt;
&lt;displayName&gt;Reset Bridge IP&lt;/displayName&gt;
&lt;/originalModuleInfo&gt;
&lt;systemInfoParameterDescriptors&gt;
&lt;descriptors&gt;
&lt;descriptor&gt;
&lt;parameterDefaultValue&gt;-1&lt;/parameterDefaultValue&gt;
&lt;parameterName&gt;AUTO_CLK_CLOCK_RATE&lt;/parameterName&gt;
&lt;parameterType&gt;java.lang.Long&lt;/parameterType&gt;
&lt;systemInfoArgs&gt;clk&lt;/systemInfoArgs&gt;
&lt;systemInfotype&gt;CLOCK_RATE&lt;/systemInfotype&gt;
&lt;/descriptor&gt;
&lt;/descriptors&gt;
&lt;/systemInfoParameterDescriptors&gt;
&lt;systemInfos&gt;
&lt;connPtSystemInfos/&gt;
&lt;/systemInfos&gt;
&lt;/componentDefinition&gt;</value>
</parameter>
<parameter>
<name>cpuHashInfo</name>
<value>&lt;cpuHashInfoDefinition&gt;
&lt;cpuHashInfoMap/&gt;
&lt;/cpuHashInfoDefinition&gt;</value>
</parameter>
<parameter>
<name>cpuInfo</name>
<value></value>
</parameter>
<parameter>
<name>defaultBoundary</name>
<value>&lt;boundaryDefinition&gt;
&lt;interfaces&gt;
&lt;interface&gt;
&lt;name&gt;in_reset&lt;/name&gt;
&lt;type&gt;reset&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;in_reset_n&lt;/name&gt;
&lt;role&gt;reset_n&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;terminationValue&gt;0&lt;/terminationValue&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;synchronousEdges&lt;/key&gt;
&lt;value&gt;NONE&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;out_reset&lt;/name&gt;
&lt;type&gt;reset&lt;/type&gt;
&lt;isStart&gt;true&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;out_reset_n&lt;/name&gt;
&lt;role&gt;reset_n&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;terminationValue&gt;0&lt;/terminationValue&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedDirectReset&lt;/key&gt;
&lt;value&gt;in_reset&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedResetSinks&lt;/key&gt;
&lt;value&gt;in_reset&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;synchronousEdges&lt;/key&gt;
&lt;value&gt;NONE&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;/interfaces&gt;
&lt;/boundaryDefinition&gt;</value>
</parameter>
<parameter>
<name>generationInfoDefinition</name>
<value>&lt;generationInfoDefinition&gt;
&lt;hdlLibraryName&gt;rst_in&lt;/hdlLibraryName&gt;
&lt;fileSets&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;rst_in&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;rst_in&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;QUARTUS_SYNTH&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;rst_in&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;rst_in&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;SIM_VERILOG&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;rst_in&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;rst_in&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;SIM_VHDL&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;rst_in&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;rst_in&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;CDC&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;rst_in&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;rst_in&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;CDC_VHDL&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;/fileSets&gt;
&lt;/generationInfoDefinition&gt;</value>
</parameter>
<parameter>
<name>hdlParameters</name>
<value>&lt;hdlParameterDescriptorDefinitionList/&gt;</value>
</parameter>
<parameter>
<name>hlsFile</name>
<value></value>
</parameter>
<parameter>
<name>liveModuleName</name>
<value>altera_reset_bridge_inst</value>
</parameter>
<parameter>
<name>logicalView</name>
<value>ip/qsys_top/rst_in.ip</value>
</parameter>
<parameter>
<name>moduleAssignmentDefinition</name>
<value>&lt;assignmentDefinition&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignmentDefinition&gt;</value>
</parameter>
<parameter>
<name>svInterfaceDefinition</name>
<value></value>
</parameter>
<parameter>
<name>transformParameters</name>
<value>&lt;transformParameterDescriptorDefinitionList/&gt;</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_generic_component</className>
<version>1.0</version>
<name>rst_in</name>
<uniqueName>rst_in</uniqueName>
<fixedName>rst_in</fixedName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>rst_controller/reset_in0</end>
<start>rst_in/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>subsys_hps/f2sdram_rst</end>
<start>rst_in/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>subsys_hps/hps2fpga_rst</end>
<start>rst_in/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>subsys_hps/lwhps2fpga_rst</end>
<start>rst_in/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>subsys_periph/reset</end>
<start>rst_in/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.rst_in</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">subsys_hps</instanceKey>
<instanceData xsi:type="data">
<parameters></parameters>
<interconnectAssignments></interconnectAssignments>
<className>hps_subsys</className>
<version>1.0</version>
<name>subsys_hps</name>
<uniqueName>hps_subsys</uniqueName>
<fixedName>hps_subsys</fixedName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>subsys_hps/f2sdram_clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>subsys_hps/hps2fpga_clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>subsys_hps/lwhps2fpga_clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>subsys_hps/f2sdram_rst</end>
<start>rst_in/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>subsys_hps/hps2fpga_rst</end>
<start>rst_in/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>subsys_hps/lwhps2fpga_rst</end>
<start>rst_in/out_reset</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>interruptsUsedSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>irqNumber</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>interrupt</className>
<version>26.1</version>
<end>irq_mapper/sender</end>
<start>subsys_hps/f2h_irq0_in</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>domainAlias</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>addressWidthSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>TRUE</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>slaveDataWidthSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>4</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
<parameter>
<name>defaultConnection</name>
<value>false</value>
</parameter>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>cpuInfoIdSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>baseAddress</name>
<value>0x0000</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>PER_BURST_TYPE_CONVERTER</value>
</parameter>
<parameter>
<name>arbitrationPriority</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>addressMapSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon</className>
<version>26.1</version>
<end>mm_interconnect_0/subsys_hps_lwhps2fpga</end>
<start>subsys_hps/lwhps2fpga</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.subsys_hps</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">subsys_periph</instanceKey>
<instanceData xsi:type="data">
<parameters></parameters>
<interconnectAssignments></interconnectAssignments>
<className>peripheral_subsys</className>
<version>1.0</version>
<name>subsys_periph</name>
<uniqueName>peripheral_subsys</uniqueName>
<fixedName>peripheral_subsys</fixedName>
<nonce>0</nonce>
<incidentConnections>
<incidentConnection>
<parameters>
<parameter>
<name>clockRateSysInfo</name>
<value>100000000</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>resetDomainSysInfo</name>
<value>1</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock</className>
<version>26.1</version>
<end>subsys_periph/clk</end>
<start>clk_100/out_clk</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>interruptsUsedSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>irqNumber</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>interrupt</className>
<version>26.1</version>
<end>subsys_periph/button_pio_irq</end>
<start>irq_mapper/receiver0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>interruptsUsedSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>irqNumber</name>
<value>0</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>interrupt</className>
<version>26.1</version>
<end>subsys_periph/dipsw_pio_irq</end>
<start>irq_mapper/receiver1</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>qsys_mm.insertDefaultSlave</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.enableOutOfOrderSupport</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>domainAlias</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.clockCrossingAdapter</name>
<value>AUTO</value>
</parameter>
<parameter>
<name>qsys_mm.widthAdapterImplementation</name>
<value>GENERIC_CONVERTER</value>
</parameter>
<parameter>
<name>addressWidthSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.optimizeRdFifoSize</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.syncResets</name>
<value>TRUE</value>
</parameter>
<parameter>
<name>qsys_mm.splitCommandsFor4KBoundary</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>slaveDataWidthSysInfo</name>
<value>-1</value>
</parameter>
<parameter>
<name>qsys_mm.maxAdditionalLatency</name>
<value>4</value>
</parameter>
<parameter>
<name>qsys_mm.enableAllPipelines</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>qsys_mm.interconnectType</name>
<value>STANDARD</value>
</parameter>
<parameter>
<name>defaultConnection</name>
<value>false</value>
</parameter>
<parameter>
<name>qsys_mm.piplineType</name>
<value>PIPELINE_STAGE</value>
</parameter>
<parameter>
<name>qsys_mm.enableInstrumentation</name>
<value>FALSE</value>
</parameter>
<parameter>
<name>cpuInfoIdSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.interconnectResetSource</name>
<value>DEFAULT</value>
</parameter>
<parameter>
<name>baseAddress</name>
<value>0x0000</value>
</parameter>
<parameter>
<name>qsys_mm.responseFifoType</name>
<value>REGISTER_BASED</value>
</parameter>
<parameter>
<name>qsys_mm.burstAdapterImplementation</name>
<value>PER_BURST_TYPE_CONVERTER</value>
</parameter>
<parameter>
<name>arbitrationPriority</name>
<value>1</value>
</parameter>
<parameter>
<name>qsys_mm.fifoDepth</name>
<value>8</value>
</parameter>
<parameter>
<name>addressMapSysInfo</name>
<value></value>
</parameter>
<parameter>
<name>qsys_mm.enableEccProtection</name>
<value>FALSE</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>avalon</className>
<version>26.1</version>
<end>subsys_periph/pb_cpu_0_s0</end>
<start>mm_interconnect_0/subsys_periph_pb_cpu_0_s0</start>
</incidentConnection>
<incidentConnection>
<parameters>
<parameter>
<name>resetDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockDomainSysInfo</name>
<value>4</value>
</parameter>
<parameter>
<name>clockResetSysInfo</name>
<value></value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>reset</className>
<version>26.1</version>
<end>subsys_periph/reset</end>
<start>rst_in/out_reset</start>
</incidentConnection>
</incidentConnections>
<path>qsys_top.subsys_periph</path>
</instanceData>
<children></children>
</node>
<node>
<instanceKey xsi:type="xs:string">user_rst_clkgate_0</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>DEVICE_FAMILY</name>
<value>Agilex 5</value>
</parameter>
<parameter>
<name>bspCpu</name>
<value>false</value>
</parameter>
<parameter>
<name>componentDefinition</name>
<value>&lt;componentDefinition&gt;
&lt;boundary&gt;
&lt;interfaces&gt;
&lt;interface&gt;
&lt;name&gt;ninit_done&lt;/name&gt;
&lt;type&gt;conduit&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;ninit_done&lt;/name&gt;
&lt;role&gt;ninit_done&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;terminationValue&gt;0&lt;/terminationValue&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedReset&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;prSafe&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;/interfaces&gt;
&lt;/boundary&gt;
&lt;originalModuleInfo&gt;
&lt;className&gt;intel_user_rst_clkgate&lt;/className&gt;
&lt;version&gt;1.0.1&lt;/version&gt;
&lt;displayName&gt;Reset Release IP&lt;/displayName&gt;
&lt;/originalModuleInfo&gt;
&lt;systemInfoParameterDescriptors&gt;
&lt;descriptors&gt;
&lt;descriptor&gt;
&lt;parameterDefaultValue&gt;&lt;/parameterDefaultValue&gt;
&lt;parameterName&gt;DEVICE_FAMILY&lt;/parameterName&gt;
&lt;parameterType&gt;java.lang.String&lt;/parameterType&gt;
&lt;systemInfotype&gt;DEVICE_FAMILY&lt;/systemInfotype&gt;
&lt;/descriptor&gt;
&lt;/descriptors&gt;
&lt;/systemInfoParameterDescriptors&gt;
&lt;systemInfos&gt;
&lt;connPtSystemInfos/&gt;
&lt;/systemInfos&gt;
&lt;/componentDefinition&gt;</value>
</parameter>
<parameter>
<name>cpuHashInfo</name>
<value>&lt;cpuHashInfoDefinition&gt;
&lt;cpuHashInfoMap/&gt;
&lt;/cpuHashInfoDefinition&gt;</value>
</parameter>
<parameter>
<name>cpuInfo</name>
<value></value>
</parameter>
<parameter>
<name>defaultBoundary</name>
<value>&lt;boundaryDefinition&gt;
&lt;interfaces&gt;
&lt;interface&gt;
&lt;name&gt;ninit_done&lt;/name&gt;
&lt;type&gt;conduit&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;ninit_done&lt;/name&gt;
&lt;role&gt;ninit_done&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;terminationValue&gt;0&lt;/terminationValue&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedReset&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;prSafe&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;/interfaces&gt;
&lt;/boundaryDefinition&gt;</value>
</parameter>
<parameter>
<name>generationInfoDefinition</name>
<value>&lt;generationInfoDefinition&gt;
&lt;hdlLibraryName&gt;user_rst_clkgate_0&lt;/hdlLibraryName&gt;
&lt;fileSets&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;user_rst_clkgate_0&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;user_rst_clkgate_0&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;QUARTUS_SYNTH&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;user_rst_clkgate_0&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;user_rst_clkgate_0&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;SIM_VERILOG&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;user_rst_clkgate_0&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;user_rst_clkgate_0&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;SIM_VHDL&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;user_rst_clkgate_0&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;user_rst_clkgate_0&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;CDC&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;fileSet&gt;
&lt;fileSetName&gt;user_rst_clkgate_0&lt;/fileSetName&gt;
&lt;fileSetFixedName&gt;user_rst_clkgate_0&lt;/fileSetFixedName&gt;
&lt;fileSetKind&gt;CDC_VHDL&lt;/fileSetKind&gt;
&lt;fileSetFiles/&gt;
&lt;fileSetFileChangeDefs/&gt;
&lt;/fileSet&gt;
&lt;/fileSets&gt;
&lt;/generationInfoDefinition&gt;</value>
</parameter>
<parameter>
<name>hdlParameters</name>
<value>&lt;hdlParameterDescriptorDefinitionList/&gt;</value>
</parameter>
<parameter>
<name>hlsFile</name>
<value></value>
</parameter>
<parameter>
<name>liveModuleName</name>
<value>intel_user_rst_clkgate_inst</value>
</parameter>
<parameter>
<name>logicalView</name>
<value>ip/qsys_top/user_rst_clkgate_0.ip</value>
</parameter>
<parameter>
<name>moduleAssignmentDefinition</name>
<value>&lt;assignmentDefinition&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignmentDefinition&gt;</value>
</parameter>
<parameter>
<name>svInterfaceDefinition</name>
<value></value>
</parameter>
<parameter>
<name>transformParameters</name>
<value>&lt;transformParameterDescriptorDefinitionList/&gt;</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_generic_component</className>
<version>1.0</version>
<name>user_rst_clkgate_0</name>
<uniqueName>user_rst_clkgate_0</uniqueName>
<fixedName>user_rst_clkgate_0</fixedName>
<nonce>0</nonce>
<incidentConnections></incidentConnections>
<path>qsys_top.user_rst_clkgate_0</path>
</instanceData>
<children></children>
</node>
</children>
</node>
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