qsys_top qsys_top 1.0 qsys_top qsys_top 0 clk_100 DERIVED_CLOCK_RATE 0 bspCpu false componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>in_clk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>in_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>out_clk</name> <type>clock</type> <isStart>true</isStart> <ports> <port> <name>out_clk</name> <role>clk</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedDirectClock</key> <value>in_clk</value> </entry> <entry> <key>clockRate</key> <value>100000000</value> </entry> <entry> <key>clockRateKnown</key> <value>true</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>altera_clock_bridge</className> <version>19.2.0</version> <displayName>Clock Bridge IP</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors> <descriptor> <parameterDefaultValue>0</parameterDefaultValue> <parameterName>DERIVED_CLOCK_RATE</parameterName> <parameterType>java.lang.Long</parameterType> <systemInfoArgs>in_clk</systemInfoArgs> <systemInfotype>CLOCK_RATE</systemInfotype> </descriptor> </descriptors> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos> <entry> <key>in_clk</key> <value> <connectionPointName>in_clk</connectionPointName> <suppliedSystemInfos/> <consumedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>0</value> </entry> </consumedSystemInfos> </value> </entry> <entry> <key>out_clk</key> <value> <connectionPointName>out_clk</connectionPointName> <suppliedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>100000000</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> </connPtSystemInfos> </systemInfos> </componentDefinition> cpuHashInfo <cpuHashInfoDefinition> <cpuHashInfoMap/> </cpuHashInfoDefinition> cpuInfo defaultBoundary <boundaryDefinition> <interfaces> <interface> <name>in_clk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>in_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>out_clk</name> <type>clock</type> <isStart>true</isStart> <ports> <port> <name>out_clk</name> <role>clk</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedDirectClock</key> <value>in_clk</value> </entry> <entry> <key>clockRate</key> <value>100000000</value> </entry> <entry> <key>clockRateKnown</key> <value>true</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundaryDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>clk_100</hdlLibraryName> <fileSets> <fileSet> <fileSetName>clk_100</fileSetName> <fileSetFixedName>clk_100</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>clk_100</fileSetName> <fileSetFixedName>clk_100</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>clk_100</fileSetName> <fileSetFixedName>clk_100</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>clk_100</fileSetName> <fileSetFixedName>clk_100</fileSetFixedName> <fileSetKind>CDC</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>clk_100</fileSetName> <fileSetFixedName>clk_100</fileSetFixedName> <fileSetKind>CDC_VHDL</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> </fileSets> </generationInfoDefinition> hdlParameters <hdlParameterDescriptorDefinitionList/> hlsFile liveModuleName altera_clock_bridge_inst logicalView ip/qsys_top/clk_100.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> svInterfaceDefinition transformParameters <transformParameterDescriptorDefinitionList/> altera_generic_component 1.0 clk_100 clk_100 clk_100 0 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clockRateSysInfo -1 clock 26.1 mm_interconnect_0/clk_100_out_clk clk_100/out_clk resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clockRateSysInfo -1 clock 26.1 rst_controller/clk clk_100/out_clk clockRateSysInfo 100000000 clockDomainSysInfo 1 resetDomainSysInfo 1 clockResetSysInfo clock 26.1 subsys_hps/f2sdram_clk clk_100/out_clk clockRateSysInfo 100000000 clockDomainSysInfo 1 resetDomainSysInfo 1 clockResetSysInfo clock 26.1 subsys_hps/hps2fpga_clk clk_100/out_clk clockRateSysInfo 100000000 clockDomainSysInfo 1 resetDomainSysInfo 1 clockResetSysInfo clock 26.1 subsys_hps/lwhps2fpga_clk clk_100/out_clk clockRateSysInfo 100000000 clockDomainSysInfo 1 resetDomainSysInfo 1 clockResetSysInfo clock 26.1 subsys_periph/clk clk_100/out_clk qsys_top.clk_100 irq_mapper IRQ_MAP 0:1,1:0 NUM_RCVRS 2 REMOVE_CLK_RST 0 SENDER_IRQ_WIDTH 32 SYNC_RESET 0 altera_irq_mapper 20.0.1 irq_mapper qsys_top_altera_irq_mapper_2001_lp4cnei 0 interruptsUsedSysInfo -1 irqNumber 0 interrupt 26.1 subsys_periph/button_pio_irq irq_mapper/receiver0 interruptsUsedSysInfo -1 irqNumber 0 interrupt 26.1 subsys_periph/dipsw_pio_irq irq_mapper/receiver1 interruptsUsedSysInfo -1 irqNumber 0 interrupt 26.1 irq_mapper/sender subsys_hps/f2h_irq0_in qsys_top.irq_mapper mm_interconnect_0 COMPOSE_CONTENTS add_instance {subsys_hps_lwhps2fpga_translator} {altera_merlin_axi_translator};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWREGION} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWREGION} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWLEN} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSIZE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWBURST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWQOS} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWQOS} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WSTRB} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WLAST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WLAST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_BRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARREGION} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARREGION} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARLEN} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARSIZE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARBURST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARQOS} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARQOS} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RLAST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_BUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUSER_ADDRCHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUSER_SAI} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARUSER_ADDRCHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARUSER_SAI} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER_DATACHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER_POISON} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER_DATACHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER_POISON} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER_DATA} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER_DATA} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWAKEUP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_BTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUNIQUE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWAKEUP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUSER_ADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUSER_SAI} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARUSER_ADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARUSER_SAI} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER_DATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER_POISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER_DATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER_DATA} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER_DATA} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER_POISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUNIQUE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWATOP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHNID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHNIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHLPID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHLPIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWATOP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHNID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHNIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHLPID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHLPIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSNOOP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARSNOOP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_ID_WIDTH} {4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {DATA_WIDTH} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_SAI_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_SAI_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USER_DATA_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_USER_ADDRCHK_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_USER_ADDRCHK_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_ID_WIDTH} {4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_ADDR_WIDTH} {29};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_WRITE_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_READ_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_WRITE_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_READ_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_WRITE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_WRITE_RESPONSE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_READ_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_WRITE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_WRITE_RESPONSE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_READ_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_ADDR_WIDTH} {29};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_SID_WIDTH} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_SID_WIDTH} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {WRITE_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {READ_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {COMBINED_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {WRITE_ACCEPTANCE_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {READ_ACCEPTANCE_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {COMBINED_ACCEPTANCE_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {READ_DATA_REORDERING_DEPTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_AXI_VERSION} {AXI4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_AXI_VERSION} {AXI4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ACE_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ACE5_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {SYNC_RESET} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {REGENERATE_ADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ENABLE_AXI5} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {IS_TRANSLATOR} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {TERMINATE_READ_CHANNEL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {TERMINATE_WRITE_CHANNEL} {0};add_instance {subsys_periph_pb_cpu_0_s0_translator} {altera_merlin_slave_translator};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ADDRESS_W} {17};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_DATA_W} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_DATA_W} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_READLATENCY} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READDATA} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READ} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITE} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_ADDRESS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_LOCK} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {WAITREQUEST_ALLOWANCE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {SYNC_RESET} {1};add_instance {subsys_hps_lwhps2fpga_agent} {altera_merlin_axi_master_ni};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ID_WIDTH} {4};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDR_WIDTH} {29};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {RDATA_WIDTH} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {WDATA_WIDTH} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {SAI_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDRCHK_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USER_DATA_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {SID_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_ADDR_USER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_PKT_DATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_PKT_ADDRCHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {AXI_VERSION} {AXI4};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ACE_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ACE5_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {WRITE_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {READ_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_READ_TERMINAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_WRITE_TERMINAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_READ_UNIVERSAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_WRITE_UNIVERSAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_CACHE_H} {113};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_CACHE_L} {110};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_PROTECTION_H} {109};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_PROTECTION_L} {107};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_RESPONSE_STATUS_L} {114};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_RESPONSE_STATUS_H} {115};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURSTWRAP_L} {82};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTE_CNT_H} {81};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_H} {31};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_L} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SRC_ID_H} {101};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SRC_ID_L} {101};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DEST_ID_H} {102};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DEST_ID_L} {102};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_THREAD_ID_H} {106};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_THREAD_ID_L} {103};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_QOS_L} {97};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_QOS_H} {100};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ORI_BURST_SIZE_L} {116};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ORI_BURST_SIZE_H} {118};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DOMAIN_H} {126};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DOMAIN_L} {125};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SNOOP_H} {124};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SNOOP_L} {121};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BARRIER_H} {120};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BARRIER_L} {119};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_WUNIQUE} {127};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_EOP_OOO} {134};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SOP_OOO} {135};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ATRACE} {141};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRACE} {142};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWAKEUP} {143};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_POISON_H} {128};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_POISON_L} {128};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATACHK_H} {129};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATACHK_L} {129};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDRCHK_H} {132};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDRCHK_L} {131};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SAI_H} {133};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SAI_L} {133};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_SEQ_H} {140};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_SEQ_L} {136};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_USER_DATA_H} {130};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_USER_DATA_L} {130};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWATOP_L} {144};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWATOP_H} {149};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHNID_L} {150};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHNID_H} {160};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHNIDEN} {161};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHLPID_L} {162};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHLPID_H} {166};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHLPIDEN} {167};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_MMUSECSID} {169};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_MMUSID_L} {168};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_MMUSID_H} {168};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATALESS} {170};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ST_DATA_W} {171};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?> <address_map> <slave id="0" name="subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0" start="0x0000000000000000" end="0x00000000000020000" responds="1" user_default="0" /> </address_map> };set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {SYNC_RESET} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_TRACE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_POISON} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ENABLE_AXI5} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {RESP_USER_WIDTH} {8};add_instance {subsys_periph_pb_cpu_0_s0_agent} {altera_merlin_slave_agent};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ORI_BURST_SIZE_H} {118};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ORI_BURST_SIZE_L} {116};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_RESPONSE_STATUS_H} {115};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_RESPONSE_STATUS_L} {114};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_PROTECTION_H} {109};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_PROTECTION_L} {107};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURSTWRAP_L} {82};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTE_CNT_H} {81};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATA_H} {31};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATA_L} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SRC_ID_H} {101};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SRC_ID_L} {101};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DEST_ID_H} {102};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DEST_ID_L} {102};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_POISON_H} {128};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_POISON_L} {128};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATACHK_H} {129};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATACHK_L} {129};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SAI_H} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SAI_L} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDRCHK_H} {132};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDRCHK_L} {131};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_EOP_OOO} {134};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SOP_OOO} {135};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_SEQ_H} {140};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_SEQ_L} {136};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_USER_DATA_H} {130};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_USER_DATA_L} {130};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ATRACE} {141};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRACE} {142};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWAKEUP} {143};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWATOP_H} {149};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWATOP_L} {144};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHNID_H} {160};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHNID_L} {150};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHNIDEN} {161};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHLPID_H} {166};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHLPID_L} {162};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHLPIDEN} {167};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_MMUSECSID} {169};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_MMUSID_H} {168};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_MMUSID_L} {168};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATALESS} {170};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ST_DATA_W} {171};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {MAX_BURSTWRAP} {127};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ID} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ECC_ENABLE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {SYNC_RESET} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_PKT_DATACHK} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ENABLE_AXI5} {0};add_instance {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {BITS_PER_SYMBOL} {172};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {MEM_TYPE} {M20K};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {SYNC_RESET} {1};add_instance {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {MEM_TYPE} {M20K};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {SYNC_RESET} {1};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {0 };set_instance_parameter_value {router} {CHANNEL_ID} {1 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 };set_instance_parameter_value {router} {END_ADDRESS} {0x20000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {64};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {109};set_instance_parameter_value {router} {PKT_PROTECTION_L} {107};set_instance_parameter_value {router} {PKT_DEST_ID_H} {102};set_instance_parameter_value {router} {PKT_DEST_ID_L} {102};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router} {PKT_TRANS_READ} {68};set_instance_parameter_value {router} {ST_DATA_W} {171};set_instance_parameter_value {router} {ST_CHANNEL_W} {2};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};set_instance_parameter_value {router} {HAS_USER_DEFAULT_SLAVE} {0};set_instance_parameter_value {router} {SYNC_RESET} {1};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {1 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x20000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {64};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {109};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {107};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {102};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {102};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_001} {ST_DATA_W} {171};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};set_instance_parameter_value {router_001} {HAS_USER_DEFAULT_SLAVE} {0};set_instance_parameter_value {router_001} {SYNC_RESET} {1};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {write read };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {64};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {109};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {107};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {102};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {102};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_002} {ST_DATA_W} {171};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};set_instance_parameter_value {router_002} {HAS_USER_DEFAULT_SLAVE} {0};set_instance_parameter_value {router_002} {SYNC_RESET} {1};add_instance {subsys_periph_pb_cpu_0_s0_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_ADDR_H} {64};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_ADDR_L} {36};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTE_CNT_H} {81};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURSTWRAP_L} {82};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_SAI_H} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_SAI_L} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ENABLE_AXI5} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_TRANS_READ} {68};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {IN_NARROW_SIZE} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_EOP_OOO} {89};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_SOP_OOO} {90};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ENABLE_OOO} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ST_DATA_W} {171};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_BYTE_CNT_H} {73};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {BURSTWRAP_CONST_MASK} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {BURSTWRAP_CONST_VALUE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ADAPTER_VERSION} {new};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {SYNC_RESET} {1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {171};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cmd_demux} {SYNC_RESET} {1};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {171};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cmd_demux_001} {SYNC_RESET} {1};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {171};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cmd_mux} {SYNC_RESET} {1};set_instance_parameter_value {cmd_mux} {ENABLE_OOO_CHUNKS} {0};set_instance_parameter_value {cmd_mux} {PKT_SOP_OOO} {135};set_instance_parameter_value {cmd_mux} {PKT_EOP_OOO} {134};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {171};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {rsp_demux} {SYNC_RESET} {1};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {171};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {rsp_mux} {SYNC_RESET} {1};set_instance_parameter_value {rsp_mux} {ENABLE_OOO_CHUNKS} {0};set_instance_parameter_value {rsp_mux} {PKT_SOP_OOO} {135};set_instance_parameter_value {rsp_mux} {PKT_EOP_OOO} {134};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {171};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {rsp_mux_001} {SYNC_RESET} {1};set_instance_parameter_value {rsp_mux_001} {ENABLE_OOO_CHUNKS} {0};set_instance_parameter_value {rsp_mux_001} {PKT_SOP_OOO} {135};set_instance_parameter_value {rsp_mux_001} {PKT_EOP_OOO} {134};add_instance {agent_pipeline} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {agent_pipeline} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {agent_pipeline} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {agent_pipeline} {USE_PACKETS} {1};set_instance_parameter_value {agent_pipeline} {USE_EMPTY} {0};set_instance_parameter_value {agent_pipeline} {CHANNEL_WIDTH} {2};set_instance_parameter_value {agent_pipeline} {MAX_CHANNEL} {0};set_instance_parameter_value {agent_pipeline} {ERROR_WIDTH} {0};set_instance_parameter_value {agent_pipeline} {PIPELINE_READY} {1};set_instance_parameter_value {agent_pipeline} {SYNC_RESET} {1};add_instance {agent_pipeline_001} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {agent_pipeline_001} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {agent_pipeline_001} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {agent_pipeline_001} {USE_PACKETS} {1};set_instance_parameter_value {agent_pipeline_001} {USE_EMPTY} {0};set_instance_parameter_value {agent_pipeline_001} {CHANNEL_WIDTH} {0};set_instance_parameter_value {agent_pipeline_001} {MAX_CHANNEL} {0};set_instance_parameter_value {agent_pipeline_001} {ERROR_WIDTH} {0};set_instance_parameter_value {agent_pipeline_001} {PIPELINE_READY} {1};set_instance_parameter_value {agent_pipeline_001} {SYNC_RESET} {1};add_instance {mux_pipeline} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline} {SYNC_RESET} {1};add_instance {mux_pipeline_001} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline_001} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline_001} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline_001} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline_001} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline_001} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline_001} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline_001} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline_001} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline_001} {SYNC_RESET} {1};add_instance {mux_pipeline_002} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline_002} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline_002} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline_002} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline_002} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline_002} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline_002} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline_002} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline_002} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline_002} {SYNC_RESET} {1};add_instance {mux_pipeline_003} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline_003} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline_003} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline_003} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline_003} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline_003} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline_003} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline_003} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline_003} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline_003} {SYNC_RESET} {1};add_instance {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {USE_RESET_REQUEST} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {SYNC_RESET} {1};add_instance {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {USE_RESET_REQUEST} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {SYNC_RESET} {1};add_instance {clk_100_out_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {clk_100_out_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {100000000};set_instance_parameter_value {clk_100_out_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {subsys_hps_lwhps2fpga_translator.m0} {subsys_hps_lwhps2fpga_agent.altera_axi_slave} {avalon};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {arbitrationPriority} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {baseAddress} {0x0000};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {defaultConnection} {false};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {domainAlias} {};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {rsp_mux.src} {subsys_hps_lwhps2fpga_agent.write_rp} {avalon_streaming};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.response};add_connection {rsp_mux_001.src} {subsys_hps_lwhps2fpga_agent.read_rp} {avalon_streaming};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.response};add_connection {subsys_periph_pb_cpu_0_s0_agent.m0} {subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {defaultConnection} {false};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {domainAlias} {};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent.rf_source} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out} {subsys_periph_pb_cpu_0_s0_agent.rf_sink} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src} {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out} {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_hps_lwhps2fpga_agent.write_cp} {router.sink} {avalon_streaming};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {subsys_hps_lwhps2fpga_agent.read_cp} {router_001.sink} {avalon_streaming};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {cmd_mux.src} {subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {avalon_streaming};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.command};add_connection {subsys_periph_pb_cpu_0_s0_burst_adapter.source0} {agent_pipeline.sink0} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.command};add_connection {agent_pipeline.source0} {subsys_periph_pb_cpu_0_s0_agent.cp} {avalon_streaming};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.command};add_connection {subsys_periph_pb_cpu_0_s0_agent.rp} {agent_pipeline_001.sink0} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.response};add_connection {agent_pipeline_001.source0} {router_002.sink} {avalon_streaming};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {agent_pipeline_001.source0/router_002.sink} {qsys_mm.response};add_connection {cmd_demux.src0} {mux_pipeline.sink0} {avalon_streaming};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.command};add_connection {mux_pipeline.source0} {cmd_mux.sink0} {avalon_streaming};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {mux_pipeline_001.sink0} {avalon_streaming};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.command};add_connection {mux_pipeline_001.source0} {cmd_mux.sink1} {avalon_streaming};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.command};add_connection {rsp_demux.src0} {mux_pipeline_002.sink0} {avalon_streaming};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.response};add_connection {mux_pipeline_002.source0} {rsp_mux.sink0} {avalon_streaming};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {mux_pipeline_003.sink0} {avalon_streaming};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.response};add_connection {mux_pipeline_003.source0} {rsp_mux_001.sink0} {avalon_streaming};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.response};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_hps_lwhps2fpga_translator.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_translator.reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_hps_lwhps2fpga_agent.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_agent.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_burst_adapter.cr0_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {agent_pipeline.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {agent_pipeline_001.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline_001.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline_002.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline_003.cr0_reset} {reset};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_hps_lwhps2fpga_translator.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_translator.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_hps_lwhps2fpga_agent.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_burst_adapter.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {agent_pipeline.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {agent_pipeline_001.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline_001.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline_002.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline_003.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.clk} {clock};add_interface {subsys_hps_lwhps2fpga} {axi4} {slave};set_interface_property {subsys_hps_lwhps2fpga} {EXPORT_OF} {subsys_hps_lwhps2fpga_translator.s0};add_interface {subsys_periph_pb_cpu_0_s0} {avalon} {master};set_interface_property {subsys_periph_pb_cpu_0_s0} {EXPORT_OF} {subsys_periph_pb_cpu_0_s0_translator.avalon_anti_slave_0};add_interface {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset} {EXPORT_OF} {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.in_reset};add_interface {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset} {EXPORT_OF} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.in_reset};add_interface {clk_100_out_clk} {clock} {slave};set_interface_property {clk_100_out_clk} {EXPORT_OF} {clk_100_out_clk_clock_bridge.in_clk};set_module_assignment {interconnect_id.subsys_hps.lwhps2fpga} {0};set_module_assignment {interconnect_id.subsys_periph.pb_cpu_0_s0} {0}; SYNC_RESET 1 altera_mm_interconnect 19.2.0 mm_interconnect_0 qsys_top_altera_mm_interconnect_1920_ykfyxdi 0 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clockRateSysInfo -1 clock 26.1 mm_interconnect_0/clk_100_out_clk clk_100/out_clk qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE domainAlias qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER addressWidthSysInfo qsys_mm.optimizeRdFifoSize FALSE qsys_mm.syncResets TRUE qsys_mm.splitCommandsFor4KBoundary FALSE slaveDataWidthSysInfo -1 qsys_mm.maxAdditionalLatency 4 qsys_mm.enableAllPipelines FALSE qsys_mm.interconnectType STANDARD defaultConnection false qsys_mm.piplineType PIPELINE_STAGE qsys_mm.enableInstrumentation FALSE cpuInfoIdSysInfo qsys_mm.interconnectResetSource DEFAULT baseAddress 0x0000 qsys_mm.responseFifoType REGISTER_BASED qsys_mm.burstAdapterImplementation PER_BURST_TYPE_CONVERTER arbitrationPriority 1 qsys_mm.fifoDepth 8 addressMapSysInfo qsys_mm.enableEccProtection FALSE avalon 26.1 subsys_periph/pb_cpu_0_s0 mm_interconnect_0/subsys_periph_pb_cpu_0_s0 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 mm_interconnect_0/subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset rst_controller/reset_out resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 mm_interconnect_0/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset rst_controller/reset_out qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE domainAlias qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER addressWidthSysInfo qsys_mm.optimizeRdFifoSize FALSE qsys_mm.syncResets TRUE qsys_mm.splitCommandsFor4KBoundary FALSE slaveDataWidthSysInfo -1 qsys_mm.maxAdditionalLatency 4 qsys_mm.enableAllPipelines FALSE qsys_mm.interconnectType STANDARD defaultConnection false qsys_mm.piplineType PIPELINE_STAGE qsys_mm.enableInstrumentation FALSE cpuInfoIdSysInfo qsys_mm.interconnectResetSource DEFAULT baseAddress 0x0000 qsys_mm.responseFifoType REGISTER_BASED qsys_mm.burstAdapterImplementation PER_BURST_TYPE_CONVERTER arbitrationPriority 1 qsys_mm.fifoDepth 8 addressMapSysInfo qsys_mm.enableEccProtection FALSE avalon 26.1 mm_interconnect_0/subsys_hps_lwhps2fpga subsys_hps/lwhps2fpga qsys_top.mm_interconnect_0 agent_pipeline BITS_PER_SYMBOL 171 CHANNEL_WIDTH 2 EMPTY_WIDTH 0 ERROR_WIDTH 0 MAX_CHANNEL 0 PACKET_WIDTH 2 PIPELINE_READY 1 SYMBOLS_PER_BEAT 1 SYNC_RESET 1 USE_EMPTY 0 USE_PACKETS 1 altera_avalon_st_pipeline_stage 19.3.0 agent_pipeline qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq 0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp subsys_periph_pb_cpu_0_s0_agent/cp agent_pipeline/source0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/agent_pipeline.cr0 agent_pipeline/cr0 clk_100_out_clk_clock_bridge/out_clk resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/agent_pipeline.cr0_reset agent_pipeline/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0 agent_pipeline/sink0 subsys_periph_pb_cpu_0_s0_burst_adapter/source0 qsys_top.mm_interconnect_0.agent_pipeline agent_pipeline_001 BITS_PER_SYMBOL 171 CHANNEL_WIDTH 0 EMPTY_WIDTH 0 ERROR_WIDTH 0 MAX_CHANNEL 0 PACKET_WIDTH 2 PIPELINE_READY 1 SYMBOLS_PER_BEAT 1 SYNC_RESET 1 USE_EMPTY 0 USE_PACKETS 1 altera_avalon_st_pipeline_stage 19.3.0 agent_pipeline_001 qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq 0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 agent_pipeline_001.source0/router_002.sink router_002/sink agent_pipeline_001/source0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/agent_pipeline_001.cr0 agent_pipeline_001/cr0 clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0 agent_pipeline_001/sink0 subsys_periph_pb_cpu_0_s0_agent/rp resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/agent_pipeline_001.cr0_reset agent_pipeline_001/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.agent_pipeline_001 clk_100_out_clk_clock_bridge DERIVED_CLOCK_RATE 0 EXPLICIT_CLOCK_RATE 100000000 NUM_CLOCK_OUTPUTS 1 altera_clock_bridge 19.2.0 clk_100_out_clk_clock_bridge qsys_top_altera_clock_bridge_1920_njakcna 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/agent_pipeline.cr0 agent_pipeline/cr0 clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/agent_pipeline_001.cr0 agent_pipeline_001/cr0 clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/cmd_demux.clk cmd_demux/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/cmd_demux_001.clk cmd_demux_001/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/cmd_mux.clk cmd_mux/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/mux_pipeline.cr0 mux_pipeline/cr0 clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_001.cr0 mux_pipeline_001/cr0 clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_002.cr0 mux_pipeline_002/cr0 clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_003.cr0 mux_pipeline_003/cr0 clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/router.clk router/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/router_001.clk router_001/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/router_002.clk router_002/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/rsp_demux.clk rsp_demux/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/rsp_mux.clk rsp_mux/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/rsp_mux_001.clk rsp_mux_001/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_agent.clk subsys_hps_lwhps2fpga_agent/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_translator.clk subsys_hps_lwhps2fpga_translator/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.clk subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent.clk subsys_periph_pb_cpu_0_s0_agent/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.clk subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/clk clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_burst_adapter.cr0 subsys_periph_pb_cpu_0_s0_burst_adapter/cr0 clk_100_out_clk_clock_bridge/out_clk clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_translator.clk subsys_periph_pb_cpu_0_s0_translator/clk clk_100_out_clk_clock_bridge/out_clk qsys_top.mm_interconnect_0.clk_100_out_clk_clock_bridge cmd_demux MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) NUM_OUTPUTS 1 ST_CHANNEL_W 2 ST_DATA_W 171 SYNC_RESET 1 VALID_WIDTH 1 altera_merlin_demultiplexer 19.2.1 cmd_demux qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/cmd_demux.clk cmd_demux/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 cmd_demux.src0/mux_pipeline.sink0 mux_pipeline/sink0 cmd_demux/src0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 router.src/cmd_demux.sink cmd_demux/sink router/src resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_demux.clk_reset cmd_demux/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.cmd_demux cmd_demux_001 MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) NUM_OUTPUTS 1 ST_CHANNEL_W 2 ST_DATA_W 171 SYNC_RESET 1 VALID_WIDTH 1 altera_merlin_demultiplexer 19.2.1 cmd_demux_001 qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/cmd_demux_001.clk cmd_demux_001/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 cmd_demux_001.src0/mux_pipeline_001.sink0 mux_pipeline_001/sink0 cmd_demux_001/src0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 router_001.src/cmd_demux_001.sink cmd_demux_001/sink router_001/src resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_demux_001.clk_reset cmd_demux_001/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.cmd_demux_001 cmd_mux ARBITRATION_SCHEME round-robin ARBITRATION_SHARES 1,1 ENABLE_OOO_CHUNKS 0 MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) NUM_INPUTS 2 PIPELINE_ARB 1 PKT_EOP_OOO 134 PKT_SOP_OOO 135 PKT_TRANS_LOCK 69 ST_CHANNEL_W 2 ST_DATA_W 171 SYNC_RESET 1 USE_EXTERNAL_ARB 0 altera_merlin_multiplexer 19.2.2 cmd_mux qsys_top_altera_merlin_multiplexer_1922_666s25q 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/cmd_mux.clk cmd_mux/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0 subsys_periph_pb_cpu_0_s0_burst_adapter/sink0 cmd_mux/src qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 mux_pipeline.source0/cmd_mux.sink0 cmd_mux/sink0 mux_pipeline/source0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 mux_pipeline_001.source0/cmd_mux.sink1 cmd_mux/sink1 mux_pipeline_001/source0 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_mux.clk_reset cmd_mux/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.cmd_mux mux_pipeline BITS_PER_SYMBOL 171 CHANNEL_WIDTH 2 EMPTY_WIDTH 0 ERROR_WIDTH 0 MAX_CHANNEL 0 PACKET_WIDTH 2 PIPELINE_READY 1 SYMBOLS_PER_BEAT 1 SYNC_RESET 1 USE_EMPTY 0 USE_PACKETS 1 altera_avalon_st_pipeline_stage 19.3.0 mux_pipeline qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/mux_pipeline.cr0 mux_pipeline/cr0 clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 cmd_demux.src0/mux_pipeline.sink0 mux_pipeline/sink0 cmd_demux/src0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 mux_pipeline.source0/cmd_mux.sink0 cmd_mux/sink0 mux_pipeline/source0 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline.cr0_reset mux_pipeline/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.mux_pipeline mux_pipeline_001 BITS_PER_SYMBOL 171 CHANNEL_WIDTH 2 EMPTY_WIDTH 0 ERROR_WIDTH 0 MAX_CHANNEL 0 PACKET_WIDTH 2 PIPELINE_READY 1 SYMBOLS_PER_BEAT 1 SYNC_RESET 1 USE_EMPTY 0 USE_PACKETS 1 altera_avalon_st_pipeline_stage 19.3.0 mux_pipeline_001 qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_001.cr0 mux_pipeline_001/cr0 clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 cmd_demux_001.src0/mux_pipeline_001.sink0 mux_pipeline_001/sink0 cmd_demux_001/src0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 mux_pipeline_001.source0/cmd_mux.sink1 cmd_mux/sink1 mux_pipeline_001/source0 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_001.cr0_reset mux_pipeline_001/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.mux_pipeline_001 mux_pipeline_002 BITS_PER_SYMBOL 171 CHANNEL_WIDTH 2 EMPTY_WIDTH 0 ERROR_WIDTH 0 MAX_CHANNEL 0 PACKET_WIDTH 2 PIPELINE_READY 1 SYMBOLS_PER_BEAT 1 SYNC_RESET 1 USE_EMPTY 0 USE_PACKETS 1 altera_avalon_st_pipeline_stage 19.3.0 mux_pipeline_002 qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_002.cr0 mux_pipeline_002/cr0 clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 mux_pipeline_002.source0/rsp_mux.sink0 rsp_mux/sink0 mux_pipeline_002/source0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 rsp_demux.src0/mux_pipeline_002.sink0 mux_pipeline_002/sink0 rsp_demux/src0 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_002.cr0_reset mux_pipeline_002/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.mux_pipeline_002 mux_pipeline_003 BITS_PER_SYMBOL 171 CHANNEL_WIDTH 2 EMPTY_WIDTH 0 ERROR_WIDTH 0 MAX_CHANNEL 0 PACKET_WIDTH 2 PIPELINE_READY 1 SYMBOLS_PER_BEAT 1 SYNC_RESET 1 USE_EMPTY 0 USE_PACKETS 1 altera_avalon_st_pipeline_stage 19.3.0 mux_pipeline_003 qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/mux_pipeline_003.cr0 mux_pipeline_003/cr0 clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 mux_pipeline_003.source0/rsp_mux_001.sink0 rsp_mux_001/sink0 mux_pipeline_003/source0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 rsp_demux.src1/mux_pipeline_003.sink0 mux_pipeline_003/sink0 rsp_demux/src1 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_003.cr0_reset mux_pipeline_003/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.mux_pipeline_003 router CHANNEL_ID 1 DECODER_TYPE 0 DEFAULT_CHANNEL 0 DEFAULT_DESTID 0 DEFAULT_RD_CHANNEL -1 DEFAULT_WR_CHANNEL -1 DESTINATION_ID 0 END_ADDRESS 0x20000 HAS_USER_DEFAULT_SLAVE 0 MEMORY_ALIASING_DECODE 0 MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) NON_SECURED_TAG 1 PKT_ADDR_H 64 PKT_ADDR_L 36 PKT_DEST_ID_H 102 PKT_DEST_ID_L 102 PKT_PROTECTION_H 109 PKT_PROTECTION_L 107 PKT_TRANS_READ 68 PKT_TRANS_WRITE 67 SECURED_RANGE_LIST 0 SECURED_RANGE_PAIRS 0 SLAVES_INFO 0:1:0x0:0x20000:both:1:0:0:1 SPAN_OFFSET START_ADDRESS 0x0 ST_CHANNEL_W 2 ST_DATA_W 171 SYNC_RESET 1 TYPE_OF_TRANSACTION both altera_merlin_router 19.2.1 router qsys_top_altera_merlin_router_1921_ox5xuhq 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/router.clk router/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 router.src/cmd_demux.sink cmd_demux/sink router/src qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_hps_lwhps2fpga_agent.write_cp/router.sink router/sink subsys_hps_lwhps2fpga_agent/write_cp resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router.clk_reset router/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.router router_001 CHANNEL_ID 1 DECODER_TYPE 0 DEFAULT_CHANNEL 0 DEFAULT_DESTID 0 DEFAULT_RD_CHANNEL -1 DEFAULT_WR_CHANNEL -1 DESTINATION_ID 0 END_ADDRESS 0x20000 HAS_USER_DEFAULT_SLAVE 0 MEMORY_ALIASING_DECODE 0 MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) NON_SECURED_TAG 1 PKT_ADDR_H 64 PKT_ADDR_L 36 PKT_DEST_ID_H 102 PKT_DEST_ID_L 102 PKT_PROTECTION_H 109 PKT_PROTECTION_L 107 PKT_TRANS_READ 68 PKT_TRANS_WRITE 67 SECURED_RANGE_LIST 0 SECURED_RANGE_PAIRS 0 SLAVES_INFO 0:1:0x0:0x20000:both:1:0:0:1 SPAN_OFFSET START_ADDRESS 0x0 ST_CHANNEL_W 2 ST_DATA_W 171 SYNC_RESET 1 TYPE_OF_TRANSACTION both altera_merlin_router 19.2.1 router_001 qsys_top_altera_merlin_router_1921_ox5xuhq 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/router_001.clk router_001/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 router_001.src/cmd_demux_001.sink cmd_demux_001/sink router_001/src qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink router_001/sink subsys_hps_lwhps2fpga_agent/read_cp resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router_001.clk_reset router_001/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.router_001 router_002 CHANNEL_ID 01,10 DECODER_TYPE 1 DEFAULT_CHANNEL -1 DEFAULT_DESTID 0 DEFAULT_RD_CHANNEL 1 DEFAULT_WR_CHANNEL 0 DESTINATION_ID 0,0 END_ADDRESS 0x0,0x0 HAS_USER_DEFAULT_SLAVE 0 MEMORY_ALIASING_DECODE 0 MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) NON_SECURED_TAG 1,1 PKT_ADDR_H 64 PKT_ADDR_L 36 PKT_DEST_ID_H 102 PKT_DEST_ID_L 102 PKT_PROTECTION_H 109 PKT_PROTECTION_L 107 PKT_TRANS_READ 68 PKT_TRANS_WRITE 67 SECURED_RANGE_LIST 0,0 SECURED_RANGE_PAIRS 0,0 SLAVES_INFO 0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1 SPAN_OFFSET START_ADDRESS 0x0,0x0 ST_CHANNEL_W 2 ST_DATA_W 171 SYNC_RESET 1 TYPE_OF_TRANSACTION write,read altera_merlin_router 19.2.1 router_002 qsys_top_altera_merlin_router_1921_sxavatq 0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 agent_pipeline_001.source0/router_002.sink router_002/sink agent_pipeline_001/source0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/router_002.clk router_002/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 router_002.src/rsp_demux.sink rsp_demux/sink router_002/src resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router_002.clk_reset router_002/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.router_002 rsp_demux MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) NUM_OUTPUTS 2 ST_CHANNEL_W 2 ST_DATA_W 171 SYNC_RESET 1 VALID_WIDTH 1 altera_merlin_demultiplexer 19.2.1 rsp_demux qsys_top_altera_merlin_demultiplexer_1921_qyizksq 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/rsp_demux.clk rsp_demux/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 router_002.src/rsp_demux.sink rsp_demux/sink router_002/src qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 rsp_demux.src0/mux_pipeline_002.sink0 mux_pipeline_002/sink0 rsp_demux/src0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 rsp_demux.src1/mux_pipeline_003.sink0 mux_pipeline_003/sink0 rsp_demux/src1 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_demux.clk_reset rsp_demux/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.rsp_demux rsp_mux ARBITRATION_SCHEME no-arb ARBITRATION_SHARES 1 ENABLE_OOO_CHUNKS 0 MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) NUM_INPUTS 1 PIPELINE_ARB 0 PKT_EOP_OOO 134 PKT_SOP_OOO 135 PKT_TRANS_LOCK 69 ST_CHANNEL_W 2 ST_DATA_W 171 SYNC_RESET 1 USE_EXTERNAL_ARB 0 altera_merlin_multiplexer 19.2.2 rsp_mux qsys_top_altera_merlin_multiplexer_1922_yjgptii 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/rsp_mux.clk rsp_mux/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 mux_pipeline_002.source0/rsp_mux.sink0 rsp_mux/sink0 mux_pipeline_002/source0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp subsys_hps_lwhps2fpga_agent/write_rp rsp_mux/src resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_mux.clk_reset rsp_mux/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.rsp_mux rsp_mux_001 ARBITRATION_SCHEME no-arb ARBITRATION_SHARES 1 ENABLE_OOO_CHUNKS 0 MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) NUM_INPUTS 1 PIPELINE_ARB 0 PKT_EOP_OOO 134 PKT_SOP_OOO 135 PKT_TRANS_LOCK 69 ST_CHANNEL_W 2 ST_DATA_W 171 SYNC_RESET 1 USE_EXTERNAL_ARB 0 altera_merlin_multiplexer 19.2.2 rsp_mux_001 qsys_top_altera_merlin_multiplexer_1922_yjgptii 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/rsp_mux_001.clk rsp_mux_001/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 mux_pipeline_003.source0/rsp_mux_001.sink0 rsp_mux_001/sink0 mux_pipeline_003/source0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp subsys_hps_lwhps2fpga_agent/read_rp rsp_mux_001/src resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_mux_001.clk_reset rsp_mux_001/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.rsp_mux_001 subsys_hps_lwhps2fpga_agent ACE5_LITE_SUPPORT 0 ACE_LITE_SUPPORT 0 ADDRCHK_WIDTH 1 ADDR_MAP <?xml version="1.0" encoding="UTF-8"?> <address_map> <slave id="0" name="subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0" start="0x0000000000000000" end="0x00000000000020000" responds="1" user_default="0" /> </address_map> ADDR_USER_WIDTH 1 ADDR_WIDTH 29 AWSNOOP_WIDTH 3 AXI_BURST_LENGTH_WIDTH 8 AXI_LOCK_WIDTH 1 AXI_VERSION AXI4 DATA_USER_WIDTH 1 ENABLE_AXI5 0 ID 0 ID_WIDTH 4 MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) PKT_ADDRCHK_H 132 PKT_ADDRCHK_L 131 PKT_ADDR_H 64 PKT_ADDR_L 36 PKT_ADDR_SIDEBAND_H 94 PKT_ADDR_SIDEBAND_L 94 PKT_ATRACE 141 PKT_AWAKEUP 143 PKT_AWATOP_H 149 PKT_AWATOP_L 144 PKT_AWSTASHLPIDEN 167 PKT_AWSTASHLPID_H 166 PKT_AWSTASHLPID_L 162 PKT_AWSTASHNIDEN 161 PKT_AWSTASHNID_H 160 PKT_AWSTASHNID_L 150 PKT_BARRIER_H 120 PKT_BARRIER_L 119 PKT_BEGIN_BURST 96 PKT_BURSTWRAP_H 88 PKT_BURSTWRAP_L 82 PKT_BURST_SIZE_H 91 PKT_BURST_SIZE_L 89 PKT_BURST_TYPE_H 93 PKT_BURST_TYPE_L 92 PKT_BYTEEN_H 35 PKT_BYTEEN_L 32 PKT_BYTE_CNT_H 81 PKT_BYTE_CNT_L 71 PKT_CACHE_H 113 PKT_CACHE_L 110 PKT_DATACHK_H 129 PKT_DATACHK_L 129 PKT_DATALESS 170 PKT_DATA_H 31 PKT_DATA_L 0 PKT_DATA_SIDEBAND_H 95 PKT_DATA_SIDEBAND_L 95 PKT_DEST_ID_H 102 PKT_DEST_ID_L 102 PKT_DOMAIN_H 126 PKT_DOMAIN_L 125 PKT_EOP_OOO 134 PKT_MMUSECSID 169 PKT_MMUSID_H 168 PKT_MMUSID_L 168 PKT_ORI_BURST_SIZE_H 118 PKT_ORI_BURST_SIZE_L 116 PKT_POISON_H 128 PKT_POISON_L 128 PKT_PROTECTION_H 109 PKT_PROTECTION_L 107 PKT_QOS_H 100 PKT_QOS_L 97 PKT_RESPONSE_STATUS_H 115 PKT_RESPONSE_STATUS_L 114 PKT_SAI_H 133 PKT_SAI_L 133 PKT_SNOOP_H 124 PKT_SNOOP_L 121 PKT_SOP_OOO 135 PKT_SRC_ID_H 101 PKT_SRC_ID_L 101 PKT_THREAD_ID_H 106 PKT_THREAD_ID_L 103 PKT_TRACE 142 PKT_TRANS_COMPRESSED_READ 65 PKT_TRANS_EXCLUSIVE 70 PKT_TRANS_LOCK 69 PKT_TRANS_POSTED 66 PKT_TRANS_READ 68 PKT_TRANS_SEQ_H 140 PKT_TRANS_SEQ_L 136 PKT_TRANS_WRITE 67 PKT_USER_DATA_H 130 PKT_USER_DATA_L 130 PKT_WUNIQUE 127 RDATA_WIDTH 32 READ_ISSUING_CAPABILITY 16 RESP_USER_WIDTH 8 ROLE_BASED_USER 0 SAI_WIDTH 1 SID_WIDTH 1 ST_CHANNEL_W 2 ST_DATA_W 171 SYNC_RESET 1 TERMINATE_READ_TERMINAL 0 TERMINATE_READ_UNIVERSAL 0 TERMINATE_WRITE_TERMINAL 0 TERMINATE_WRITE_UNIVERSAL 0 USER_DATA_WIDTH 1 USE_ADDR_USER 1 USE_PKT_ADDRCHK 1 USE_PKT_DATACHK 0 USE_POISON 1 USE_TRACE 1 WDATA_WIDTH 32 WRITE_ISSUING_CAPABILITY 16 altera_merlin_axi_master_ni 19.11.7 subsys_hps_lwhps2fpga_agent qsys_top_altera_merlin_axi_master_ni_19117_qautany 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_agent.clk subsys_hps_lwhps2fpga_agent/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp subsys_hps_lwhps2fpga_agent/write_rp rsp_mux/src qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp subsys_hps_lwhps2fpga_agent/read_rp rsp_mux_001/src qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink router_001/sink subsys_hps_lwhps2fpga_agent/read_cp qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_hps_lwhps2fpga_agent.write_cp/router.sink router/sink subsys_hps_lwhps2fpga_agent/write_cp qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE domainAlias qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER addressWidthSysInfo qsys_mm.optimizeRdFifoSize FALSE qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE slaveDataWidthSysInfo -1 qsys_mm.enableAllPipelines FALSE qsys_mm.interconnectType STANDARD defaultConnection false qsys_mm.piplineType PIPELINE_STAGE qsys_mm.enableInstrumentation FALSE cpuInfoIdSysInfo qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER baseAddress 0x0000 qsys_mm.responseFifoType REGISTER_BASED arbitrationPriority 1 qsys_mm.fifoDepth 8 addressMapSysInfo qsys_mm.enableEccProtection FALSE avalon 26.1 subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave subsys_hps_lwhps2fpga_agent/altera_axi_slave subsys_hps_lwhps2fpga_translator/m0 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_hps_lwhps2fpga_agent.clk_reset subsys_hps_lwhps2fpga_agent/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_agent subsys_hps_lwhps2fpga_translator ACE5_LITE_SUPPORT 0 ACE_LITE_SUPPORT 0 COMBINED_ACCEPTANCE_CAPABILITY 16 COMBINED_ISSUING_CAPABILITY 16 DATA_WIDTH 32 ENABLE_AXI5 0 IS_TRANSLATOR 1 M0_ADDR_WIDTH 29 M0_AWSNOOP_WIDTH 3 M0_AXI_VERSION AXI4 M0_BURST_LENGTH_WIDTH 8 M0_ID_WIDTH 4 M0_LOCK_WIDTH 1 M0_READ_ADDR_USER_WIDTH 1 M0_READ_DATA_USER_WIDTH 1 M0_SAI_WIDTH 1 M0_SID_WIDTH 16 M0_USER_ADDRCHK_WIDTH 1 M0_WRITE_ADDR_USER_WIDTH 1 M0_WRITE_DATA_USER_WIDTH 1 M0_WRITE_RESPONSE_DATA_USER_WIDTH 1 READ_ACCEPTANCE_CAPABILITY 16 READ_DATA_REORDERING_DEPTH 1 READ_ISSUING_CAPABILITY 16 REGENERATE_ADDRCHK 0 ROLE_BASED_USER 0 S0_ADDR_WIDTH 29 S0_AWSNOOP_WIDTH 3 S0_AXI_VERSION AXI4 S0_BURST_LENGTH_WIDTH 8 S0_ID_WIDTH 4 S0_LOCK_WIDTH 1 S0_READ_ADDR_USER_WIDTH 1 S0_READ_DATA_USER_WIDTH 1 S0_SAI_WIDTH 1 S0_SID_WIDTH 16 S0_USER_ADDRCHK_WIDTH 1 S0_WRITE_ADDR_USER_WIDTH 1 S0_WRITE_DATA_USER_WIDTH 1 S0_WRITE_RESPONSE_DATA_USER_WIDTH 1 SYNC_RESET 1 TERMINATE_READ_CHANNEL 0 TERMINATE_WRITE_CHANNEL 0 USER_DATA_WIDTH 1 USE_M0_ARADDRCHK 0 USE_M0_ARCACHE 1 USE_M0_ARLOCK 1 USE_M0_ARMMUSECSID 0 USE_M0_ARMMUSID 0 USE_M0_ARPROT 1 USE_M0_ARQOS 1 USE_M0_ARREGION 1 USE_M0_ARTRACE 0 USE_M0_ARUSER 1 USE_M0_ARUSER_ADDRCHK 1 USE_M0_ARUSER_SAI 1 USE_M0_AWADDRCHK 0 USE_M0_AWAKEUP 0 USE_M0_AWATOP 0 USE_M0_AWCACHE 1 USE_M0_AWLOCK 1 USE_M0_AWMMUSECSID 0 USE_M0_AWMMUSID 0 USE_M0_AWPROT 1 USE_M0_AWQOS 1 USE_M0_AWREGION 1 USE_M0_AWSTASHLPID 0 USE_M0_AWSTASHLPIDEN 0 USE_M0_AWSTASHNID 0 USE_M0_AWSTASHNIDEN 0 USE_M0_AWTRACE 0 USE_M0_AWUNIQUE 1 USE_M0_AWUSER 1 USE_M0_AWUSER_ADDRCHK 1 USE_M0_AWUSER_SAI 1 USE_M0_BRESP 1 USE_M0_BTRACE 0 USE_M0_BUSER 1 USE_M0_RDATACHK 0 USE_M0_RPOISON 0 USE_M0_RRESP 1 USE_M0_RTRACE 0 USE_M0_RUSER 1 USE_M0_RUSER_DATA 1 USE_M0_RUSER_DATACHK 1 USE_M0_RUSER_POISON 1 USE_M0_WDATACHK 0 USE_M0_WLAST 1 USE_M0_WPOISON 0 USE_M0_WTRACE 0 USE_M0_WUSER 1 USE_M0_WUSER_DATA 1 USE_M0_WUSER_DATACHK 1 USE_M0_WUSER_POISON 1 USE_S0_ARADDRCHK 0 USE_S0_ARBURST 1 USE_S0_ARCACHE 1 USE_S0_ARID 1 USE_S0_ARLEN 1 USE_S0_ARLOCK 1 USE_S0_ARMMUSECSID 0 USE_S0_ARMMUSID 0 USE_S0_ARPROT 1 USE_S0_ARQOS 0 USE_S0_ARREGION 0 USE_S0_ARSIZE 1 USE_S0_ARSNOOP 1 USE_S0_ARTRACE 0 USE_S0_ARUSER 0 USE_S0_ARUSER_ADDRCHK 0 USE_S0_ARUSER_SAI 0 USE_S0_AWADDRCHK 0 USE_S0_AWAKEUP 0 USE_S0_AWATOP 0 USE_S0_AWBURST 1 USE_S0_AWCACHE 1 USE_S0_AWID 1 USE_S0_AWLEN 1 USE_S0_AWLOCK 1 USE_S0_AWMMUSECSID 0 USE_S0_AWMMUSID 0 USE_S0_AWPROT 1 USE_S0_AWQOS 0 USE_S0_AWREGION 0 USE_S0_AWSIZE 1 USE_S0_AWSNOOP 1 USE_S0_AWSTASHLPID 0 USE_S0_AWSTASHLPIDEN 0 USE_S0_AWSTASHNID 0 USE_S0_AWSTASHNIDEN 0 USE_S0_AWTRACE 0 USE_S0_AWUNIQUE 0 USE_S0_AWUSER 0 USE_S0_AWUSER_ADDRCHK 0 USE_S0_AWUSER_SAI 0 USE_S0_BID 1 USE_S0_BRESP 1 USE_S0_BTRACE 0 USE_S0_BUSER 0 USE_S0_RDATACHK 0 USE_S0_RID 1 USE_S0_RLAST 1 USE_S0_RPOISON 0 USE_S0_RRESP 1 USE_S0_RTRACE 0 USE_S0_RUSER 0 USE_S0_RUSER_DATA 0 USE_S0_RUSER_DATACHK 0 USE_S0_RUSER_POISON 0 USE_S0_WDATACHK 0 USE_S0_WLAST 1 USE_S0_WPOISON 0 USE_S0_WSTRB 1 USE_S0_WTRACE 0 USE_S0_WUSER 0 USE_S0_WUSER_DATA 0 USE_S0_WUSER_DATACHK 0 USE_S0_WUSER_POISON 0 WRITE_ACCEPTANCE_CAPABILITY 16 WRITE_ISSUING_CAPABILITY 16 altera_merlin_axi_translator 19.8.7 subsys_hps_lwhps2fpga_translator qsys_top_altera_merlin_axi_translator_1987_lty7xoq 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_translator.clk subsys_hps_lwhps2fpga_translator/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE domainAlias qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER addressWidthSysInfo qsys_mm.optimizeRdFifoSize FALSE qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE slaveDataWidthSysInfo -1 qsys_mm.enableAllPipelines FALSE qsys_mm.interconnectType STANDARD defaultConnection false qsys_mm.piplineType PIPELINE_STAGE qsys_mm.enableInstrumentation FALSE cpuInfoIdSysInfo qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER baseAddress 0x0000 qsys_mm.responseFifoType REGISTER_BASED arbitrationPriority 1 qsys_mm.fifoDepth 8 addressMapSysInfo qsys_mm.enableEccProtection FALSE avalon 26.1 subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave subsys_hps_lwhps2fpga_agent/altera_axi_slave subsys_hps_lwhps2fpga_translator/m0 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_hps_lwhps2fpga_translator.clk_reset subsys_hps_lwhps2fpga_translator/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_translator subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge ACTIVE_LOW_RESET 0 NUM_RESET_OUTPUTS 1 O_SYNCHRONOUS_EDGES deassert SYNCHRONOUS_EDGES deassert SYNC_RESET 1 USE_RESET_REQUEST 0 altera_reset_bridge 19.2.0 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge qsys_top_altera_reset_bridge_1920_xf2264i 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.clk subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/clk clk_100_out_clk_clock_bridge/out_clk resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_demux.clk_reset cmd_demux/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_demux_001.clk_reset cmd_demux_001/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/cmd_mux.clk_reset cmd_mux/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router.clk_reset router/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router_001.clk_reset router_001/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/router_002.clk_reset router_002/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_demux.clk_reset rsp_demux/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_mux.clk_reset rsp_mux/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/rsp_mux_001.clk_reset rsp_mux_001/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_hps_lwhps2fpga_agent.clk_reset subsys_hps_lwhps2fpga_agent/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_hps_lwhps2fpga_translator.clk_reset subsys_hps_lwhps2fpga_translator/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent.clk_reset subsys_periph_pb_cpu_0_s0_agent/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_burst_adapter.cr0_reset subsys_periph_pb_cpu_0_s0_burst_adapter/cr0_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_translator.reset subsys_periph_pb_cpu_0_s0_translator/reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge subsys_periph_pb_cpu_0_s0_agent AVS_BURSTCOUNT_SYMBOLS 0 AVS_BURSTCOUNT_W 3 AV_LINEWRAPBURSTS 0 ECC_ENABLE 0 ENABLE_AXI5 0 ID 0 MAX_BURSTWRAP 127 MAX_BYTE_CNT 4 MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) PKT_ADDRCHK_H 132 PKT_ADDRCHK_L 131 PKT_ADDR_H 64 PKT_ADDR_L 36 PKT_ATRACE 141 PKT_AWAKEUP 143 PKT_AWATOP_H 149 PKT_AWATOP_L 144 PKT_AWSTASHLPIDEN 167 PKT_AWSTASHLPID_H 166 PKT_AWSTASHLPID_L 162 PKT_AWSTASHNIDEN 161 PKT_AWSTASHNID_H 160 PKT_AWSTASHNID_L 150 PKT_BEGIN_BURST 96 PKT_BURSTWRAP_H 88 PKT_BURSTWRAP_L 82 PKT_BURST_SIZE_H 91 PKT_BURST_SIZE_L 89 PKT_BYTEEN_H 35 PKT_BYTEEN_L 32 PKT_BYTE_CNT_H 81 PKT_BYTE_CNT_L 71 PKT_DATACHK_H 129 PKT_DATACHK_L 129 PKT_DATALESS 170 PKT_DATA_H 31 PKT_DATA_L 0 PKT_DEST_ID_H 102 PKT_DEST_ID_L 102 PKT_EOP_OOO 134 PKT_MMUSECSID 169 PKT_MMUSID_H 168 PKT_MMUSID_L 168 PKT_ORI_BURST_SIZE_H 118 PKT_ORI_BURST_SIZE_L 116 PKT_POISON_H 128 PKT_POISON_L 128 PKT_PROTECTION_H 109 PKT_PROTECTION_L 107 PKT_RESPONSE_STATUS_H 115 PKT_RESPONSE_STATUS_L 114 PKT_SAI_H 133 PKT_SAI_L 133 PKT_SOP_OOO 135 PKT_SRC_ID_H 101 PKT_SRC_ID_L 101 PKT_SYMBOL_W 8 PKT_TRACE 142 PKT_TRANS_COMPRESSED_READ 65 PKT_TRANS_LOCK 69 PKT_TRANS_POSTED 66 PKT_TRANS_READ 68 PKT_TRANS_SEQ_H 140 PKT_TRANS_SEQ_L 136 PKT_TRANS_WRITE 67 PKT_USER_DATA_H 130 PKT_USER_DATA_L 130 PREVENT_FIFO_OVERFLOW 1 ROLE_BASED_USER 0 ST_CHANNEL_W 2 ST_DATA_W 171 SUPPRESS_0_BYTEEN_CMD 1 SYNC_RESET 1 USE_MEMORY_BLOCKS 0 USE_PKT_DATACHK 0 USE_READRESPONSE 0 USE_WRITERESPONSE 0 altera_merlin_slave_agent 19.3.0 subsys_periph_pb_cpu_0_s0_agent qsys_top_altera_merlin_slave_agent_1930_jxauz3i 0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp subsys_periph_pb_cpu_0_s0_agent/cp agent_pipeline/source0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent.clk subsys_periph_pb_cpu_0_s0_agent/clk clk_100_out_clk_clock_bridge/out_clk resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent.clk_reset subsys_periph_pb_cpu_0_s0_agent/clk_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE domainAlias qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER addressWidthSysInfo qsys_mm.optimizeRdFifoSize FALSE qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE slaveDataWidthSysInfo -1 qsys_mm.enableAllPipelines FALSE qsys_mm.interconnectType STANDARD defaultConnection false qsys_mm.piplineType PIPELINE_STAGE qsys_mm.enableInstrumentation FALSE cpuInfoIdSysInfo qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER baseAddress 0x0000 qsys_mm.responseFifoType REGISTER_BASED arbitrationPriority 1 qsys_mm.fifoDepth 8 addressMapSysInfo qsys_mm.enableEccProtection FALSE avalon 26.1 subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0 subsys_periph_pb_cpu_0_s0_translator/avalon_universal_slave_0 subsys_periph_pb_cpu_0_s0_agent/m0 qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/in subsys_periph_pb_cpu_0_s0_agent/rdata_fifo_src qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/in subsys_periph_pb_cpu_0_s0_agent/rf_source qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0 agent_pipeline_001/sink0 subsys_periph_pb_cpu_0_s0_agent/rp qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink subsys_periph_pb_cpu_0_s0_agent/rdata_fifo_sink subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/out qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink subsys_periph_pb_cpu_0_s0_agent/rf_sink subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/out qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent subsys_periph_pb_cpu_0_s0_agent_rdata_fifo BITS_PER_SYMBOL 34 CHANNEL_WIDTH 0 EMPTY_LATENCY 0 EMPTY_WIDTH 1 ENABLE_EXPLICIT_MAXCHANNEL false ERROR_WIDTH 0 EXPLICIT_MAXCHANNEL 0 FIFO_DEPTH 2 MEM_TYPE M20K SYMBOLS_PER_BEAT 1 SYNC_RESET 1 USE_ALMOST_EMPTY_IF 0 USE_ALMOST_FULL_IF 0 USE_FILL_LEVEL 0 USE_MEMORY_BLOCKS 0 USE_PACKETS 0 USE_STORE_FORWARD 0 altera_avalon_sc_fifo 19.3.2 subsys_periph_pb_cpu_0_s0_agent_rdata_fifo qsys_top_altera_avalon_sc_fifo_1932_22gxxgi 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/in subsys_periph_pb_cpu_0_s0_agent/rdata_fifo_src qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink subsys_periph_pb_cpu_0_s0_agent/rdata_fifo_sink subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/out resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk_reset subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/clk_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rdata_fifo subsys_periph_pb_cpu_0_s0_agent_rsp_fifo BITS_PER_SYMBOL 172 CHANNEL_WIDTH 0 EMPTY_LATENCY 1 EMPTY_WIDTH 1 ENABLE_EXPLICIT_MAXCHANNEL false ERROR_WIDTH 0 EXPLICIT_MAXCHANNEL 0 FIFO_DEPTH 2 MEM_TYPE M20K SYMBOLS_PER_BEAT 1 SYNC_RESET 1 USE_ALMOST_EMPTY_IF 0 USE_ALMOST_FULL_IF 0 USE_FILL_LEVEL 0 USE_MEMORY_BLOCKS 0 USE_PACKETS 1 USE_STORE_FORWARD 0 altera_avalon_sc_fifo 19.3.2 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo qsys_top_altera_avalon_sc_fifo_1932_22gxxgi 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/clk clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/in subsys_periph_pb_cpu_0_s0_agent/rf_source qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink subsys_periph_pb_cpu_0_s0_agent/rf_sink subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/out resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/clk_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge ACTIVE_LOW_RESET 0 NUM_RESET_OUTPUTS 1 O_SYNCHRONOUS_EDGES deassert SYNCHRONOUS_EDGES deassert SYNC_RESET 1 USE_RESET_REQUEST 0 altera_reset_bridge 19.2.0 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge qsys_top_altera_reset_bridge_1920_xf2264i 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.clk subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/clk clk_100_out_clk_clock_bridge/out_clk resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/agent_pipeline.cr0_reset agent_pipeline/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/agent_pipeline_001.cr0_reset agent_pipeline_001/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline.cr0_reset mux_pipeline/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_001.cr0_reset mux_pipeline_001/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_002.cr0_reset mux_pipeline_002/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/mux_pipeline_003.cr0_reset mux_pipeline_003/cr0_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk_reset subsys_periph_pb_cpu_0_s0_agent_rdata_fifo/clk_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo/clk_reset subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge/out_reset qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge subsys_periph_pb_cpu_0_s0_burst_adapter ADAPTER_VERSION new BURSTWRAP_CONST_MASK 0 BURSTWRAP_CONST_VALUE 0 BYTEENABLE_SYNTHESIS 1 COMPRESSED_READ_SUPPORT 1 ENABLE_AXI5 0 ENABLE_OOO 0 INCOMPLETE_WRAP_SUPPORT 0 IN_NARROW_SIZE 1 MERLIN_PACKET_FORMAT dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0) NO_WRAP_SUPPORT 0 OUT_BURSTWRAP_H 88 OUT_BYTE_CNT_H 73 OUT_COMPLETE_WRAP 0 OUT_FIXED 0 OUT_NARROW_SIZE 0 PIPE_INPUTS 0 PKT_ADDR_H 64 PKT_ADDR_L 36 PKT_BEGIN_BURST 96 PKT_BURSTWRAP_H 88 PKT_BURSTWRAP_L 82 PKT_BURST_SIZE_H 91 PKT_BURST_SIZE_L 89 PKT_BURST_TYPE_H 93 PKT_BURST_TYPE_L 92 PKT_BYTEEN_H 35 PKT_BYTEEN_L 32 PKT_BYTE_CNT_H 81 PKT_BYTE_CNT_L 71 PKT_EOP_OOO 89 PKT_SAI_H 133 PKT_SAI_L 133 PKT_SOP_OOO 90 PKT_TRANS_COMPRESSED_READ 65 PKT_TRANS_READ 68 PKT_TRANS_WRITE 67 ROLE_BASED_USER 0 ST_CHANNEL_W 2 ST_DATA_W 171 SYNC_RESET 1 altera_merlin_burst_adapter 19.4.0 subsys_periph_pb_cpu_0_s0_burst_adapter qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_burst_adapter.cr0 subsys_periph_pb_cpu_0_s0_burst_adapter/cr0 clk_100_out_clk_clock_bridge/out_clk qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0 subsys_periph_pb_cpu_0_s0_burst_adapter/sink0 cmd_mux/src resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_burst_adapter.cr0_reset subsys_periph_pb_cpu_0_s0_burst_adapter/cr0_reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_mm.piplineType PIPELINE_STAGE qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE qsys_mm.enableInstrumentation FALSE qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER qsys_mm.optimizeRdFifoSize FALSE qsys_mm.responseFifoType REGISTER_BASED qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE qsys_mm.fifoDepth 8 qsys_mm.enableAllPipelines FALSE qsys_mm.enableEccProtection FALSE qsys_mm.interconnectType STANDARD avalon_streaming 26.1 subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0 agent_pipeline/sink0 subsys_periph_pb_cpu_0_s0_burst_adapter/source0 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter my_altera_avalon_st_pipeline_stage BITS_PER_SYMBOL 171 CHANNEL_WIDTH 2 EMPTY_WIDTH 0 ERROR_WIDTH 0 MAX_CHANNEL 0 PACKET_WIDTH 2 PIPELINE_READY 1 SYMBOLS_PER_BEAT 1 SYNC_RESET 1 USE_EMPTY 0 USE_PACKETS 1 altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage 19.4.0 my_altera_avalon_st_pipeline_stage qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di 0 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage my_altera_avalon_st_pipeline_stage BITS_PER_SYMBOL 171 CHANNEL_WIDTH 2 EMPTY_WIDTH 0 ERROR_WIDTH 0 MAX_CHANNEL 0 PACKET_WIDTH 2 PIPELINE_READY 1 SYMBOLS_PER_BEAT 1 SYNC_RESET 1 USE_EMPTY 0 USE_PACKETS 1 altera_avalon_st_pipeline_stage 19.3.0 my_altera_avalon_st_pipeline_stage qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq 0 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage.my_altera_avalon_st_pipeline_stage subsys_periph_pb_cpu_0_s0_translator AV_ADDRESSGROUP 0 AV_ADDRESS_SYMBOLS 1 AV_ADDRESS_W 17 AV_ALWAYSBURSTMAXBURST 0 AV_BITS_PER_SYMBOL 8 AV_BURSTBOUNDARIES 0 AV_BURSTCOUNT_SYMBOLS 0 AV_BURSTCOUNT_W 1 AV_BYTEENABLE_W 4 AV_CONSTANT_BURST_BEHAVIOR 0 AV_DATA_HOLD 0 AV_DATA_HOLD_CYCLES 0 AV_DATA_W 32 AV_INTERLEAVEBURSTS 0 AV_ISBIGENDIAN 0 AV_LINEWRAPBURSTS 0 AV_MAX_PENDING_READ_TRANSACTIONS 1 AV_MAX_PENDING_WRITE_TRANSACTIONS 0 AV_READLATENCY 0 AV_READ_WAIT 0 AV_READ_WAIT_CYCLES 0 AV_REGISTERINCOMINGSIGNALS 0 AV_REGISTEROUTGOINGSIGNALS 0 AV_SETUP_WAIT 0 AV_SETUP_WAIT_CYCLES 0 AV_SYMBOLS_PER_WORD 4 AV_TIMING_UNITS 1 AV_WRITE_WAIT 0 AV_WRITE_WAIT_CYCLES 0 CHIPSELECT_THROUGH_READLATENCY 0 CLOCK_RATE 100000000 SYNC_RESET 1 UAV_ADDRESSGROUP 0 UAV_ADDRESS_W 29 UAV_BURSTCOUNT_W 3 UAV_BYTEENABLE_W 4 UAV_CONSTANT_BURST_BEHAVIOR 0 UAV_DATA_W 32 USE_ADDRESS 1 USE_AV_CLKEN 0 USE_BEGINBURSTTRANSFER 0 USE_BEGINTRANSFER 0 USE_BURSTCOUNT 1 USE_BYTEENABLE 1 USE_CHIPSELECT 0 USE_DEBUGACCESS 1 USE_LOCK 0 USE_OUTPUTENABLE 0 USE_READ 1 USE_READDATA 1 USE_READDATAVALID 1 USE_READRESPONSE 0 USE_UAV_CLKEN 0 USE_WAITREQUEST 1 USE_WRITE 1 USE_WRITEBYTEENABLE 0 USE_WRITEDATA 1 USE_WRITERESPONSE 0 WAITREQUEST_ALLOWANCE 0 altera_merlin_slave_translator 19.1 subsys_periph_pb_cpu_0_s0_translator qsys_top_altera_merlin_slave_translator_191_xg7rzxi 0 clockRateSysInfo 100000000 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clock 26.1 clk_100_out_clk_clock_bridge.out_clk/subsys_periph_pb_cpu_0_s0_translator.clk subsys_periph_pb_cpu_0_s0_translator/clk clk_100_out_clk_clock_bridge/out_clk resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset/subsys_periph_pb_cpu_0_s0_translator.reset subsys_periph_pb_cpu_0_s0_translator/reset subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge/out_reset qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE domainAlias qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER addressWidthSysInfo qsys_mm.optimizeRdFifoSize FALSE qsys_mm.maxAdditionalLatency 1 qsys_mm.splitCommandsFor4KBoundary FALSE qsys_mm.syncResets FALSE slaveDataWidthSysInfo -1 qsys_mm.enableAllPipelines FALSE qsys_mm.interconnectType STANDARD defaultConnection false qsys_mm.piplineType PIPELINE_STAGE qsys_mm.enableInstrumentation FALSE cpuInfoIdSysInfo qsys_mm.interconnectResetSource DEFAULT qsys_mm.burstAdapterImplementation GENERIC_CONVERTER baseAddress 0x0000 qsys_mm.responseFifoType REGISTER_BASED arbitrationPriority 1 qsys_mm.fifoDepth 8 addressMapSysInfo qsys_mm.enableEccProtection FALSE avalon 26.1 subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0 subsys_periph_pb_cpu_0_s0_translator/avalon_universal_slave_0 subsys_periph_pb_cpu_0_s0_agent/m0 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_translator rst_controller ADAPT_RESET_REQUEST 0 MIN_RST_ASSERTION_TIME 3 NUM_RESET_INPUTS 1 OUTPUT_RESET_SYNC_EDGES both RESET_REQUEST_PRESENT 0 RESET_REQ_EARLY_DSRT_TIME 1 RESET_REQ_WAIT_TIME 1 SYNC_DEPTH 2 USE_RESET_REQUEST_IN0 0 USE_RESET_REQUEST_IN1 0 USE_RESET_REQUEST_IN10 0 USE_RESET_REQUEST_IN11 0 USE_RESET_REQUEST_IN12 0 USE_RESET_REQUEST_IN13 0 USE_RESET_REQUEST_IN14 0 USE_RESET_REQUEST_IN15 0 USE_RESET_REQUEST_IN2 0 USE_RESET_REQUEST_IN3 0 USE_RESET_REQUEST_IN4 0 USE_RESET_REQUEST_IN5 0 USE_RESET_REQUEST_IN6 0 USE_RESET_REQUEST_IN7 0 USE_RESET_REQUEST_IN8 0 USE_RESET_REQUEST_IN9 0 USE_RESET_REQUEST_INPUT 0 altera_reset_controller 19.2.4 rst_controller altera_reset_controller altera_reset_controller 0 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo clockRateSysInfo -1 clock 26.1 rst_controller/clk clk_100/out_clk resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 mm_interconnect_0/subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset rst_controller/reset_out resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 mm_interconnect_0/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset rst_controller/reset_out resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 rst_controller/reset_in0 rst_in/out_reset qsys_top.rst_controller rst_in AUTO_CLK_CLOCK_RATE -1 bspCpu false componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>in_reset</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>in_reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>out_reset</name> <type>reset</type> <isStart>true</isStart> <ports> <port> <name>out_reset_n</name> <role>reset_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedDirectReset</key> <value>in_reset</value> </entry> <entry> <key>associatedResetSinks</key> <value>in_reset</value> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>altera_reset_bridge</className> <version>19.2.0</version> <displayName>Reset Bridge IP</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors> <descriptor> <parameterDefaultValue>-1</parameterDefaultValue> <parameterName>AUTO_CLK_CLOCK_RATE</parameterName> <parameterType>java.lang.Long</parameterType> <systemInfoArgs>clk</systemInfoArgs> <systemInfotype>CLOCK_RATE</systemInfotype> </descriptor> </descriptors> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos/> </systemInfos> </componentDefinition> cpuHashInfo <cpuHashInfoDefinition> <cpuHashInfoMap/> </cpuHashInfoDefinition> cpuInfo defaultBoundary <boundaryDefinition> <interfaces> <interface> <name>in_reset</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>in_reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>out_reset</name> <type>reset</type> <isStart>true</isStart> <ports> <port> <name>out_reset_n</name> <role>reset_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedDirectReset</key> <value>in_reset</value> </entry> <entry> <key>associatedResetSinks</key> <value>in_reset</value> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundaryDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>rst_in</hdlLibraryName> <fileSets> <fileSet> <fileSetName>rst_in</fileSetName> <fileSetFixedName>rst_in</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>rst_in</fileSetName> <fileSetFixedName>rst_in</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>rst_in</fileSetName> <fileSetFixedName>rst_in</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>rst_in</fileSetName> <fileSetFixedName>rst_in</fileSetFixedName> <fileSetKind>CDC</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>rst_in</fileSetName> <fileSetFixedName>rst_in</fileSetFixedName> <fileSetKind>CDC_VHDL</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> </fileSets> </generationInfoDefinition> hdlParameters <hdlParameterDescriptorDefinitionList/> hlsFile liveModuleName altera_reset_bridge_inst logicalView ip/qsys_top/rst_in.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> svInterfaceDefinition transformParameters <transformParameterDescriptorDefinitionList/> altera_generic_component 1.0 rst_in rst_in rst_in 0 resetDomainSysInfo -1 clockDomainSysInfo -1 clockResetSysInfo reset 26.1 rst_controller/reset_in0 rst_in/out_reset resetDomainSysInfo 4 clockDomainSysInfo 4 clockResetSysInfo reset 26.1 subsys_hps/f2sdram_rst rst_in/out_reset resetDomainSysInfo 4 clockDomainSysInfo 4 clockResetSysInfo reset 26.1 subsys_hps/hps2fpga_rst rst_in/out_reset resetDomainSysInfo 4 clockDomainSysInfo 4 clockResetSysInfo reset 26.1 subsys_hps/lwhps2fpga_rst rst_in/out_reset resetDomainSysInfo 4 clockDomainSysInfo 4 clockResetSysInfo reset 26.1 subsys_periph/reset rst_in/out_reset qsys_top.rst_in subsys_hps hps_subsys 1.0 subsys_hps hps_subsys hps_subsys 0 clockRateSysInfo 100000000 clockDomainSysInfo 1 resetDomainSysInfo 1 clockResetSysInfo clock 26.1 subsys_hps/f2sdram_clk clk_100/out_clk clockRateSysInfo 100000000 clockDomainSysInfo 1 resetDomainSysInfo 1 clockResetSysInfo clock 26.1 subsys_hps/hps2fpga_clk clk_100/out_clk clockRateSysInfo 100000000 clockDomainSysInfo 1 resetDomainSysInfo 1 clockResetSysInfo clock 26.1 subsys_hps/lwhps2fpga_clk clk_100/out_clk resetDomainSysInfo 4 clockDomainSysInfo 4 clockResetSysInfo reset 26.1 subsys_hps/f2sdram_rst rst_in/out_reset resetDomainSysInfo 4 clockDomainSysInfo 4 clockResetSysInfo reset 26.1 subsys_hps/hps2fpga_rst rst_in/out_reset resetDomainSysInfo 4 clockDomainSysInfo 4 clockResetSysInfo reset 26.1 subsys_hps/lwhps2fpga_rst rst_in/out_reset interruptsUsedSysInfo -1 irqNumber 0 interrupt 26.1 irq_mapper/sender subsys_hps/f2h_irq0_in qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE domainAlias qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER addressWidthSysInfo qsys_mm.optimizeRdFifoSize FALSE qsys_mm.syncResets TRUE qsys_mm.splitCommandsFor4KBoundary FALSE slaveDataWidthSysInfo -1 qsys_mm.maxAdditionalLatency 4 qsys_mm.enableAllPipelines FALSE qsys_mm.interconnectType STANDARD defaultConnection false qsys_mm.piplineType PIPELINE_STAGE qsys_mm.enableInstrumentation FALSE cpuInfoIdSysInfo qsys_mm.interconnectResetSource DEFAULT baseAddress 0x0000 qsys_mm.responseFifoType REGISTER_BASED qsys_mm.burstAdapterImplementation PER_BURST_TYPE_CONVERTER arbitrationPriority 1 qsys_mm.fifoDepth 8 addressMapSysInfo qsys_mm.enableEccProtection FALSE avalon 26.1 mm_interconnect_0/subsys_hps_lwhps2fpga subsys_hps/lwhps2fpga qsys_top.subsys_hps subsys_periph peripheral_subsys 1.0 subsys_periph peripheral_subsys peripheral_subsys 0 clockRateSysInfo 100000000 clockDomainSysInfo 1 resetDomainSysInfo 1 clockResetSysInfo clock 26.1 subsys_periph/clk clk_100/out_clk interruptsUsedSysInfo -1 irqNumber 0 interrupt 26.1 subsys_periph/button_pio_irq irq_mapper/receiver0 interruptsUsedSysInfo -1 irqNumber 0 interrupt 26.1 subsys_periph/dipsw_pio_irq irq_mapper/receiver1 qsys_mm.insertDefaultSlave FALSE qsys_mm.enableOutOfOrderSupport FALSE domainAlias qsys_mm.clockCrossingAdapter AUTO qsys_mm.widthAdapterImplementation GENERIC_CONVERTER addressWidthSysInfo qsys_mm.optimizeRdFifoSize FALSE qsys_mm.syncResets TRUE qsys_mm.splitCommandsFor4KBoundary FALSE slaveDataWidthSysInfo -1 qsys_mm.maxAdditionalLatency 4 qsys_mm.enableAllPipelines FALSE qsys_mm.interconnectType STANDARD defaultConnection false qsys_mm.piplineType PIPELINE_STAGE qsys_mm.enableInstrumentation FALSE cpuInfoIdSysInfo qsys_mm.interconnectResetSource DEFAULT baseAddress 0x0000 qsys_mm.responseFifoType REGISTER_BASED qsys_mm.burstAdapterImplementation PER_BURST_TYPE_CONVERTER arbitrationPriority 1 qsys_mm.fifoDepth 8 addressMapSysInfo qsys_mm.enableEccProtection FALSE avalon 26.1 subsys_periph/pb_cpu_0_s0 mm_interconnect_0/subsys_periph_pb_cpu_0_s0 resetDomainSysInfo 4 clockDomainSysInfo 4 clockResetSysInfo reset 26.1 subsys_periph/reset rst_in/out_reset qsys_top.subsys_periph user_rst_clkgate_0 DEVICE_FAMILY Agilex 5 bspCpu false componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>ninit_done</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>ninit_done</name> <role>ninit_done</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> <entry> <key>prSafe</key> <value>false</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>intel_user_rst_clkgate</className> <version>1.0.1</version> <displayName>Reset Release IP</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>DEVICE_FAMILY</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE_FAMILY</systemInfotype> </descriptor> </descriptors> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos/> </systemInfos> </componentDefinition> cpuHashInfo <cpuHashInfoDefinition> <cpuHashInfoMap/> </cpuHashInfoDefinition> cpuInfo defaultBoundary <boundaryDefinition> <interfaces> <interface> <name>ninit_done</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>ninit_done</name> <role>ninit_done</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> <entry> <key>prSafe</key> <value>false</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundaryDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>user_rst_clkgate_0</hdlLibraryName> <fileSets> <fileSet> <fileSetName>user_rst_clkgate_0</fileSetName> <fileSetFixedName>user_rst_clkgate_0</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>user_rst_clkgate_0</fileSetName> <fileSetFixedName>user_rst_clkgate_0</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>user_rst_clkgate_0</fileSetName> <fileSetFixedName>user_rst_clkgate_0</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>user_rst_clkgate_0</fileSetName> <fileSetFixedName>user_rst_clkgate_0</fileSetFixedName> <fileSetKind>CDC</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> <fileSet> <fileSetName>user_rst_clkgate_0</fileSetName> <fileSetFixedName>user_rst_clkgate_0</fileSetFixedName> <fileSetKind>CDC_VHDL</fileSetKind> <fileSetFiles/> <fileSetFileChangeDefs/> </fileSet> </fileSets> </generationInfoDefinition> hdlParameters <hdlParameterDescriptorDefinitionList/> hlsFile liveModuleName intel_user_rst_clkgate_inst logicalView ip/qsys_top/user_rst_clkgate_0.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> svInterfaceDefinition transformParameters <transformParameterDescriptorDefinitionList/> altera_generic_component 1.0 user_rst_clkgate_0 user_rst_clkgate_0 user_rst_clkgate_0 0 qsys_top.user_rst_clkgate_0