thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
80 lines
7.7 KiB
CSV
80 lines
7.7 KiB
CSV
# system info qsys_top on 2026.04.08.10:52:54
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system_info:
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name,value
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DEVICE,A5EB013BB23BE4SCS
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DEVICE_FAMILY,Agilex 5
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GENERATION_ID,0
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#
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#
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# Files generated for qsys_top on 2026.04.08.10:52:54
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files:
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filepath,kind,attributes,module,is_top
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sim/qsys_top.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top,true
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altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top_altera_mm_interconnect_1920_ykfyxdi,false
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altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv,SYSTEM_VERILOG,,qsys_top_altera_irq_mapper_2001_lp4cnei,false
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altera_reset_controller_1924/sim/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
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altera_reset_controller_1924/sim/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
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altera_reset_controller_1924/sim/altera_reset_controller.sdc,SDC_ENTITY,NO_SDC_PROMOTION,altera_reset_controller,false
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altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_translator_1987_lty7xoq,false
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altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_translator_191_xg7rzxi,false
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altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_master_ni_19117_qautany,false
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altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_master_ni_19117_qautany,false
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altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_agent_1930_jxauz3i,false
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altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_agent_1930_jxauz3i,false
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altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v,VERILOG,,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi,false
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altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_router_1921_ox5xuhq,false
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altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_router_1921_sxavatq,false
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altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
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altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
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altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
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altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
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altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
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altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
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altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
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altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
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altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q,false
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altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_666s25q,false
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altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_666s25q,false
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altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_demultiplexer_1921_qyizksq,false
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altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_yjgptii,false
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altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_yjgptii,false
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altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di,false
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altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv,SYSTEM_VERILOG,,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq,false
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altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq,false
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#
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# Map from instance-path to kind of module
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instances:
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instancePath,module
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qsys_top.clk_100,clk_100
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qsys_top.rst_in,rst_in
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qsys_top.user_rst_clkgate_0,user_rst_clkgate_0
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qsys_top.subsys_hps,hps_subsys
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qsys_top.subsys_periph,peripheral_subsys
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qsys_top.mm_interconnect_0,qsys_top_altera_mm_interconnect_1920_ykfyxdi
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qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_translator,qsys_top_altera_merlin_axi_translator_1987_lty7xoq
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qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_translator,qsys_top_altera_merlin_slave_translator_191_xg7rzxi
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qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_agent,qsys_top_altera_merlin_axi_master_ni_19117_qautany
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qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent,qsys_top_altera_merlin_slave_agent_1930_jxauz3i
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qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi
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qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rdata_fifo,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi
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qsys_top.mm_interconnect_0.router,qsys_top_altera_merlin_router_1921_ox5xuhq
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qsys_top.mm_interconnect_0.router_001,qsys_top_altera_merlin_router_1921_ox5xuhq
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qsys_top.mm_interconnect_0.router_002,qsys_top_altera_merlin_router_1921_sxavatq
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qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy
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qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage,qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di
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qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage.my_altera_avalon_st_pipeline_stage,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
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qsys_top.mm_interconnect_0.cmd_demux,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
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qsys_top.mm_interconnect_0.cmd_demux_001,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
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qsys_top.mm_interconnect_0.cmd_mux,qsys_top_altera_merlin_multiplexer_1922_666s25q
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qsys_top.mm_interconnect_0.rsp_demux,qsys_top_altera_merlin_demultiplexer_1921_qyizksq
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qsys_top.mm_interconnect_0.rsp_mux,qsys_top_altera_merlin_multiplexer_1922_yjgptii
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qsys_top.mm_interconnect_0.rsp_mux_001,qsys_top_altera_merlin_multiplexer_1922_yjgptii
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qsys_top.mm_interconnect_0.agent_pipeline,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
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qsys_top.mm_interconnect_0.agent_pipeline_001,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
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qsys_top.mm_interconnect_0.mux_pipeline,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
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qsys_top.mm_interconnect_0.mux_pipeline_001,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
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qsys_top.mm_interconnect_0.mux_pipeline_002,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
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qsys_top.mm_interconnect_0.mux_pipeline_003,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
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qsys_top.irq_mapper,qsys_top_altera_irq_mapper_2001_lp4cnei
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qsys_top.rst_controller,altera_reset_controller
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