thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
149 lines
17 KiB
Plaintext
149 lines
17 KiB
Plaintext
component qsys_top is
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port (
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clk_100_clk : in std_logic := 'X'; -- clk
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reset_reset_n : in std_logic := 'X'; -- reset_n
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ninit_done_ninit_done : out std_logic; -- ninit_done
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h2f_reset_reset : out std_logic; -- reset
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subsys_hps_hps2fpga_awid : out std_logic_vector(3 downto 0); -- awid
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subsys_hps_hps2fpga_awaddr : out std_logic_vector(37 downto 0); -- awaddr
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subsys_hps_hps2fpga_awlen : out std_logic_vector(7 downto 0); -- awlen
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subsys_hps_hps2fpga_awsize : out std_logic_vector(2 downto 0); -- awsize
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subsys_hps_hps2fpga_awburst : out std_logic_vector(1 downto 0); -- awburst
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subsys_hps_hps2fpga_awlock : out std_logic; -- awlock
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subsys_hps_hps2fpga_awcache : out std_logic_vector(3 downto 0); -- awcache
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subsys_hps_hps2fpga_awprot : out std_logic_vector(2 downto 0); -- awprot
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subsys_hps_hps2fpga_awvalid : out std_logic; -- awvalid
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subsys_hps_hps2fpga_awready : in std_logic := 'X'; -- awready
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subsys_hps_hps2fpga_wdata : out std_logic_vector(127 downto 0); -- wdata
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subsys_hps_hps2fpga_wstrb : out std_logic_vector(15 downto 0); -- wstrb
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subsys_hps_hps2fpga_wlast : out std_logic; -- wlast
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subsys_hps_hps2fpga_wvalid : out std_logic; -- wvalid
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subsys_hps_hps2fpga_wready : in std_logic := 'X'; -- wready
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subsys_hps_hps2fpga_bid : in std_logic_vector(3 downto 0) := (others => 'X'); -- bid
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subsys_hps_hps2fpga_bresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp
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subsys_hps_hps2fpga_bvalid : in std_logic := 'X'; -- bvalid
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subsys_hps_hps2fpga_bready : out std_logic; -- bready
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subsys_hps_hps2fpga_arid : out std_logic_vector(3 downto 0); -- arid
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subsys_hps_hps2fpga_araddr : out std_logic_vector(37 downto 0); -- araddr
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subsys_hps_hps2fpga_arlen : out std_logic_vector(7 downto 0); -- arlen
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subsys_hps_hps2fpga_arsize : out std_logic_vector(2 downto 0); -- arsize
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subsys_hps_hps2fpga_arburst : out std_logic_vector(1 downto 0); -- arburst
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subsys_hps_hps2fpga_arlock : out std_logic; -- arlock
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subsys_hps_hps2fpga_arcache : out std_logic_vector(3 downto 0); -- arcache
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subsys_hps_hps2fpga_arprot : out std_logic_vector(2 downto 0); -- arprot
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subsys_hps_hps2fpga_arvalid : out std_logic; -- arvalid
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subsys_hps_hps2fpga_arready : in std_logic := 'X'; -- arready
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subsys_hps_hps2fpga_rid : in std_logic_vector(3 downto 0) := (others => 'X'); -- rid
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subsys_hps_hps2fpga_rdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- rdata
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subsys_hps_hps2fpga_rresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp
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subsys_hps_hps2fpga_rlast : in std_logic := 'X'; -- rlast
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subsys_hps_hps2fpga_rvalid : in std_logic := 'X'; -- rvalid
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subsys_hps_hps2fpga_rready : out std_logic; -- rready
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subsys_hps_h2f_warm_reset_handshake_reset_req : out std_logic; -- reset_req
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subsys_hps_h2f_warm_reset_handshake_reset_ack : in std_logic := 'X'; -- reset_ack
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hps_io_hps_osc_clk : in std_logic := 'X'; -- hps_osc_clk
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hps_io_sdmmc_data0 : inout std_logic := 'X'; -- sdmmc_data0
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hps_io_sdmmc_data1 : inout std_logic := 'X'; -- sdmmc_data1
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hps_io_sdmmc_cclk : out std_logic; -- sdmmc_cclk
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hps_io_sdmmc_data2 : inout std_logic := 'X'; -- sdmmc_data2
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hps_io_sdmmc_data3 : inout std_logic := 'X'; -- sdmmc_data3
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hps_io_sdmmc_cmd : inout std_logic := 'X'; -- sdmmc_cmd
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hps_io_usb0_clk : in std_logic := 'X'; -- usb0_clk
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hps_io_usb0_stp : out std_logic; -- usb0_stp
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hps_io_usb0_dir : in std_logic := 'X'; -- usb0_dir
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hps_io_usb0_data0 : inout std_logic := 'X'; -- usb0_data0
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hps_io_usb0_data1 : inout std_logic := 'X'; -- usb0_data1
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hps_io_usb0_nxt : in std_logic := 'X'; -- usb0_nxt
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hps_io_usb0_data2 : inout std_logic := 'X'; -- usb0_data2
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hps_io_usb0_data3 : inout std_logic := 'X'; -- usb0_data3
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hps_io_usb0_data4 : inout std_logic := 'X'; -- usb0_data4
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hps_io_usb0_data5 : inout std_logic := 'X'; -- usb0_data5
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hps_io_usb0_data6 : inout std_logic := 'X'; -- usb0_data6
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hps_io_usb0_data7 : inout std_logic := 'X'; -- usb0_data7
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hps_io_emac0_tx_clk : out std_logic; -- emac0_tx_clk
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hps_io_emac0_tx_ctl : out std_logic; -- emac0_tx_ctl
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hps_io_emac0_rx_clk : in std_logic := 'X'; -- emac0_rx_clk
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hps_io_emac0_rx_ctl : in std_logic := 'X'; -- emac0_rx_ctl
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hps_io_emac0_txd0 : out std_logic; -- emac0_txd0
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hps_io_emac0_txd1 : out std_logic; -- emac0_txd1
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hps_io_emac0_rxd0 : in std_logic := 'X'; -- emac0_rxd0
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hps_io_emac0_rxd1 : in std_logic := 'X'; -- emac0_rxd1
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hps_io_emac0_txd2 : out std_logic; -- emac0_txd2
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hps_io_emac0_txd3 : out std_logic; -- emac0_txd3
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hps_io_emac0_rxd2 : in std_logic := 'X'; -- emac0_rxd2
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hps_io_emac0_rxd3 : in std_logic := 'X'; -- emac0_rxd3
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hps_io_mdio0_mdio : inout std_logic := 'X'; -- mdio0_mdio
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hps_io_mdio0_mdc : out std_logic; -- mdio0_mdc
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hps_io_uart1_tx : out std_logic; -- uart1_tx
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hps_io_uart1_rx : in std_logic := 'X'; -- uart1_rx
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hps_io_i2c1_sda : inout std_logic := 'X'; -- i2c1_sda
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hps_io_i2c1_scl : inout std_logic := 'X'; -- i2c1_scl
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hps_io_gpio28 : inout std_logic := 'X'; -- gpio28
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hps_io_gpio34 : inout std_logic := 'X'; -- gpio34
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hps_io_gpio40 : inout std_logic := 'X'; -- gpio40
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hps_io_gpio41 : inout std_logic := 'X'; -- gpio41
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f2h_irq1_in_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
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f2sdram_araddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- araddr
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f2sdram_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst
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f2sdram_arcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- arcache
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f2sdram_arid : in std_logic_vector(4 downto 0) := (others => 'X'); -- arid
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f2sdram_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- arlen
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f2sdram_arlock : in std_logic := 'X'; -- arlock
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f2sdram_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
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f2sdram_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- arqos
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f2sdram_arready : out std_logic; -- arready
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f2sdram_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize
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f2sdram_arvalid : in std_logic := 'X'; -- arvalid
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f2sdram_awaddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- awaddr
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f2sdram_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst
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f2sdram_awcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- awcache
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f2sdram_awid : in std_logic_vector(4 downto 0) := (others => 'X'); -- awid
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f2sdram_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- awlen
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f2sdram_awlock : in std_logic := 'X'; -- awlock
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f2sdram_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
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f2sdram_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- awqos
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f2sdram_awready : out std_logic; -- awready
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f2sdram_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize
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f2sdram_awvalid : in std_logic := 'X'; -- awvalid
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f2sdram_bid : out std_logic_vector(4 downto 0); -- bid
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f2sdram_bready : in std_logic := 'X'; -- bready
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f2sdram_bresp : out std_logic_vector(1 downto 0); -- bresp
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f2sdram_bvalid : out std_logic; -- bvalid
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f2sdram_rdata : out std_logic_vector(255 downto 0); -- rdata
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f2sdram_rid : out std_logic_vector(4 downto 0); -- rid
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f2sdram_rlast : out std_logic; -- rlast
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f2sdram_rready : in std_logic := 'X'; -- rready
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f2sdram_rresp : out std_logic_vector(1 downto 0); -- rresp
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f2sdram_rvalid : out std_logic; -- rvalid
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f2sdram_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- wdata
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f2sdram_wlast : in std_logic := 'X'; -- wlast
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f2sdram_wready : out std_logic; -- wready
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f2sdram_wstrb : in std_logic_vector(31 downto 0) := (others => 'X'); -- wstrb
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f2sdram_wvalid : in std_logic := 'X'; -- wvalid
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f2sdram_aruser : in std_logic_vector(7 downto 0) := (others => 'X'); -- aruser
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f2sdram_awuser : in std_logic_vector(7 downto 0) := (others => 'X'); -- awuser
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f2sdram_wuser : in std_logic_vector(7 downto 0) := (others => 'X'); -- wuser
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f2sdram_buser : out std_logic_vector(7 downto 0); -- buser
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f2sdram_arregion : in std_logic_vector(3 downto 0) := (others => 'X'); -- arregion
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f2sdram_ruser : out std_logic_vector(7 downto 0); -- ruser
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f2sdram_awregion : in std_logic_vector(3 downto 0) := (others => 'X'); -- awregion
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emif_hps_emif_mem_0_mem_cs : out std_logic_vector(0 downto 0); -- mem_cs
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emif_hps_emif_mem_0_mem_ca : out std_logic_vector(5 downto 0); -- mem_ca
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emif_hps_emif_mem_0_mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
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emif_hps_emif_mem_0_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
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emif_hps_emif_mem_0_mem_dqs_t : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_t
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emif_hps_emif_mem_0_mem_dqs_c : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_c
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emif_hps_emif_mem_0_mem_dmi : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dmi
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emif_hps_emif_mem_ck_0_mem_ck_t : out std_logic_vector(0 downto 0); -- mem_ck_t
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emif_hps_emif_mem_ck_0_mem_ck_c : out std_logic_vector(0 downto 0); -- mem_ck_c
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emif_hps_emif_mem_reset_n_mem_reset_n : out std_logic; -- mem_reset_n
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emif_hps_emif_oct_0_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
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emif_hps_emif_ref_clk_0_clk : in std_logic := 'X'; -- clk
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button_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
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dipsw_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
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led_pio_external_connection_in_port : in std_logic_vector(2 downto 0) := (others => 'X'); -- in_port
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led_pio_external_connection_out_port : out std_logic_vector(2 downto 0) -- out_port
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);
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end component qsys_top;
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