component qsys_top is port ( clk_100_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n ninit_done_ninit_done : out std_logic; -- ninit_done h2f_reset_reset : out std_logic; -- reset subsys_hps_hps2fpga_awid : out std_logic_vector(3 downto 0); -- awid subsys_hps_hps2fpga_awaddr : out std_logic_vector(37 downto 0); -- awaddr subsys_hps_hps2fpga_awlen : out std_logic_vector(7 downto 0); -- awlen subsys_hps_hps2fpga_awsize : out std_logic_vector(2 downto 0); -- awsize subsys_hps_hps2fpga_awburst : out std_logic_vector(1 downto 0); -- awburst subsys_hps_hps2fpga_awlock : out std_logic; -- awlock subsys_hps_hps2fpga_awcache : out std_logic_vector(3 downto 0); -- awcache subsys_hps_hps2fpga_awprot : out std_logic_vector(2 downto 0); -- awprot subsys_hps_hps2fpga_awvalid : out std_logic; -- awvalid subsys_hps_hps2fpga_awready : in std_logic := 'X'; -- awready subsys_hps_hps2fpga_wdata : out std_logic_vector(127 downto 0); -- wdata subsys_hps_hps2fpga_wstrb : out std_logic_vector(15 downto 0); -- wstrb subsys_hps_hps2fpga_wlast : out std_logic; -- wlast subsys_hps_hps2fpga_wvalid : out std_logic; -- wvalid subsys_hps_hps2fpga_wready : in std_logic := 'X'; -- wready subsys_hps_hps2fpga_bid : in std_logic_vector(3 downto 0) := (others => 'X'); -- bid subsys_hps_hps2fpga_bresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp subsys_hps_hps2fpga_bvalid : in std_logic := 'X'; -- bvalid subsys_hps_hps2fpga_bready : out std_logic; -- bready subsys_hps_hps2fpga_arid : out std_logic_vector(3 downto 0); -- arid subsys_hps_hps2fpga_araddr : out std_logic_vector(37 downto 0); -- araddr subsys_hps_hps2fpga_arlen : out std_logic_vector(7 downto 0); -- arlen subsys_hps_hps2fpga_arsize : out std_logic_vector(2 downto 0); -- arsize subsys_hps_hps2fpga_arburst : out std_logic_vector(1 downto 0); -- arburst subsys_hps_hps2fpga_arlock : out std_logic; -- arlock subsys_hps_hps2fpga_arcache : out std_logic_vector(3 downto 0); -- arcache subsys_hps_hps2fpga_arprot : out std_logic_vector(2 downto 0); -- arprot subsys_hps_hps2fpga_arvalid : out std_logic; -- arvalid subsys_hps_hps2fpga_arready : in std_logic := 'X'; -- arready subsys_hps_hps2fpga_rid : in std_logic_vector(3 downto 0) := (others => 'X'); -- rid subsys_hps_hps2fpga_rdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- rdata subsys_hps_hps2fpga_rresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp subsys_hps_hps2fpga_rlast : in std_logic := 'X'; -- rlast subsys_hps_hps2fpga_rvalid : in std_logic := 'X'; -- rvalid subsys_hps_hps2fpga_rready : out std_logic; -- rready subsys_hps_h2f_warm_reset_handshake_reset_req : out std_logic; -- reset_req subsys_hps_h2f_warm_reset_handshake_reset_ack : in std_logic := 'X'; -- reset_ack hps_io_hps_osc_clk : in std_logic := 'X'; -- hps_osc_clk hps_io_sdmmc_data0 : inout std_logic := 'X'; -- sdmmc_data0 hps_io_sdmmc_data1 : inout std_logic := 'X'; -- sdmmc_data1 hps_io_sdmmc_cclk : out std_logic; -- sdmmc_cclk hps_io_sdmmc_data2 : inout std_logic := 'X'; -- sdmmc_data2 hps_io_sdmmc_data3 : inout std_logic := 'X'; -- sdmmc_data3 hps_io_sdmmc_cmd : inout std_logic := 'X'; -- sdmmc_cmd hps_io_usb0_clk : in std_logic := 'X'; -- usb0_clk hps_io_usb0_stp : out std_logic; -- usb0_stp hps_io_usb0_dir : in std_logic := 'X'; -- usb0_dir hps_io_usb0_data0 : inout std_logic := 'X'; -- usb0_data0 hps_io_usb0_data1 : inout std_logic := 'X'; -- usb0_data1 hps_io_usb0_nxt : in std_logic := 'X'; -- usb0_nxt hps_io_usb0_data2 : inout std_logic := 'X'; -- usb0_data2 hps_io_usb0_data3 : inout std_logic := 'X'; -- usb0_data3 hps_io_usb0_data4 : inout std_logic := 'X'; -- usb0_data4 hps_io_usb0_data5 : inout std_logic := 'X'; -- usb0_data5 hps_io_usb0_data6 : inout std_logic := 'X'; -- usb0_data6 hps_io_usb0_data7 : inout std_logic := 'X'; -- usb0_data7 hps_io_emac0_tx_clk : out std_logic; -- emac0_tx_clk hps_io_emac0_tx_ctl : out std_logic; -- emac0_tx_ctl hps_io_emac0_rx_clk : in std_logic := 'X'; -- emac0_rx_clk hps_io_emac0_rx_ctl : in std_logic := 'X'; -- emac0_rx_ctl hps_io_emac0_txd0 : out std_logic; -- emac0_txd0 hps_io_emac0_txd1 : out std_logic; -- emac0_txd1 hps_io_emac0_rxd0 : in std_logic := 'X'; -- emac0_rxd0 hps_io_emac0_rxd1 : in std_logic := 'X'; -- emac0_rxd1 hps_io_emac0_txd2 : out std_logic; -- emac0_txd2 hps_io_emac0_txd3 : out std_logic; -- emac0_txd3 hps_io_emac0_rxd2 : in std_logic := 'X'; -- emac0_rxd2 hps_io_emac0_rxd3 : in std_logic := 'X'; -- emac0_rxd3 hps_io_mdio0_mdio : inout std_logic := 'X'; -- mdio0_mdio hps_io_mdio0_mdc : out std_logic; -- mdio0_mdc hps_io_uart1_tx : out std_logic; -- uart1_tx hps_io_uart1_rx : in std_logic := 'X'; -- uart1_rx hps_io_i2c1_sda : inout std_logic := 'X'; -- i2c1_sda hps_io_i2c1_scl : inout std_logic := 'X'; -- i2c1_scl hps_io_gpio28 : inout std_logic := 'X'; -- gpio28 hps_io_gpio34 : inout std_logic := 'X'; -- gpio34 hps_io_gpio40 : inout std_logic := 'X'; -- gpio40 hps_io_gpio41 : inout std_logic := 'X'; -- gpio41 f2h_irq1_in_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq f2sdram_araddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- araddr f2sdram_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst f2sdram_arcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- arcache f2sdram_arid : in std_logic_vector(4 downto 0) := (others => 'X'); -- arid f2sdram_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- arlen f2sdram_arlock : in std_logic := 'X'; -- arlock f2sdram_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot f2sdram_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- arqos f2sdram_arready : out std_logic; -- arready f2sdram_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize f2sdram_arvalid : in std_logic := 'X'; -- arvalid f2sdram_awaddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- awaddr f2sdram_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst f2sdram_awcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- awcache f2sdram_awid : in std_logic_vector(4 downto 0) := (others => 'X'); -- awid f2sdram_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- awlen f2sdram_awlock : in std_logic := 'X'; -- awlock f2sdram_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot f2sdram_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- awqos f2sdram_awready : out std_logic; -- awready f2sdram_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize f2sdram_awvalid : in std_logic := 'X'; -- awvalid f2sdram_bid : out std_logic_vector(4 downto 0); -- bid f2sdram_bready : in std_logic := 'X'; -- bready f2sdram_bresp : out std_logic_vector(1 downto 0); -- bresp f2sdram_bvalid : out std_logic; -- bvalid f2sdram_rdata : out std_logic_vector(255 downto 0); -- rdata f2sdram_rid : out std_logic_vector(4 downto 0); -- rid f2sdram_rlast : out std_logic; -- rlast f2sdram_rready : in std_logic := 'X'; -- rready f2sdram_rresp : out std_logic_vector(1 downto 0); -- rresp f2sdram_rvalid : out std_logic; -- rvalid f2sdram_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- wdata f2sdram_wlast : in std_logic := 'X'; -- wlast f2sdram_wready : out std_logic; -- wready f2sdram_wstrb : in std_logic_vector(31 downto 0) := (others => 'X'); -- wstrb f2sdram_wvalid : in std_logic := 'X'; -- wvalid f2sdram_aruser : in std_logic_vector(7 downto 0) := (others => 'X'); -- aruser f2sdram_awuser : in std_logic_vector(7 downto 0) := (others => 'X'); -- awuser f2sdram_wuser : in std_logic_vector(7 downto 0) := (others => 'X'); -- wuser f2sdram_buser : out std_logic_vector(7 downto 0); -- buser f2sdram_arregion : in std_logic_vector(3 downto 0) := (others => 'X'); -- arregion f2sdram_ruser : out std_logic_vector(7 downto 0); -- ruser f2sdram_awregion : in std_logic_vector(3 downto 0) := (others => 'X'); -- awregion emif_hps_emif_mem_0_mem_cs : out std_logic_vector(0 downto 0); -- mem_cs emif_hps_emif_mem_0_mem_ca : out std_logic_vector(5 downto 0); -- mem_ca emif_hps_emif_mem_0_mem_cke : out std_logic_vector(0 downto 0); -- mem_cke emif_hps_emif_mem_0_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq emif_hps_emif_mem_0_mem_dqs_t : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_t emif_hps_emif_mem_0_mem_dqs_c : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_c emif_hps_emif_mem_0_mem_dmi : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dmi emif_hps_emif_mem_ck_0_mem_ck_t : out std_logic_vector(0 downto 0); -- mem_ck_t emif_hps_emif_mem_ck_0_mem_ck_c : out std_logic_vector(0 downto 0); -- mem_ck_c emif_hps_emif_mem_reset_n_mem_reset_n : out std_logic; -- mem_reset_n emif_hps_emif_oct_0_oct_rzqin : in std_logic := 'X'; -- oct_rzqin emif_hps_emif_ref_clk_0_clk : in std_logic := 'X'; -- clk button_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export dipsw_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export led_pio_external_connection_in_port : in std_logic_vector(2 downto 0) := (others => 'X'); -- in_port led_pio_external_connection_out_port : out std_logic_vector(2 downto 0) -- out_port ); end component qsys_top;