thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
7222 lines
366 KiB
XML
Executable File
7222 lines
366 KiB
XML
Executable File
<?xml version="1.0" ?>
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<!--Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus Prime License Agreement,
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the Altera FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Altera and sold by Altera or its authorized distributors.-->
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<ipxact:design xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
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<ipxact:vendor>Altera Corporation</ipxact:vendor>
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<ipxact:library>peripheral_subsys</ipxact:library>
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<ipxact:name>peripheral_subsys</ipxact:name>
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<ipxact:version>1.0</ipxact:version>
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<ipxact:componentInstances></ipxact:componentInstances>
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<ipxact:vendorExtensions>
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<altera:catalog_card_info>
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<altera:name>$${FILENAME}</altera:name>
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<altera:displayName>$${FILENAME}</altera:displayName>
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<altera:version>1.0</altera:version>
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<altera:description></altera:description>
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<altera:tags></altera:tags>
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<altera:categories>Systems</altera:categories>
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<altera:tool>QsysPro</altera:tool>
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</altera:catalog_card_info>
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<altera:altera_system_parameters>
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<ipxact:parameters>
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<ipxact:parameter parameterId="board" type="string">
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<ipxact:name>board</ipxact:name>
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<ipxact:displayName>Board</ipxact:displayName>
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<ipxact:value>default</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="bonusData" type="string">
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<ipxact:name>bonusData</ipxact:name>
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<ipxact:displayName>bonusData</ipxact:displayName>
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<ipxact:value>bonusData
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{
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element button_pio
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{
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datum _sortIndex
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{
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value = "3";
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type = "int";
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}
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}
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element dipsw_pio
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{
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datum _sortIndex
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{
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value = "4";
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type = "int";
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}
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}
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element led_pio
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{
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datum _sortIndex
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{
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value = "5";
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type = "int";
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}
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}
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element pb_cpu_0
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{
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datum _sortIndex
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{
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value = "6";
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type = "int";
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}
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}
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element periph_clk
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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element periph_rst_in
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{
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datum _sortIndex
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{
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value = "1";
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type = "int";
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}
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}
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element sysid
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{
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datum _sortIndex
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{
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value = "2";
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type = "int";
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}
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}
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}
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</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="cpuInfo" type="string">
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<ipxact:name>cpuInfo</ipxact:name>
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<ipxact:displayName>cpuInfo</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="designId" type="string">
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<ipxact:name>designId</ipxact:name>
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<ipxact:displayName>designId</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="device" type="string">
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<ipxact:name>device</ipxact:name>
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<ipxact:displayName>Device</ipxact:displayName>
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<ipxact:value>A5EB013BB23BE4SCS</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="deviceFamily" type="string">
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<ipxact:name>deviceFamily</ipxact:name>
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<ipxact:displayName>Device family</ipxact:displayName>
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<ipxact:value>Agilex 5</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
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<ipxact:name>deviceSpeedGrade</ipxact:name>
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<ipxact:displayName>Device Speed Grade</ipxact:displayName>
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<ipxact:value>4</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="dflBitArray" type="string">
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<ipxact:name>dflBitArray</ipxact:name>
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<ipxact:displayName>dflBitArray</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="fabricMode" type="string">
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<ipxact:name>fabricMode</ipxact:name>
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<ipxact:displayName>fabricMode</ipxact:displayName>
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<ipxact:value>QSYS</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="generateLegacySim" type="bit">
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<ipxact:name>generateLegacySim</ipxact:name>
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<ipxact:displayName>generateLegacySim</ipxact:displayName>
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<ipxact:value>false</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="generationId" type="int">
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<ipxact:name>generationId</ipxact:name>
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<ipxact:displayName>Generation Id</ipxact:displayName>
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<ipxact:value>0</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="globalResetBus" type="bit">
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<ipxact:name>globalResetBus</ipxact:name>
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<ipxact:displayName>Global reset</ipxact:displayName>
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<ipxact:value>false</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="hdlLanguage" type="string">
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<ipxact:name>hdlLanguage</ipxact:name>
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<ipxact:displayName>hdlLanguage</ipxact:displayName>
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<ipxact:value>VERILOG</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
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<ipxact:name>hideFromIPCatalog</ipxact:name>
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<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
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<ipxact:value>false</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
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<ipxact:name>lockedInterfaceDefinition</ipxact:name>
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<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="sopcBorderPoints" type="bit">
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<ipxact:name>sopcBorderPoints</ipxact:name>
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<ipxact:displayName>Use SOPC Builder port naming</ipxact:displayName>
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<ipxact:value>false</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="systemHash" type="longint">
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<ipxact:name>systemHash</ipxact:name>
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<ipxact:displayName>systemHash</ipxact:displayName>
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<ipxact:value>0</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="systemInfos" type="string">
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<ipxact:name>systemInfos</ipxact:name>
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<ipxact:displayName>systemInfos</ipxact:displayName>
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<ipxact:value><systemInfosDefinition>
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<connPtSystemInfos>
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<entry>
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<key>clk</key>
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<value>
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<connectionPointName>clk</connectionPointName>
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<suppliedSystemInfos>
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<entry>
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<key>CLOCK_DOMAIN</key>
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<value>1</value>
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</entry>
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<entry>
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<key>CLOCK_RATE</key>
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<value>100000000</value>
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</entry>
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<entry>
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<key>RESET_DOMAIN</key>
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<value>1</value>
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</entry>
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</suppliedSystemInfos>
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<consumedSystemInfos/>
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</value>
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</entry>
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<entry>
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<key>pb_cpu_0_s0</key>
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<value>
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<connectionPointName>pb_cpu_0_s0</connectionPointName>
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<suppliedSystemInfos>
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<entry>
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<key>CPU_INFO_ID</key>
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<value></value>
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</entry>
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</suppliedSystemInfos>
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<consumedSystemInfos>
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<entry>
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<key>ADDRESS_MAP</key>
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<value>&lt;address-map&gt;&lt;slave name='sysid.control_slave' start='0x10000' end='0x10008' datawidth='32' /&gt;&lt;slave name='button_pio.s1' start='0x10060' end='0x10070' datawidth='32' /&gt;&lt;slave name='dipsw_pio.s1' start='0x10070' end='0x10080' datawidth='32' /&gt;&lt;slave name='led_pio.s1' start='0x10080' end='0x10090' datawidth='32' /&gt;&lt;/address-map&gt;</value>
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</entry>
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<entry>
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<key>ADDRESS_WIDTH</key>
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<value>17</value>
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</entry>
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<entry>
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<key>MAX_SLAVE_DATA_WIDTH</key>
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<value>32</value>
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</entry>
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</consumedSystemInfos>
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</value>
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</entry>
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</connPtSystemInfos>
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</systemInfosDefinition></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="systemScripts" type="string">
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<ipxact:name>systemScripts</ipxact:name>
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<ipxact:displayName>systemScripts</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="testBenchDutName" type="string">
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<ipxact:name>testBenchDutName</ipxact:name>
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<ipxact:displayName>Use Test Bench Naming Pattern</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="timeStamp" type="longint">
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<ipxact:name>timeStamp</ipxact:name>
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<ipxact:displayName>timeStamp</ipxact:displayName>
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<ipxact:value>0</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="useTestBenchNamingPattern" type="bit">
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<ipxact:name>useTestBenchNamingPattern</ipxact:name>
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<ipxact:displayName>Use Test Bench Naming Pattern</ipxact:displayName>
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<ipxact:value>false</ipxact:value>
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</ipxact:parameter>
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</ipxact:parameters>
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</altera:altera_system_parameters>
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<altera:instance_parameters></altera:instance_parameters>
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<altera:instance_script></altera:instance_script>
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<altera:modules>
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<altera:module altera:enabled="true" altera:auto_export="false">
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<altera:entity_info>
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<ipxact:vendor>Altera Corporation</ipxact:vendor>
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<ipxact:library>button_pio</ipxact:library>
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<ipxact:name>altera_generic_component</ipxact:name>
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<ipxact:version>1.0</ipxact:version>
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</altera:entity_info>
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<altera:altera_module_parameters>
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<ipxact:parameters>
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<ipxact:parameter parameterId="bspCpu" type="bit">
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<ipxact:name>bspCpu</ipxact:name>
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<ipxact:displayName>BSP CPU</ipxact:displayName>
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<ipxact:value>false</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="componentDefinition" type="string">
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<ipxact:name>componentDefinition</ipxact:name>
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<ipxact:displayName>Component definition</ipxact:displayName>
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<ipxact:value><componentDefinition>
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<boundary>
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<interfaces>
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<interface>
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<name>clk</name>
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<type>clock</type>
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<isStart>false</isStart>
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<ports>
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<port>
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<name>clk</name>
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<role>clk</role>
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<direction>Input</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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</ports>
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<assignments>
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<assignmentValueMap/>
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</assignments>
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<parameters>
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<parameterValueMap>
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<entry>
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<key>clockRate</key>
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<value>0</value>
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</entry>
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<entry>
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<key>externallyDriven</key>
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<value>false</value>
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</entry>
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<entry>
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<key>ptfSchematicName</key>
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</entry>
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</parameterValueMap>
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</parameters>
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</interface>
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<interface>
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<name>reset</name>
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<type>reset</type>
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<isStart>false</isStart>
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<ports>
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<port>
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<name>reset_n</name>
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<role>reset_n</role>
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<direction>Input</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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</ports>
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<assignments>
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<assignmentValueMap/>
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</assignments>
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<parameters>
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<parameterValueMap>
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<entry>
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<key>associatedClock</key>
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<value>clk</value>
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</entry>
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<entry>
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<key>synchronousEdges</key>
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<value>DEASSERT</value>
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</entry>
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</parameterValueMap>
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</parameters>
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</interface>
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<interface>
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<name>s1</name>
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<type>avalon</type>
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<isStart>false</isStart>
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<ports>
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<port>
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<name>address</name>
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<role>address</role>
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<direction>Input</direction>
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<width>2</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC_VECTOR</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>write_n</name>
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<role>write_n</role>
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<direction>Input</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>writedata</name>
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<role>writedata</role>
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<direction>Input</direction>
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<width>32</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC_VECTOR</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>chipselect</name>
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<role>chipselect</role>
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<direction>Input</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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|
<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>readdata</name>
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<role>readdata</role>
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<direction>Output</direction>
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<width>32</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC_VECTOR</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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</ports>
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<assignments>
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<assignmentValueMap>
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<entry>
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<key>embeddedsw.configuration.isFlash</key>
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<value>0</value>
|
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</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
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<value>0</value>
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|
</entry>
|
|
<entry>
|
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<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
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|
</entry>
|
|
<entry>
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<key>embeddedsw.configuration.isPrintableDevice</key>
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<value>0</value>
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|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
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<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
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<value>0</value>
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|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
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|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
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|
<value>8</value>
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|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
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<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>export</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>irq</name>
|
|
<type>interrupt</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>irq</name>
|
|
<role>irq</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.dts.irq.tx_type</key>
|
|
<value>RISING_EDGE</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
<value>button_pio.s1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedReceiverOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToReceiver</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_avalon_pio</className>
|
|
<version>19.2.3</version>
|
|
<displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>DEVICE_FAMILY</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_FAMILY</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue>0</parameterDefaultValue>
|
|
<parameterName>clockRate</parameterName>
|
|
<parameterType>java.lang.Long</parameterType>
|
|
<systemInfoArgs>clk</systemInfoArgs>
|
|
<systemInfotype>CLOCK_RATE</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>clk</key>
|
|
<value>
|
|
<connectionPointName>clk</connectionPointName>
|
|
<suppliedSystemInfos/>
|
|
<consumedSystemInfos>
|
|
<entry>
|
|
<key>CLOCK_RATE</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
</consumedSystemInfos>
|
|
</value>
|
|
</entry>
|
|
<entry>
|
|
<key>s1</key>
|
|
<value>
|
|
<connectionPointName>s1</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
<value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
<value>32</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuHashInfo" type="string">
|
|
<ipxact:name>cpuHashInfo</ipxact:name>
|
|
<ipxact:displayName>CPU Hash Info</ipxact:displayName>
|
|
<ipxact:value><cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuInfo" type="string">
|
|
<ipxact:name>cpuInfo</ipxact:name>
|
|
<ipxact:displayName>Cpu Info</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="defaultBoundary" type="string">
|
|
<ipxact:name>defaultBoundary</ipxact:name>
|
|
<ipxact:displayName>Default boundary</ipxact:displayName>
|
|
<ipxact:value><boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s1</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<role>write_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<role>chipselect</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
<cmsisInfo>
|
|
<cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt;
|
|
&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt;
|
|
&lt;peripherals&gt;
|
|
&lt;peripheral&gt;
|
|
&lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt;
|
|
&lt;addressBlock&gt;
|
|
&lt;offset&gt;0x0&lt;/offset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;usage&gt;registers&lt;/usage&gt;
|
|
&lt;/addressBlock&gt;
|
|
&lt;registers&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;DATA&lt;/name&gt;
|
|
&lt;displayName&gt;Data&lt;/displayName&gt;
|
|
&lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;data&lt;/name&gt;
|
|
&lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;DIRECTION&lt;/name&gt;
|
|
&lt;displayName&gt;Direction&lt;/displayName&gt;
|
|
&lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;direction&lt;/name&gt;
|
|
&lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;IRQ_MASK&lt;/name&gt;
|
|
&lt;displayName&gt;Interrupt mask&lt;/displayName&gt;
|
|
&lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x8&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt;
|
|
&lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;EDGE_CAP&lt;/name&gt;
|
|
&lt;displayName&gt;Edge capture&lt;/displayName&gt;
|
|
&lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0xc&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt;
|
|
&lt;description&gt;Edge detection for each input port.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;SET_BIT&lt;/name&gt;
|
|
&lt;displayName&gt;Outset&lt;/displayName&gt;
|
|
&lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x10&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;outset&lt;/name&gt;
|
|
&lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;CLEAR_BITS&lt;/name&gt;
|
|
&lt;displayName&gt;Outclear&lt;/displayName&gt;
|
|
&lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x14&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;outclear&lt;/name&gt;
|
|
&lt;description&gt;Specifies which output bit to clear.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;/registers&gt;
|
|
&lt;/peripheral&gt;
|
|
&lt;/peripherals&gt;
|
|
&lt;/device&gt; </cmsisSrcFileContents>
|
|
<addressGroup></addressGroup>
|
|
<cmsisVars/>
|
|
</cmsisInfo>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>export</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>irq</name>
|
|
<type>interrupt</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>irq</name>
|
|
<role>irq</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.dts.irq.tx_type</key>
|
|
<value>RISING_EDGE</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
<value>button_pio.s1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedReceiverOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToReceiver</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="generationInfoDefinition" type="string">
|
|
<ipxact:name>generationInfoDefinition</ipxact:name>
|
|
<ipxact:displayName>Generation Behavior</ipxact:displayName>
|
|
<ipxact:value><generationInfoDefinition>
|
|
<hdlLibraryName>button_pio</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>button_pio</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>button_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>button_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>button_pio</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>button_pio</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hdlParameters" type="string">
|
|
<ipxact:name>hdlParameters</ipxact:name>
|
|
<ipxact:displayName>HDL Parameters</ipxact:displayName>
|
|
<ipxact:value><hdlParameterDescriptorDefinitionList/></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hlsFile" type="string">
|
|
<ipxact:name>hlsFile</ipxact:name>
|
|
<ipxact:displayName>HLS file</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="liveModuleName" type="string">
|
|
<ipxact:name>liveModuleName</ipxact:name>
|
|
<ipxact:displayName>Live Module Name</ipxact:displayName>
|
|
<ipxact:value>altera_avalon_pio_inst</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="logicalView" type="string">
|
|
<ipxact:name>logicalView</ipxact:name>
|
|
<ipxact:displayName>Logical view</ipxact:displayName>
|
|
<ipxact:value>ip/peripheral_subsys/button_pio.ip</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="moduleAssignmentDefinition" type="string">
|
|
<ipxact:name>moduleAssignmentDefinition</ipxact:name>
|
|
<ipxact:displayName>Module Assignments</ipxact:displayName>
|
|
<ipxact:value><assignmentDefinition>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.CAPTURE</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DATA_WIDTH</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.EDGE_TYPE</key>
|
|
<value>FALLING</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.FREQ</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_IN</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_OUT</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_TRI</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.IRQ_TYPE</key>
|
|
<value>EDGE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.RESET_VALUE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.compatible</key>
|
|
<value>altr,pio-1.0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.group</key>
|
|
<value>gpio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.name</key>
|
|
<value>pio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,gpio-bank-width</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,interrupt-type</key>
|
|
<value>2</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,interrupt_type</key>
|
|
<value>2</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.edge_type</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.level_trigger</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.resetvalue</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.vendor</key>
|
|
<value>altr</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignmentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="svInterfaceDefinition" type="string">
|
|
<ipxact:name>svInterfaceDefinition</ipxact:name>
|
|
<ipxact:displayName>SystemVerilog Interface definition</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="transformParameters" type="string">
|
|
<ipxact:name>transformParameters</ipxact:name>
|
|
<ipxact:displayName>Transform Parameters</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
</ipxact:parameters>
|
|
</altera:altera_module_parameters>
|
|
<altera:altera_ecc_parameter_mappings altera:parentModule=""></altera:altera_ecc_parameter_mappings>
|
|
</altera:module>
|
|
<altera:module altera:enabled="true" altera:auto_export="false">
|
|
<altera:entity_info>
|
|
<ipxact:vendor>Altera Corporation</ipxact:vendor>
|
|
<ipxact:library>dipsw_pio</ipxact:library>
|
|
<ipxact:name>altera_generic_component</ipxact:name>
|
|
<ipxact:version>1.0</ipxact:version>
|
|
</altera:entity_info>
|
|
<altera:altera_module_parameters>
|
|
<ipxact:parameters>
|
|
<ipxact:parameter parameterId="bspCpu" type="bit">
|
|
<ipxact:name>bspCpu</ipxact:name>
|
|
<ipxact:displayName>BSP CPU</ipxact:displayName>
|
|
<ipxact:value>false</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="componentDefinition" type="string">
|
|
<ipxact:name>componentDefinition</ipxact:name>
|
|
<ipxact:displayName>Component definition</ipxact:displayName>
|
|
<ipxact:value><componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s1</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<role>write_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<role>chipselect</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>export</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>irq</name>
|
|
<type>interrupt</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>irq</name>
|
|
<role>irq</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.dts.irq.tx_type</key>
|
|
<value>RISING_EDGE</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
<value>dipsw_pio.s1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedReceiverOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToReceiver</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_avalon_pio</className>
|
|
<version>19.2.3</version>
|
|
<displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>DEVICE_FAMILY</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_FAMILY</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue>0</parameterDefaultValue>
|
|
<parameterName>clockRate</parameterName>
|
|
<parameterType>java.lang.Long</parameterType>
|
|
<systemInfoArgs>clk</systemInfoArgs>
|
|
<systemInfotype>CLOCK_RATE</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>clk</key>
|
|
<value>
|
|
<connectionPointName>clk</connectionPointName>
|
|
<suppliedSystemInfos/>
|
|
<consumedSystemInfos>
|
|
<entry>
|
|
<key>CLOCK_RATE</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
</consumedSystemInfos>
|
|
</value>
|
|
</entry>
|
|
<entry>
|
|
<key>s1</key>
|
|
<value>
|
|
<connectionPointName>s1</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
<value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
<value>32</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuHashInfo" type="string">
|
|
<ipxact:name>cpuHashInfo</ipxact:name>
|
|
<ipxact:displayName>CPU Hash Info</ipxact:displayName>
|
|
<ipxact:value><cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuInfo" type="string">
|
|
<ipxact:name>cpuInfo</ipxact:name>
|
|
<ipxact:displayName>Cpu Info</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="defaultBoundary" type="string">
|
|
<ipxact:name>defaultBoundary</ipxact:name>
|
|
<ipxact:displayName>Default boundary</ipxact:displayName>
|
|
<ipxact:value><boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s1</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<role>write_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<role>chipselect</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
<cmsisInfo>
|
|
<cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt;
|
|
&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt;
|
|
&lt;peripherals&gt;
|
|
&lt;peripheral&gt;
|
|
&lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt;
|
|
&lt;addressBlock&gt;
|
|
&lt;offset&gt;0x0&lt;/offset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;usage&gt;registers&lt;/usage&gt;
|
|
&lt;/addressBlock&gt;
|
|
&lt;registers&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;DATA&lt;/name&gt;
|
|
&lt;displayName&gt;Data&lt;/displayName&gt;
|
|
&lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;data&lt;/name&gt;
|
|
&lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;DIRECTION&lt;/name&gt;
|
|
&lt;displayName&gt;Direction&lt;/displayName&gt;
|
|
&lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;direction&lt;/name&gt;
|
|
&lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;IRQ_MASK&lt;/name&gt;
|
|
&lt;displayName&gt;Interrupt mask&lt;/displayName&gt;
|
|
&lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x8&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt;
|
|
&lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;EDGE_CAP&lt;/name&gt;
|
|
&lt;displayName&gt;Edge capture&lt;/displayName&gt;
|
|
&lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0xc&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt;
|
|
&lt;description&gt;Edge detection for each input port.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;SET_BIT&lt;/name&gt;
|
|
&lt;displayName&gt;Outset&lt;/displayName&gt;
|
|
&lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x10&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;outset&lt;/name&gt;
|
|
&lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;CLEAR_BITS&lt;/name&gt;
|
|
&lt;displayName&gt;Outclear&lt;/displayName&gt;
|
|
&lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x14&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;outclear&lt;/name&gt;
|
|
&lt;description&gt;Specifies which output bit to clear.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;/registers&gt;
|
|
&lt;/peripheral&gt;
|
|
&lt;/peripherals&gt;
|
|
&lt;/device&gt; </cmsisSrcFileContents>
|
|
<addressGroup></addressGroup>
|
|
<cmsisVars/>
|
|
</cmsisInfo>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>export</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>irq</name>
|
|
<type>interrupt</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>irq</name>
|
|
<role>irq</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.dts.irq.tx_type</key>
|
|
<value>RISING_EDGE</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
<value>dipsw_pio.s1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedReceiverOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToReceiver</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="generationInfoDefinition" type="string">
|
|
<ipxact:name>generationInfoDefinition</ipxact:name>
|
|
<ipxact:displayName>Generation Behavior</ipxact:displayName>
|
|
<ipxact:value><generationInfoDefinition>
|
|
<hdlLibraryName>dipsw_pio</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>dipsw_pio</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>dipsw_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>dipsw_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>dipsw_pio</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>dipsw_pio</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hdlParameters" type="string">
|
|
<ipxact:name>hdlParameters</ipxact:name>
|
|
<ipxact:displayName>HDL Parameters</ipxact:displayName>
|
|
<ipxact:value><hdlParameterDescriptorDefinitionList/></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hlsFile" type="string">
|
|
<ipxact:name>hlsFile</ipxact:name>
|
|
<ipxact:displayName>HLS file</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="liveModuleName" type="string">
|
|
<ipxact:name>liveModuleName</ipxact:name>
|
|
<ipxact:displayName>Live Module Name</ipxact:displayName>
|
|
<ipxact:value>altera_avalon_pio_inst</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="logicalView" type="string">
|
|
<ipxact:name>logicalView</ipxact:name>
|
|
<ipxact:displayName>Logical view</ipxact:displayName>
|
|
<ipxact:value>ip/peripheral_subsys/dipsw_pio.ip</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="moduleAssignmentDefinition" type="string">
|
|
<ipxact:name>moduleAssignmentDefinition</ipxact:name>
|
|
<ipxact:displayName>Module Assignments</ipxact:displayName>
|
|
<ipxact:value><assignmentDefinition>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.CAPTURE</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DATA_WIDTH</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.EDGE_TYPE</key>
|
|
<value>FALLING</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.FREQ</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_IN</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_OUT</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_TRI</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.IRQ_TYPE</key>
|
|
<value>EDGE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.RESET_VALUE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.compatible</key>
|
|
<value>altr,pio-1.0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.group</key>
|
|
<value>gpio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.name</key>
|
|
<value>pio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,gpio-bank-width</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,interrupt-type</key>
|
|
<value>2</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,interrupt_type</key>
|
|
<value>2</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.edge_type</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.level_trigger</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.resetvalue</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.vendor</key>
|
|
<value>altr</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignmentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="svInterfaceDefinition" type="string">
|
|
<ipxact:name>svInterfaceDefinition</ipxact:name>
|
|
<ipxact:displayName>SystemVerilog Interface definition</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="transformParameters" type="string">
|
|
<ipxact:name>transformParameters</ipxact:name>
|
|
<ipxact:displayName>Transform Parameters</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
</ipxact:parameters>
|
|
</altera:altera_module_parameters>
|
|
<altera:altera_ecc_parameter_mappings altera:parentModule=""></altera:altera_ecc_parameter_mappings>
|
|
</altera:module>
|
|
<altera:module altera:enabled="true" altera:auto_export="false">
|
|
<altera:entity_info>
|
|
<ipxact:vendor>Altera Corporation</ipxact:vendor>
|
|
<ipxact:library>led_pio</ipxact:library>
|
|
<ipxact:name>altera_generic_component</ipxact:name>
|
|
<ipxact:version>1.0</ipxact:version>
|
|
</altera:entity_info>
|
|
<altera:altera_module_parameters>
|
|
<ipxact:parameters>
|
|
<ipxact:parameter parameterId="bspCpu" type="bit">
|
|
<ipxact:name>bspCpu</ipxact:name>
|
|
<ipxact:displayName>BSP CPU</ipxact:displayName>
|
|
<ipxact:value>false</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="componentDefinition" type="string">
|
|
<ipxact:name>componentDefinition</ipxact:name>
|
|
<ipxact:displayName>Component definition</ipxact:displayName>
|
|
<ipxact:value><componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s1</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<role>write_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<role>chipselect</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>in_port</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>out_port</name>
|
|
<role>out_port</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_avalon_pio</className>
|
|
<version>19.2.3</version>
|
|
<displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>DEVICE_FAMILY</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_FAMILY</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue>0</parameterDefaultValue>
|
|
<parameterName>clockRate</parameterName>
|
|
<parameterType>java.lang.Long</parameterType>
|
|
<systemInfoArgs>clk</systemInfoArgs>
|
|
<systemInfotype>CLOCK_RATE</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>clk</key>
|
|
<value>
|
|
<connectionPointName>clk</connectionPointName>
|
|
<suppliedSystemInfos/>
|
|
<consumedSystemInfos>
|
|
<entry>
|
|
<key>CLOCK_RATE</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
</consumedSystemInfos>
|
|
</value>
|
|
</entry>
|
|
<entry>
|
|
<key>s1</key>
|
|
<value>
|
|
<connectionPointName>s1</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
<value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
<value>32</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuHashInfo" type="string">
|
|
<ipxact:name>cpuHashInfo</ipxact:name>
|
|
<ipxact:displayName>CPU Hash Info</ipxact:displayName>
|
|
<ipxact:value><cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuInfo" type="string">
|
|
<ipxact:name>cpuInfo</ipxact:name>
|
|
<ipxact:displayName>Cpu Info</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="defaultBoundary" type="string">
|
|
<ipxact:name>defaultBoundary</ipxact:name>
|
|
<ipxact:displayName>Default boundary</ipxact:displayName>
|
|
<ipxact:value><boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s1</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>write_n</name>
|
|
<role>write_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>chipselect</name>
|
|
<role>chipselect</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>NATIVE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>4</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
<cmsisInfo>
|
|
<cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt;
|
|
&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt;
|
|
&lt;peripherals&gt;
|
|
&lt;peripheral&gt;
|
|
&lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt;
|
|
&lt;addressBlock&gt;
|
|
&lt;offset&gt;0x0&lt;/offset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;usage&gt;registers&lt;/usage&gt;
|
|
&lt;/addressBlock&gt;
|
|
&lt;registers&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;DATA&lt;/name&gt;
|
|
&lt;displayName&gt;Data&lt;/displayName&gt;
|
|
&lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;data&lt;/name&gt;
|
|
&lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;DIRECTION&lt;/name&gt;
|
|
&lt;displayName&gt;Direction&lt;/displayName&gt;
|
|
&lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;direction&lt;/name&gt;
|
|
&lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;IRQ_MASK&lt;/name&gt;
|
|
&lt;displayName&gt;Interrupt mask&lt;/displayName&gt;
|
|
&lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x8&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt;
|
|
&lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;EDGE_CAP&lt;/name&gt;
|
|
&lt;displayName&gt;Edge capture&lt;/displayName&gt;
|
|
&lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0xc&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt;
|
|
&lt;description&gt;Edge detection for each input port.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-write&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;SET_BIT&lt;/name&gt;
|
|
&lt;displayName&gt;Outset&lt;/displayName&gt;
|
|
&lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x10&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;outset&lt;/name&gt;
|
|
&lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;CLEAR_BITS&lt;/name&gt;
|
|
&lt;displayName&gt;Outclear&lt;/displayName&gt;
|
|
&lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x14&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;resetValue&gt;0x0&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;outclear&lt;/name&gt;
|
|
&lt;description&gt;Specifies which output bit to clear.&lt;/description&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;write-only&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;/registers&gt;
|
|
&lt;/peripheral&gt;
|
|
&lt;/peripherals&gt;
|
|
&lt;/device&gt; </cmsisSrcFileContents>
|
|
<addressGroup></addressGroup>
|
|
<cmsisVars/>
|
|
</cmsisInfo>
|
|
</interface>
|
|
<interface>
|
|
<name>external_connection</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_port</name>
|
|
<role>in_port</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>out_port</name>
|
|
<role>out_port</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="generationInfoDefinition" type="string">
|
|
<ipxact:name>generationInfoDefinition</ipxact:name>
|
|
<ipxact:displayName>Generation Behavior</ipxact:displayName>
|
|
<ipxact:value><generationInfoDefinition>
|
|
<hdlLibraryName>led_pio</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>led_pio</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>led_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>led_pio</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>led_pio</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>led_pio</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hdlParameters" type="string">
|
|
<ipxact:name>hdlParameters</ipxact:name>
|
|
<ipxact:displayName>HDL Parameters</ipxact:displayName>
|
|
<ipxact:value><hdlParameterDescriptorDefinitionList/></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hlsFile" type="string">
|
|
<ipxact:name>hlsFile</ipxact:name>
|
|
<ipxact:displayName>HLS file</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="liveModuleName" type="string">
|
|
<ipxact:name>liveModuleName</ipxact:name>
|
|
<ipxact:displayName>Live Module Name</ipxact:displayName>
|
|
<ipxact:value>altera_avalon_pio_inst</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="logicalView" type="string">
|
|
<ipxact:name>logicalView</ipxact:name>
|
|
<ipxact:displayName>Logical view</ipxact:displayName>
|
|
<ipxact:value>ip/peripheral_subsys/led_pio.ip</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="moduleAssignmentDefinition" type="string">
|
|
<ipxact:name>moduleAssignmentDefinition</ipxact:name>
|
|
<ipxact:displayName>Module Assignments</ipxact:displayName>
|
|
<ipxact:value><assignmentDefinition>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.CAPTURE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DATA_WIDTH</key>
|
|
<value>3</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.EDGE_TYPE</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.FREQ</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_IN</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_OUT</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.HAS_TRI</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.IRQ_TYPE</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.RESET_VALUE</key>
|
|
<value>7</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.compatible</key>
|
|
<value>altr,pio-1.0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.group</key>
|
|
<value>gpio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.name</key>
|
|
<value>pio</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.altr,gpio-bank-width</key>
|
|
<value>3</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.resetvalue</key>
|
|
<value>7</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.vendor</key>
|
|
<value>altr</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignmentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="svInterfaceDefinition" type="string">
|
|
<ipxact:name>svInterfaceDefinition</ipxact:name>
|
|
<ipxact:displayName>SystemVerilog Interface definition</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="transformParameters" type="string">
|
|
<ipxact:name>transformParameters</ipxact:name>
|
|
<ipxact:displayName>Transform Parameters</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
</ipxact:parameters>
|
|
</altera:altera_module_parameters>
|
|
<altera:altera_ecc_parameter_mappings altera:parentModule=""></altera:altera_ecc_parameter_mappings>
|
|
</altera:module>
|
|
<altera:module altera:enabled="true" altera:auto_export="false">
|
|
<altera:entity_info>
|
|
<ipxact:vendor>Altera Corporation</ipxact:vendor>
|
|
<ipxact:library>pb_cpu_0</ipxact:library>
|
|
<ipxact:name>altera_generic_component</ipxact:name>
|
|
<ipxact:version>1.0</ipxact:version>
|
|
</altera:entity_info>
|
|
<altera:altera_module_parameters>
|
|
<ipxact:parameters>
|
|
<ipxact:parameter parameterId="bspCpu" type="bit">
|
|
<ipxact:name>bspCpu</ipxact:name>
|
|
<ipxact:displayName>BSP CPU</ipxact:displayName>
|
|
<ipxact:value>false</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="componentDefinition" type="string">
|
|
<ipxact:name>componentDefinition</ipxact:name>
|
|
<ipxact:displayName>Component definition</ipxact:displayName>
|
|
<ipxact:value><componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s0</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>s0_waitrequest</name>
|
|
<role>waitrequest</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_readdatavalid</name>
|
|
<role>readdatavalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_burstcount</name>
|
|
<role>burstcount</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>17</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_write</name>
|
|
<role>write</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_read</name>
|
|
<role>read</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_byteenable</name>
|
|
<role>byteenable</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_debugaccess</name>
|
|
<role>debugaccess</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>DYNAMIC</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>131072</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>SYMBOLS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
<value>pb_cpu_0.m0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>m0</name>
|
|
<type>avalon</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>m0_waitrequest</name>
|
|
<role>waitrequest</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_readdatavalid</name>
|
|
<role>readdatavalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_burstcount</name>
|
|
<role>burstcount</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_address</name>
|
|
<role>address</role>
|
|
<direction>Output</direction>
|
|
<width>17</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_write</name>
|
|
<role>write</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_read</name>
|
|
<role>read</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_byteenable</name>
|
|
<role>byteenable</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_debugaccess</name>
|
|
<role>debugaccess</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>adaptsTo</key>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>SYMBOLS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dBSBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>doStreamReads</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>doStreamWrites</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isAsynchronous</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isReadable</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isWriteable</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maxAddressWidth</key>
|
|
<value>32</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optimizedReadsWithBE</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_avalon_mm_bridge</className>
|
|
<version>20.1.0</version>
|
|
<displayName>Avalon Memory Mapped Pipeline Bridge Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue>10</parameterDefaultValue>
|
|
<parameterName>SYSINFO_ADDR_WIDTH</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<systemInfoArgs>m0</systemInfoArgs>
|
|
<systemInfotype>ADDRESS_WIDTH</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>m0</key>
|
|
<value>
|
|
<connectionPointName>m0</connectionPointName>
|
|
<suppliedSystemInfos/>
|
|
<consumedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>17</value>
|
|
</entry>
|
|
</consumedSystemInfos>
|
|
</value>
|
|
</entry>
|
|
<entry>
|
|
<key>s0</key>
|
|
<value>
|
|
<connectionPointName>s0</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuHashInfo" type="string">
|
|
<ipxact:name>cpuHashInfo</ipxact:name>
|
|
<ipxact:displayName>CPU Hash Info</ipxact:displayName>
|
|
<ipxact:value><cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuInfo" type="string">
|
|
<ipxact:name>cpuInfo</ipxact:name>
|
|
<ipxact:displayName>Cpu Info</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="defaultBoundary" type="string">
|
|
<ipxact:name>defaultBoundary</ipxact:name>
|
|
<ipxact:displayName>Default boundary</ipxact:displayName>
|
|
<ipxact:value><boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>s0</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>s0_waitrequest</name>
|
|
<role>waitrequest</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_readdatavalid</name>
|
|
<role>readdatavalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_burstcount</name>
|
|
<role>burstcount</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>17</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_write</name>
|
|
<role>write</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_read</name>
|
|
<role>read</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_byteenable</name>
|
|
<role>byteenable</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_debugaccess</name>
|
|
<role>debugaccess</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>DYNAMIC</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>131072</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>SYMBOLS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
<value>pb_cpu_0.m0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>m0</name>
|
|
<type>avalon</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>m0_waitrequest</name>
|
|
<role>waitrequest</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_readdatavalid</name>
|
|
<role>readdatavalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_burstcount</name>
|
|
<role>burstcount</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_writedata</name>
|
|
<role>writedata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_address</name>
|
|
<role>address</role>
|
|
<direction>Output</direction>
|
|
<width>17</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_write</name>
|
|
<role>write</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_read</name>
|
|
<role>read</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_byteenable</name>
|
|
<role>byteenable</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>m0_debugaccess</name>
|
|
<role>debugaccess</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>adaptsTo</key>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>SYMBOLS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dBSBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>doStreamReads</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>doStreamWrites</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isAsynchronous</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isReadable</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isWriteable</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maxAddressWidth</key>
|
|
<value>32</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="generationInfoDefinition" type="string">
|
|
<ipxact:name>generationInfoDefinition</ipxact:name>
|
|
<ipxact:displayName>Generation Behavior</ipxact:displayName>
|
|
<ipxact:value><generationInfoDefinition>
|
|
<hdlLibraryName>pb_cpu_0</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hdlParameters" type="string">
|
|
<ipxact:name>hdlParameters</ipxact:name>
|
|
<ipxact:displayName>HDL Parameters</ipxact:displayName>
|
|
<ipxact:value><hdlParameterDescriptorDefinitionList>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>Bridge data width</description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>DATA_WIDTH</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>32</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>Symbol (byte) width</description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>SYMBOL_WIDTH</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>8</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>HDL_ADDR_WIDTH</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>17</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>Bridge burstcount width</description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>BURSTCOUNT_WIDTH</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>1</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>When enabled, the command (or response) networks are pipelined, potentially increasing the frequency at the expense of increase logic and latency.</description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>PIPELINE_COMMAND</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>1</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>When enabled, the command (or response) networks are pipelined, potentially increasing the frequency at the expense of increase logic and latency.</description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>PIPELINE_RESPONSE</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>1</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>0 means allows asynchronous resets, 1 means internal reset synchronization </description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>SYNC_RESET</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>0</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<description>0 means writeresponsvalid is disabled, 1 means writeresponsevalid is enabled </description>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>USE_WRITERESPONSE</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>0</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>S0_WAITREQUEST_ALLOWANCE</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>0</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
<hdlParameterDescriptorDefinition>
|
|
<enabled>true</enabled>
|
|
<exported>false</exported>
|
|
<parameterHdlType>INTEGER</parameterHdlType>
|
|
<parameterName>M0_WAITREQUEST_ALLOWANCE</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<parameterValue>0</parameterValue>
|
|
</hdlParameterDescriptorDefinition>
|
|
</hdlParameterDescriptorDefinitionList></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hlsFile" type="string">
|
|
<ipxact:name>hlsFile</ipxact:name>
|
|
<ipxact:displayName>HLS file</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="liveModuleName" type="string">
|
|
<ipxact:name>liveModuleName</ipxact:name>
|
|
<ipxact:displayName>Live Module Name</ipxact:displayName>
|
|
<ipxact:value>altera_avalon_mm_bridge_inst</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="logicalView" type="string">
|
|
<ipxact:name>logicalView</ipxact:name>
|
|
<ipxact:displayName>Logical view</ipxact:displayName>
|
|
<ipxact:value>ip/peripheral_subsys/pb_cpu_0.ip</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="moduleAssignmentDefinition" type="string">
|
|
<ipxact:name>moduleAssignmentDefinition</ipxact:name>
|
|
<ipxact:displayName>Module Assignments</ipxact:displayName>
|
|
<ipxact:value><assignmentDefinition>
|
|
<assignmentValueMap/>
|
|
</assignmentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="svInterfaceDefinition" type="string">
|
|
<ipxact:name>svInterfaceDefinition</ipxact:name>
|
|
<ipxact:displayName>SystemVerilog Interface definition</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="transformParameters" type="string">
|
|
<ipxact:name>transformParameters</ipxact:name>
|
|
<ipxact:displayName>Transform Parameters</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
</ipxact:parameters>
|
|
</altera:altera_module_parameters>
|
|
<altera:altera_ecc_parameter_mappings altera:parentModule=""></altera:altera_ecc_parameter_mappings>
|
|
</altera:module>
|
|
<altera:module altera:enabled="true" altera:auto_export="false">
|
|
<altera:entity_info>
|
|
<ipxact:vendor>Altera Corporation</ipxact:vendor>
|
|
<ipxact:library>periph_clk</ipxact:library>
|
|
<ipxact:name>altera_generic_component</ipxact:name>
|
|
<ipxact:version>1.0</ipxact:version>
|
|
</altera:entity_info>
|
|
<altera:altera_module_parameters>
|
|
<ipxact:parameters>
|
|
<ipxact:parameter parameterId="bspCpu" type="bit">
|
|
<ipxact:name>bspCpu</ipxact:name>
|
|
<ipxact:displayName>BSP CPU</ipxact:displayName>
|
|
<ipxact:value>false</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="componentDefinition" type="string">
|
|
<ipxact:name>componentDefinition</ipxact:name>
|
|
<ipxact:displayName>Component definition</ipxact:displayName>
|
|
<ipxact:value><componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>in_clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>out_clk</name>
|
|
<type>clock</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>out_clk</name>
|
|
<role>clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedDirectClock</key>
|
|
<value>in_clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
<entry>
|
|
<key>clockRateKnown</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_clock_bridge</className>
|
|
<version>19.2.0</version>
|
|
<displayName>Clock Bridge Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue>0</parameterDefaultValue>
|
|
<parameterName>DERIVED_CLOCK_RATE</parameterName>
|
|
<parameterType>java.lang.Long</parameterType>
|
|
<systemInfoArgs>in_clk</systemInfoArgs>
|
|
<systemInfotype>CLOCK_RATE</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>in_clk</key>
|
|
<value>
|
|
<connectionPointName>in_clk</connectionPointName>
|
|
<suppliedSystemInfos/>
|
|
<consumedSystemInfos>
|
|
<entry>
|
|
<key>CLOCK_RATE</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
</consumedSystemInfos>
|
|
</value>
|
|
</entry>
|
|
<entry>
|
|
<key>out_clk</key>
|
|
<value>
|
|
<connectionPointName>out_clk</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>CLOCK_RATE</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuHashInfo" type="string">
|
|
<ipxact:name>cpuHashInfo</ipxact:name>
|
|
<ipxact:displayName>CPU Hash Info</ipxact:displayName>
|
|
<ipxact:value><cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuInfo" type="string">
|
|
<ipxact:name>cpuInfo</ipxact:name>
|
|
<ipxact:displayName>Cpu Info</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="defaultBoundary" type="string">
|
|
<ipxact:name>defaultBoundary</ipxact:name>
|
|
<ipxact:displayName>Default boundary</ipxact:displayName>
|
|
<ipxact:value><boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>in_clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>out_clk</name>
|
|
<type>clock</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>out_clk</name>
|
|
<role>clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedDirectClock</key>
|
|
<value>in_clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>100000000</value>
|
|
</entry>
|
|
<entry>
|
|
<key>clockRateKnown</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="generationInfoDefinition" type="string">
|
|
<ipxact:name>generationInfoDefinition</ipxact:name>
|
|
<ipxact:displayName>Generation Behavior</ipxact:displayName>
|
|
<ipxact:value><generationInfoDefinition>
|
|
<hdlLibraryName>periph_clk</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>periph_clk</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>periph_clk</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>periph_clk</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>periph_clk</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>periph_clk</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hdlParameters" type="string">
|
|
<ipxact:name>hdlParameters</ipxact:name>
|
|
<ipxact:displayName>HDL Parameters</ipxact:displayName>
|
|
<ipxact:value><hdlParameterDescriptorDefinitionList/></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hlsFile" type="string">
|
|
<ipxact:name>hlsFile</ipxact:name>
|
|
<ipxact:displayName>HLS file</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="liveModuleName" type="string">
|
|
<ipxact:name>liveModuleName</ipxact:name>
|
|
<ipxact:displayName>Live Module Name</ipxact:displayName>
|
|
<ipxact:value>altera_clock_bridge_inst</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="logicalView" type="string">
|
|
<ipxact:name>logicalView</ipxact:name>
|
|
<ipxact:displayName>Logical view</ipxact:displayName>
|
|
<ipxact:value>ip/peripheral_subsys/periph_clk.ip</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="moduleAssignmentDefinition" type="string">
|
|
<ipxact:name>moduleAssignmentDefinition</ipxact:name>
|
|
<ipxact:displayName>Module Assignments</ipxact:displayName>
|
|
<ipxact:value><assignmentDefinition>
|
|
<assignmentValueMap/>
|
|
</assignmentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="svInterfaceDefinition" type="string">
|
|
<ipxact:name>svInterfaceDefinition</ipxact:name>
|
|
<ipxact:displayName>SystemVerilog Interface definition</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="transformParameters" type="string">
|
|
<ipxact:name>transformParameters</ipxact:name>
|
|
<ipxact:displayName>Transform Parameters</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
</ipxact:parameters>
|
|
</altera:altera_module_parameters>
|
|
<altera:altera_ecc_parameter_mappings altera:parentModule=""></altera:altera_ecc_parameter_mappings>
|
|
</altera:module>
|
|
<altera:module altera:enabled="true" altera:auto_export="false">
|
|
<altera:entity_info>
|
|
<ipxact:vendor>Altera Corporation</ipxact:vendor>
|
|
<ipxact:library>periph_rst_in</ipxact:library>
|
|
<ipxact:name>altera_generic_component</ipxact:name>
|
|
<ipxact:version>1.0</ipxact:version>
|
|
</altera:entity_info>
|
|
<altera:altera_module_parameters>
|
|
<ipxact:parameters>
|
|
<ipxact:parameter parameterId="bspCpu" type="bit">
|
|
<ipxact:name>bspCpu</ipxact:name>
|
|
<ipxact:displayName>BSP CPU</ipxact:displayName>
|
|
<ipxact:value>false</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="componentDefinition" type="string">
|
|
<ipxact:name>componentDefinition</ipxact:name>
|
|
<ipxact:displayName>Component definition</ipxact:displayName>
|
|
<ipxact:value><componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>in_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>out_reset</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>out_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_reset_bridge</className>
|
|
<version>19.2.0</version>
|
|
<displayName>Reset Bridge Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue>-1</parameterDefaultValue>
|
|
<parameterName>AUTO_CLK_CLOCK_RATE</parameterName>
|
|
<parameterType>java.lang.Long</parameterType>
|
|
<systemInfoArgs>clk</systemInfoArgs>
|
|
<systemInfotype>CLOCK_RATE</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos/>
|
|
</systemInfos>
|
|
</componentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuHashInfo" type="string">
|
|
<ipxact:name>cpuHashInfo</ipxact:name>
|
|
<ipxact:displayName>CPU Hash Info</ipxact:displayName>
|
|
<ipxact:value><cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuInfo" type="string">
|
|
<ipxact:name>cpuInfo</ipxact:name>
|
|
<ipxact:displayName>Cpu Info</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="defaultBoundary" type="string">
|
|
<ipxact:name>defaultBoundary</ipxact:name>
|
|
<ipxact:displayName>Default boundary</ipxact:displayName>
|
|
<ipxact:value><boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>in_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>in_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>out_reset</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>out_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>in_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="generationInfoDefinition" type="string">
|
|
<ipxact:name>generationInfoDefinition</ipxact:name>
|
|
<ipxact:displayName>Generation Behavior</ipxact:displayName>
|
|
<ipxact:value><generationInfoDefinition>
|
|
<hdlLibraryName>periph_rst_in</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>periph_rst_in</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>periph_rst_in</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>periph_rst_in</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>periph_rst_in</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>periph_rst_in</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hdlParameters" type="string">
|
|
<ipxact:name>hdlParameters</ipxact:name>
|
|
<ipxact:displayName>HDL Parameters</ipxact:displayName>
|
|
<ipxact:value><hdlParameterDescriptorDefinitionList/></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hlsFile" type="string">
|
|
<ipxact:name>hlsFile</ipxact:name>
|
|
<ipxact:displayName>HLS file</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="liveModuleName" type="string">
|
|
<ipxact:name>liveModuleName</ipxact:name>
|
|
<ipxact:displayName>Live Module Name</ipxact:displayName>
|
|
<ipxact:value>altera_reset_bridge_inst</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="logicalView" type="string">
|
|
<ipxact:name>logicalView</ipxact:name>
|
|
<ipxact:displayName>Logical view</ipxact:displayName>
|
|
<ipxact:value>ip/peripheral_subsys/periph_rst_in.ip</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="moduleAssignmentDefinition" type="string">
|
|
<ipxact:name>moduleAssignmentDefinition</ipxact:name>
|
|
<ipxact:displayName>Module Assignments</ipxact:displayName>
|
|
<ipxact:value><assignmentDefinition>
|
|
<assignmentValueMap/>
|
|
</assignmentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="svInterfaceDefinition" type="string">
|
|
<ipxact:name>svInterfaceDefinition</ipxact:name>
|
|
<ipxact:displayName>SystemVerilog Interface definition</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="transformParameters" type="string">
|
|
<ipxact:name>transformParameters</ipxact:name>
|
|
<ipxact:displayName>Transform Parameters</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
</ipxact:parameters>
|
|
</altera:altera_module_parameters>
|
|
<altera:altera_ecc_parameter_mappings altera:parentModule=""></altera:altera_ecc_parameter_mappings>
|
|
</altera:module>
|
|
<altera:module altera:enabled="true" altera:auto_export="false">
|
|
<altera:entity_info>
|
|
<ipxact:vendor>Altera Corporation</ipxact:vendor>
|
|
<ipxact:library>sysid</ipxact:library>
|
|
<ipxact:name>altera_generic_component</ipxact:name>
|
|
<ipxact:version>1.0</ipxact:version>
|
|
</altera:entity_info>
|
|
<altera:altera_module_parameters>
|
|
<ipxact:parameters>
|
|
<ipxact:parameter parameterId="bspCpu" type="bit">
|
|
<ipxact:name>bspCpu</ipxact:name>
|
|
<ipxact:displayName>BSP CPU</ipxact:displayName>
|
|
<ipxact:value>false</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="componentDefinition" type="string">
|
|
<ipxact:name>componentDefinition</ipxact:name>
|
|
<ipxact:displayName>Component definition</ipxact:displayName>
|
|
<ipxact:value><componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clock</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>control_slave</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>DYNAMIC</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>altera_avalon_sysid_qsys</className>
|
|
<version>19.1.7</version>
|
|
<displayName>System ID Peripheral Intel FPGA IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue>0</parameterDefaultValue>
|
|
<parameterName>TIMESTAMP</parameterName>
|
|
<parameterType>java.lang.Integer</parameterType>
|
|
<systemInfotype>GENERATION_ID</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>control_slave</key>
|
|
<value>
|
|
<connectionPointName>control_slave</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
<value>&lt;address-map&gt;&lt;slave name='control_slave' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>3</value>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
<value>32</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuHashInfo" type="string">
|
|
<ipxact:name>cpuHashInfo</ipxact:name>
|
|
<ipxact:displayName>CPU Hash Info</ipxact:displayName>
|
|
<ipxact:value><cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuInfo" type="string">
|
|
<ipxact:name>cpuInfo</ipxact:name>
|
|
<ipxact:displayName>Cpu Info</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="defaultBoundary" type="string">
|
|
<ipxact:name>defaultBoundary</ipxact:name>
|
|
<ipxact:displayName>Default boundary</ipxact:displayName>
|
|
<ipxact:value><boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>clock</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>DEASSERT</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>control_slave</name>
|
|
<type>avalon</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>readdata</name>
|
|
<role>readdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>address</name>
|
|
<role>address</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isFlash</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isMemoryDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isNonVolatileStorage</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.isPrintableDevice</key>
|
|
<value>0</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>addressAlignment</key>
|
|
<value>DYNAMIC</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressGroup</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressSpan</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>alwaysBurstMaxBurst</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>clk</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bitsPerSymbol</key>
|
|
<value>8</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgedAddressOffset</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>burstOnBurstBoundariesOnly</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>burstcountUnits</key>
|
|
<value>WORDS</value>
|
|
</entry>
|
|
<entry>
|
|
<key>constantBurstBehavior</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>explicitAddressSpan</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>holdTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>interleaveBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isBigEndian</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isFlash</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isMemoryDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isNonVolatileStorage</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>linewrapBursts</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingReadTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumPendingWriteTransactions</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumReadLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumResponseLatency</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>minimumUninterruptedRunLength</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>printableDevice</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitStates</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readWaitTime</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerIncomingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>registerOutgoingSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>setupTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>timingUnits</key>
|
|
<value>Cycles</value>
|
|
</entry>
|
|
<entry>
|
|
<key>transparentBridge</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestAllowance</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>waitrequestTimeout</key>
|
|
<value>1024</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wellBehavedWaitrequest</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeLatency</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitStates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeWaitTime</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
<cmsisInfo>
|
|
<cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt;
|
|
&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt;
|
|
&lt;peripherals&gt;
|
|
&lt;peripheral&gt;
|
|
&lt;name&gt;altera_avalon_sysid&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt;
|
|
&lt;addressBlock&gt;
|
|
&lt;offset&gt;0x0&lt;/offset&gt;
|
|
&lt;size&gt;8&lt;/size&gt;
|
|
&lt;usage&gt;registers&lt;/usage&gt;
|
|
&lt;/addressBlock&gt;
|
|
&lt;registers&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;ID&lt;/name&gt;
|
|
&lt;displayName&gt;System ID&lt;/displayName&gt;
|
|
&lt;description&gt;A unique 32-bit value that is based on the contents of the QSys system. The id is similar to a check-sum value; QSys systems with different components, different configuration options, or both, produce different id values.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-only&lt;/access&gt;
|
|
&lt;resetValue&gt;${sysid_id_value}&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;id&lt;/name&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-only&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;register&gt;
|
|
&lt;name&gt;TIMESTAMP&lt;/name&gt;
|
|
&lt;displayName&gt;Time stamp&lt;/displayName&gt;
|
|
&lt;description&gt;A unique 32-bit value that is based on the system generation time. The value is equivalent to the number of seconds after Jan. 1, 1970.&lt;/description&gt;
|
|
&lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
|
|
&lt;size&gt;32&lt;/size&gt;
|
|
&lt;access&gt;read-only&lt;/access&gt;
|
|
&lt;resetValue&gt;${sysid_timestamp_value}&lt;/resetValue&gt;
|
|
&lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
|
|
&lt;fields&gt;
|
|
&lt;field&gt;&lt;name&gt;timestamp&lt;/name&gt;
|
|
&lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
|
|
&lt;bitWidth&gt;32&lt;/bitWidth&gt;
|
|
&lt;access&gt;read-only&lt;/access&gt;
|
|
&lt;/field&gt;
|
|
&lt;/fields&gt;
|
|
&lt;/register&gt;
|
|
&lt;/registers&gt;
|
|
&lt;/peripheral&gt;
|
|
&lt;/peripherals&gt;
|
|
&lt;/device&gt; </cmsisSrcFileContents>
|
|
<addressGroup></addressGroup>
|
|
<cmsisVars>
|
|
<entry>
|
|
<key>sysid_timestamp_value</key>
|
|
<value>0x0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>sysid_id_value</key>
|
|
<value>0xacd5cafe</value>
|
|
</entry>
|
|
</cmsisVars>
|
|
</cmsisInfo>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="generationInfoDefinition" type="string">
|
|
<ipxact:name>generationInfoDefinition</ipxact:name>
|
|
<ipxact:displayName>Generation Behavior</ipxact:displayName>
|
|
<ipxact:value><generationInfoDefinition>
|
|
<hdlLibraryName>sysid</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>QUARTUS_SYNTH</fileSetName>
|
|
<fileSetFixedName>sysid</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VERILOG</fileSetName>
|
|
<fileSetFixedName>sysid</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>SIM_VHDL</fileSetName>
|
|
<fileSetFixedName>sysid</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC</fileSetName>
|
|
<fileSetFixedName>sysid</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>CDC_VHDL</fileSetName>
|
|
<fileSetFixedName>sysid</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hdlParameters" type="string">
|
|
<ipxact:name>hdlParameters</ipxact:name>
|
|
<ipxact:displayName>HDL Parameters</ipxact:displayName>
|
|
<ipxact:value><hdlParameterDescriptorDefinitionList/></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hlsFile" type="string">
|
|
<ipxact:name>hlsFile</ipxact:name>
|
|
<ipxact:displayName>HLS file</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="liveModuleName" type="string">
|
|
<ipxact:name>liveModuleName</ipxact:name>
|
|
<ipxact:displayName>Live Module Name</ipxact:displayName>
|
|
<ipxact:value>altera_avalon_sysid_qsys_inst</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="logicalView" type="string">
|
|
<ipxact:name>logicalView</ipxact:name>
|
|
<ipxact:displayName>Logical view</ipxact:displayName>
|
|
<ipxact:value>ip/peripheral_subsys/sysid.ip</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="moduleAssignmentDefinition" type="string">
|
|
<ipxact:name>moduleAssignmentDefinition</ipxact:name>
|
|
<ipxact:displayName>Module Assignments</ipxact:displayName>
|
|
<ipxact:value><assignmentDefinition>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.ID</key>
|
|
<value>-1395275010</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.TIMESTAMP</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.compatible</key>
|
|
<value>altr,sysid-1.0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.group</key>
|
|
<value>sysid</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.name</key>
|
|
<value>sysid</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.id</key>
|
|
<value>-1395275010</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.params.timestamp</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.dts.vendor</key>
|
|
<value>altr</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignmentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="svInterfaceDefinition" type="string">
|
|
<ipxact:name>svInterfaceDefinition</ipxact:name>
|
|
<ipxact:displayName>SystemVerilog Interface definition</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="transformParameters" type="string">
|
|
<ipxact:name>transformParameters</ipxact:name>
|
|
<ipxact:displayName>Transform Parameters</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
</ipxact:parameters>
|
|
</altera:altera_module_parameters>
|
|
<altera:altera_ecc_parameter_mappings altera:parentModule=""></altera:altera_ecc_parameter_mappings>
|
|
</altera:module>
|
|
</altera:modules>
|
|
<altera:connections>
|
|
<altera:connection altera:kind="avalon" altera:version="26.1" altera:start="pb_cpu_0.m0" altera:end="sysid.control_slave">
|
|
<altera:connection_parameter altera:parameter_name="arbitrationPriority" altera:parameter_value="1"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="baseAddress" altera:parameter_value="0x00010000"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="defaultConnection" altera:parameter_value="false"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="domainAlias" altera:parameter_value=""></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.burstAdapterImplementation" altera:parameter_value="GENERIC_CONVERTER"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.clockCrossingAdapter" altera:parameter_value="AUTO"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableAllPipelines" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableEccProtection" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableInstrumentation" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableOutOfOrderSupport" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.fifoDepth" altera:parameter_value="8"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.insertDefaultSlave" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.interconnectResetSource" altera:parameter_value="DEFAULT"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.interconnectType" altera:parameter_value="STANDARD"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.maxAdditionalLatency" altera:parameter_value="1"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.optimizeRdFifoSize" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.piplineType" altera:parameter_value="PIPELINE_STAGE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.responseFifoType" altera:parameter_value="REGISTER_BASED"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.splitCommandsFor4KBoundary" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.syncResets" altera:parameter_value="TRUE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.widthAdapterImplementation" altera:parameter_value="GENERIC_CONVERTER"></altera:connection_parameter>
|
|
</altera:connection>
|
|
<altera:connection altera:kind="avalon" altera:version="26.1" altera:start="pb_cpu_0.m0" altera:end="led_pio.s1">
|
|
<altera:connection_parameter altera:parameter_name="arbitrationPriority" altera:parameter_value="1"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="baseAddress" altera:parameter_value="0x00010080"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="defaultConnection" altera:parameter_value="false"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="domainAlias" altera:parameter_value=""></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.burstAdapterImplementation" altera:parameter_value="GENERIC_CONVERTER"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.clockCrossingAdapter" altera:parameter_value="AUTO"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableAllPipelines" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableEccProtection" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableInstrumentation" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableOutOfOrderSupport" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.fifoDepth" altera:parameter_value="8"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.insertDefaultSlave" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.interconnectResetSource" altera:parameter_value="DEFAULT"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.interconnectType" altera:parameter_value="STANDARD"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.maxAdditionalLatency" altera:parameter_value="1"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.optimizeRdFifoSize" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.piplineType" altera:parameter_value="PIPELINE_STAGE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.responseFifoType" altera:parameter_value="REGISTER_BASED"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.splitCommandsFor4KBoundary" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.syncResets" altera:parameter_value="TRUE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.widthAdapterImplementation" altera:parameter_value="GENERIC_CONVERTER"></altera:connection_parameter>
|
|
</altera:connection>
|
|
<altera:connection altera:kind="avalon" altera:version="26.1" altera:start="pb_cpu_0.m0" altera:end="dipsw_pio.s1">
|
|
<altera:connection_parameter altera:parameter_name="arbitrationPriority" altera:parameter_value="1"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="baseAddress" altera:parameter_value="0x00010070"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="defaultConnection" altera:parameter_value="false"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="domainAlias" altera:parameter_value=""></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.burstAdapterImplementation" altera:parameter_value="GENERIC_CONVERTER"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.clockCrossingAdapter" altera:parameter_value="AUTO"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableAllPipelines" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableEccProtection" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableInstrumentation" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableOutOfOrderSupport" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.fifoDepth" altera:parameter_value="8"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.insertDefaultSlave" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.interconnectResetSource" altera:parameter_value="DEFAULT"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.interconnectType" altera:parameter_value="STANDARD"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.maxAdditionalLatency" altera:parameter_value="1"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.optimizeRdFifoSize" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.piplineType" altera:parameter_value="PIPELINE_STAGE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.responseFifoType" altera:parameter_value="REGISTER_BASED"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.splitCommandsFor4KBoundary" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.syncResets" altera:parameter_value="TRUE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.widthAdapterImplementation" altera:parameter_value="GENERIC_CONVERTER"></altera:connection_parameter>
|
|
</altera:connection>
|
|
<altera:connection altera:kind="avalon" altera:version="26.1" altera:start="pb_cpu_0.m0" altera:end="button_pio.s1">
|
|
<altera:connection_parameter altera:parameter_name="arbitrationPriority" altera:parameter_value="1"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="baseAddress" altera:parameter_value="0x00010060"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="defaultConnection" altera:parameter_value="false"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="domainAlias" altera:parameter_value=""></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.burstAdapterImplementation" altera:parameter_value="GENERIC_CONVERTER"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.clockCrossingAdapter" altera:parameter_value="AUTO"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableAllPipelines" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableEccProtection" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableInstrumentation" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.enableOutOfOrderSupport" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.fifoDepth" altera:parameter_value="8"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.insertDefaultSlave" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.interconnectResetSource" altera:parameter_value="DEFAULT"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.interconnectType" altera:parameter_value="STANDARD"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.maxAdditionalLatency" altera:parameter_value="1"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.optimizeRdFifoSize" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.piplineType" altera:parameter_value="PIPELINE_STAGE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.responseFifoType" altera:parameter_value="REGISTER_BASED"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.splitCommandsFor4KBoundary" altera:parameter_value="FALSE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.syncResets" altera:parameter_value="TRUE"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="qsys_mm.widthAdapterImplementation" altera:parameter_value="GENERIC_CONVERTER"></altera:connection_parameter>
|
|
</altera:connection>
|
|
<altera:connection altera:kind="clock" altera:version="26.1" altera:start="periph_clk.out_clk" altera:end="sysid.clk"></altera:connection>
|
|
<altera:connection altera:kind="clock" altera:version="26.1" altera:start="periph_clk.out_clk" altera:end="pb_cpu_0.clk"></altera:connection>
|
|
<altera:connection altera:kind="clock" altera:version="26.1" altera:start="periph_clk.out_clk" altera:end="led_pio.clk"></altera:connection>
|
|
<altera:connection altera:kind="clock" altera:version="26.1" altera:start="periph_clk.out_clk" altera:end="dipsw_pio.clk"></altera:connection>
|
|
<altera:connection altera:kind="clock" altera:version="26.1" altera:start="periph_clk.out_clk" altera:end="button_pio.clk"></altera:connection>
|
|
<altera:connection altera:kind="reset" altera:version="26.1" altera:start="periph_rst_in.out_reset" altera:end="sysid.reset"></altera:connection>
|
|
<altera:connection altera:kind="reset" altera:version="26.1" altera:start="periph_rst_in.out_reset" altera:end="led_pio.reset"></altera:connection>
|
|
<altera:connection altera:kind="reset" altera:version="26.1" altera:start="periph_rst_in.out_reset" altera:end="dipsw_pio.reset"></altera:connection>
|
|
<altera:connection altera:kind="reset" altera:version="26.1" altera:start="periph_rst_in.out_reset" altera:end="button_pio.reset"></altera:connection>
|
|
<altera:connection altera:kind="reset" altera:version="26.1" altera:start="periph_rst_in.out_reset" altera:end="pb_cpu_0.reset"></altera:connection>
|
|
</altera:connections>
|
|
<altera:interconnect_requirements></altera:interconnect_requirements>
|
|
<altera:wire_level_connections></altera:wire_level_connections>
|
|
<altera:hdl_parameters></altera:hdl_parameters>
|
|
<altera:hdl_parameter_mappings></altera:hdl_parameter_mappings>
|
|
<altera:preserved_ports_for_debug></altera:preserved_ports_for_debug>
|
|
<altera:altera_group_hierarchy_contents></altera:altera_group_hierarchy_contents>
|
|
<altera:altera_interface_boundary>
|
|
<altera:interface_mapping altera:name="button_pio_external_connection" altera:internal="button_pio.external_connection" altera:type="conduit" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="button_pio_irq" altera:internal="button_pio.irq" altera:type="interrupt" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="clk" altera:internal="periph_clk.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="dipsw_pio_external_connection" altera:internal="dipsw_pio.external_connection" altera:type="conduit" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="dipsw_pio_irq" altera:internal="dipsw_pio.irq" altera:type="interrupt" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="led_pio_external_connection" altera:internal="led_pio.external_connection" altera:type="conduit" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="pb_cpu_0_s0" altera:internal="pb_cpu_0.s0" altera:type="avalon" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="reset" altera:internal="periph_rst_in.in_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
|
|
</altera:altera_interface_boundary>
|
|
<ipxact:components>
|
|
<ipxact:component>
|
|
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
|
<ipxact:library>addressMap</ipxact:library>
|
|
<ipxact:name>addressMap</ipxact:name>
|
|
<ipxact:version>1.0</ipxact:version>
|
|
<ipxact:busInterfaces>
|
|
<ipxact:busInterface>
|
|
<ipxact:name>sysid.control_slave</ipxact:name>
|
|
<ipxact:busType vendor="intel" library="intel" name="avalon" version="26.1"></ipxact:busType>
|
|
</ipxact:busInterface>
|
|
<ipxact:busInterface>
|
|
<ipxact:name>led_pio.s1</ipxact:name>
|
|
<ipxact:busType vendor="intel" library="intel" name="avalon" version="26.1"></ipxact:busType>
|
|
</ipxact:busInterface>
|
|
<ipxact:busInterface>
|
|
<ipxact:name>dipsw_pio.s1</ipxact:name>
|
|
<ipxact:busType vendor="intel" library="intel" name="avalon" version="26.1"></ipxact:busType>
|
|
</ipxact:busInterface>
|
|
<ipxact:busInterface>
|
|
<ipxact:name>button_pio.s1</ipxact:name>
|
|
<ipxact:busType vendor="intel" library="intel" name="avalon" version="26.1"></ipxact:busType>
|
|
</ipxact:busInterface>
|
|
<ipxact:busInterface>
|
|
<ipxact:name>pb_cpu_0.m0</ipxact:name>
|
|
<ipxact:busType vendor="intel" library="intel" name="avalon" version="26.1"></ipxact:busType>
|
|
<ipxact:master>
|
|
<ipxact:addressSpaceRef addressSpaceRef="pb_cpu_0.m0">
|
|
<ipxact:baseAddress>0x0001_0000</ipxact:baseAddress>
|
|
</ipxact:addressSpaceRef>
|
|
</ipxact:master>
|
|
</ipxact:busInterface>
|
|
</ipxact:busInterfaces>
|
|
<ipxact:addressSpaces>
|
|
<ipxact:addressSpace>
|
|
<ipxact:name>pb_cpu_0.m0</ipxact:name>
|
|
<ipxact:segments>
|
|
<ipxact:segment>
|
|
<ipxact:name>sysid.control_slave</ipxact:name>
|
|
<ipxact:addressOffset>0x0001_0000</ipxact:addressOffset>
|
|
<ipxact:range>0x0000_0008</ipxact:range>
|
|
</ipxact:segment>
|
|
<ipxact:segment>
|
|
<ipxact:name>led_pio.s1</ipxact:name>
|
|
<ipxact:addressOffset>0x0001_0080</ipxact:addressOffset>
|
|
<ipxact:range>0x0000_0010</ipxact:range>
|
|
</ipxact:segment>
|
|
<ipxact:segment>
|
|
<ipxact:name>dipsw_pio.s1</ipxact:name>
|
|
<ipxact:addressOffset>0x0001_0070</ipxact:addressOffset>
|
|
<ipxact:range>0x0000_0010</ipxact:range>
|
|
</ipxact:segment>
|
|
<ipxact:segment>
|
|
<ipxact:name>button_pio.s1</ipxact:name>
|
|
<ipxact:addressOffset>0x0001_0060</ipxact:addressOffset>
|
|
<ipxact:range>0x0000_0010</ipxact:range>
|
|
</ipxact:segment>
|
|
</ipxact:segments>
|
|
</ipxact:addressSpace>
|
|
</ipxact:addressSpaces>
|
|
<ipxact:memoryMaps></ipxact:memoryMaps>
|
|
</ipxact:component>
|
|
</ipxact:components>
|
|
<altera:altera_has_warnings>false</altera:altera_has_warnings>
|
|
<altera:altera_has_errors>false</altera:altera_has_errors>
|
|
</ipxact:vendorExtensions>
|
|
</ipxact:design> |