Altera Corporation
peripheral_subsys
peripheral_subsys
1.0
$${FILENAME}
$${FILENAME}
1.0
Systems
QsysPro
board
Board
default
bonusData
bonusData
bonusData
{
element button_pio
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element dipsw_pio
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element led_pio
{
datum _sortIndex
{
value = "5";
type = "int";
}
}
element pb_cpu_0
{
datum _sortIndex
{
value = "6";
type = "int";
}
}
element periph_clk
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element periph_rst_in
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element sysid
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
}
cpuInfo
cpuInfo
designId
designId
device
Device
A5EB013BB23BE4SCS
deviceFamily
Device family
Agilex 5
deviceSpeedGrade
Device Speed Grade
4
dflBitArray
dflBitArray
fabricMode
fabricMode
QSYS
generateLegacySim
generateLegacySim
false
generationId
Generation Id
0
globalResetBus
Global reset
false
hdlLanguage
hdlLanguage
VERILOG
hideFromIPCatalog
Hide from IP Catalog
false
lockedInterfaceDefinition
lockedInterfaceDefinition
sopcBorderPoints
Use SOPC Builder port naming
false
systemHash
systemHash
0
systemInfos
systemInfos
<systemInfosDefinition>
<connPtSystemInfos>
<entry>
<key>clk</key>
<value>
<connectionPointName>clk</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_DOMAIN</key>
<value>1</value>
</entry>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
<entry>
<key>RESET_DOMAIN</key>
<value>1</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
<entry>
<key>pb_cpu_0_s0</key>
<value>
<connectionPointName>pb_cpu_0_s0</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CPU_INFO_ID</key>
<value></value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value><address-map><slave name='sysid.control_slave' start='0x10000' end='0x10008' datawidth='32' /><slave name='button_pio.s1' start='0x10060' end='0x10070' datawidth='32' /><slave name='dipsw_pio.s1' start='0x10070' end='0x10080' datawidth='32' /><slave name='led_pio.s1' start='0x10080' end='0x10090' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
<value>32</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
</connPtSystemInfos>
</systemInfosDefinition>
systemScripts
systemScripts
testBenchDutName
Use Test Bench Naming Pattern
timeStamp
timeStamp
0
useTestBenchNamingPattern
Use Test Bench Naming Pattern
false
Altera Corporation
button_pio
altera_generic_component
1.0
bspCpu
BSP CPU
false
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>write_n</name>
<role>write_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>chipselect</name>
<role>chipselect</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>NATIVE</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>4</value>
</entry>
<entry>
<key>addressUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>external_connection</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_port</name>
<role>export</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>irq</name>
<type>interrupt</type>
<isStart>false</isStart>
<ports>
<port>
<name>irq</name>
<role>irq</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.dts.irq.tx_type</key>
<value>RISING_EDGE</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
<value>button_pio.s1</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bridgedReceiverOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToReceiver</key>
</entry>
<entry>
<key>irqScheme</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>altera_avalon_pio</className>
<version>19.2.3</version>
<displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>DEVICE_FAMILY</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>0</parameterDefaultValue>
<parameterName>clockRate</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>clk</key>
<value>
<connectionPointName>clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>s1</key>
<value>
<connectionPointName>s1</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
<value>32</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>write_n</name>
<role>write_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>chipselect</name>
<role>chipselect</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>NATIVE</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>4</value>
</entry>
<entry>
<key>addressUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
<cmsisInfo>
<cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
<peripherals>
<peripheral>
<name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>32</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DATA</name>
<displayName>Data</displayName>
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>data</name>
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIRECTION</name>
<displayName>Direction</displayName>
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>direction</name>
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IRQ_MASK</name>
<displayName>Interrupt mask</displayName>
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>interruptmask</name>
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EDGE_CAP</name>
<displayName>Edge capture</displayName>
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>edgecapture</name>
<description>Edge detection for each input port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SET_BIT</name>
<displayName>Outset</displayName>
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outset</name>
<description>Specifies which bit of the output port to set.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CLEAR_BITS</name>
<displayName>Outclear</displayName>
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outclear</name>
<description>Specifies which output bit to clear.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device> </cmsisSrcFileContents>
<addressGroup></addressGroup>
<cmsisVars/>
</cmsisInfo>
</interface>
<interface>
<name>external_connection</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_port</name>
<role>export</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>irq</name>
<type>interrupt</type>
<isStart>false</isStart>
<ports>
<port>
<name>irq</name>
<role>irq</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.dts.irq.tx_type</key>
<value>RISING_EDGE</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
<value>button_pio.s1</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bridgedReceiverOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToReceiver</key>
</entry>
<entry>
<key>irqScheme</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>button_pio</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>QUARTUS_SYNTH</fileSetName>
<fileSetFixedName>button_pio</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VERILOG</fileSetName>
<fileSetFixedName>button_pio</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VHDL</fileSetName>
<fileSetFixedName>button_pio</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC</fileSetName>
<fileSetFixedName>button_pio</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC_VHDL</fileSetName>
<fileSetFixedName>button_pio</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
altera_avalon_pio_inst
logicalView
Logical view
ip/peripheral_subsys/button_pio.ip
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap>
<entry>
<key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.CAPTURE</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DATA_WIDTH</key>
<value>4</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.EDGE_TYPE</key>
<value>FALLING</value>
</entry>
<entry>
<key>embeddedsw.CMacro.FREQ</key>
<value>100000000</value>
</entry>
<entry>
<key>embeddedsw.CMacro.HAS_IN</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.CMacro.HAS_OUT</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.HAS_TRI</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.IRQ_TYPE</key>
<value>EDGE</value>
</entry>
<entry>
<key>embeddedsw.CMacro.RESET_VALUE</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.dts.compatible</key>
<value>altr,pio-1.0</value>
</entry>
<entry>
<key>embeddedsw.dts.group</key>
<value>gpio</value>
</entry>
<entry>
<key>embeddedsw.dts.name</key>
<value>pio</value>
</entry>
<entry>
<key>embeddedsw.dts.params.altr,gpio-bank-width</key>
<value>4</value>
</entry>
<entry>
<key>embeddedsw.dts.params.altr,interrupt-type</key>
<value>2</value>
</entry>
<entry>
<key>embeddedsw.dts.params.altr,interrupt_type</key>
<value>2</value>
</entry>
<entry>
<key>embeddedsw.dts.params.edge_type</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.dts.params.level_trigger</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.dts.params.resetvalue</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.dts.vendor</key>
<value>altr</value>
</entry>
</assignmentValueMap>
</assignmentDefinition>
svInterfaceDefinition
SystemVerilog Interface definition
transformParameters
Transform Parameters
Altera Corporation
dipsw_pio
altera_generic_component
1.0
bspCpu
BSP CPU
false
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>write_n</name>
<role>write_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>chipselect</name>
<role>chipselect</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>NATIVE</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>4</value>
</entry>
<entry>
<key>addressUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>external_connection</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_port</name>
<role>export</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>irq</name>
<type>interrupt</type>
<isStart>false</isStart>
<ports>
<port>
<name>irq</name>
<role>irq</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.dts.irq.tx_type</key>
<value>RISING_EDGE</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
<value>dipsw_pio.s1</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bridgedReceiverOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToReceiver</key>
</entry>
<entry>
<key>irqScheme</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>altera_avalon_pio</className>
<version>19.2.3</version>
<displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>DEVICE_FAMILY</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>0</parameterDefaultValue>
<parameterName>clockRate</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>clk</key>
<value>
<connectionPointName>clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>s1</key>
<value>
<connectionPointName>s1</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
<value>32</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>write_n</name>
<role>write_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>chipselect</name>
<role>chipselect</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>NATIVE</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>4</value>
</entry>
<entry>
<key>addressUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
<cmsisInfo>
<cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
<peripherals>
<peripheral>
<name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>32</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DATA</name>
<displayName>Data</displayName>
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>data</name>
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIRECTION</name>
<displayName>Direction</displayName>
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>direction</name>
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IRQ_MASK</name>
<displayName>Interrupt mask</displayName>
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>interruptmask</name>
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EDGE_CAP</name>
<displayName>Edge capture</displayName>
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>edgecapture</name>
<description>Edge detection for each input port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SET_BIT</name>
<displayName>Outset</displayName>
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outset</name>
<description>Specifies which bit of the output port to set.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CLEAR_BITS</name>
<displayName>Outclear</displayName>
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outclear</name>
<description>Specifies which output bit to clear.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device> </cmsisSrcFileContents>
<addressGroup></addressGroup>
<cmsisVars/>
</cmsisInfo>
</interface>
<interface>
<name>external_connection</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_port</name>
<role>export</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>irq</name>
<type>interrupt</type>
<isStart>false</isStart>
<ports>
<port>
<name>irq</name>
<role>irq</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.dts.irq.tx_type</key>
<value>RISING_EDGE</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
<value>dipsw_pio.s1</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bridgedReceiverOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToReceiver</key>
</entry>
<entry>
<key>irqScheme</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>dipsw_pio</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>QUARTUS_SYNTH</fileSetName>
<fileSetFixedName>dipsw_pio</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VERILOG</fileSetName>
<fileSetFixedName>dipsw_pio</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VHDL</fileSetName>
<fileSetFixedName>dipsw_pio</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC</fileSetName>
<fileSetFixedName>dipsw_pio</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC_VHDL</fileSetName>
<fileSetFixedName>dipsw_pio</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
altera_avalon_pio_inst
logicalView
Logical view
ip/peripheral_subsys/dipsw_pio.ip
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap>
<entry>
<key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.CAPTURE</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DATA_WIDTH</key>
<value>4</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.EDGE_TYPE</key>
<value>FALLING</value>
</entry>
<entry>
<key>embeddedsw.CMacro.FREQ</key>
<value>100000000</value>
</entry>
<entry>
<key>embeddedsw.CMacro.HAS_IN</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.CMacro.HAS_OUT</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.HAS_TRI</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.IRQ_TYPE</key>
<value>EDGE</value>
</entry>
<entry>
<key>embeddedsw.CMacro.RESET_VALUE</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.dts.compatible</key>
<value>altr,pio-1.0</value>
</entry>
<entry>
<key>embeddedsw.dts.group</key>
<value>gpio</value>
</entry>
<entry>
<key>embeddedsw.dts.name</key>
<value>pio</value>
</entry>
<entry>
<key>embeddedsw.dts.params.altr,gpio-bank-width</key>
<value>4</value>
</entry>
<entry>
<key>embeddedsw.dts.params.altr,interrupt-type</key>
<value>2</value>
</entry>
<entry>
<key>embeddedsw.dts.params.altr,interrupt_type</key>
<value>2</value>
</entry>
<entry>
<key>embeddedsw.dts.params.edge_type</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.dts.params.level_trigger</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.dts.params.resetvalue</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.dts.vendor</key>
<value>altr</value>
</entry>
</assignmentValueMap>
</assignmentDefinition>
svInterfaceDefinition
SystemVerilog Interface definition
transformParameters
Transform Parameters
Altera Corporation
led_pio
altera_generic_component
1.0
bspCpu
BSP CPU
false
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>write_n</name>
<role>write_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>chipselect</name>
<role>chipselect</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>NATIVE</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>4</value>
</entry>
<entry>
<key>addressUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>external_connection</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_port</name>
<role>in_port</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>out_port</name>
<role>out_port</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>altera_avalon_pio</className>
<version>19.2.3</version>
<displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>DEVICE_FAMILY</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>0</parameterDefaultValue>
<parameterName>clockRate</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>clk</key>
<value>
<connectionPointName>clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>s1</key>
<value>
<connectionPointName>s1</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
<value>32</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>write_n</name>
<role>write_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>chipselect</name>
<role>chipselect</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>NATIVE</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>4</value>
</entry>
<entry>
<key>addressUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
<cmsisInfo>
<cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
<peripherals>
<peripheral>
<name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>32</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DATA</name>
<displayName>Data</displayName>
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>data</name>
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIRECTION</name>
<displayName>Direction</displayName>
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>direction</name>
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IRQ_MASK</name>
<displayName>Interrupt mask</displayName>
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>interruptmask</name>
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EDGE_CAP</name>
<displayName>Edge capture</displayName>
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>edgecapture</name>
<description>Edge detection for each input port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SET_BIT</name>
<displayName>Outset</displayName>
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outset</name>
<description>Specifies which bit of the output port to set.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CLEAR_BITS</name>
<displayName>Outclear</displayName>
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outclear</name>
<description>Specifies which output bit to clear.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device> </cmsisSrcFileContents>
<addressGroup></addressGroup>
<cmsisVars/>
</cmsisInfo>
</interface>
<interface>
<name>external_connection</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_port</name>
<role>in_port</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>out_port</name>
<role>out_port</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>led_pio</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>QUARTUS_SYNTH</fileSetName>
<fileSetFixedName>led_pio</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VERILOG</fileSetName>
<fileSetFixedName>led_pio</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VHDL</fileSetName>
<fileSetFixedName>led_pio</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC</fileSetName>
<fileSetFixedName>led_pio</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC_VHDL</fileSetName>
<fileSetFixedName>led_pio</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
altera_avalon_pio_inst
logicalView
Logical view
ip/peripheral_subsys/led_pio.ip
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap>
<entry>
<key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.CAPTURE</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DATA_WIDTH</key>
<value>3</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.EDGE_TYPE</key>
<value>NONE</value>
</entry>
<entry>
<key>embeddedsw.CMacro.FREQ</key>
<value>100000000</value>
</entry>
<entry>
<key>embeddedsw.CMacro.HAS_IN</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.CMacro.HAS_OUT</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.CMacro.HAS_TRI</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.CMacro.IRQ_TYPE</key>
<value>NONE</value>
</entry>
<entry>
<key>embeddedsw.CMacro.RESET_VALUE</key>
<value>7</value>
</entry>
<entry>
<key>embeddedsw.dts.compatible</key>
<value>altr,pio-1.0</value>
</entry>
<entry>
<key>embeddedsw.dts.group</key>
<value>gpio</value>
</entry>
<entry>
<key>embeddedsw.dts.name</key>
<value>pio</value>
</entry>
<entry>
<key>embeddedsw.dts.params.altr,gpio-bank-width</key>
<value>3</value>
</entry>
<entry>
<key>embeddedsw.dts.params.resetvalue</key>
<value>7</value>
</entry>
<entry>
<key>embeddedsw.dts.vendor</key>
<value>altr</value>
</entry>
</assignmentValueMap>
</assignmentDefinition>
svInterfaceDefinition
SystemVerilog Interface definition
transformParameters
Transform Parameters
Altera Corporation
pb_cpu_0
altera_generic_component
1.0
bspCpu
BSP CPU
false
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s0</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>s0_waitrequest</name>
<role>waitrequest</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_readdatavalid</name>
<role>readdatavalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_burstcount</name>
<role>burstcount</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_address</name>
<role>address</role>
<direction>Input</direction>
<width>17</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_write</name>
<role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_read</name>
<role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_byteenable</name>
<role>byteenable</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_debugaccess</name>
<role>debugaccess</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
<value>SYMBOLS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
<value>pb_cpu_0.m0</value>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>1</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>m0</name>
<type>avalon</type>
<isStart>true</isStart>
<ports>
<port>
<name>m0_waitrequest</name>
<role>waitrequest</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_readdata</name>
<role>readdata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_readdatavalid</name>
<role>readdatavalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_burstcount</name>
<role>burstcount</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_writedata</name>
<role>writedata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_address</name>
<role>address</role>
<direction>Output</direction>
<width>17</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_write</name>
<role>write</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_read</name>
<role>read</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_byteenable</name>
<role>byteenable</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_debugaccess</name>
<role>debugaccess</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>adaptsTo</key>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressUnits</key>
<value>SYMBOLS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>dBSBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>doStreamReads</key>
<value>false</value>
</entry>
<entry>
<key>doStreamWrites</key>
<value>false</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isAsynchronous</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isReadable</key>
<value>false</value>
</entry>
<entry>
<key>isWriteable</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maxAddressWidth</key>
<value>32</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>enableConcurrentSubordinateAccess</key>
<value>0</value>
</entry>
<entry>
<key>optimizedReadsWithBE</key>
<value>0</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>altera_avalon_mm_bridge</className>
<version>20.1.0</version>
<displayName>Avalon Memory Mapped Pipeline Bridge Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue>10</parameterDefaultValue>
<parameterName>SYSINFO_ADDR_WIDTH</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfoArgs>m0</systemInfoArgs>
<systemInfotype>ADDRESS_WIDTH</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>m0</key>
<value>
<connectionPointName>m0</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>ADDRESS_WIDTH</key>
<value>17</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>s0</key>
<value>
<connectionPointName>s0</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s0</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>s0_waitrequest</name>
<role>waitrequest</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_readdatavalid</name>
<role>readdatavalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_burstcount</name>
<role>burstcount</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_address</name>
<role>address</role>
<direction>Input</direction>
<width>17</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_write</name>
<role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_read</name>
<role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_byteenable</name>
<role>byteenable</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_debugaccess</name>
<role>debugaccess</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
<value>SYMBOLS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
<value>pb_cpu_0.m0</value>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>1</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>m0</name>
<type>avalon</type>
<isStart>true</isStart>
<ports>
<port>
<name>m0_waitrequest</name>
<role>waitrequest</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_readdata</name>
<role>readdata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_readdatavalid</name>
<role>readdatavalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_burstcount</name>
<role>burstcount</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_writedata</name>
<role>writedata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_address</name>
<role>address</role>
<direction>Output</direction>
<width>17</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_write</name>
<role>write</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_read</name>
<role>read</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_byteenable</name>
<role>byteenable</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>m0_debugaccess</name>
<role>debugaccess</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>adaptsTo</key>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressUnits</key>
<value>SYMBOLS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>dBSBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>doStreamReads</key>
<value>false</value>
</entry>
<entry>
<key>doStreamWrites</key>
<value>false</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isAsynchronous</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isReadable</key>
<value>false</value>
</entry>
<entry>
<key>isWriteable</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maxAddressWidth</key>
<value>32</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>enableConcurrentSubordinateAccess</key>
<value>0</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>pb_cpu_0</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>QUARTUS_SYNTH</fileSetName>
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VERILOG</fileSetName>
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VHDL</fileSetName>
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC</fileSetName>
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC_VHDL</fileSetName>
<fileSetFixedName>pb_cpu_0</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList>
<hdlParameterDescriptorDefinition>
<description>Bridge data width</description>
<enabled>true</enabled>
<exported>false</exported>
<parameterHdlType>INTEGER</parameterHdlType>
<parameterName>DATA_WIDTH</parameterName>
<parameterType>java.lang.Integer</parameterType>
<parameterValue>32</parameterValue>
</hdlParameterDescriptorDefinition>
<hdlParameterDescriptorDefinition>
<description>Symbol (byte) width</description>
<enabled>true</enabled>
<exported>false</exported>
<parameterHdlType>INTEGER</parameterHdlType>
<parameterName>SYMBOL_WIDTH</parameterName>
<parameterType>java.lang.Integer</parameterType>
<parameterValue>8</parameterValue>
</hdlParameterDescriptorDefinition>
<hdlParameterDescriptorDefinition>
<enabled>true</enabled>
<exported>false</exported>
<parameterHdlType>INTEGER</parameterHdlType>
<parameterName>HDL_ADDR_WIDTH</parameterName>
<parameterType>java.lang.Integer</parameterType>
<parameterValue>17</parameterValue>
</hdlParameterDescriptorDefinition>
<hdlParameterDescriptorDefinition>
<description>Bridge burstcount width</description>
<enabled>true</enabled>
<exported>false</exported>
<parameterHdlType>INTEGER</parameterHdlType>
<parameterName>BURSTCOUNT_WIDTH</parameterName>
<parameterType>java.lang.Integer</parameterType>
<parameterValue>1</parameterValue>
</hdlParameterDescriptorDefinition>
<hdlParameterDescriptorDefinition>
<description>When enabled, the command (or response) networks are pipelined, potentially increasing the frequency at the expense of increase logic and latency.</description>
<enabled>true</enabled>
<exported>false</exported>
<parameterHdlType>INTEGER</parameterHdlType>
<parameterName>PIPELINE_COMMAND</parameterName>
<parameterType>java.lang.Integer</parameterType>
<parameterValue>1</parameterValue>
</hdlParameterDescriptorDefinition>
<hdlParameterDescriptorDefinition>
<description>When enabled, the command (or response) networks are pipelined, potentially increasing the frequency at the expense of increase logic and latency.</description>
<enabled>true</enabled>
<exported>false</exported>
<parameterHdlType>INTEGER</parameterHdlType>
<parameterName>PIPELINE_RESPONSE</parameterName>
<parameterType>java.lang.Integer</parameterType>
<parameterValue>1</parameterValue>
</hdlParameterDescriptorDefinition>
<hdlParameterDescriptorDefinition>
<description>0 means allows asynchronous resets, 1 means internal reset synchronization </description>
<enabled>true</enabled>
<exported>false</exported>
<parameterHdlType>INTEGER</parameterHdlType>
<parameterName>SYNC_RESET</parameterName>
<parameterType>java.lang.Integer</parameterType>
<parameterValue>0</parameterValue>
</hdlParameterDescriptorDefinition>
<hdlParameterDescriptorDefinition>
<description>0 means writeresponsvalid is disabled, 1 means writeresponsevalid is enabled </description>
<enabled>true</enabled>
<exported>false</exported>
<parameterHdlType>INTEGER</parameterHdlType>
<parameterName>USE_WRITERESPONSE</parameterName>
<parameterType>java.lang.Integer</parameterType>
<parameterValue>0</parameterValue>
</hdlParameterDescriptorDefinition>
<hdlParameterDescriptorDefinition>
<enabled>true</enabled>
<exported>false</exported>
<parameterHdlType>INTEGER</parameterHdlType>
<parameterName>S0_WAITREQUEST_ALLOWANCE</parameterName>
<parameterType>java.lang.Integer</parameterType>
<parameterValue>0</parameterValue>
</hdlParameterDescriptorDefinition>
<hdlParameterDescriptorDefinition>
<enabled>true</enabled>
<exported>false</exported>
<parameterHdlType>INTEGER</parameterHdlType>
<parameterName>M0_WAITREQUEST_ALLOWANCE</parameterName>
<parameterType>java.lang.Integer</parameterType>
<parameterValue>0</parameterValue>
</hdlParameterDescriptorDefinition>
</hdlParameterDescriptorDefinitionList>
hlsFile
HLS file
liveModuleName
Live Module Name
altera_avalon_mm_bridge_inst
logicalView
Logical view
ip/peripheral_subsys/pb_cpu_0.ip
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>
svInterfaceDefinition
SystemVerilog Interface definition
transformParameters
Transform Parameters
Altera Corporation
periph_clk
altera_generic_component
1.0
bspCpu
BSP CPU
false
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>in_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_clk</name>
<type>clock</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_clk</name>
<role>clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedDirectClock</key>
<value>in_clk</value>
</entry>
<entry>
<key>clockRate</key>
<value>100000000</value>
</entry>
<entry>
<key>clockRateKnown</key>
<value>true</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>altera_clock_bridge</className>
<version>19.2.0</version>
<displayName>Clock Bridge Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue>0</parameterDefaultValue>
<parameterName>DERIVED_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>in_clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>in_clk</key>
<value>
<connectionPointName>in_clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>out_clk</key>
<value>
<connectionPointName>out_clk</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>in_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_clk</name>
<type>clock</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_clk</name>
<role>clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedDirectClock</key>
<value>in_clk</value>
</entry>
<entry>
<key>clockRate</key>
<value>100000000</value>
</entry>
<entry>
<key>clockRateKnown</key>
<value>true</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>periph_clk</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>QUARTUS_SYNTH</fileSetName>
<fileSetFixedName>periph_clk</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VERILOG</fileSetName>
<fileSetFixedName>periph_clk</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VHDL</fileSetName>
<fileSetFixedName>periph_clk</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC</fileSetName>
<fileSetFixedName>periph_clk</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC_VHDL</fileSetName>
<fileSetFixedName>periph_clk</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
altera_clock_bridge_inst
logicalView
Logical view
ip/peripheral_subsys/periph_clk.ip
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>
svInterfaceDefinition
SystemVerilog Interface definition
transformParameters
Transform Parameters
Altera Corporation
periph_rst_in
altera_generic_component
1.0
bspCpu
BSP CPU
false
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>in_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_reset</name>
<type>reset</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_reset_n</name>
<role>reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedDirectReset</key>
<value>in_reset</value>
</entry>
<entry>
<key>associatedResetSinks</key>
<value>in_reset</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>altera_reset_bridge</className>
<version>19.2.0</version>
<displayName>Reset Bridge Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_CLK_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos/>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>in_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_reset</name>
<type>reset</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_reset_n</name>
<role>reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedDirectReset</key>
<value>in_reset</value>
</entry>
<entry>
<key>associatedResetSinks</key>
<value>in_reset</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>periph_rst_in</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>QUARTUS_SYNTH</fileSetName>
<fileSetFixedName>periph_rst_in</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VERILOG</fileSetName>
<fileSetFixedName>periph_rst_in</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VHDL</fileSetName>
<fileSetFixedName>periph_rst_in</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC</fileSetName>
<fileSetFixedName>periph_rst_in</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC_VHDL</fileSetName>
<fileSetFixedName>periph_rst_in</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
altera_reset_bridge_inst
logicalView
Logical view
ip/peripheral_subsys/periph_rst_in.ip
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>
svInterfaceDefinition
SystemVerilog Interface definition
transformParameters
Transform Parameters
Altera Corporation
sysid
altera_generic_component
1.0
bspCpu
BSP CPU
false
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clock</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>control_slave</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>8</value>
</entry>
<entry>
<key>addressUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>altera_avalon_sysid_qsys</className>
<version>19.1.7</version>
<displayName>System ID Peripheral Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue>0</parameterDefaultValue>
<parameterName>TIMESTAMP</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfotype>GENERATION_ID</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>control_slave</key>
<value>
<connectionPointName>control_slave</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value><address-map><slave name='control_slave' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
<value>32</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clock</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>control_slave</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>8</value>
</entry>
<entry>
<key>addressUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
<cmsisInfo>
<cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
<peripherals>
<peripheral>
<name>altera_avalon_sysid</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>8</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ID</name>
<displayName>System ID</displayName>
<description>A unique 32-bit value that is based on the contents of the QSys system. The id is similar to a check-sum value; QSys systems with different components, different configuration options, or both, produce different id values.</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>${sysid_id_value}</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>id</name>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TIMESTAMP</name>
<displayName>Time stamp</displayName>
<description>A unique 32-bit value that is based on the system generation time. The value is equivalent to the number of seconds after Jan. 1, 1970.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>${sysid_timestamp_value}</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>timestamp</name>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device> </cmsisSrcFileContents>
<addressGroup></addressGroup>
<cmsisVars>
<entry>
<key>sysid_timestamp_value</key>
<value>0x0</value>
</entry>
<entry>
<key>sysid_id_value</key>
<value>0xacd5cafe</value>
</entry>
</cmsisVars>
</cmsisInfo>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>sysid</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>QUARTUS_SYNTH</fileSetName>
<fileSetFixedName>sysid</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VERILOG</fileSetName>
<fileSetFixedName>sysid</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>SIM_VHDL</fileSetName>
<fileSetFixedName>sysid</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC</fileSetName>
<fileSetFixedName>sysid</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>CDC_VHDL</fileSetName>
<fileSetFixedName>sysid</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
altera_avalon_sysid_qsys_inst
logicalView
Logical view
ip/peripheral_subsys/sysid.ip
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap>
<entry>
<key>embeddedsw.CMacro.ID</key>
<value>-1395275010</value>
</entry>
<entry>
<key>embeddedsw.CMacro.TIMESTAMP</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.dts.compatible</key>
<value>altr,sysid-1.0</value>
</entry>
<entry>
<key>embeddedsw.dts.group</key>
<value>sysid</value>
</entry>
<entry>
<key>embeddedsw.dts.name</key>
<value>sysid</value>
</entry>
<entry>
<key>embeddedsw.dts.params.id</key>
<value>-1395275010</value>
</entry>
<entry>
<key>embeddedsw.dts.params.timestamp</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.dts.vendor</key>
<value>altr</value>
</entry>
</assignmentValueMap>
</assignmentDefinition>
svInterfaceDefinition
SystemVerilog Interface definition
transformParameters
Transform Parameters
Intel Corporation
addressMap
addressMap
1.0
sysid.control_slave
led_pio.s1
dipsw_pio.s1
button_pio.s1
pb_cpu_0.m0
0x0001_0000
pb_cpu_0.m0
sysid.control_slave
0x0001_0000
0x0000_0008
led_pio.s1
0x0001_0080
0x0000_0010
dipsw_pio.s1
0x0001_0070
0x0000_0010
button_pio.s1
0x0001_0060
0x0000_0010
false
false