thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
7810 lines
409 KiB
XML
Executable File
7810 lines
409 KiB
XML
Executable File
<?xml version="1.0" ?>
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<!--Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.-->
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<ipxact:design xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
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<ipxact:vendor>Altera Corporation</ipxact:vendor>
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<ipxact:library>hps_subsys</ipxact:library>
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<ipxact:name>hps_subsys</ipxact:name>
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<ipxact:version>1.0</ipxact:version>
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<ipxact:componentInstances></ipxact:componentInstances>
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<ipxact:vendorExtensions>
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<altera:catalog_card_info>
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<altera:name>$${FILENAME}</altera:name>
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<altera:displayName>$${FILENAME}</altera:displayName>
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<altera:version>1.0</altera:version>
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<altera:description></altera:description>
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<altera:tags></altera:tags>
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<altera:categories>Systems</altera:categories>
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<altera:tool>QsysPro</altera:tool>
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</altera:catalog_card_info>
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<altera:altera_system_parameters>
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<ipxact:parameters>
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<ipxact:parameter parameterId="board" type="string">
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<ipxact:name>board</ipxact:name>
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<ipxact:displayName>Board</ipxact:displayName>
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<ipxact:value>default</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="bonusData" type="string">
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<ipxact:name>bonusData</ipxact:name>
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<ipxact:displayName>bonusData</ipxact:displayName>
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<ipxact:value>bonusData
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{
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element agilex_hps
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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element emif_hps
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{
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datum _sortIndex
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{
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value = "1";
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type = "int";
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}
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}
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}
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</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="cpuInfo" type="string">
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<ipxact:name>cpuInfo</ipxact:name>
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<ipxact:displayName>cpuInfo</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="designId" type="string">
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<ipxact:name>designId</ipxact:name>
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<ipxact:displayName>designId</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="device" type="string">
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<ipxact:name>device</ipxact:name>
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<ipxact:displayName>Device</ipxact:displayName>
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<ipxact:value>A5EB013BB23BE4SCS</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="deviceFamily" type="string">
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<ipxact:name>deviceFamily</ipxact:name>
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<ipxact:displayName>Device family</ipxact:displayName>
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<ipxact:value>Agilex 5</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
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<ipxact:name>deviceSpeedGrade</ipxact:name>
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<ipxact:displayName>Device Speed Grade</ipxact:displayName>
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<ipxact:value>4</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="dflBitArray" type="string">
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<ipxact:name>dflBitArray</ipxact:name>
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<ipxact:displayName>dflBitArray</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="fabricMode" type="string">
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<ipxact:name>fabricMode</ipxact:name>
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<ipxact:displayName>fabricMode</ipxact:displayName>
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<ipxact:value>QSYS</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="generateLegacySim" type="bit">
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<ipxact:name>generateLegacySim</ipxact:name>
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<ipxact:displayName>generateLegacySim</ipxact:displayName>
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<ipxact:value>false</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="generationId" type="int">
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<ipxact:name>generationId</ipxact:name>
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<ipxact:displayName>Generation Id</ipxact:displayName>
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<ipxact:value>0</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="globalResetBus" type="bit">
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<ipxact:name>globalResetBus</ipxact:name>
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<ipxact:displayName>Global reset</ipxact:displayName>
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<ipxact:value>false</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="hdlLanguage" type="string">
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<ipxact:name>hdlLanguage</ipxact:name>
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<ipxact:displayName>hdlLanguage</ipxact:displayName>
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<ipxact:value>VERILOG</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
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<ipxact:name>hideFromIPCatalog</ipxact:name>
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<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
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<ipxact:value>false</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
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<ipxact:name>lockedInterfaceDefinition</ipxact:name>
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<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="sopcBorderPoints" type="bit">
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<ipxact:name>sopcBorderPoints</ipxact:name>
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<ipxact:displayName>Use SOPC Builder port naming</ipxact:displayName>
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<ipxact:value>false</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="systemHash" type="longint">
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<ipxact:name>systemHash</ipxact:name>
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<ipxact:displayName>systemHash</ipxact:displayName>
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<ipxact:value>0</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="systemInfos" type="string">
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<ipxact:name>systemInfos</ipxact:name>
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<ipxact:displayName>systemInfos</ipxact:displayName>
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<ipxact:value><systemInfosDefinition>
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<connPtSystemInfos>
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<entry>
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<key>f2sdram</key>
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<value>
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<connectionPointName>f2sdram</connectionPointName>
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<suppliedSystemInfos>
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<entry>
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<key>CPU_INFO_ID</key>
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<value></value>
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</entry>
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</suppliedSystemInfos>
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<consumedSystemInfos>
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<entry>
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<key>ADDRESS_MAP</key>
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<value>&lt;address-map&gt;&lt;slave name='agilex_hps.f2sdram' start='0x0' end='0x100000000' datawidth='256' /&gt;&lt;/address-map&gt;</value>
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</entry>
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<entry>
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<key>ADDRESS_WIDTH</key>
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<value>32</value>
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</entry>
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<entry>
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<key>MAX_SLAVE_DATA_WIDTH</key>
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<value>256</value>
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</entry>
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</consumedSystemInfos>
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</value>
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</entry>
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</connPtSystemInfos>
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</systemInfosDefinition></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="systemScripts" type="string">
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<ipxact:name>systemScripts</ipxact:name>
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<ipxact:displayName>systemScripts</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="testBenchDutName" type="string">
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<ipxact:name>testBenchDutName</ipxact:name>
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<ipxact:displayName>Use Test Bench Naming Pattern</ipxact:displayName>
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<ipxact:value></ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="timeStamp" type="longint">
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<ipxact:name>timeStamp</ipxact:name>
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<ipxact:displayName>timeStamp</ipxact:displayName>
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<ipxact:value>0</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="useTestBenchNamingPattern" type="bit">
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<ipxact:name>useTestBenchNamingPattern</ipxact:name>
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<ipxact:displayName>Use Test Bench Naming Pattern</ipxact:displayName>
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<ipxact:value>false</ipxact:value>
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</ipxact:parameter>
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</ipxact:parameters>
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</altera:altera_system_parameters>
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<altera:instance_parameters></altera:instance_parameters>
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<altera:instance_script></altera:instance_script>
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<altera:modules>
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<altera:module altera:enabled="true" altera:auto_export="false">
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<altera:entity_info>
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<ipxact:vendor>Altera Corporation</ipxact:vendor>
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<ipxact:library>agilex_hps</ipxact:library>
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<ipxact:name>altera_generic_component</ipxact:name>
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<ipxact:version>1.0</ipxact:version>
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</altera:entity_info>
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<altera:altera_module_parameters>
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<ipxact:parameters>
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<ipxact:parameter parameterId="bspCpu" type="bit">
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<ipxact:name>bspCpu</ipxact:name>
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<ipxact:displayName>BSP CPU</ipxact:displayName>
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<ipxact:value>true</ipxact:value>
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</ipxact:parameter>
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<ipxact:parameter parameterId="componentDefinition" type="string">
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<ipxact:name>componentDefinition</ipxact:name>
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<ipxact:displayName>Component definition</ipxact:displayName>
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<ipxact:value><componentDefinition>
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<boundary>
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<interfaces>
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<interface>
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<name>h2f_reset</name>
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<type>reset</type>
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<isStart>true</isStart>
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<ports>
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<port>
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<name>h2f_reset_reset</name>
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<role>reset</role>
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<direction>Output</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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</ports>
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<assignments>
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<assignmentValueMap/>
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</assignments>
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<parameters>
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<parameterValueMap>
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<entry>
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<key>associatedClock</key>
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</entry>
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<entry>
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<key>associatedDirectReset</key>
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</entry>
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<entry>
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<key>associatedResetSinks</key>
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<value>none</value>
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</entry>
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<entry>
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<key>synchronousEdges</key>
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<value>NONE</value>
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</entry>
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</parameterValueMap>
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</parameters>
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</interface>
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<interface>
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<name>hps2fpga_axi_clock</name>
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<type>clock</type>
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<isStart>false</isStart>
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<ports>
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<port>
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<name>hps2fpga_axi_clock_clk</name>
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<role>clk</role>
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<direction>Input</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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</ports>
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<assignments>
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<assignmentValueMap/>
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</assignments>
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<parameters>
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<parameterValueMap>
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<entry>
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<key>clockRate</key>
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<value>0</value>
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</entry>
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<entry>
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<key>externallyDriven</key>
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<value>false</value>
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</entry>
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<entry>
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<key>ptfSchematicName</key>
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</entry>
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</parameterValueMap>
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</parameters>
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</interface>
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<interface>
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<name>hps2fpga_axi_reset</name>
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<type>reset</type>
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<isStart>false</isStart>
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<ports>
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<port>
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<name>hps2fpga_axi_reset_reset</name>
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<role>reset</role>
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<direction>Input</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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</ports>
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<assignments>
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<assignmentValueMap/>
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</assignments>
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<parameters>
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<parameterValueMap>
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<entry>
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<key>associatedClock</key>
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</entry>
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<entry>
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<key>synchronousEdges</key>
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<value>NONE</value>
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</entry>
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</parameterValueMap>
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</parameters>
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</interface>
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<interface>
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<name>hps2fpga</name>
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<type>axi4</type>
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<isStart>true</isStart>
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<ports>
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<port>
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<name>hps2fpga_awid</name>
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<role>awid</role>
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<direction>Output</direction>
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<width>4</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC_VECTOR</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>hps2fpga_awaddr</name>
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<role>awaddr</role>
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<direction>Output</direction>
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<width>38</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC_VECTOR</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>hps2fpga_awlen</name>
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<role>awlen</role>
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<direction>Output</direction>
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<width>8</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC_VECTOR</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>hps2fpga_awsize</name>
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<role>awsize</role>
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<direction>Output</direction>
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<width>3</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC_VECTOR</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>hps2fpga_awburst</name>
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<role>awburst</role>
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<direction>Output</direction>
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<width>2</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC_VECTOR</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>hps2fpga_awlock</name>
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<role>awlock</role>
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<direction>Output</direction>
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<width>1</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>hps2fpga_awcache</name>
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<role>awcache</role>
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<direction>Output</direction>
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<width>4</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC_VECTOR</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>hps2fpga_awprot</name>
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<role>awprot</role>
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<direction>Output</direction>
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<width>3</width>
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<lowerBound>0</lowerBound>
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|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
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<terminationValue>0</terminationValue>
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|
</port>
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<port>
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<name>hps2fpga_awvalid</name>
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<role>awvalid</role>
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<direction>Output</direction>
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<width>1</width>
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|
<lowerBound>0</lowerBound>
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|
<vhdlType>STD_LOGIC</vhdlType>
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<terminationValue>0</terminationValue>
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|
</port>
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<port>
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<name>hps2fpga_awready</name>
|
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<role>awready</role>
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<direction>Input</direction>
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<width>1</width>
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|
<lowerBound>0</lowerBound>
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|
<vhdlType>STD_LOGIC</vhdlType>
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|
<terminationValue>0</terminationValue>
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</port>
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<port>
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|
<name>hps2fpga_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Output</direction>
|
|
<width>128</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
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<terminationValue>0</terminationValue>
|
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</port>
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|
<port>
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<name>hps2fpga_wstrb</name>
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<role>wstrb</role>
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<direction>Output</direction>
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<width>16</width>
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<lowerBound>0</lowerBound>
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<vhdlType>STD_LOGIC_VECTOR</vhdlType>
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<terminationValue>0</terminationValue>
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</port>
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<port>
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<name>hps2fpga_wlast</name>
|
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<role>wlast</role>
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<direction>Output</direction>
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<width>1</width>
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|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
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<port>
|
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<name>hps2fpga_wvalid</name>
|
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<role>wvalid</role>
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<direction>Output</direction>
|
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<width>1</width>
|
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<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
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<port>
|
|
<name>hps2fpga_wready</name>
|
|
<role>wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bid</name>
|
|
<role>bid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bready</name>
|
|
<role>bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arid</name>
|
|
<role>arid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Output</direction>
|
|
<width>38</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arready</name>
|
|
<role>arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rid</name>
|
|
<role>rid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Input</direction>
|
|
<width>128</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rready</name>
|
|
<role>rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>hps2fpga_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>hps2fpga_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noRepeatedIdsBetweenSubordinates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesINCRBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesWRAPBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesFIXEDBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga_axi_clock</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_axi_clock_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga_axi_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_axi_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga</name>
|
|
<type>axi4</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_awid</name>
|
|
<role>awid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awaddr</name>
|
|
<role>awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlen</name>
|
|
<role>awlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awsize</name>
|
|
<role>awsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awburst</name>
|
|
<role>awburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlock</name>
|
|
<role>awlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awcache</name>
|
|
<role>awcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awprot</name>
|
|
<role>awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awvalid</name>
|
|
<role>awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awready</name>
|
|
<role>awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wstrb</name>
|
|
<role>wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wlast</name>
|
|
<role>wlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wvalid</name>
|
|
<role>wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wready</name>
|
|
<role>wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bid</name>
|
|
<role>bid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bready</name>
|
|
<role>bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arid</name>
|
|
<role>arid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arready</name>
|
|
<role>arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rid</name>
|
|
<role>rid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rready</name>
|
|
<role>rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>lwhps2fpga_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>lwhps2fpga_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noRepeatedIdsBetweenSubordinates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesINCRBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesWRAPBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesFIXEDBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>emac0_app_rst</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>emac0_app_rst_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>none</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>h2f_warm_reset_handshake</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_req</name>
|
|
<role>reset_req</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_ack</name>
|
|
<role>reset_ack</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps_io</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps_io_hps_osc_clk</name>
|
|
<role>hps_osc_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data0</name>
|
|
<role>sdmmc_data0</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data1</name>
|
|
<role>sdmmc_data1</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cclk</name>
|
|
<role>sdmmc_cclk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data2</name>
|
|
<role>sdmmc_data2</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data3</name>
|
|
<role>sdmmc_data3</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cmd</name>
|
|
<role>sdmmc_cmd</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_clk</name>
|
|
<role>usb0_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_stp</name>
|
|
<role>usb0_stp</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_dir</name>
|
|
<role>usb0_dir</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data0</name>
|
|
<role>usb0_data0</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data1</name>
|
|
<role>usb0_data1</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_nxt</name>
|
|
<role>usb0_nxt</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data2</name>
|
|
<role>usb0_data2</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data3</name>
|
|
<role>usb0_data3</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data4</name>
|
|
<role>usb0_data4</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data5</name>
|
|
<role>usb0_data5</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data6</name>
|
|
<role>usb0_data6</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data7</name>
|
|
<role>usb0_data7</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_clk</name>
|
|
<role>emac0_tx_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_ctl</name>
|
|
<role>emac0_tx_ctl</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_clk</name>
|
|
<role>emac0_rx_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_ctl</name>
|
|
<role>emac0_rx_ctl</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd0</name>
|
|
<role>emac0_txd0</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd1</name>
|
|
<role>emac0_txd1</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd0</name>
|
|
<role>emac0_rxd0</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd1</name>
|
|
<role>emac0_rxd1</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd2</name>
|
|
<role>emac0_txd2</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd3</name>
|
|
<role>emac0_txd3</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd2</name>
|
|
<role>emac0_rxd2</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd3</name>
|
|
<role>emac0_rxd3</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdio</name>
|
|
<role>mdio0_mdio</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdc</name>
|
|
<role>mdio0_mdc</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_tx</name>
|
|
<role>uart1_tx</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_rx</name>
|
|
<role>uart1_rx</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_sda</name>
|
|
<role>i2c1_sda</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_scl</name>
|
|
<role>i2c1_scl</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio28</name>
|
|
<role>gpio28</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio34</name>
|
|
<role>gpio34</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio40</name>
|
|
<role>gpio40</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio41</name>
|
|
<role>gpio41</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>fpga2hps_interrupt_irq1</name>
|
|
<type>interrupt</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>fpga2hps_interrupt_irq1_irq</name>
|
|
<role>irq</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value></value>
|
|
</entry>
|
|
<entry>
|
|
<key>irqMap</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>fpga2hps_interrupt_irq0</name>
|
|
<type>interrupt</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>fpga2hps_interrupt_irq0_irq</name>
|
|
<role>irq</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value></value>
|
|
</entry>
|
|
<entry>
|
|
<key>irqMap</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram_axi_clock</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_axi_clock_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram_axi_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_axi_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram</name>
|
|
<type>axi4</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arid</name>
|
|
<role>arid</role>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arqos</name>
|
|
<role>arqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arready</name>
|
|
<role>arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awaddr</name>
|
|
<role>awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awburst</name>
|
|
<role>awburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awcache</name>
|
|
<role>awcache</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awid</name>
|
|
<role>awid</role>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlen</name>
|
|
<role>awlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlock</name>
|
|
<role>awlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awprot</name>
|
|
<role>awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awqos</name>
|
|
<role>awqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awready</name>
|
|
<role>awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awsize</name>
|
|
<role>awsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awvalid</name>
|
|
<role>awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bid</name>
|
|
<role>bid</role>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bready</name>
|
|
<role>bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rid</name>
|
|
<role>rid</role>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rready</name>
|
|
<role>rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wlast</name>
|
|
<role>wlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wready</name>
|
|
<role>wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wstrb</name>
|
|
<role>wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wvalid</name>
|
|
<role>wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_aruser</name>
|
|
<role>aruser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awuser</name>
|
|
<role>awuser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wuser</name>
|
|
<role>wuser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_buser</name>
|
|
<role>buser</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arregion</name>
|
|
<role>arregion</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_ruser</name>
|
|
<role>ruser</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awregion</name>
|
|
<role>awregion</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>f2sdram_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>f2sdram_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readDataReorderingDepth</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noNarrowTransfer</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>io96b0_to_hps</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_clk</name>
|
|
<role>ch0_axil_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_reset_n</name>
|
|
<role>ch0_axil_reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arready</name>
|
|
<role>ch0_axil_arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awready</name>
|
|
<role>ch0_axil_awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bresp</name>
|
|
<role>ch0_axil_bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bvalid</name>
|
|
<role>ch0_axil_bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rdata</name>
|
|
<role>ch0_axil_rdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rresp</name>
|
|
<role>ch0_axil_rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rvalid</name>
|
|
<role>ch0_axil_rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wready</name>
|
|
<role>ch0_axil_wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_araddr</name>
|
|
<role>ch0_axil_araddr</role>
|
|
<direction>Output</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arvalid</name>
|
|
<role>ch0_axil_arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awaddr</name>
|
|
<role>ch0_axil_awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awvalid</name>
|
|
<role>ch0_axil_awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bready</name>
|
|
<role>ch0_axil_bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rready</name>
|
|
<role>ch0_axil_rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wdata</name>
|
|
<role>ch0_axil_wdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wstrb</name>
|
|
<role>ch0_axil_wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wvalid</name>
|
|
<role>ch0_axil_wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arprot</name>
|
|
<role>ch0_axil_arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awprot</name>
|
|
<role>ch0_axil_awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_clk</name>
|
|
<role>axi4_ch0_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_reset_n</name>
|
|
<role>axi4_ch0_reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arready</name>
|
|
<role>axi4_ch0_arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awready</name>
|
|
<role>axi4_ch0_awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bid</name>
|
|
<role>axi4_ch0_bid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bresp</name>
|
|
<role>axi4_ch0_bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bvalid</name>
|
|
<role>axi4_ch0_bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rdata</name>
|
|
<role>axi4_ch0_rdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rid</name>
|
|
<role>axi4_ch0_rid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rlast</name>
|
|
<role>axi4_ch0_rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rresp</name>
|
|
<role>axi4_ch0_rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_ruser</name>
|
|
<role>axi4_ch0_ruser</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rvalid</name>
|
|
<role>axi4_ch0_rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wready</name>
|
|
<role>axi4_ch0_wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_araddr</name>
|
|
<role>axi4_ch0_araddr</role>
|
|
<direction>Output</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arburst</name>
|
|
<role>axi4_ch0_arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arid</name>
|
|
<role>axi4_ch0_arid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arlen</name>
|
|
<role>axi4_ch0_arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arlock</name>
|
|
<role>axi4_ch0_arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arqos</name>
|
|
<role>axi4_ch0_arqos</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arsize</name>
|
|
<role>axi4_ch0_arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_aruser</name>
|
|
<role>axi4_ch0_aruser</role>
|
|
<direction>Output</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arvalid</name>
|
|
<role>axi4_ch0_arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awaddr</name>
|
|
<role>axi4_ch0_awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awburst</name>
|
|
<role>axi4_ch0_awburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awid</name>
|
|
<role>axi4_ch0_awid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awlen</name>
|
|
<role>axi4_ch0_awlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awlock</name>
|
|
<role>axi4_ch0_awlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awqos</name>
|
|
<role>axi4_ch0_awqos</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awsize</name>
|
|
<role>axi4_ch0_awsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awuser</name>
|
|
<role>axi4_ch0_awuser</role>
|
|
<direction>Output</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awvalid</name>
|
|
<role>axi4_ch0_awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bready</name>
|
|
<role>axi4_ch0_bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rready</name>
|
|
<role>axi4_ch0_rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wdata</name>
|
|
<role>axi4_ch0_wdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wlast</name>
|
|
<role>axi4_ch0_wlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wstrb</name>
|
|
<role>axi4_ch0_wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wuser</name>
|
|
<role>axi4_ch0_wuser</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wvalid</name>
|
|
<role>axi4_ch0_wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arprot</name>
|
|
<role>axi4_ch0_arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awprot</name>
|
|
<role>axi4_ch0_awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>intel_agilex_5_soc</className>
|
|
<version>13.0.0</version>
|
|
<displayName>Hard Processor System IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>AUTO_BOARD</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>BOARD</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>device_family</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_FAMILY</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>device_name</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>device_trait_iobank_rev</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>DEVICE_IOBANK_REVISION</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos>
|
|
<entry>
|
|
<key>f2sdram</key>
|
|
<value>
|
|
<connectionPointName>f2sdram</connectionPointName>
|
|
<suppliedSystemInfos>
|
|
<entry>
|
|
<key>ADDRESS_MAP</key>
|
|
<value>&lt;address-map&gt;&lt;slave name='f2sdram' start='0x0' end='0x100000000' datawidth='256' /&gt;&lt;/address-map&gt;</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ADDRESS_WIDTH</key>
|
|
<value>32</value>
|
|
</entry>
|
|
<entry>
|
|
<key>MAX_SLAVE_DATA_WIDTH</key>
|
|
<value>256</value>
|
|
</entry>
|
|
</suppliedSystemInfos>
|
|
<consumedSystemInfos/>
|
|
</value>
|
|
</entry>
|
|
</connPtSystemInfos>
|
|
</systemInfos>
|
|
</componentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuHashInfo" type="string">
|
|
<ipxact:name>cpuHashInfo</ipxact:name>
|
|
<ipxact:displayName>CPU Hash Info</ipxact:displayName>
|
|
<ipxact:value><cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuInfo" type="string">
|
|
<ipxact:name>cpuInfo</ipxact:name>
|
|
<ipxact:displayName>Cpu Info</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="defaultBoundary" type="string">
|
|
<ipxact:name>defaultBoundary</ipxact:name>
|
|
<ipxact:displayName>Default boundary</ipxact:displayName>
|
|
<ipxact:value><boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>h2f_reset</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>h2f_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>none</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps2fpga_axi_clock</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps2fpga_axi_clock_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps2fpga_axi_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps2fpga_axi_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps2fpga</name>
|
|
<type>axi4</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps2fpga_awid</name>
|
|
<role>awid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awaddr</name>
|
|
<role>awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>38</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awlen</name>
|
|
<role>awlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awsize</name>
|
|
<role>awsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awburst</name>
|
|
<role>awburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awlock</name>
|
|
<role>awlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awcache</name>
|
|
<role>awcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awprot</name>
|
|
<role>awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awvalid</name>
|
|
<role>awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_awready</name>
|
|
<role>awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Output</direction>
|
|
<width>128</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wstrb</name>
|
|
<role>wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>16</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wlast</name>
|
|
<role>wlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wvalid</name>
|
|
<role>wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_wready</name>
|
|
<role>wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bid</name>
|
|
<role>bid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_bready</name>
|
|
<role>bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arid</name>
|
|
<role>arid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Output</direction>
|
|
<width>38</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_arready</name>
|
|
<role>arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rid</name>
|
|
<role>rid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Input</direction>
|
|
<width>128</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps2fpga_rready</name>
|
|
<role>rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>hps2fpga_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>hps2fpga_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noRepeatedIdsBetweenSubordinates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesINCRBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesWRAPBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesFIXEDBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga_axi_clock</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_axi_clock_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga_axi_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_axi_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>lwhps2fpga</name>
|
|
<type>axi4</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>lwhps2fpga_awid</name>
|
|
<role>awid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awaddr</name>
|
|
<role>awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlen</name>
|
|
<role>awlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awsize</name>
|
|
<role>awsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awburst</name>
|
|
<role>awburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awlock</name>
|
|
<role>awlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awcache</name>
|
|
<role>awcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awprot</name>
|
|
<role>awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awvalid</name>
|
|
<role>awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_awready</name>
|
|
<role>awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wstrb</name>
|
|
<role>wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wlast</name>
|
|
<role>wlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wvalid</name>
|
|
<role>wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_wready</name>
|
|
<role>wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bid</name>
|
|
<role>bid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_bready</name>
|
|
<role>bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arid</name>
|
|
<role>arid</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Output</direction>
|
|
<width>29</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_arready</name>
|
|
<role>arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rid</name>
|
|
<role>rid</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>lwhps2fpga_rready</name>
|
|
<role>rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>lwhps2fpga_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>lwhps2fpga_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedIssuingCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>enableConcurrentSubordinateAccess</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noRepeatedIdsBetweenSubordinates</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesINCRBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesWRAPBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>issuesFIXEDBursts</key>
|
|
<value>true</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>emac0_app_rst</name>
|
|
<type>reset</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>emac0_app_rst_reset_n</name>
|
|
<role>reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedDirectReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedResetSinks</key>
|
|
<value>none</value>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>h2f_warm_reset_handshake</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_req</name>
|
|
<role>reset_req</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>h2f_warm_reset_handshake_reset_ack</name>
|
|
<role>reset_ack</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>hps_io</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>hps_io_hps_osc_clk</name>
|
|
<role>hps_osc_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data0</name>
|
|
<role>sdmmc_data0</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data1</name>
|
|
<role>sdmmc_data1</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cclk</name>
|
|
<role>sdmmc_cclk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data2</name>
|
|
<role>sdmmc_data2</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_data3</name>
|
|
<role>sdmmc_data3</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_sdmmc_cmd</name>
|
|
<role>sdmmc_cmd</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_clk</name>
|
|
<role>usb0_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_stp</name>
|
|
<role>usb0_stp</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_dir</name>
|
|
<role>usb0_dir</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data0</name>
|
|
<role>usb0_data0</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data1</name>
|
|
<role>usb0_data1</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_nxt</name>
|
|
<role>usb0_nxt</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data2</name>
|
|
<role>usb0_data2</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data3</name>
|
|
<role>usb0_data3</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data4</name>
|
|
<role>usb0_data4</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data5</name>
|
|
<role>usb0_data5</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data6</name>
|
|
<role>usb0_data6</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_usb0_data7</name>
|
|
<role>usb0_data7</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_clk</name>
|
|
<role>emac0_tx_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_tx_ctl</name>
|
|
<role>emac0_tx_ctl</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_clk</name>
|
|
<role>emac0_rx_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rx_ctl</name>
|
|
<role>emac0_rx_ctl</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd0</name>
|
|
<role>emac0_txd0</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd1</name>
|
|
<role>emac0_txd1</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd0</name>
|
|
<role>emac0_rxd0</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd1</name>
|
|
<role>emac0_rxd1</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd2</name>
|
|
<role>emac0_txd2</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_txd3</name>
|
|
<role>emac0_txd3</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd2</name>
|
|
<role>emac0_rxd2</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_emac0_rxd3</name>
|
|
<role>emac0_rxd3</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdio</name>
|
|
<role>mdio0_mdio</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_mdio0_mdc</name>
|
|
<role>mdio0_mdc</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_tx</name>
|
|
<role>uart1_tx</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_uart1_rx</name>
|
|
<role>uart1_rx</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_sda</name>
|
|
<role>i2c1_sda</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_i2c1_scl</name>
|
|
<role>i2c1_scl</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio28</name>
|
|
<role>gpio28</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio34</name>
|
|
<role>gpio34</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio40</name>
|
|
<role>gpio40</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>hps_io_gpio41</name>
|
|
<role>gpio41</role>
|
|
<direction>Bidir</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>fpga2hps_interrupt_irq1</name>
|
|
<type>interrupt</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>fpga2hps_interrupt_irq1_irq</name>
|
|
<role>irq</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value></value>
|
|
</entry>
|
|
<entry>
|
|
<key>irqMap</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>fpga2hps_interrupt_irq0</name>
|
|
<type>interrupt</type>
|
|
<isStart>true</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>fpga2hps_interrupt_irq0_irq</name>
|
|
<role>irq</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedAddressablePoint</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value></value>
|
|
</entry>
|
|
<entry>
|
|
<key>irqMap</key>
|
|
</entry>
|
|
<entry>
|
|
<key>irqScheme</key>
|
|
<value>INDIVIDUAL_REQUESTS</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram_axi_clock</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_axi_clock_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram_axi_reset</name>
|
|
<type>reset</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_axi_reset_reset</name>
|
|
<role>reset</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>synchronousEdges</key>
|
|
<value>NONE</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>f2sdram</name>
|
|
<type>axi4</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>f2sdram_araddr</name>
|
|
<role>araddr</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arburst</name>
|
|
<role>arburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arcache</name>
|
|
<role>arcache</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arid</name>
|
|
<role>arid</role>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlen</name>
|
|
<role>arlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arlock</name>
|
|
<role>arlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arprot</name>
|
|
<role>arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arqos</name>
|
|
<role>arqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arready</name>
|
|
<role>arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arsize</name>
|
|
<role>arsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arvalid</name>
|
|
<role>arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awaddr</name>
|
|
<role>awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awburst</name>
|
|
<role>awburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awcache</name>
|
|
<role>awcache</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awid</name>
|
|
<role>awid</role>
|
|
<direction>Input</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlen</name>
|
|
<role>awlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awlock</name>
|
|
<role>awlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awprot</name>
|
|
<role>awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awqos</name>
|
|
<role>awqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awready</name>
|
|
<role>awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awsize</name>
|
|
<role>awsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awvalid</name>
|
|
<role>awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bid</name>
|
|
<role>bid</role>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bready</name>
|
|
<role>bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bresp</name>
|
|
<role>bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_bvalid</name>
|
|
<role>bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rdata</name>
|
|
<role>rdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rid</name>
|
|
<role>rid</role>
|
|
<direction>Output</direction>
|
|
<width>5</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rlast</name>
|
|
<role>rlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rready</name>
|
|
<role>rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rresp</name>
|
|
<role>rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_rvalid</name>
|
|
<role>rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wdata</name>
|
|
<role>wdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wlast</name>
|
|
<role>wlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wready</name>
|
|
<role>wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wstrb</name>
|
|
<role>wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wvalid</name>
|
|
<role>wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_aruser</name>
|
|
<role>aruser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awuser</name>
|
|
<role>awuser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_wuser</name>
|
|
<role>wuser</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_buser</name>
|
|
<role>buser</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_arregion</name>
|
|
<role>arregion</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_ruser</name>
|
|
<role>ruser</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>f2sdram_awregion</name>
|
|
<role>awregion</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
<value>f2sdram_axi_clock</value>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
<value>f2sdram_axi_reset</value>
|
|
</entry>
|
|
<entry>
|
|
<key>optionalAssociatedReset</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>trustzoneAware</key>
|
|
<value>true</value>
|
|
</entry>
|
|
<entry>
|
|
<key>wakeupSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>uniqueIdSupport</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>poison</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>traceSignals</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>isTranslator</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingReads</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingWrites</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>maximumOutstandingTransactions</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dataCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>addressCheck</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>securityAttribute</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>userData</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>writeAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>combinedAcceptanceCapability</key>
|
|
<value>16</value>
|
|
</entry>
|
|
<entry>
|
|
<key>readDataReorderingDepth</key>
|
|
<value>1</value>
|
|
</entry>
|
|
<entry>
|
|
<key>bridgesToMaster</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureGuid</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhGroupId</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterId</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterName</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterVersion</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterData</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhParameterDataLength</key>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMajorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureMinorVersion</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureId</key>
|
|
<value>35</value>
|
|
</entry>
|
|
<entry>
|
|
<key>dfhFeatureType</key>
|
|
<value>3</value>
|
|
</entry>
|
|
<entry>
|
|
<key>noNarrowTransfer</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>io96b0_to_hps</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_clk</name>
|
|
<role>ch0_axil_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_reset_n</name>
|
|
<role>ch0_axil_reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arready</name>
|
|
<role>ch0_axil_arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awready</name>
|
|
<role>ch0_axil_awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bresp</name>
|
|
<role>ch0_axil_bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bvalid</name>
|
|
<role>ch0_axil_bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rdata</name>
|
|
<role>ch0_axil_rdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rresp</name>
|
|
<role>ch0_axil_rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rvalid</name>
|
|
<role>ch0_axil_rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wready</name>
|
|
<role>ch0_axil_wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_araddr</name>
|
|
<role>ch0_axil_araddr</role>
|
|
<direction>Output</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arvalid</name>
|
|
<role>ch0_axil_arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awaddr</name>
|
|
<role>ch0_axil_awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awvalid</name>
|
|
<role>ch0_axil_awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_bready</name>
|
|
<role>ch0_axil_bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_rready</name>
|
|
<role>ch0_axil_rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wdata</name>
|
|
<role>ch0_axil_wdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wstrb</name>
|
|
<role>ch0_axil_wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_wvalid</name>
|
|
<role>ch0_axil_wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_arprot</name>
|
|
<role>ch0_axil_arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_ch0_axil_awprot</name>
|
|
<role>ch0_axil_awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_clk</name>
|
|
<role>axi4_ch0_clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_reset_n</name>
|
|
<role>axi4_ch0_reset_n</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arready</name>
|
|
<role>axi4_ch0_arready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awready</name>
|
|
<role>axi4_ch0_awready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bid</name>
|
|
<role>axi4_ch0_bid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bresp</name>
|
|
<role>axi4_ch0_bresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bvalid</name>
|
|
<role>axi4_ch0_bvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rdata</name>
|
|
<role>axi4_ch0_rdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rid</name>
|
|
<role>axi4_ch0_rid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rlast</name>
|
|
<role>axi4_ch0_rlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rresp</name>
|
|
<role>axi4_ch0_rresp</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_ruser</name>
|
|
<role>axi4_ch0_ruser</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rvalid</name>
|
|
<role>axi4_ch0_rvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wready</name>
|
|
<role>axi4_ch0_wready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_araddr</name>
|
|
<role>axi4_ch0_araddr</role>
|
|
<direction>Output</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arburst</name>
|
|
<role>axi4_ch0_arburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arid</name>
|
|
<role>axi4_ch0_arid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arlen</name>
|
|
<role>axi4_ch0_arlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arlock</name>
|
|
<role>axi4_ch0_arlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arqos</name>
|
|
<role>axi4_ch0_arqos</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arsize</name>
|
|
<role>axi4_ch0_arsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_aruser</name>
|
|
<role>axi4_ch0_aruser</role>
|
|
<direction>Output</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arvalid</name>
|
|
<role>axi4_ch0_arvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awaddr</name>
|
|
<role>axi4_ch0_awaddr</role>
|
|
<direction>Output</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awburst</name>
|
|
<role>axi4_ch0_awburst</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awid</name>
|
|
<role>axi4_ch0_awid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awlen</name>
|
|
<role>axi4_ch0_awlen</role>
|
|
<direction>Output</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awlock</name>
|
|
<role>axi4_ch0_awlock</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awqos</name>
|
|
<role>axi4_ch0_awqos</role>
|
|
<direction>Output</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awsize</name>
|
|
<role>axi4_ch0_awsize</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awuser</name>
|
|
<role>axi4_ch0_awuser</role>
|
|
<direction>Output</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awvalid</name>
|
|
<role>axi4_ch0_awvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_bready</name>
|
|
<role>axi4_ch0_bready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_rready</name>
|
|
<role>axi4_ch0_rready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wdata</name>
|
|
<role>axi4_ch0_wdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wlast</name>
|
|
<role>axi4_ch0_wlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wstrb</name>
|
|
<role>axi4_ch0_wstrb</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wuser</name>
|
|
<role>axi4_ch0_wuser</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_wvalid</name>
|
|
<role>axi4_ch0_wvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_arprot</name>
|
|
<role>axi4_ch0_arprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>io96b0_to_hps_axi4_ch0_awprot</name>
|
|
<role>axi4_ch0_awprot</role>
|
|
<direction>Output</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="generationInfoDefinition" type="string">
|
|
<ipxact:name>generationInfoDefinition</ipxact:name>
|
|
<ipxact:displayName>Generation Behavior</ipxact:displayName>
|
|
<ipxact:value><generationInfoDefinition>
|
|
<hdlLibraryName>agilex_hps</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>agilex_hps</fileSetName>
|
|
<fileSetFixedName>agilex_hps</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>agilex_hps</fileSetName>
|
|
<fileSetFixedName>agilex_hps</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>agilex_hps</fileSetName>
|
|
<fileSetFixedName>agilex_hps</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>agilex_hps</fileSetName>
|
|
<fileSetFixedName>agilex_hps</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>agilex_hps</fileSetName>
|
|
<fileSetFixedName>agilex_hps</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hdlParameters" type="string">
|
|
<ipxact:name>hdlParameters</ipxact:name>
|
|
<ipxact:displayName>HDL Parameters</ipxact:displayName>
|
|
<ipxact:value><hdlParameterDescriptorDefinitionList/></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hlsFile" type="string">
|
|
<ipxact:name>hlsFile</ipxact:name>
|
|
<ipxact:displayName>HLS file</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="liveModuleName" type="string">
|
|
<ipxact:name>liveModuleName</ipxact:name>
|
|
<ipxact:displayName>Live Module Name</ipxact:displayName>
|
|
<ipxact:value>intel_agilex_5_soc_inst</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="logicalView" type="string">
|
|
<ipxact:name>logicalView</ipxact:name>
|
|
<ipxact:displayName>Logical view</ipxact:displayName>
|
|
<ipxact:value>ip/hps_subsys/agilex_hps.ip</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="moduleAssignmentDefinition" type="string">
|
|
<ipxact:name>moduleAssignmentDefinition</ipxact:name>
|
|
<ipxact:displayName>Module Assignments</ipxact:displayName>
|
|
<ipxact:value><assignmentDefinition>
|
|
<assignmentValueMap>
|
|
<entry>
|
|
<key>embeddedsw.CMacro.CPU_FREQ</key>
|
|
<value>50000000u</value>
|
|
</entry>
|
|
<entry>
|
|
<key>embeddedsw.configuration.cpuArchitecture</key>
|
|
<value>sm_hps</value>
|
|
</entry>
|
|
</assignmentValueMap>
|
|
</assignmentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="svInterfaceDefinition" type="string">
|
|
<ipxact:name>svInterfaceDefinition</ipxact:name>
|
|
<ipxact:displayName>System Verilog Interface definition</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="transformParameters" type="string">
|
|
<ipxact:name>transformParameters</ipxact:name>
|
|
<ipxact:displayName>Transform Parameters</ipxact:displayName>
|
|
<ipxact:value><transformParameterDescriptorDefinitionList/></ipxact:value>
|
|
</ipxact:parameter>
|
|
</ipxact:parameters>
|
|
</altera:altera_module_parameters>
|
|
<altera:altera_ecc_parameter_mappings altera:parentModule=""></altera:altera_ecc_parameter_mappings>
|
|
</altera:module>
|
|
<altera:module altera:enabled="true" altera:auto_export="false">
|
|
<altera:entity_info>
|
|
<ipxact:vendor>Altera Corporation</ipxact:vendor>
|
|
<ipxact:library>emif_hps</ipxact:library>
|
|
<ipxact:name>altera_generic_component</ipxact:name>
|
|
<ipxact:version>1.0</ipxact:version>
|
|
</altera:entity_info>
|
|
<altera:altera_module_parameters>
|
|
<ipxact:parameters>
|
|
<ipxact:parameter parameterId="bspCpu" type="bit">
|
|
<ipxact:name>bspCpu</ipxact:name>
|
|
<ipxact:displayName>BSP CPU</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="componentDefinition" type="string">
|
|
<ipxact:name>componentDefinition</ipxact:name>
|
|
<ipxact:displayName>Component definition</ipxact:displayName>
|
|
<ipxact:value><componentDefinition>
|
|
<boundary>
|
|
<interfaces>
|
|
<interface>
|
|
<name>io96b0_to_hps</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>s0_noc_axi4lite_clock</name>
|
|
<role>ch0_axil_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_reset_n</name>
|
|
<role>ch0_axil_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awaddr</name>
|
|
<role>ch0_axil_awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awvalid</name>
|
|
<role>ch0_axil_awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awready</name>
|
|
<role>ch0_axil_awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_araddr</name>
|
|
<role>ch0_axil_araddr</role>
|
|
<direction>Input</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arvalid</name>
|
|
<role>ch0_axil_arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arready</name>
|
|
<role>ch0_axil_arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wdata</name>
|
|
<role>ch0_axil_wdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wvalid</name>
|
|
<role>ch0_axil_wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wready</name>
|
|
<role>ch0_axil_wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rresp</name>
|
|
<role>ch0_axil_rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rdata</name>
|
|
<role>ch0_axil_rdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rvalid</name>
|
|
<role>ch0_axil_rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rready</name>
|
|
<role>ch0_axil_rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bresp</name>
|
|
<role>ch0_axil_bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bvalid</name>
|
|
<role>ch0_axil_bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bready</name>
|
|
<role>ch0_axil_bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awprot</name>
|
|
<role>ch0_axil_awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arprot</name>
|
|
<role>ch0_axil_arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wstrb</name>
|
|
<role>ch0_axil_wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awaddr</name>
|
|
<role>axi4_ch0_awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awburst</name>
|
|
<role>axi4_ch0_awburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awid</name>
|
|
<role>axi4_ch0_awid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awlen</name>
|
|
<role>axi4_ch0_awlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awlock</name>
|
|
<role>axi4_ch0_awlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awqos</name>
|
|
<role>axi4_ch0_awqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awsize</name>
|
|
<role>axi4_ch0_awsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awvalid</name>
|
|
<role>axi4_ch0_awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awuser</name>
|
|
<role>axi4_ch0_awuser</role>
|
|
<direction>Input</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awprot</name>
|
|
<role>axi4_ch0_awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awready</name>
|
|
<role>axi4_ch0_awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_araddr</name>
|
|
<role>axi4_ch0_araddr</role>
|
|
<direction>Input</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arburst</name>
|
|
<role>axi4_ch0_arburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arid</name>
|
|
<role>axi4_ch0_arid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arlen</name>
|
|
<role>axi4_ch0_arlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arlock</name>
|
|
<role>axi4_ch0_arlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arqos</name>
|
|
<role>axi4_ch0_arqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arsize</name>
|
|
<role>axi4_ch0_arsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arvalid</name>
|
|
<role>axi4_ch0_arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_aruser</name>
|
|
<role>axi4_ch0_aruser</role>
|
|
<direction>Input</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arprot</name>
|
|
<role>axi4_ch0_arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arready</name>
|
|
<role>axi4_ch0_arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wdata</name>
|
|
<role>axi4_ch0_wdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wstrb</name>
|
|
<role>axi4_ch0_wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wlast</name>
|
|
<role>axi4_ch0_wlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wvalid</name>
|
|
<role>axi4_ch0_wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wready</name>
|
|
<role>axi4_ch0_wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bready</name>
|
|
<role>axi4_ch0_bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bid</name>
|
|
<role>axi4_ch0_bid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bresp</name>
|
|
<role>axi4_ch0_bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bvalid</name>
|
|
<role>axi4_ch0_bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rready</name>
|
|
<role>axi4_ch0_rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rdata</name>
|
|
<role>axi4_ch0_rdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rid</name>
|
|
<role>axi4_ch0_rid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rlast</name>
|
|
<role>axi4_ch0_rlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rresp</name>
|
|
<role>axi4_ch0_rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rvalid</name>
|
|
<role>axi4_ch0_rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>noc_aclk_0</name>
|
|
<role>axi4_ch0_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>noc_rst_n_0</name>
|
|
<role>axi4_ch0_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wuser</name>
|
|
<role>axi4_ch0_wuser</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_ruser</name>
|
|
<role>axi4_ch0_ruser</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_cs</name>
|
|
<role>mem_cs</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_ca</name>
|
|
<role>mem_ca</role>
|
|
<direction>Output</direction>
|
|
<width>6</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_cke</name>
|
|
<role>mem_cke</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dq</name>
|
|
<role>mem_dq</role>
|
|
<direction>Bidir</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dqs_t</name>
|
|
<role>mem_dqs_t</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dqs_c</name>
|
|
<role>mem_dqs_c</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dmi</name>
|
|
<role>mem_dmi</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_ck_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_ck_t</name>
|
|
<role>mem_ck_t</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_ck_c</name>
|
|
<role>mem_ck_c</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_reset_n</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_reset_n</name>
|
|
<role>mem_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>oct_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>oct_rzqin_0</name>
|
|
<role>oct_rzqin</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>ref_clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>ref_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundary>
|
|
<originalModuleInfo>
|
|
<className>emif_io96b_hps</className>
|
|
<version>4.0.0</version>
|
|
<displayName>External Memory Interfaces for HPS IP</displayName>
|
|
</originalModuleInfo>
|
|
<systemInfoParameterDescriptors>
|
|
<descriptors>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_BOARD</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>BOARD</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_BOARD_TRAIT</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>BOARD_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_BASE_DIE</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>BASE_DEVICE</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_DIE_REVISIONS</parameterName>
|
|
<parameterType>[Ljava.lang.String;</parameterType>
|
|
<systemInfotype>DEVICE_DIE_REVISIONS</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_FAMILY</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_FAMILY</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_GROUP</parameterName>
|
|
<parameterType>[Ljava.lang.String;</parameterType>
|
|
<systemInfoArgs>DEVICE_GROUP</systemInfoArgs>
|
|
<systemInfotype>DEVICE_INFO</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_IOBANK_REVISION</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>DEVICE_IOBANK_REVISION</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_POWER_MODEL</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>DEVICE_POWER_MODEL</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_SPEEDGRADE</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_DEVICE_TEMPERATURE_GRADE</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>DEVICE_TEMPERATURE_GRADE</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
<descriptor>
|
|
<parameterDefaultValue></parameterDefaultValue>
|
|
<parameterName>SYSINFO_SUPPORTS_VID</parameterName>
|
|
<parameterType>java.lang.String</parameterType>
|
|
<systemInfoArgs>SUPPORTS_VID</systemInfoArgs>
|
|
<systemInfotype>PART_TRAIT</systemInfotype>
|
|
</descriptor>
|
|
</descriptors>
|
|
</systemInfoParameterDescriptors>
|
|
<systemInfos>
|
|
<connPtSystemInfos/>
|
|
</systemInfos>
|
|
</componentDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuHashInfo" type="string">
|
|
<ipxact:name>cpuHashInfo</ipxact:name>
|
|
<ipxact:displayName>CPU Hash Info</ipxact:displayName>
|
|
<ipxact:value><cpuHashInfoDefinition>
|
|
<cpuHashInfoMap/>
|
|
</cpuHashInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="cpuInfo" type="string">
|
|
<ipxact:name>cpuInfo</ipxact:name>
|
|
<ipxact:displayName>Cpu Info</ipxact:displayName>
|
|
<ipxact:value><cpuInfoDefinition>
|
|
<version>1</version>
|
|
<cpuGroups/>
|
|
<exportedModules/>
|
|
<systemInformation>
|
|
<name>emif_io96b_hps</name>
|
|
<deviceFamily>Agilex 5</deviceFamily>
|
|
<generateLegacySim>false</generateLegacySim>
|
|
</systemInformation>
|
|
</cpuInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="defaultBoundary" type="string">
|
|
<ipxact:name>defaultBoundary</ipxact:name>
|
|
<ipxact:displayName>Default boundary</ipxact:displayName>
|
|
<ipxact:value><boundaryDefinition>
|
|
<interfaces>
|
|
<interface>
|
|
<name>io96b0_to_hps</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>s0_noc_axi4lite_clock</name>
|
|
<role>ch0_axil_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_reset_n</name>
|
|
<role>ch0_axil_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awaddr</name>
|
|
<role>ch0_axil_awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awvalid</name>
|
|
<role>ch0_axil_awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awready</name>
|
|
<role>ch0_axil_awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_araddr</name>
|
|
<role>ch0_axil_araddr</role>
|
|
<direction>Input</direction>
|
|
<width>27</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arvalid</name>
|
|
<role>ch0_axil_arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arready</name>
|
|
<role>ch0_axil_arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wdata</name>
|
|
<role>ch0_axil_wdata</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wvalid</name>
|
|
<role>ch0_axil_wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wready</name>
|
|
<role>ch0_axil_wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rresp</name>
|
|
<role>ch0_axil_rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rdata</name>
|
|
<role>ch0_axil_rdata</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rvalid</name>
|
|
<role>ch0_axil_rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_rready</name>
|
|
<role>ch0_axil_rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bresp</name>
|
|
<role>ch0_axil_bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bvalid</name>
|
|
<role>ch0_axil_bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_bready</name>
|
|
<role>ch0_axil_bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_awprot</name>
|
|
<role>ch0_axil_awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_arprot</name>
|
|
<role>ch0_axil_arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_noc_axi4lite_wstrb</name>
|
|
<role>ch0_axil_wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awaddr</name>
|
|
<role>axi4_ch0_awaddr</role>
|
|
<direction>Input</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awburst</name>
|
|
<role>axi4_ch0_awburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awid</name>
|
|
<role>axi4_ch0_awid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awlen</name>
|
|
<role>axi4_ch0_awlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awlock</name>
|
|
<role>axi4_ch0_awlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awqos</name>
|
|
<role>axi4_ch0_awqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awsize</name>
|
|
<role>axi4_ch0_awsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awvalid</name>
|
|
<role>axi4_ch0_awvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awuser</name>
|
|
<role>axi4_ch0_awuser</role>
|
|
<direction>Input</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awprot</name>
|
|
<role>axi4_ch0_awprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_awready</name>
|
|
<role>axi4_ch0_awready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_araddr</name>
|
|
<role>axi4_ch0_araddr</role>
|
|
<direction>Input</direction>
|
|
<width>40</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arburst</name>
|
|
<role>axi4_ch0_arburst</role>
|
|
<direction>Input</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arid</name>
|
|
<role>axi4_ch0_arid</role>
|
|
<direction>Input</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arlen</name>
|
|
<role>axi4_ch0_arlen</role>
|
|
<direction>Input</direction>
|
|
<width>8</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arlock</name>
|
|
<role>axi4_ch0_arlock</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arqos</name>
|
|
<role>axi4_ch0_arqos</role>
|
|
<direction>Input</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arsize</name>
|
|
<role>axi4_ch0_arsize</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arvalid</name>
|
|
<role>axi4_ch0_arvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_aruser</name>
|
|
<role>axi4_ch0_aruser</role>
|
|
<direction>Input</direction>
|
|
<width>14</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arprot</name>
|
|
<role>axi4_ch0_arprot</role>
|
|
<direction>Input</direction>
|
|
<width>3</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_arready</name>
|
|
<role>axi4_ch0_arready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wdata</name>
|
|
<role>axi4_ch0_wdata</role>
|
|
<direction>Input</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wstrb</name>
|
|
<role>axi4_ch0_wstrb</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wlast</name>
|
|
<role>axi4_ch0_wlast</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wvalid</name>
|
|
<role>axi4_ch0_wvalid</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wready</name>
|
|
<role>axi4_ch0_wready</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bready</name>
|
|
<role>axi4_ch0_bready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bid</name>
|
|
<role>axi4_ch0_bid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bresp</name>
|
|
<role>axi4_ch0_bresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_bvalid</name>
|
|
<role>axi4_ch0_bvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rready</name>
|
|
<role>axi4_ch0_rready</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rdata</name>
|
|
<role>axi4_ch0_rdata</role>
|
|
<direction>Output</direction>
|
|
<width>256</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rid</name>
|
|
<role>axi4_ch0_rid</role>
|
|
<direction>Output</direction>
|
|
<width>7</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rlast</name>
|
|
<role>axi4_ch0_rlast</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rresp</name>
|
|
<role>axi4_ch0_rresp</role>
|
|
<direction>Output</direction>
|
|
<width>2</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_rvalid</name>
|
|
<role>axi4_ch0_rvalid</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>noc_aclk_0</name>
|
|
<role>axi4_ch0_clk</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>noc_rst_n_0</name>
|
|
<role>axi4_ch0_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_wuser</name>
|
|
<role>axi4_ch0_wuser</role>
|
|
<direction>Input</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>s0_axi4_ruser</name>
|
|
<role>axi4_ch0_ruser</role>
|
|
<direction>Output</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_cs</name>
|
|
<role>mem_cs</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_ca</name>
|
|
<role>mem_ca</role>
|
|
<direction>Output</direction>
|
|
<width>6</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_cke</name>
|
|
<role>mem_cke</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dq</name>
|
|
<role>mem_dq</role>
|
|
<direction>Bidir</direction>
|
|
<width>32</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dqs_t</name>
|
|
<role>mem_dqs_t</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dqs_c</name>
|
|
<role>mem_dqs_c</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_dmi</name>
|
|
<role>mem_dmi</role>
|
|
<direction>Bidir</direction>
|
|
<width>4</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_ck_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_ck_t</name>
|
|
<role>mem_ck_t</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
<port>
|
|
<name>mem_0_ck_c</name>
|
|
<role>mem_ck_c</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>mem_reset_n</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>mem_0_reset_n</name>
|
|
<role>mem_reset_n</role>
|
|
<direction>Output</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>oct_0</name>
|
|
<type>conduit</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>oct_rzqin_0</name>
|
|
<role>oct_rzqin</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>associatedClock</key>
|
|
</entry>
|
|
<entry>
|
|
<key>associatedReset</key>
|
|
</entry>
|
|
<entry>
|
|
<key>prSafe</key>
|
|
<value>false</value>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
<interface>
|
|
<name>ref_clk</name>
|
|
<type>clock</type>
|
|
<isStart>false</isStart>
|
|
<ports>
|
|
<port>
|
|
<name>ref_clk</name>
|
|
<role>clk</role>
|
|
<direction>Input</direction>
|
|
<width>1</width>
|
|
<lowerBound>0</lowerBound>
|
|
<vhdlType>STD_LOGIC</vhdlType>
|
|
<terminationValue>0</terminationValue>
|
|
</port>
|
|
</ports>
|
|
<assignments>
|
|
<assignmentValueMap/>
|
|
</assignments>
|
|
<parameters>
|
|
<parameterValueMap>
|
|
<entry>
|
|
<key>clockRate</key>
|
|
<value>0</value>
|
|
</entry>
|
|
<entry>
|
|
<key>externallyDriven</key>
|
|
<value>false</value>
|
|
</entry>
|
|
<entry>
|
|
<key>ptfSchematicName</key>
|
|
</entry>
|
|
</parameterValueMap>
|
|
</parameters>
|
|
</interface>
|
|
</interfaces>
|
|
</boundaryDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="generationInfoDefinition" type="string">
|
|
<ipxact:name>generationInfoDefinition</ipxact:name>
|
|
<ipxact:displayName>Generation Behavior</ipxact:displayName>
|
|
<ipxact:value><generationInfoDefinition>
|
|
<hdlLibraryName>emif_io96b_hps</hdlLibraryName>
|
|
<fileSets>
|
|
<fileSet>
|
|
<fileSetName>emif_io96b_hps</fileSetName>
|
|
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
|
|
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>emif_io96b_hps</fileSetName>
|
|
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
|
|
<fileSetKind>SIM_VERILOG</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>emif_io96b_hps</fileSetName>
|
|
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
|
|
<fileSetKind>SIM_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>emif_io96b_hps</fileSetName>
|
|
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
|
|
<fileSetKind>CDC</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
<fileSet>
|
|
<fileSetName>emif_io96b_hps</fileSetName>
|
|
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
|
|
<fileSetKind>CDC_VHDL</fileSetKind>
|
|
<fileSetFiles/>
|
|
<fileSetFileChangeDefs/>
|
|
</fileSet>
|
|
</fileSets>
|
|
</generationInfoDefinition></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hdlParameters" type="string">
|
|
<ipxact:name>hdlParameters</ipxact:name>
|
|
<ipxact:displayName>HDL Parameters</ipxact:displayName>
|
|
<ipxact:value><hdlParameterDescriptorDefinitionList/></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="hlsFile" type="string">
|
|
<ipxact:name>hlsFile</ipxact:name>
|
|
<ipxact:displayName>HLS file</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="liveModuleName" type="string">
|
|
<ipxact:name>liveModuleName</ipxact:name>
|
|
<ipxact:displayName>Live Module Name</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="logicalView" type="string">
|
|
<ipxact:name>logicalView</ipxact:name>
|
|
<ipxact:displayName>Logical view</ipxact:displayName>
|
|
<ipxact:value>ip/qsys_top/emif_io96b_hps.ip</ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="moduleAssignmentDefinition" type="string">
|
|
<ipxact:name>moduleAssignmentDefinition</ipxact:name>
|
|
<ipxact:displayName>Module Assignments</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="svInterfaceDefinition" type="string">
|
|
<ipxact:name>svInterfaceDefinition</ipxact:name>
|
|
<ipxact:displayName>System Verilog Interface definition</ipxact:displayName>
|
|
<ipxact:value></ipxact:value>
|
|
</ipxact:parameter>
|
|
<ipxact:parameter parameterId="transformParameters" type="string">
|
|
<ipxact:name>transformParameters</ipxact:name>
|
|
<ipxact:displayName>Transform Parameters</ipxact:displayName>
|
|
<ipxact:value><transformParameterDescriptorDefinitionList/></ipxact:value>
|
|
</ipxact:parameter>
|
|
</ipxact:parameters>
|
|
</altera:altera_module_parameters>
|
|
<altera:altera_ecc_parameter_mappings altera:parentModule=""></altera:altera_ecc_parameter_mappings>
|
|
</altera:module>
|
|
</altera:modules>
|
|
<altera:connections>
|
|
<altera:connection altera:kind="conduit" altera:version="25.3" altera:start="emif_hps.io96b0_to_hps" altera:end="agilex_hps.io96b0_to_hps">
|
|
<altera:connection_parameter altera:parameter_name="endPort" altera:parameter_value=""></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="endPortLSB" altera:parameter_value="0"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="startPort" altera:parameter_value=""></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="startPortLSB" altera:parameter_value="0"></altera:connection_parameter>
|
|
<altera:connection_parameter altera:parameter_name="width" altera:parameter_value="0"></altera:connection_parameter>
|
|
</altera:connection>
|
|
</altera:connections>
|
|
<altera:interconnect_requirements></altera:interconnect_requirements>
|
|
<altera:wire_level_connections></altera:wire_level_connections>
|
|
<altera:hdl_parameters></altera:hdl_parameters>
|
|
<altera:hdl_parameter_mappings></altera:hdl_parameter_mappings>
|
|
<altera:preserved_ports_for_debug></altera:preserved_ports_for_debug>
|
|
<altera:altera_group_hierarchy_contents></altera:altera_group_hierarchy_contents>
|
|
<altera:altera_interface_boundary>
|
|
<altera:interface_mapping altera:name="emif_hps_emif_mem_0" altera:internal="emif_hps.mem_0" altera:type="conduit" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="emif_hps_emif_mem_ck_0" altera:internal="emif_hps.mem_ck_0" altera:type="conduit" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="emif_hps_emif_mem_reset_n" altera:internal="emif_hps.mem_reset_n" altera:type="conduit" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="emif_hps_emif_oct_0" altera:internal="emif_hps.oct_0" altera:type="conduit" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="emif_hps_emif_ref_clk" altera:internal="emif_hps.ref_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="f2h_irq0_in" altera:internal="agilex_hps.fpga2hps_interrupt_irq0" altera:type="interrupt" altera:dir="start"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="f2h_irq1_in" altera:internal="agilex_hps.fpga2hps_interrupt_irq1" altera:type="interrupt" altera:dir="start"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="f2sdram" altera:internal="agilex_hps.f2sdram" altera:type="axi4" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="f2sdram_clk" altera:internal="agilex_hps.f2sdram_axi_clock" altera:type="clock" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="f2sdram_rst" altera:internal="agilex_hps.f2sdram_axi_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="fpga2hps" altera:internal="agilex_hps.fpga2hps"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="fpga2hps_clk" altera:internal="agilex_hps.fpga2hps_clock"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="fpga2hps_rst" altera:internal="agilex_hps.fpga2hps_reset"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="h2f_reset" altera:internal="agilex_hps.h2f_reset" altera:type="reset" altera:dir="start"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="h2f_warm_reset_handshake" altera:internal="agilex_hps.h2f_warm_reset_handshake" altera:type="conduit" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="hps2fpga" altera:internal="agilex_hps.hps2fpga" altera:type="axi4" altera:dir="start"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="hps2fpga_clk" altera:internal="agilex_hps.hps2fpga_axi_clock" altera:type="clock" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="hps2fpga_rst" altera:internal="agilex_hps.hps2fpga_axi_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="hps_io" altera:internal="agilex_hps.hps_io" altera:type="conduit" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="lwhps2fpga" altera:internal="agilex_hps.lwhps2fpga" altera:type="axi4" altera:dir="start"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="lwhps2fpga_clk" altera:internal="agilex_hps.lwhps2fpga_axi_clock" altera:type="clock" altera:dir="end"></altera:interface_mapping>
|
|
<altera:interface_mapping altera:name="lwhps2fpga_rst" altera:internal="agilex_hps.lwhps2fpga_axi_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
|
|
</altera:altera_interface_boundary>
|
|
<ipxact:components>
|
|
<ipxact:component>
|
|
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
|
<ipxact:library>addressMap</ipxact:library>
|
|
<ipxact:name>addressMap</ipxact:name>
|
|
<ipxact:version>1.0</ipxact:version>
|
|
<ipxact:busInterfaces>
|
|
<ipxact:busInterface>
|
|
<ipxact:name>agilex_hps.hps2fpga</ipxact:name>
|
|
<ipxact:busType vendor="intel" library="intel" name="axi4" version="25.3"></ipxact:busType>
|
|
<ipxact:master></ipxact:master>
|
|
</ipxact:busInterface>
|
|
<ipxact:busInterface>
|
|
<ipxact:name>agilex_hps.lwhps2fpga</ipxact:name>
|
|
<ipxact:busType vendor="intel" library="intel" name="axi4" version="25.3"></ipxact:busType>
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<ipxact:master></ipxact:master>
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|
</ipxact:busInterface>
|
|
</ipxact:busInterfaces>
|
|
<ipxact:addressSpaces></ipxact:addressSpaces>
|
|
<ipxact:memoryMaps></ipxact:memoryMaps>
|
|
</ipxact:component>
|
|
</ipxact:components>
|
|
<altera:altera_has_warnings>false</altera:altera_has_warnings>
|
|
<altera:altera_has_errors>false</altera:altera_has_errors>
|
|
</ipxact:vendorExtensions>
|
|
</ipxact:design> |