Altera Corporation
hps_subsys
hps_subsys
1.0
$${FILENAME}
$${FILENAME}
1.0
Systems
QsysPro
board
Board
default
bonusData
bonusData
bonusData
{
element agilex_hps
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element emif_hps
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
}
cpuInfo
cpuInfo
designId
designId
device
Device
A5EB013BB23BE4SCS
deviceFamily
Device family
Agilex 5
deviceSpeedGrade
Device Speed Grade
4
dflBitArray
dflBitArray
fabricMode
fabricMode
QSYS
generateLegacySim
generateLegacySim
false
generationId
Generation Id
0
globalResetBus
Global reset
false
hdlLanguage
hdlLanguage
VERILOG
hideFromIPCatalog
Hide from IP Catalog
false
lockedInterfaceDefinition
lockedInterfaceDefinition
sopcBorderPoints
Use SOPC Builder port naming
false
systemHash
systemHash
0
systemInfos
systemInfos
<systemInfosDefinition>
<connPtSystemInfos>
<entry>
<key>f2sdram</key>
<value>
<connectionPointName>f2sdram</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CPU_INFO_ID</key>
<value></value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value><address-map><slave name='agilex_hps.f2sdram' start='0x0' end='0x100000000' datawidth='256' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>32</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
<value>256</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
</connPtSystemInfos>
</systemInfosDefinition>
systemScripts
systemScripts
testBenchDutName
Use Test Bench Naming Pattern
timeStamp
timeStamp
0
useTestBenchNamingPattern
Use Test Bench Naming Pattern
false
Altera Corporation
agilex_hps
altera_generic_component
1.0
bspCpu
BSP CPU
true
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>h2f_reset</name>
<type>reset</type>
<isStart>true</isStart>
<ports>
<port>
<name>h2f_reset_reset</name>
<role>reset</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedDirectReset</key>
</entry>
<entry>
<key>associatedResetSinks</key>
<value>none</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps2fpga_axi_clock</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>hps2fpga_axi_clock_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps2fpga_axi_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>hps2fpga_axi_reset_reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps2fpga</name>
<type>axi4</type>
<isStart>true</isStart>
<ports>
<port>
<name>hps2fpga_awid</name>
<role>awid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awaddr</name>
<role>awaddr</role>
<direction>Output</direction>
<width>38</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awlen</name>
<role>awlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awsize</name>
<role>awsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awburst</name>
<role>awburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awlock</name>
<role>awlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awcache</name>
<role>awcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awprot</name>
<role>awprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awvalid</name>
<role>awvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awready</name>
<role>awready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wdata</name>
<role>wdata</role>
<direction>Output</direction>
<width>128</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wstrb</name>
<role>wstrb</role>
<direction>Output</direction>
<width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wlast</name>
<role>wlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wvalid</name>
<role>wvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wready</name>
<role>wready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bid</name>
<role>bid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bresp</name>
<role>bresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bvalid</name>
<role>bvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bready</name>
<role>bready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arid</name>
<role>arid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_araddr</name>
<role>araddr</role>
<direction>Output</direction>
<width>38</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arlen</name>
<role>arlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arsize</name>
<role>arsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arburst</name>
<role>arburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arlock</name>
<role>arlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arcache</name>
<role>arcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arprot</name>
<role>arprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arvalid</name>
<role>arvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arready</name>
<role>arready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rid</name>
<role>rid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rdata</name>
<role>rdata</role>
<direction>Input</direction>
<width>128</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rresp</name>
<role>rresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rlast</name>
<role>rlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rvalid</name>
<role>rvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rready</name>
<role>rready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>hps2fpga_axi_clock</value>
</entry>
<entry>
<key>associatedReset</key>
<value>hps2fpga_axi_reset</value>
</entry>
<entry>
<key>optionalAssociatedReset</key>
<value>false</value>
</entry>
<entry>
<key>trustzoneAware</key>
<value>true</value>
</entry>
<entry>
<key>wakeupSignals</key>
<value>false</value>
</entry>
<entry>
<key>uniqueIdSupport</key>
<value>false</value>
</entry>
<entry>
<key>poison</key>
<value>false</value>
</entry>
<entry>
<key>traceSignals</key>
<value>false</value>
</entry>
<entry>
<key>isTranslator</key>
<value>false</value>
</entry>
<entry>
<key>maximumOutstandingReads</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingWrites</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingTransactions</key>
<value>1</value>
</entry>
<entry>
<key>dataCheck</key>
<value>false</value>
</entry>
<entry>
<key>addressCheck</key>
<value>false</value>
</entry>
<entry>
<key>securityAttribute</key>
<value>false</value>
</entry>
<entry>
<key>userData</key>
<value>false</value>
</entry>
<entry>
<key>readIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>writeIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>combinedIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>enableConcurrentSubordinateAccess</key>
<value>0</value>
</entry>
<entry>
<key>noRepeatedIdsBetweenSubordinates</key>
<value>0</value>
</entry>
<entry>
<key>issuesINCRBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesWRAPBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesFIXEDBursts</key>
<value>true</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>lwhps2fpga_axi_clock</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>lwhps2fpga_axi_clock_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>lwhps2fpga_axi_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>lwhps2fpga_axi_reset_reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>lwhps2fpga</name>
<type>axi4</type>
<isStart>true</isStart>
<ports>
<port>
<name>lwhps2fpga_awid</name>
<role>awid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awaddr</name>
<role>awaddr</role>
<direction>Output</direction>
<width>29</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awlen</name>
<role>awlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awsize</name>
<role>awsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awburst</name>
<role>awburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awlock</name>
<role>awlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awcache</name>
<role>awcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awprot</name>
<role>awprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awvalid</name>
<role>awvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awready</name>
<role>awready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wdata</name>
<role>wdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wstrb</name>
<role>wstrb</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wlast</name>
<role>wlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wvalid</name>
<role>wvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wready</name>
<role>wready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bid</name>
<role>bid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bresp</name>
<role>bresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bvalid</name>
<role>bvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bready</name>
<role>bready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arid</name>
<role>arid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_araddr</name>
<role>araddr</role>
<direction>Output</direction>
<width>29</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arlen</name>
<role>arlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arsize</name>
<role>arsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arburst</name>
<role>arburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arlock</name>
<role>arlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arcache</name>
<role>arcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arprot</name>
<role>arprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arvalid</name>
<role>arvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arready</name>
<role>arready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rid</name>
<role>rid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rdata</name>
<role>rdata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rresp</name>
<role>rresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rlast</name>
<role>rlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rvalid</name>
<role>rvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rready</name>
<role>rready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>lwhps2fpga_axi_clock</value>
</entry>
<entry>
<key>associatedReset</key>
<value>lwhps2fpga_axi_reset</value>
</entry>
<entry>
<key>optionalAssociatedReset</key>
<value>false</value>
</entry>
<entry>
<key>trustzoneAware</key>
<value>true</value>
</entry>
<entry>
<key>wakeupSignals</key>
<value>false</value>
</entry>
<entry>
<key>uniqueIdSupport</key>
<value>false</value>
</entry>
<entry>
<key>poison</key>
<value>false</value>
</entry>
<entry>
<key>traceSignals</key>
<value>false</value>
</entry>
<entry>
<key>isTranslator</key>
<value>false</value>
</entry>
<entry>
<key>maximumOutstandingReads</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingWrites</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingTransactions</key>
<value>1</value>
</entry>
<entry>
<key>dataCheck</key>
<value>false</value>
</entry>
<entry>
<key>addressCheck</key>
<value>false</value>
</entry>
<entry>
<key>securityAttribute</key>
<value>false</value>
</entry>
<entry>
<key>userData</key>
<value>false</value>
</entry>
<entry>
<key>readIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>writeIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>combinedIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>enableConcurrentSubordinateAccess</key>
<value>0</value>
</entry>
<entry>
<key>noRepeatedIdsBetweenSubordinates</key>
<value>0</value>
</entry>
<entry>
<key>issuesINCRBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesWRAPBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesFIXEDBursts</key>
<value>true</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>emac0_app_rst</name>
<type>reset</type>
<isStart>true</isStart>
<ports>
<port>
<name>emac0_app_rst_reset_n</name>
<role>reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedDirectReset</key>
</entry>
<entry>
<key>associatedResetSinks</key>
<value>none</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>h2f_warm_reset_handshake</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>h2f_warm_reset_handshake_reset_req</name>
<role>reset_req</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>h2f_warm_reset_handshake_reset_ack</name>
<role>reset_ack</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps_io</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>hps_io_hps_osc_clk</name>
<role>hps_osc_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data0</name>
<role>sdmmc_data0</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data1</name>
<role>sdmmc_data1</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_cclk</name>
<role>sdmmc_cclk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data2</name>
<role>sdmmc_data2</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data3</name>
<role>sdmmc_data3</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_cmd</name>
<role>sdmmc_cmd</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_clk</name>
<role>usb0_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_stp</name>
<role>usb0_stp</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_dir</name>
<role>usb0_dir</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data0</name>
<role>usb0_data0</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data1</name>
<role>usb0_data1</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_nxt</name>
<role>usb0_nxt</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data2</name>
<role>usb0_data2</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data3</name>
<role>usb0_data3</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data4</name>
<role>usb0_data4</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data5</name>
<role>usb0_data5</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data6</name>
<role>usb0_data6</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data7</name>
<role>usb0_data7</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_tx_clk</name>
<role>emac0_tx_clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_tx_ctl</name>
<role>emac0_tx_ctl</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rx_clk</name>
<role>emac0_rx_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rx_ctl</name>
<role>emac0_rx_ctl</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd0</name>
<role>emac0_txd0</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd1</name>
<role>emac0_txd1</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd0</name>
<role>emac0_rxd0</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd1</name>
<role>emac0_rxd1</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd2</name>
<role>emac0_txd2</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd3</name>
<role>emac0_txd3</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd2</name>
<role>emac0_rxd2</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd3</name>
<role>emac0_rxd3</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_mdio0_mdio</name>
<role>mdio0_mdio</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_mdio0_mdc</name>
<role>mdio0_mdc</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_uart1_tx</name>
<role>uart1_tx</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_uart1_rx</name>
<role>uart1_rx</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_i2c1_sda</name>
<role>i2c1_sda</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_i2c1_scl</name>
<role>i2c1_scl</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio28</name>
<role>gpio28</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio34</name>
<role>gpio34</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio40</name>
<role>gpio40</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio41</name>
<role>gpio41</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>fpga2hps_interrupt_irq1</name>
<type>interrupt</type>
<isStart>true</isStart>
<ports>
<port>
<name>fpga2hps_interrupt_irq1_irq</name>
<role>irq</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
</entry>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
<value></value>
</entry>
<entry>
<key>irqMap</key>
</entry>
<entry>
<key>irqScheme</key>
<value>INDIVIDUAL_REQUESTS</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>fpga2hps_interrupt_irq0</name>
<type>interrupt</type>
<isStart>true</isStart>
<ports>
<port>
<name>fpga2hps_interrupt_irq0_irq</name>
<role>irq</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
</entry>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
<value></value>
</entry>
<entry>
<key>irqMap</key>
</entry>
<entry>
<key>irqScheme</key>
<value>INDIVIDUAL_REQUESTS</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>f2sdram_axi_clock</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>f2sdram_axi_clock_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>f2sdram_axi_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>f2sdram_axi_reset_reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>f2sdram</name>
<type>axi4</type>
<isStart>false</isStart>
<ports>
<port>
<name>f2sdram_araddr</name>
<role>araddr</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arburst</name>
<role>arburst</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arcache</name>
<role>arcache</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arid</name>
<role>arid</role>
<direction>Input</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arlen</name>
<role>arlen</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arlock</name>
<role>arlock</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arprot</name>
<role>arprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arqos</name>
<role>arqos</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arready</name>
<role>arready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arsize</name>
<role>arsize</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arvalid</name>
<role>arvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awaddr</name>
<role>awaddr</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awburst</name>
<role>awburst</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awcache</name>
<role>awcache</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awid</name>
<role>awid</role>
<direction>Input</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awlen</name>
<role>awlen</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awlock</name>
<role>awlock</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awprot</name>
<role>awprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awqos</name>
<role>awqos</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awready</name>
<role>awready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awsize</name>
<role>awsize</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awvalid</name>
<role>awvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bid</name>
<role>bid</role>
<direction>Output</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bready</name>
<role>bready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bresp</name>
<role>bresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bvalid</name>
<role>bvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rdata</name>
<role>rdata</role>
<direction>Output</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rid</name>
<role>rid</role>
<direction>Output</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rlast</name>
<role>rlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rready</name>
<role>rready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rresp</name>
<role>rresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rvalid</name>
<role>rvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wdata</name>
<role>wdata</role>
<direction>Input</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wlast</name>
<role>wlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wready</name>
<role>wready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wstrb</name>
<role>wstrb</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wvalid</name>
<role>wvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_aruser</name>
<role>aruser</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awuser</name>
<role>awuser</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wuser</name>
<role>wuser</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_buser</name>
<role>buser</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arregion</name>
<role>arregion</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_ruser</name>
<role>ruser</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awregion</name>
<role>awregion</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>f2sdram_axi_clock</value>
</entry>
<entry>
<key>associatedReset</key>
<value>f2sdram_axi_reset</value>
</entry>
<entry>
<key>optionalAssociatedReset</key>
<value>false</value>
</entry>
<entry>
<key>trustzoneAware</key>
<value>true</value>
</entry>
<entry>
<key>wakeupSignals</key>
<value>false</value>
</entry>
<entry>
<key>uniqueIdSupport</key>
<value>false</value>
</entry>
<entry>
<key>poison</key>
<value>false</value>
</entry>
<entry>
<key>traceSignals</key>
<value>false</value>
</entry>
<entry>
<key>isTranslator</key>
<value>false</value>
</entry>
<entry>
<key>maximumOutstandingReads</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingWrites</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingTransactions</key>
<value>1</value>
</entry>
<entry>
<key>dataCheck</key>
<value>false</value>
</entry>
<entry>
<key>addressCheck</key>
<value>false</value>
</entry>
<entry>
<key>securityAttribute</key>
<value>false</value>
</entry>
<entry>
<key>userData</key>
<value>false</value>
</entry>
<entry>
<key>readAcceptanceCapability</key>
<value>16</value>
</entry>
<entry>
<key>writeAcceptanceCapability</key>
<value>16</value>
</entry>
<entry>
<key>combinedAcceptanceCapability</key>
<value>16</value>
</entry>
<entry>
<key>readDataReorderingDepth</key>
<value>1</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
<entry>
<key>noNarrowTransfer</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>io96b0_to_hps</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>io96b0_to_hps_ch0_axil_clk</name>
<role>ch0_axil_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_reset_n</name>
<role>ch0_axil_reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_arready</name>
<role>ch0_axil_arready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_awready</name>
<role>ch0_axil_awready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_bresp</name>
<role>ch0_axil_bresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_bvalid</name>
<role>ch0_axil_bvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_rdata</name>
<role>ch0_axil_rdata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_rresp</name>
<role>ch0_axil_rresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_rvalid</name>
<role>ch0_axil_rvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_wready</name>
<role>ch0_axil_wready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_araddr</name>
<role>ch0_axil_araddr</role>
<direction>Output</direction>
<width>27</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_arvalid</name>
<role>ch0_axil_arvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_awaddr</name>
<role>ch0_axil_awaddr</role>
<direction>Output</direction>
<width>27</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_awvalid</name>
<role>ch0_axil_awvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_bready</name>
<role>ch0_axil_bready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_rready</name>
<role>ch0_axil_rready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_wdata</name>
<role>ch0_axil_wdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_wstrb</name>
<role>ch0_axil_wstrb</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_wvalid</name>
<role>ch0_axil_wvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_arprot</name>
<role>ch0_axil_arprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_awprot</name>
<role>ch0_axil_awprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_clk</name>
<role>axi4_ch0_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_reset_n</name>
<role>axi4_ch0_reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arready</name>
<role>axi4_ch0_arready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awready</name>
<role>axi4_ch0_awready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_bid</name>
<role>axi4_ch0_bid</role>
<direction>Input</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_bresp</name>
<role>axi4_ch0_bresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_bvalid</name>
<role>axi4_ch0_bvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rdata</name>
<role>axi4_ch0_rdata</role>
<direction>Input</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rid</name>
<role>axi4_ch0_rid</role>
<direction>Input</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rlast</name>
<role>axi4_ch0_rlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rresp</name>
<role>axi4_ch0_rresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_ruser</name>
<role>axi4_ch0_ruser</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rvalid</name>
<role>axi4_ch0_rvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wready</name>
<role>axi4_ch0_wready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_araddr</name>
<role>axi4_ch0_araddr</role>
<direction>Output</direction>
<width>40</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arburst</name>
<role>axi4_ch0_arburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arid</name>
<role>axi4_ch0_arid</role>
<direction>Output</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arlen</name>
<role>axi4_ch0_arlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arlock</name>
<role>axi4_ch0_arlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arqos</name>
<role>axi4_ch0_arqos</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arsize</name>
<role>axi4_ch0_arsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_aruser</name>
<role>axi4_ch0_aruser</role>
<direction>Output</direction>
<width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arvalid</name>
<role>axi4_ch0_arvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awaddr</name>
<role>axi4_ch0_awaddr</role>
<direction>Output</direction>
<width>40</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awburst</name>
<role>axi4_ch0_awburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awid</name>
<role>axi4_ch0_awid</role>
<direction>Output</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awlen</name>
<role>axi4_ch0_awlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awlock</name>
<role>axi4_ch0_awlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awqos</name>
<role>axi4_ch0_awqos</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awsize</name>
<role>axi4_ch0_awsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awuser</name>
<role>axi4_ch0_awuser</role>
<direction>Output</direction>
<width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awvalid</name>
<role>axi4_ch0_awvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_bready</name>
<role>axi4_ch0_bready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rready</name>
<role>axi4_ch0_rready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wdata</name>
<role>axi4_ch0_wdata</role>
<direction>Output</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wlast</name>
<role>axi4_ch0_wlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wstrb</name>
<role>axi4_ch0_wstrb</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wuser</name>
<role>axi4_ch0_wuser</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wvalid</name>
<role>axi4_ch0_wvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arprot</name>
<role>axi4_ch0_arprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awprot</name>
<role>axi4_ch0_awprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>intel_agilex_5_soc</className>
<version>13.0.0</version>
<displayName>Hard Processor System IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>AUTO_BOARD</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>BOARD</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>device_family</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>device_name</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>device_trait_iobank_rev</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfoArgs>DEVICE_IOBANK_REVISION</systemInfoArgs>
<systemInfotype>PART_TRAIT</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>f2sdram</key>
<value>
<connectionPointName>f2sdram</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value><address-map><slave name='f2sdram' start='0x0' end='0x100000000' datawidth='256' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>32</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
<value>256</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>h2f_reset</name>
<type>reset</type>
<isStart>true</isStart>
<ports>
<port>
<name>h2f_reset_reset</name>
<role>reset</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedDirectReset</key>
</entry>
<entry>
<key>associatedResetSinks</key>
<value>none</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps2fpga_axi_clock</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>hps2fpga_axi_clock_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps2fpga_axi_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>hps2fpga_axi_reset_reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps2fpga</name>
<type>axi4</type>
<isStart>true</isStart>
<ports>
<port>
<name>hps2fpga_awid</name>
<role>awid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awaddr</name>
<role>awaddr</role>
<direction>Output</direction>
<width>38</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awlen</name>
<role>awlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awsize</name>
<role>awsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awburst</name>
<role>awburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awlock</name>
<role>awlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awcache</name>
<role>awcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awprot</name>
<role>awprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awvalid</name>
<role>awvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awready</name>
<role>awready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wdata</name>
<role>wdata</role>
<direction>Output</direction>
<width>128</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wstrb</name>
<role>wstrb</role>
<direction>Output</direction>
<width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wlast</name>
<role>wlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wvalid</name>
<role>wvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wready</name>
<role>wready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bid</name>
<role>bid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bresp</name>
<role>bresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bvalid</name>
<role>bvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bready</name>
<role>bready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arid</name>
<role>arid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_araddr</name>
<role>araddr</role>
<direction>Output</direction>
<width>38</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arlen</name>
<role>arlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arsize</name>
<role>arsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arburst</name>
<role>arburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arlock</name>
<role>arlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arcache</name>
<role>arcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arprot</name>
<role>arprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arvalid</name>
<role>arvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arready</name>
<role>arready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rid</name>
<role>rid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rdata</name>
<role>rdata</role>
<direction>Input</direction>
<width>128</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rresp</name>
<role>rresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rlast</name>
<role>rlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rvalid</name>
<role>rvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rready</name>
<role>rready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>hps2fpga_axi_clock</value>
</entry>
<entry>
<key>associatedReset</key>
<value>hps2fpga_axi_reset</value>
</entry>
<entry>
<key>optionalAssociatedReset</key>
<value>false</value>
</entry>
<entry>
<key>trustzoneAware</key>
<value>true</value>
</entry>
<entry>
<key>wakeupSignals</key>
<value>false</value>
</entry>
<entry>
<key>uniqueIdSupport</key>
<value>false</value>
</entry>
<entry>
<key>poison</key>
<value>false</value>
</entry>
<entry>
<key>traceSignals</key>
<value>false</value>
</entry>
<entry>
<key>isTranslator</key>
<value>false</value>
</entry>
<entry>
<key>maximumOutstandingReads</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingWrites</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingTransactions</key>
<value>1</value>
</entry>
<entry>
<key>dataCheck</key>
<value>false</value>
</entry>
<entry>
<key>addressCheck</key>
<value>false</value>
</entry>
<entry>
<key>securityAttribute</key>
<value>false</value>
</entry>
<entry>
<key>userData</key>
<value>false</value>
</entry>
<entry>
<key>readIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>writeIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>combinedIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>enableConcurrentSubordinateAccess</key>
<value>0</value>
</entry>
<entry>
<key>noRepeatedIdsBetweenSubordinates</key>
<value>0</value>
</entry>
<entry>
<key>issuesINCRBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesWRAPBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesFIXEDBursts</key>
<value>true</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>lwhps2fpga_axi_clock</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>lwhps2fpga_axi_clock_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>lwhps2fpga_axi_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>lwhps2fpga_axi_reset_reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>lwhps2fpga</name>
<type>axi4</type>
<isStart>true</isStart>
<ports>
<port>
<name>lwhps2fpga_awid</name>
<role>awid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awaddr</name>
<role>awaddr</role>
<direction>Output</direction>
<width>29</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awlen</name>
<role>awlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awsize</name>
<role>awsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awburst</name>
<role>awburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awlock</name>
<role>awlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awcache</name>
<role>awcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awprot</name>
<role>awprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awvalid</name>
<role>awvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awready</name>
<role>awready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wdata</name>
<role>wdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wstrb</name>
<role>wstrb</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wlast</name>
<role>wlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wvalid</name>
<role>wvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wready</name>
<role>wready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bid</name>
<role>bid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bresp</name>
<role>bresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bvalid</name>
<role>bvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bready</name>
<role>bready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arid</name>
<role>arid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_araddr</name>
<role>araddr</role>
<direction>Output</direction>
<width>29</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arlen</name>
<role>arlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arsize</name>
<role>arsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arburst</name>
<role>arburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arlock</name>
<role>arlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arcache</name>
<role>arcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arprot</name>
<role>arprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arvalid</name>
<role>arvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arready</name>
<role>arready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rid</name>
<role>rid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rdata</name>
<role>rdata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rresp</name>
<role>rresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rlast</name>
<role>rlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rvalid</name>
<role>rvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rready</name>
<role>rready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>lwhps2fpga_axi_clock</value>
</entry>
<entry>
<key>associatedReset</key>
<value>lwhps2fpga_axi_reset</value>
</entry>
<entry>
<key>optionalAssociatedReset</key>
<value>false</value>
</entry>
<entry>
<key>trustzoneAware</key>
<value>true</value>
</entry>
<entry>
<key>wakeupSignals</key>
<value>false</value>
</entry>
<entry>
<key>uniqueIdSupport</key>
<value>false</value>
</entry>
<entry>
<key>poison</key>
<value>false</value>
</entry>
<entry>
<key>traceSignals</key>
<value>false</value>
</entry>
<entry>
<key>isTranslator</key>
<value>false</value>
</entry>
<entry>
<key>maximumOutstandingReads</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingWrites</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingTransactions</key>
<value>1</value>
</entry>
<entry>
<key>dataCheck</key>
<value>false</value>
</entry>
<entry>
<key>addressCheck</key>
<value>false</value>
</entry>
<entry>
<key>securityAttribute</key>
<value>false</value>
</entry>
<entry>
<key>userData</key>
<value>false</value>
</entry>
<entry>
<key>readIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>writeIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>combinedIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>enableConcurrentSubordinateAccess</key>
<value>0</value>
</entry>
<entry>
<key>noRepeatedIdsBetweenSubordinates</key>
<value>0</value>
</entry>
<entry>
<key>issuesINCRBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesWRAPBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesFIXEDBursts</key>
<value>true</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>emac0_app_rst</name>
<type>reset</type>
<isStart>true</isStart>
<ports>
<port>
<name>emac0_app_rst_reset_n</name>
<role>reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedDirectReset</key>
</entry>
<entry>
<key>associatedResetSinks</key>
<value>none</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>h2f_warm_reset_handshake</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>h2f_warm_reset_handshake_reset_req</name>
<role>reset_req</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>h2f_warm_reset_handshake_reset_ack</name>
<role>reset_ack</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps_io</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>hps_io_hps_osc_clk</name>
<role>hps_osc_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data0</name>
<role>sdmmc_data0</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data1</name>
<role>sdmmc_data1</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_cclk</name>
<role>sdmmc_cclk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data2</name>
<role>sdmmc_data2</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data3</name>
<role>sdmmc_data3</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_cmd</name>
<role>sdmmc_cmd</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_clk</name>
<role>usb0_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_stp</name>
<role>usb0_stp</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_dir</name>
<role>usb0_dir</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data0</name>
<role>usb0_data0</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data1</name>
<role>usb0_data1</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_nxt</name>
<role>usb0_nxt</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data2</name>
<role>usb0_data2</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data3</name>
<role>usb0_data3</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data4</name>
<role>usb0_data4</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data5</name>
<role>usb0_data5</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data6</name>
<role>usb0_data6</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data7</name>
<role>usb0_data7</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_tx_clk</name>
<role>emac0_tx_clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_tx_ctl</name>
<role>emac0_tx_ctl</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rx_clk</name>
<role>emac0_rx_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rx_ctl</name>
<role>emac0_rx_ctl</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd0</name>
<role>emac0_txd0</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd1</name>
<role>emac0_txd1</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd0</name>
<role>emac0_rxd0</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd1</name>
<role>emac0_rxd1</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd2</name>
<role>emac0_txd2</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd3</name>
<role>emac0_txd3</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd2</name>
<role>emac0_rxd2</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd3</name>
<role>emac0_rxd3</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_mdio0_mdio</name>
<role>mdio0_mdio</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_mdio0_mdc</name>
<role>mdio0_mdc</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_uart1_tx</name>
<role>uart1_tx</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_uart1_rx</name>
<role>uart1_rx</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_i2c1_sda</name>
<role>i2c1_sda</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_i2c1_scl</name>
<role>i2c1_scl</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio28</name>
<role>gpio28</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio34</name>
<role>gpio34</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio40</name>
<role>gpio40</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio41</name>
<role>gpio41</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>fpga2hps_interrupt_irq1</name>
<type>interrupt</type>
<isStart>true</isStart>
<ports>
<port>
<name>fpga2hps_interrupt_irq1_irq</name>
<role>irq</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
</entry>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
<value></value>
</entry>
<entry>
<key>irqMap</key>
</entry>
<entry>
<key>irqScheme</key>
<value>INDIVIDUAL_REQUESTS</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>fpga2hps_interrupt_irq0</name>
<type>interrupt</type>
<isStart>true</isStart>
<ports>
<port>
<name>fpga2hps_interrupt_irq0_irq</name>
<role>irq</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
</entry>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
<value></value>
</entry>
<entry>
<key>irqMap</key>
</entry>
<entry>
<key>irqScheme</key>
<value>INDIVIDUAL_REQUESTS</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>f2sdram_axi_clock</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>f2sdram_axi_clock_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>f2sdram_axi_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>f2sdram_axi_reset_reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>f2sdram</name>
<type>axi4</type>
<isStart>false</isStart>
<ports>
<port>
<name>f2sdram_araddr</name>
<role>araddr</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arburst</name>
<role>arburst</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arcache</name>
<role>arcache</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arid</name>
<role>arid</role>
<direction>Input</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arlen</name>
<role>arlen</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arlock</name>
<role>arlock</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arprot</name>
<role>arprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arqos</name>
<role>arqos</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arready</name>
<role>arready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arsize</name>
<role>arsize</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arvalid</name>
<role>arvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awaddr</name>
<role>awaddr</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awburst</name>
<role>awburst</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awcache</name>
<role>awcache</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awid</name>
<role>awid</role>
<direction>Input</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awlen</name>
<role>awlen</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awlock</name>
<role>awlock</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awprot</name>
<role>awprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awqos</name>
<role>awqos</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awready</name>
<role>awready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awsize</name>
<role>awsize</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awvalid</name>
<role>awvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bid</name>
<role>bid</role>
<direction>Output</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bready</name>
<role>bready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bresp</name>
<role>bresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bvalid</name>
<role>bvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rdata</name>
<role>rdata</role>
<direction>Output</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rid</name>
<role>rid</role>
<direction>Output</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rlast</name>
<role>rlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rready</name>
<role>rready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rresp</name>
<role>rresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rvalid</name>
<role>rvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wdata</name>
<role>wdata</role>
<direction>Input</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wlast</name>
<role>wlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wready</name>
<role>wready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wstrb</name>
<role>wstrb</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wvalid</name>
<role>wvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_aruser</name>
<role>aruser</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awuser</name>
<role>awuser</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wuser</name>
<role>wuser</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_buser</name>
<role>buser</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arregion</name>
<role>arregion</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_ruser</name>
<role>ruser</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awregion</name>
<role>awregion</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>f2sdram_axi_clock</value>
</entry>
<entry>
<key>associatedReset</key>
<value>f2sdram_axi_reset</value>
</entry>
<entry>
<key>optionalAssociatedReset</key>
<value>false</value>
</entry>
<entry>
<key>trustzoneAware</key>
<value>true</value>
</entry>
<entry>
<key>wakeupSignals</key>
<value>false</value>
</entry>
<entry>
<key>uniqueIdSupport</key>
<value>false</value>
</entry>
<entry>
<key>poison</key>
<value>false</value>
</entry>
<entry>
<key>traceSignals</key>
<value>false</value>
</entry>
<entry>
<key>isTranslator</key>
<value>false</value>
</entry>
<entry>
<key>maximumOutstandingReads</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingWrites</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingTransactions</key>
<value>1</value>
</entry>
<entry>
<key>dataCheck</key>
<value>false</value>
</entry>
<entry>
<key>addressCheck</key>
<value>false</value>
</entry>
<entry>
<key>securityAttribute</key>
<value>false</value>
</entry>
<entry>
<key>userData</key>
<value>false</value>
</entry>
<entry>
<key>readAcceptanceCapability</key>
<value>16</value>
</entry>
<entry>
<key>writeAcceptanceCapability</key>
<value>16</value>
</entry>
<entry>
<key>combinedAcceptanceCapability</key>
<value>16</value>
</entry>
<entry>
<key>readDataReorderingDepth</key>
<value>1</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
<entry>
<key>noNarrowTransfer</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>io96b0_to_hps</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>io96b0_to_hps_ch0_axil_clk</name>
<role>ch0_axil_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_reset_n</name>
<role>ch0_axil_reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_arready</name>
<role>ch0_axil_arready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_awready</name>
<role>ch0_axil_awready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_bresp</name>
<role>ch0_axil_bresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_bvalid</name>
<role>ch0_axil_bvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_rdata</name>
<role>ch0_axil_rdata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_rresp</name>
<role>ch0_axil_rresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_rvalid</name>
<role>ch0_axil_rvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_wready</name>
<role>ch0_axil_wready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_araddr</name>
<role>ch0_axil_araddr</role>
<direction>Output</direction>
<width>27</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_arvalid</name>
<role>ch0_axil_arvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_awaddr</name>
<role>ch0_axil_awaddr</role>
<direction>Output</direction>
<width>27</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_awvalid</name>
<role>ch0_axil_awvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_bready</name>
<role>ch0_axil_bready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_rready</name>
<role>ch0_axil_rready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_wdata</name>
<role>ch0_axil_wdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_wstrb</name>
<role>ch0_axil_wstrb</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_wvalid</name>
<role>ch0_axil_wvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_arprot</name>
<role>ch0_axil_arprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_ch0_axil_awprot</name>
<role>ch0_axil_awprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_clk</name>
<role>axi4_ch0_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_reset_n</name>
<role>axi4_ch0_reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arready</name>
<role>axi4_ch0_arready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awready</name>
<role>axi4_ch0_awready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_bid</name>
<role>axi4_ch0_bid</role>
<direction>Input</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_bresp</name>
<role>axi4_ch0_bresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_bvalid</name>
<role>axi4_ch0_bvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rdata</name>
<role>axi4_ch0_rdata</role>
<direction>Input</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rid</name>
<role>axi4_ch0_rid</role>
<direction>Input</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rlast</name>
<role>axi4_ch0_rlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rresp</name>
<role>axi4_ch0_rresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_ruser</name>
<role>axi4_ch0_ruser</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rvalid</name>
<role>axi4_ch0_rvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wready</name>
<role>axi4_ch0_wready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_araddr</name>
<role>axi4_ch0_araddr</role>
<direction>Output</direction>
<width>40</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arburst</name>
<role>axi4_ch0_arburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arid</name>
<role>axi4_ch0_arid</role>
<direction>Output</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arlen</name>
<role>axi4_ch0_arlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arlock</name>
<role>axi4_ch0_arlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arqos</name>
<role>axi4_ch0_arqos</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arsize</name>
<role>axi4_ch0_arsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_aruser</name>
<role>axi4_ch0_aruser</role>
<direction>Output</direction>
<width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arvalid</name>
<role>axi4_ch0_arvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awaddr</name>
<role>axi4_ch0_awaddr</role>
<direction>Output</direction>
<width>40</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awburst</name>
<role>axi4_ch0_awburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awid</name>
<role>axi4_ch0_awid</role>
<direction>Output</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awlen</name>
<role>axi4_ch0_awlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awlock</name>
<role>axi4_ch0_awlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awqos</name>
<role>axi4_ch0_awqos</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awsize</name>
<role>axi4_ch0_awsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awuser</name>
<role>axi4_ch0_awuser</role>
<direction>Output</direction>
<width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awvalid</name>
<role>axi4_ch0_awvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_bready</name>
<role>axi4_ch0_bready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_rready</name>
<role>axi4_ch0_rready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wdata</name>
<role>axi4_ch0_wdata</role>
<direction>Output</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wlast</name>
<role>axi4_ch0_wlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wstrb</name>
<role>axi4_ch0_wstrb</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wuser</name>
<role>axi4_ch0_wuser</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_wvalid</name>
<role>axi4_ch0_wvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_arprot</name>
<role>axi4_ch0_arprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>io96b0_to_hps_axi4_ch0_awprot</name>
<role>axi4_ch0_awprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>agilex_hps</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>agilex_hps</fileSetName>
<fileSetFixedName>agilex_hps</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>agilex_hps</fileSetName>
<fileSetFixedName>agilex_hps</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>agilex_hps</fileSetName>
<fileSetFixedName>agilex_hps</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>agilex_hps</fileSetName>
<fileSetFixedName>agilex_hps</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>agilex_hps</fileSetName>
<fileSetFixedName>agilex_hps</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
intel_agilex_5_soc_inst
logicalView
Logical view
ip/hps_subsys/agilex_hps.ip
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap>
<entry>
<key>embeddedsw.CMacro.CPU_FREQ</key>
<value>50000000u</value>
</entry>
<entry>
<key>embeddedsw.configuration.cpuArchitecture</key>
<value>sm_hps</value>
</entry>
</assignmentValueMap>
</assignmentDefinition>
svInterfaceDefinition
System Verilog Interface definition
transformParameters
Transform Parameters
<transformParameterDescriptorDefinitionList/>
Altera Corporation
emif_hps
altera_generic_component
1.0
bspCpu
BSP CPU
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>io96b0_to_hps</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>s0_noc_axi4lite_clock</name>
<role>ch0_axil_clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_reset_n</name>
<role>ch0_axil_reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_awaddr</name>
<role>ch0_axil_awaddr</role>
<direction>Input</direction>
<width>27</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_awvalid</name>
<role>ch0_axil_awvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_awready</name>
<role>ch0_axil_awready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_araddr</name>
<role>ch0_axil_araddr</role>
<direction>Input</direction>
<width>27</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_arvalid</name>
<role>ch0_axil_arvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_arready</name>
<role>ch0_axil_arready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_wdata</name>
<role>ch0_axil_wdata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_wvalid</name>
<role>ch0_axil_wvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_wready</name>
<role>ch0_axil_wready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_rresp</name>
<role>ch0_axil_rresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_rdata</name>
<role>ch0_axil_rdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_rvalid</name>
<role>ch0_axil_rvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_rready</name>
<role>ch0_axil_rready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_bresp</name>
<role>ch0_axil_bresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_bvalid</name>
<role>ch0_axil_bvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_bready</name>
<role>ch0_axil_bready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_awprot</name>
<role>ch0_axil_awprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_arprot</name>
<role>ch0_axil_arprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_wstrb</name>
<role>ch0_axil_wstrb</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awaddr</name>
<role>axi4_ch0_awaddr</role>
<direction>Input</direction>
<width>40</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awburst</name>
<role>axi4_ch0_awburst</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awid</name>
<role>axi4_ch0_awid</role>
<direction>Input</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awlen</name>
<role>axi4_ch0_awlen</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awlock</name>
<role>axi4_ch0_awlock</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awqos</name>
<role>axi4_ch0_awqos</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awsize</name>
<role>axi4_ch0_awsize</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awvalid</name>
<role>axi4_ch0_awvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awuser</name>
<role>axi4_ch0_awuser</role>
<direction>Input</direction>
<width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awprot</name>
<role>axi4_ch0_awprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awready</name>
<role>axi4_ch0_awready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_araddr</name>
<role>axi4_ch0_araddr</role>
<direction>Input</direction>
<width>40</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arburst</name>
<role>axi4_ch0_arburst</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arid</name>
<role>axi4_ch0_arid</role>
<direction>Input</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arlen</name>
<role>axi4_ch0_arlen</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arlock</name>
<role>axi4_ch0_arlock</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arqos</name>
<role>axi4_ch0_arqos</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arsize</name>
<role>axi4_ch0_arsize</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arvalid</name>
<role>axi4_ch0_arvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_aruser</name>
<role>axi4_ch0_aruser</role>
<direction>Input</direction>
<width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arprot</name>
<role>axi4_ch0_arprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arready</name>
<role>axi4_ch0_arready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wdata</name>
<role>axi4_ch0_wdata</role>
<direction>Input</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wstrb</name>
<role>axi4_ch0_wstrb</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wlast</name>
<role>axi4_ch0_wlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wvalid</name>
<role>axi4_ch0_wvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wready</name>
<role>axi4_ch0_wready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_bready</name>
<role>axi4_ch0_bready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_bid</name>
<role>axi4_ch0_bid</role>
<direction>Output</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_bresp</name>
<role>axi4_ch0_bresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_bvalid</name>
<role>axi4_ch0_bvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rready</name>
<role>axi4_ch0_rready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rdata</name>
<role>axi4_ch0_rdata</role>
<direction>Output</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rid</name>
<role>axi4_ch0_rid</role>
<direction>Output</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rlast</name>
<role>axi4_ch0_rlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rresp</name>
<role>axi4_ch0_rresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rvalid</name>
<role>axi4_ch0_rvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>noc_aclk_0</name>
<role>axi4_ch0_clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>noc_rst_n_0</name>
<role>axi4_ch0_reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wuser</name>
<role>axi4_ch0_wuser</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_ruser</name>
<role>axi4_ch0_ruser</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>mem_0</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>mem_0_cs</name>
<role>mem_cs</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_ca</name>
<role>mem_ca</role>
<direction>Output</direction>
<width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_cke</name>
<role>mem_cke</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_dq</name>
<role>mem_dq</role>
<direction>Bidir</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_dqs_t</name>
<role>mem_dqs_t</role>
<direction>Bidir</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_dqs_c</name>
<role>mem_dqs_c</role>
<direction>Bidir</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_dmi</name>
<role>mem_dmi</role>
<direction>Bidir</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>mem_ck_0</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>mem_0_ck_t</name>
<role>mem_ck_t</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_ck_c</name>
<role>mem_ck_c</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>mem_reset_n</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>mem_0_reset_n</name>
<role>mem_reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>oct_0</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>oct_rzqin_0</name>
<role>oct_rzqin</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>ref_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>ref_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>emif_io96b_hps</className>
<version>4.0.0</version>
<displayName>External Memory Interfaces for HPS IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_BOARD</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>BOARD</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_BOARD_TRAIT</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>BOARD_TRAIT</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_DEVICE</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_DEVICE_BASE_DIE</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfoArgs>BASE_DEVICE</systemInfoArgs>
<systemInfotype>PART_TRAIT</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_DEVICE_DIE_REVISIONS</parameterName>
<parameterType>[Ljava.lang.String;</parameterType>
<systemInfotype>DEVICE_DIE_REVISIONS</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_DEVICE_FAMILY</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_DEVICE_GROUP</parameterName>
<parameterType>[Ljava.lang.String;</parameterType>
<systemInfoArgs>DEVICE_GROUP</systemInfoArgs>
<systemInfotype>DEVICE_INFO</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_DEVICE_IOBANK_REVISION</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfoArgs>DEVICE_IOBANK_REVISION</systemInfoArgs>
<systemInfotype>PART_TRAIT</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_DEVICE_POWER_MODEL</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfoArgs>DEVICE_POWER_MODEL</systemInfoArgs>
<systemInfotype>PART_TRAIT</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_DEVICE_SPEEDGRADE</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_DEVICE_TEMPERATURE_GRADE</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfoArgs>DEVICE_TEMPERATURE_GRADE</systemInfoArgs>
<systemInfotype>PART_TRAIT</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>SYSINFO_SUPPORTS_VID</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfoArgs>SUPPORTS_VID</systemInfoArgs>
<systemInfotype>PART_TRAIT</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos/>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
<cpuInfoDefinition>
<version>1</version>
<cpuGroups/>
<exportedModules/>
<systemInformation>
<name>emif_io96b_hps</name>
<deviceFamily>Agilex 5</deviceFamily>
<generateLegacySim>false</generateLegacySim>
</systemInformation>
</cpuInfoDefinition>
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>io96b0_to_hps</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>s0_noc_axi4lite_clock</name>
<role>ch0_axil_clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_reset_n</name>
<role>ch0_axil_reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_awaddr</name>
<role>ch0_axil_awaddr</role>
<direction>Input</direction>
<width>27</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_awvalid</name>
<role>ch0_axil_awvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_awready</name>
<role>ch0_axil_awready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_araddr</name>
<role>ch0_axil_araddr</role>
<direction>Input</direction>
<width>27</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_arvalid</name>
<role>ch0_axil_arvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_arready</name>
<role>ch0_axil_arready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_wdata</name>
<role>ch0_axil_wdata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_wvalid</name>
<role>ch0_axil_wvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_wready</name>
<role>ch0_axil_wready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_rresp</name>
<role>ch0_axil_rresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_rdata</name>
<role>ch0_axil_rdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_rvalid</name>
<role>ch0_axil_rvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_rready</name>
<role>ch0_axil_rready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_bresp</name>
<role>ch0_axil_bresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_bvalid</name>
<role>ch0_axil_bvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_bready</name>
<role>ch0_axil_bready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_awprot</name>
<role>ch0_axil_awprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_arprot</name>
<role>ch0_axil_arprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_noc_axi4lite_wstrb</name>
<role>ch0_axil_wstrb</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awaddr</name>
<role>axi4_ch0_awaddr</role>
<direction>Input</direction>
<width>40</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awburst</name>
<role>axi4_ch0_awburst</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awid</name>
<role>axi4_ch0_awid</role>
<direction>Input</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awlen</name>
<role>axi4_ch0_awlen</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awlock</name>
<role>axi4_ch0_awlock</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awqos</name>
<role>axi4_ch0_awqos</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awsize</name>
<role>axi4_ch0_awsize</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awvalid</name>
<role>axi4_ch0_awvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awuser</name>
<role>axi4_ch0_awuser</role>
<direction>Input</direction>
<width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awprot</name>
<role>axi4_ch0_awprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_awready</name>
<role>axi4_ch0_awready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_araddr</name>
<role>axi4_ch0_araddr</role>
<direction>Input</direction>
<width>40</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arburst</name>
<role>axi4_ch0_arburst</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arid</name>
<role>axi4_ch0_arid</role>
<direction>Input</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arlen</name>
<role>axi4_ch0_arlen</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arlock</name>
<role>axi4_ch0_arlock</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arqos</name>
<role>axi4_ch0_arqos</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arsize</name>
<role>axi4_ch0_arsize</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arvalid</name>
<role>axi4_ch0_arvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_aruser</name>
<role>axi4_ch0_aruser</role>
<direction>Input</direction>
<width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arprot</name>
<role>axi4_ch0_arprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_arready</name>
<role>axi4_ch0_arready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wdata</name>
<role>axi4_ch0_wdata</role>
<direction>Input</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wstrb</name>
<role>axi4_ch0_wstrb</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wlast</name>
<role>axi4_ch0_wlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wvalid</name>
<role>axi4_ch0_wvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wready</name>
<role>axi4_ch0_wready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_bready</name>
<role>axi4_ch0_bready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_bid</name>
<role>axi4_ch0_bid</role>
<direction>Output</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_bresp</name>
<role>axi4_ch0_bresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_bvalid</name>
<role>axi4_ch0_bvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rready</name>
<role>axi4_ch0_rready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rdata</name>
<role>axi4_ch0_rdata</role>
<direction>Output</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rid</name>
<role>axi4_ch0_rid</role>
<direction>Output</direction>
<width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rlast</name>
<role>axi4_ch0_rlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rresp</name>
<role>axi4_ch0_rresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_rvalid</name>
<role>axi4_ch0_rvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>noc_aclk_0</name>
<role>axi4_ch0_clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>noc_rst_n_0</name>
<role>axi4_ch0_reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_wuser</name>
<role>axi4_ch0_wuser</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>s0_axi4_ruser</name>
<role>axi4_ch0_ruser</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>mem_0</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>mem_0_cs</name>
<role>mem_cs</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_ca</name>
<role>mem_ca</role>
<direction>Output</direction>
<width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_cke</name>
<role>mem_cke</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_dq</name>
<role>mem_dq</role>
<direction>Bidir</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_dqs_t</name>
<role>mem_dqs_t</role>
<direction>Bidir</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_dqs_c</name>
<role>mem_dqs_c</role>
<direction>Bidir</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_dmi</name>
<role>mem_dmi</role>
<direction>Bidir</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>mem_ck_0</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>mem_0_ck_t</name>
<role>mem_ck_t</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>mem_0_ck_c</name>
<role>mem_ck_c</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>mem_reset_n</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>mem_0_reset_n</name>
<role>mem_reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>oct_0</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>oct_rzqin_0</name>
<role>oct_rzqin</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>ref_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>ref_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>emif_io96b_hps</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>emif_io96b_hps</fileSetName>
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>emif_io96b_hps</fileSetName>
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>emif_io96b_hps</fileSetName>
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>emif_io96b_hps</fileSetName>
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>emif_io96b_hps</fileSetName>
<fileSetFixedName>emif_io96b_hps</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
logicalView
Logical view
ip/qsys_top/emif_io96b_hps.ip
moduleAssignmentDefinition
Module Assignments
svInterfaceDefinition
System Verilog Interface definition
transformParameters
Transform Parameters
<transformParameterDescriptorDefinitionList/>
Intel Corporation
addressMap
addressMap
1.0
agilex_hps.hps2fpga
agilex_hps.lwhps2fpga
false
false