thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
150 lines
5.4 KiB
Markdown
150 lines
5.4 KiB
Markdown
# Ch277 closeout — BNEL squash-on-not-taken; qbert hits MMI (PCPYLD) one instruction later
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**Status:** Closed. **Verdict from re-running qbert.elf:**
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`elf_first_unsupported_opcode (pc=0x00112C84 instr=0x71295389)` —
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opcode `0x1C` (R5900 EE **MMI**) + funct `0x09` (MMI2 sub-group)
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+ sa `0x0E` = **PCPYLD** (Parallel Copy Lower Doubleword). qbert
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ran the BNEL correctly (squashed not-taken — PC went 0xC7C →
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0xC84 = +8 bytes, confirming the squash path), then trapped on
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the very next instruction, an MMI/PCPYLD.
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## Numbers
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| Chapter | Blocker | qbert retire_count |
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|---------|---------|---------------------|
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| Post-Ch274 (BEQL) | SD at 0x00112DAC | 26,985 |
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| Post-Ch275 (SD) | DSLL at 0x00112C54 | 27,006 |
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| Post-Ch276 (DSLL) | BNEL at 0x00112C7C | 27,016 |
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| **Post-Ch277 (BNEL)** | **PCPYLD at 0x00112C84** | **27,017** |
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1-retire delta — BNEL itself retired (the squash path), then
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PCPYLD trapped before retiring.
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## What landed
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### RTL — surgical edits in `ee_core_stub.sv`
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1. `localparam OP_BNEL = 6'h15` alongside `OP_BNE`/`OP_BEQL`.
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2. `is_bnel` decode signal.
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3. Added `is_bnel` to the `is_branch` group.
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4. Extended `branch_taken` with `(is_bnel && (rs_val != rt_val))`.
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5. **Generalized the squash signal**: renamed `is_beql_squash`
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to `is_branch_likely_squash`, now covering BEQL (squash on
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`rs == rt`... wait, *not* equal — branch likely SQUASHES on
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the NOT-TAKEN condition) and BNEL (squash on `rs == rt`):
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```sv
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assign is_branch_likely_squash =
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(is_beql && (rs_val != rt_val)) // Ch274 — BEQL not-taken
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|| (is_bnel && (rs_val == rt_val)); // Ch277 — BNEL not-taken
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```
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`retire_advance` updated to reference the new name. Adding
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BLEZL/BGTZL/REGIMM-likely later is now a one-line OR-extension.
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6. Added `!is_bnel` to the `is_nop_class` allow-list.
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About 6 LOC of real change. Pure pattern-reuse from Ch274.
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### Focused TB — `tb_ee_core_bnel.sv`
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Three cases mirroring `tb_ee_core_beql`:
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1. **BNEL TAKEN** (`$t0 = 5`, `$t1 = 7`, differ → taken): branch
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reaches target; delay slot executes (writes a sentinel into
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`$t5`). Cross-check: `$t6 = 0xCAFE` at target.
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2. **BNEL NOT-TAKEN** (`$t2 = $t3 = 3`, equal → squash): delay
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slot squashed. Inline BNE chain verifies `$t5` stays at
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`0xBEEF0000` (the OR-INTO probe didn't execute). `$t7 = 0x2222`
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at PC+8.
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3. **BNE NOT-TAKEN cross-check** (same operands): plain BNE's
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delay slot DOES execute → `$t5 = 0xBABE0CAB`. Proves BNEL
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differs.
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Result: `retired=21 halt=1 trap=0 pc=0xbfc00158 errors=0 PASS`.
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### Makefile + regression
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- `tb_ee_core_bnel` target.
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- Added to both PHONY list and `run:` master.
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- Regression: 164 → **165**.
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## Recommendation for Codex's Ch278 — PCPYLD (MMI2)
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**`pcpyld $t2, $a1, $t1`** at PC `0x00112C84`, instr `0x71295389`.
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Decoded:
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- opcode `0x1C` (MMI prefix)
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- funct `0x09` (MMI2 sub-group selector)
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- sa `0x0E` (PCPYLD sub-instruction)
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- rs `5` (`$a1`), rt `9` (`$t1`), rd `10` (`$t2`)
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PCPYLD architectural semantics (R5900 EE, 128-bit MMI):
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```
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rd[127:64] = rs[63:0] // upper 64 of rd = lower 64 of rs
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rd[63:0] = rt[63:0] // lower 64 of rd = lower 64 of rt
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```
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For our **32-bit register model**:
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- We can't represent `rd[127:64]` (no upper bits).
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- `rd[63:0] = rt[63:0]` collapses to `$rd[31:0] = $rt[31:0]`
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(lower 32 bits).
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**Minimal Ch278 scope**:
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1. Decode the MMI2/PCPYLD path: opcode `0x1C` + funct `0x09` +
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sa `0x0E` → set `is_pcpyld`.
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2. Add to `is_rtype_alu` group.
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3. In `rtype_alu_wb`: `else if (is_pcpyld) rtype_alu_wb = rt_val;`
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(low 32 bits of $rt → $rd).
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4. Add `!is_pcpyld` to `is_nop_class` allow-list.
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Document the approximation explicitly in the RTL: upper bits of
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$rd (which would carry $rs's lower 64 in a real EE) are not
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modelled. For qbert's specific call pattern at this PC, the
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data being shuffled is likely 128-bit packed bytes for a
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strlen-style byte-walker (`$a0 = 0x80808080` is the classic
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"detect high bit per byte" mask); the **low 32 bits** are the
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relevant observable.
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**Important Codex caution**: do NOT NOP-class the entire MMI
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opcode (`0x1C`). MMI has ~80 sub-instructions (MMI0/MMI1/MMI2/
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MMI3 sub-tables); some are real data movement (PCPYLD, PCPYUD,
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PCPYH), some are arithmetic (PADDB, PSUBB, PMULTW), some are
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SIMD compares (PCEQB, PCEQH). Each needs its own decode arm or
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careful approximation. The qbert track is fine with one
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sub-instruction per chapter — same incremental cadence we've
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maintained throughout.
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**Likely follow-ons** after PCPYLD: any other MMI2 op qbert's
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byte-walker uses. Common candidates given the `0x80808080`
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sentinel: **PCEQB** (parallel compare equal byte) and **PMFHL**
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(parallel move from HI/LO).
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## Files changed
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- `rtl/ee/ee_core_stub.sv` — 6 surgical edits.
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- `sim/tb/integration/tb_ee_core_bnel.sv` — new focused TB.
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- `sim/Makefile` — target + both regression lists.
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## Regression
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In flight; expected **165/165**.
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## Pattern review
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Seven qbert chapters (Ch271–Ch277). The qbert-driven track keeps
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producing one chapter per blocker at sub-half-day cadence:
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| Chapter | Blocker | retire_count |
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|---------|---------|--------------|
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| Ch271 SQ | (init) | 12 → 26,958 |
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| Ch272 DADDU | | → 26,960 |
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| Ch273 SYSCALL HLE | | → 26,980 |
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| Ch274 BEQL | | → 26,985 |
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| Ch275 SD | | → 27,006 |
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| Ch276 DSLL | | → 27,016 |
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| **Ch277 BNEL** | | **→ 27,017** |
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The MMI surface (PCPYLD and likely siblings) will broaden the
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opcode count quickly — that's expected when a real program
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starts using SIMD-style operations for stdlib-class work.
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