Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

synth/de25_nano/top_psmct32_raster_demo/files.f

@@ -0,0 +1,115 @@
+# retroDE_ps2 — Ch148 (Ch159 retargeted) synthesis filelist for the
+# DE25-Nano PSMCT32 raster demo.
+#
+# This filelist contains ONLY the modules in the Ch123 dependency tree
+# (audited in Ch144) plus the Ch155+ BRAM wrapper additions. Synthesis
+# tools (Quartus / Vivado) accept this as a `-F filelist.f` argument
+# or import it directly.
+#
+# Ch159 swap: the board-shaped wrapper now instantiates
+# `top_psmct32_raster_demo_bram` (vram_bram_stub-backed) instead of
+# the legacy `top_psmct32_raster_demo` (vram_stub-backed). Both top
+# wrappers are kept compiled below so the file list is forward-
+# compatible with either board-top instantiation; Quartus only
+# elaborates the wrapper actually instantiated by
+# `de25_nano_psmct32_raster_demo_top.sv`.
+#
+# Path convention: relative to the repo root. Tools should be invoked
+# from the repo root, or paths can be made absolute by the project file.
+#
+# To validate the filelist + fixture presence without running synthesis:
+#   make -C sim top_psmct32_raster_demo_synth_check
+
+# ---------------------------------------------------------------------
+# Common debug + trace package (compiled first; type aliases used
+# below).
+# ---------------------------------------------------------------------
+rtl/debug/trace_pkg.sv
+
+# ---------------------------------------------------------------------
+# Memory blocks (BIOS ROM + EE RAM + EE memory map).
+# ---------------------------------------------------------------------
+rtl/memory/bios_rom_stub.sv
+rtl/memory/ee_ram_stub.sv
+rtl/memory/ee_memory_map_stub.sv
+
+# ---------------------------------------------------------------------
+# EE core + GS-priv MMIO bridge.
+# ---------------------------------------------------------------------
+rtl/ee/ee_core_stub.sv
+rtl/gif_gs/ee_gs_priv_bridge_stub.sv
+
+# ---------------------------------------------------------------------
+# DMAC channel-2 (NORMAL transfer; DMAC reads RAM, streams to GIF).
+# ---------------------------------------------------------------------
+rtl/dmac/dmac_reg_stub.sv
+
+# ---------------------------------------------------------------------
+# GIF + GS data plane.
+#
+# Ch159 — both VRAM shapes are kept on the file list:
+#   * `vram_stub`         (legacy byte-addressable + per-bit RMW; used
+#                          by the Ch146 wrapper and every legacy sim TB)
+#   * `vram_bram_stub`    (Ch154 BRAM-friendly, 2048×32-bit, sync-read,
+#                          byte-WE only; used by the Ch155+ wrapper and
+#                          inferred as M20K by Quartus)
+#   * `vram_normalize_pkg` (Ch155 pure-comb writer-side normalization)
+# Quartus only elaborates whichever VRAM the actually-instantiated top
+# wrapper depends on; the unused module is trimmed at hierarchy
+# resolution.
+# ---------------------------------------------------------------------
+rtl/gif_gs/gif_packed_stub.sv
+rtl/gif_gs/gs_stub.sv
+rtl/gif_gs/gif_image_xfer_stub.sv
+rtl/gif_gs/vram_normalize_pkg.sv
+rtl/gif_gs/vram_stub.sv
+rtl/gif_gs/vram_bram_stub.sv
+rtl/gif_gs/gs_pcrtc_stub.sv
+
+# ---------------------------------------------------------------------
+# Swizzle math primitives. The PSMCT32 demo only enables PSMCT32_SWIZZLE,
+# but gs_pcrtc_stub / gif_image_xfer_stub / gs_stub unconditionally
+# *instantiate* all four swizzle modules (the per-PSM muxer just
+# doesn't select them when their gate is 0). Quartus requires every
+# instantiated module to have a definition even when its outputs are
+# unused; the unused instances trim cleanly at fitter so the resource
+# cost is zero. iverilog (sim) trimmed them silently before; Quartus
+# (Ch152) made the dependency explicit.
+# ---------------------------------------------------------------------
+rtl/gif_gs/gs_swizzle_psmct32_stub.sv
+rtl/gif_gs/gs_swizzle_psmct16_stub.sv
+rtl/gif_gs/gs_swizzle_psmt8_stub.sv
+rtl/gif_gs/gs_swizzle_psmt4_stub.sv
+
+# ---------------------------------------------------------------------
+# Board-agnostic top wrappers.
+#   * `top_psmct32_raster_demo`      — Ch146 legacy vram_stub-backed
+#   * `top_psmct32_raster_demo_bram` — Ch155+ BRAM-backed
+#                                      (Ch159 board-top swap target)
+# ---------------------------------------------------------------------
+rtl/top/top_psmct32_raster_demo.sv
+rtl/top/top_psmct32_raster_demo_bram.sv
+
+# ---------------------------------------------------------------------
+# Ch165 — Terasic-derived ADV7513 I²C wake-up FSM + the bit-bang
+# I²C controller it drives. Plain Verilog (not SystemVerilog); the
+# wake-up walks a 38-entry LUT of canonical ADV7513 register writes
+# to bring the chip out of standby.
+# ---------------------------------------------------------------------
+rtl/platform/I2C_Controller.v
+rtl/platform/I2C_HDMI_Config.v
+
+# ---------------------------------------------------------------------
+# DE25-Nano PLL sim stub (Ch151) — pass-through clock + lock counter.
+# Mimics Quartus's IOPLL "pll" module signature so synthesis can swap
+# in the real IP via `\`ifdef USE_PLL_IP` without changing RTL.
+# ---------------------------------------------------------------------
+rtl/top/de25_nano_pll_stub.sv
+
+# ---------------------------------------------------------------------
+# DE25-Nano board-shaped wrapper (Ch149+Ch151) — board signal names,
+# PLL + reset-release sequencer, status LEDs, raw video pass-through.
+# Board pin assignments (.qsf), PLL .ip enablement, and PHY shim are
+# deferred to later chapters.
+# ---------------------------------------------------------------------
+rtl/top/de25_nano_psmct32_raster_demo_top.sv