ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
116 lines
5.4 KiB
FortranFixed
116 lines
5.4 KiB
FortranFixed
# retroDE_ps2 — Ch148 (Ch159 retargeted) synthesis filelist for the
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# DE25-Nano PSMCT32 raster demo.
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#
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# This filelist contains ONLY the modules in the Ch123 dependency tree
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# (audited in Ch144) plus the Ch155+ BRAM wrapper additions. Synthesis
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# tools (Quartus / Vivado) accept this as a `-F filelist.f` argument
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# or import it directly.
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#
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# Ch159 swap: the board-shaped wrapper now instantiates
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# `top_psmct32_raster_demo_bram` (vram_bram_stub-backed) instead of
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# the legacy `top_psmct32_raster_demo` (vram_stub-backed). Both top
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# wrappers are kept compiled below so the file list is forward-
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# compatible with either board-top instantiation; Quartus only
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# elaborates the wrapper actually instantiated by
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# `de25_nano_psmct32_raster_demo_top.sv`.
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#
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# Path convention: relative to the repo root. Tools should be invoked
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# from the repo root, or paths can be made absolute by the project file.
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#
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# To validate the filelist + fixture presence without running synthesis:
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# make -C sim top_psmct32_raster_demo_synth_check
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# ---------------------------------------------------------------------
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# Common debug + trace package (compiled first; type aliases used
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# below).
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# ---------------------------------------------------------------------
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rtl/debug/trace_pkg.sv
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# ---------------------------------------------------------------------
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# Memory blocks (BIOS ROM + EE RAM + EE memory map).
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# ---------------------------------------------------------------------
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rtl/memory/bios_rom_stub.sv
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rtl/memory/ee_ram_stub.sv
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rtl/memory/ee_memory_map_stub.sv
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# ---------------------------------------------------------------------
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# EE core + GS-priv MMIO bridge.
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# ---------------------------------------------------------------------
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rtl/ee/ee_core_stub.sv
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rtl/gif_gs/ee_gs_priv_bridge_stub.sv
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# ---------------------------------------------------------------------
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# DMAC channel-2 (NORMAL transfer; DMAC reads RAM, streams to GIF).
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# ---------------------------------------------------------------------
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rtl/dmac/dmac_reg_stub.sv
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# ---------------------------------------------------------------------
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# GIF + GS data plane.
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#
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# Ch159 — both VRAM shapes are kept on the file list:
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# * `vram_stub` (legacy byte-addressable + per-bit RMW; used
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# by the Ch146 wrapper and every legacy sim TB)
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# * `vram_bram_stub` (Ch154 BRAM-friendly, 2048×32-bit, sync-read,
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# byte-WE only; used by the Ch155+ wrapper and
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# inferred as M20K by Quartus)
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# * `vram_normalize_pkg` (Ch155 pure-comb writer-side normalization)
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# Quartus only elaborates whichever VRAM the actually-instantiated top
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# wrapper depends on; the unused module is trimmed at hierarchy
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# resolution.
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# ---------------------------------------------------------------------
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rtl/gif_gs/gif_packed_stub.sv
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rtl/gif_gs/gs_stub.sv
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rtl/gif_gs/gif_image_xfer_stub.sv
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rtl/gif_gs/vram_normalize_pkg.sv
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rtl/gif_gs/vram_stub.sv
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rtl/gif_gs/vram_bram_stub.sv
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rtl/gif_gs/gs_pcrtc_stub.sv
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# ---------------------------------------------------------------------
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# Swizzle math primitives. The PSMCT32 demo only enables PSMCT32_SWIZZLE,
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# but gs_pcrtc_stub / gif_image_xfer_stub / gs_stub unconditionally
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# *instantiate* all four swizzle modules (the per-PSM muxer just
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# doesn't select them when their gate is 0). Quartus requires every
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# instantiated module to have a definition even when its outputs are
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# unused; the unused instances trim cleanly at fitter so the resource
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# cost is zero. iverilog (sim) trimmed them silently before; Quartus
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# (Ch152) made the dependency explicit.
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# ---------------------------------------------------------------------
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rtl/gif_gs/gs_swizzle_psmct32_stub.sv
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rtl/gif_gs/gs_swizzle_psmct16_stub.sv
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rtl/gif_gs/gs_swizzle_psmt8_stub.sv
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rtl/gif_gs/gs_swizzle_psmt4_stub.sv
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# ---------------------------------------------------------------------
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# Board-agnostic top wrappers.
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# * `top_psmct32_raster_demo` — Ch146 legacy vram_stub-backed
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# * `top_psmct32_raster_demo_bram` — Ch155+ BRAM-backed
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# (Ch159 board-top swap target)
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# ---------------------------------------------------------------------
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rtl/top/top_psmct32_raster_demo.sv
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rtl/top/top_psmct32_raster_demo_bram.sv
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# ---------------------------------------------------------------------
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# Ch165 — Terasic-derived ADV7513 I²C wake-up FSM + the bit-bang
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# I²C controller it drives. Plain Verilog (not SystemVerilog); the
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# wake-up walks a 38-entry LUT of canonical ADV7513 register writes
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# to bring the chip out of standby.
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# ---------------------------------------------------------------------
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rtl/platform/I2C_Controller.v
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rtl/platform/I2C_HDMI_Config.v
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# ---------------------------------------------------------------------
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# DE25-Nano PLL sim stub (Ch151) — pass-through clock + lock counter.
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# Mimics Quartus's IOPLL "pll" module signature so synthesis can swap
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# in the real IP via `\`ifdef USE_PLL_IP` without changing RTL.
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# ---------------------------------------------------------------------
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rtl/top/de25_nano_pll_stub.sv
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# ---------------------------------------------------------------------
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# DE25-Nano board-shaped wrapper (Ch149+Ch151) — board signal names,
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# PLL + reset-release sequencer, status LEDs, raw video pass-through.
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# Board pin assignments (.qsf), PLL .ip enablement, and PHY shim are
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# deferred to later chapters.
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# ---------------------------------------------------------------------
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rtl/top/de25_nano_psmct32_raster_demo_top.sv
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