Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
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# top_psmct32_raster_demo on DE25-Nano (current as of Ch165)
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This directory is the **DE25-Nano synthesis project** for
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[`rtl/top/de25_nano_psmct32_raster_demo_top.sv`](../../../rtl/top/de25_nano_psmct32_raster_demo_top.sv)
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(the Ch149 board wrapper, retargeted in **Ch159** to instantiate
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the BRAM-backed `top_psmct32_raster_demo_bram` instead of the
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Ch146 legacy `top_psmct32_raster_demo`). The directory grew
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across these chapters:
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| Chapter | Added |
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|---------|----------------------------------------------------------------------------------------------------|
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| Ch148 | `files.f` (RTL filelist, Ch123 dep tree only) + this README. |
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| Ch149 | (RTL only — `de25_nano_psmct32_raster_demo_top.sv` lives in `rtl/top/`). |
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| Ch150 | `de25_nano_psmct32_raster_demo_top.qsf` + `.sdc` — minimal Quartus scaffold. |
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| Ch151 | (RTL only — `de25_nano_pll_stub.sv` + PLL/lock-gated-reset rework of board top). |
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| Ch152 | `build_quartus.sh` + `parse_reports.py` — first real Quartus compile (fit FAILED). |
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| Ch159 | Board-top swap to `top_psmct32_raster_demo_bram` (Ch155-Ch158 BRAM/normalize/PCRTC stack); fit + STA succeed. `baseline_ch152/` snapshots the prior fit-failed reports for diff. |
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| Ch160 | SDC retarget from 50 MHz → 30 MHz (down-clock profile); `build_quartus.sh` runs `quartus_asm` on clean STA → first `.sof` bitstream produced. `baseline_ch159/` snapshots the 50 MHz timing-miss reports. |
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| Ch161 | Real Quartus IOPLL `.ip` commit (50 MHz refclk → 30 MHz outclk_0) + `USE_PLL_IP=1` macro + `ip/` symlink in build_quartus.sh; SDC restored to 20 ns CLOCK2_50 (the IP's auto-generated SDC handles the post-PLL clock). The `.sof` now genuinely runs at 30 MHz on hardware. `baseline_ch160/` snapshots the SDC-profile-only state. |
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| Ch162 | `STRIP_HW_DIVIDER` parameter on `ee_core_stub` removes the auto-inferred 32-bit DIVU divider from the synth path on hardware builds (default off in sim preserves every existing TB). Fmax 30.74 → **33.6 MHz** (+9.4 %); fit ALMs −892, registers −734. New critical path: PCRTC magnification divider in `gs_pcrtc_stub` (`hwin_rel / hmag_factor`). `baseline_ch161/` snapshots the pre-strip state. |
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| Ch163 | `STRIP_PCRTC_MAG_DIV` parameter on `gs_pcrtc_stub` strips the PCRTC magnification dividers (constant divisor 1 when MAGH=MAGV=0). Fmax 33.6 → **81.83 MHz** at 30 MHz target (+143 %), then PLL `.ip` retuned 30 MHz → **50 MHz** outclk_0; STA closes at 50 MHz with +7.500 ns setup slack and Fmax 80.0 MHz. **First .sof that genuinely runs at 50 MHz on the DE25-Nano.** `baseline_ch162/` + `baseline_ch163_30mhz/` snapshots the milestones. |
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| Ch164 | First video-PHY shim — pins HDMI_TX_CLK + HDMI_TX_D[23:0] + HS/VS/DE on the DE25-Nano ADV7513 (pinout sourced from `retroDE_nes`). Wrapper drives them combinationally from VIDEO_* (R in MSBs of HDMI_TX_D). HDMI_TX_CLK = design_clk = 50 MHz post-PLL. ADV7513 I²C wake-up FSM still deferred (Ch165) so a real monitor stays dark — but pixels are now off-chip on the HDMI connector. STA stays clean (+7.536 ns slack); pins 17 → 45. `baseline_ch163_50mhz/` snapshots the pre-shim state. |
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| Ch165 | ADV7513 I²C wake-up FSM (Terasic-derived; ported from `retroDE_splash/rtl/platform/`). Adds 4 control pins (`HDMI_I2C_SCL/SDA` open-drain bus + `HDMI_TX_INT` interrupt + `HDMI_MCLK` audio reference); `LED[3] = ~hdmi_init_done`. The 38-entry LUT walks ADV7513 register writes (power-up + HPD override + AVI InfoFrame + HDMI mode select), turning the chip from standby into "transmitting RGB on the HDMI port". Pins 45 → 49; STA setup slack +7.198 ns; `.sof` clean. **First .sof that should drive a real HDMI monitor.** `baseline_ch164/` snapshots the pre-wake-up state. |
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## Ch163 strip-PCRTC-divider + 50 MHz close state
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The full journey from Ch152's fit failure to a real 50 MHz
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bitstream:
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| Metric | Ch152 (50 MHz) | Ch159 (50 MHz) | Ch161 (real PLL @ 30 MHz) | Ch162 (strip EE div, 30 MHz) | **Ch163 (strip both, 50 MHz)** |
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|-----------------------------------|-------------------|-----------------------|---------------------------|-------------------------------------|--------------------------------------|
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| Fit status | **FAILED** | Successful (30,364) | Successful (30,898) | Successful (30,006) | **Successful (27,543)** |
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| Fit RAM blocks | 6 | 14 | 14 | 14 | 14 |
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| Fit PLLs | 0 | 0 | 1 | 1 | **1 (50 MHz outclk0)** |
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| Setup slack worst (design domain) | (did not run) | −6.950 ns | +0.565 ns @ 30 MHz | +3.567 ns @ 30 MHz | **+7.500 ns @ 50 MHz** |
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| **Fmax (design domain)** | (did not run) | 37.11 MHz | 30.74 MHz | 33.6 MHz | **80.0 MHz** |
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| `.sof` produced | (skipped) | (skipped) | yes — 30 MHz on hardware | yes — Fmax 33.6 MHz / 30 MHz target | **yes — 50 MHz on hardware** |
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Ch163 lands in two stages:
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- **Stage A**: with `STRIP_PCRTC_MAG_DIV=1` on the board top
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but the PLL still at 30 MHz output, Fmax jumps from 33.6 MHz
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(Ch162) to **81.83 MHz** at the 30 MHz target — +143 %, well
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past 50 MHz.
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- **Stage B**: retune `pll.ip` from 30 MHz → 50 MHz output
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(`gui_output_clock_frequency0` = 50.0; `gui_output_clock_frequency_ps0`
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= 20000.0), `quartus_ipgenerate` regenerates the .qip / synth
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files. CLOCK2_50 stays at the physical 50 MHz period in the
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SDC; the IOPLL's auto-generated SDC declares the new
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outclk_0. Quartus rebuild → STA closes at 50 MHz with
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**+7.500 ns** of setup slack and Fmax **80.0 MHz**.
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The Stage B `.sof` is the first bitstream that genuinely runs
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at 50 MHz on the DE25-Nano. The Ch161 PLL hardware-real
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contract carries through; the IOPLL takes 50 MHz CLOCK2_50 in
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and emits 50 MHz outclk_0, so the chip-internal clock
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distribution still goes through the dedicated IOPLL clock
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network even at the 1:1 frequency relation.
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## Ch162 strip-divider state (vs Ch161 / Ch160 / Ch159 / Ch152 baselines)
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| Metric | Ch152 (50 MHz) | Ch159 (50 MHz) | Ch160 (30 MHz profile) | Ch161 (real PLL @ 30 MHz) | Ch162 (real PLL + strip divider) |
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|-----------------------------------|-------------------|-----------------------|---------------------------|-----------------------------------|-------------------------------------|
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| Fit status | **FAILED** | Successful (30,364) | Successful (31,056) | Successful (30,898) | Successful (30,006) |
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| Fit registers | 121,176 | 39,085 | 37,381 | 37,352 | 36,618 |
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| Fit RAM blocks | 6 | 14 | 14 | 14 | 14 |
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| Fit PLLs | 0 | 0 | 0 | 1 | 1 |
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| Setup slack worst (design domain) | (did not run) | −6.950 ns | +0.805 ns | +0.565 ns @ `iopll_0_outclk0` | **+3.567 ns** @ `iopll_0_outclk0` |
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| **Fmax (design domain)** | (did not run) | 37.11 MHz | 30.74 MHz | 30.74 MHz | **33.6 MHz** (+9.4 %) |
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| `.sof` produced | (skipped) | (skipped) | yes (profile only) | yes — 30 MHz on hardware | **yes — 33.6 MHz Fmax / 30 MHz target** |
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Stripping the EE-core 32-bit DIVU divider freed +3 ns of setup
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margin and 892 ALMs / 734 registers. The new STA worst path
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moves to the **PCRTC magnification divider** in
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[`gs_pcrtc_stub.sv`](../../../rtl/gif_gs/gs_pcrtc_stub.sv)
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(`vram_x_unshift = hwin_rel / hmag_factor` and the matching y
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form). **Ch163 gates that divider** via `STRIP_PCRTC_MAG_DIV`
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and retunes the PLL to 50 MHz — see the Ch163 section above
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for the milestone numbers.
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## Ch161 real-PLL state (vs Ch160 / Ch159 / Ch152 baselines)
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| Metric | Ch152 (50 MHz) | Ch159 (50 MHz) | Ch160 (30 MHz profile) | Ch161 (real PLL @ 30 MHz) |
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|-----------------------------------|-------------------|---------------------------|---------------------------|-----------------------------------|
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| Fit status | **FAILED** | Successful (30,364) | Successful (31,056) | Successful (30,898) |
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| Fit registers | 121,176 | 39,085 | 37,381 | 37,352 |
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| Fit RAM blocks | 6 | 14 | 14 | 14 |
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| **Fit PLLs** | 0 | 0 | 0 | **1** (real IOPLL) |
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| Setup slack worst (design domain) | (did not run) | −6.950 ns | +0.805 ns | **+0.565 ns** @ `iopll_0_outclk0` |
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| Fmax (design domain) | (did not run) | 37.11 MHz | 30.74 MHz | **30.74 MHz** |
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| `.sof` produced | (skipped) | (skipped) | yes (profile only) | **yes — 30 MHz on hardware** |
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The Ch161 `.sof` is the first bitstream that genuinely runs at
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the constrained frequency on the real DE25-Nano: the IOPLL
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takes the 50 MHz CLOCK2_50 input and divides to 30 MHz inside
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the chip, so the entire design downstream of `u_pll.outclk_0`
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operates at 30 MHz. Critical path was the EE core's auto-
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generated 64-bit DIVU divider — **closed in Ch162** via
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`STRIP_HW_DIVIDER`. New critical path (Ch162 onward): the PCRTC
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magnification divider in `gs_pcrtc_stub.sv` (`hwin_rel /
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hmag_factor`); see the Ch162 section above.
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## Ch160 down-clock + first .sof state (vs Ch159 / Ch152 baselines)
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| Metric | Ch152 (50 MHz) | Ch159 (50 MHz) | Ch160 (30 MHz) |
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|-------------------------------|---------------------------|---------------------------|---------------------------|
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| Fit status | **FAILED** (155k / 331 %) | Successful (30,364 / 65 %) | Successful (31,056 / 66 %) |
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| STA setup slack worst | (did not run) | −6.950 ns | **+0.805 ns** |
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| Fmax | (did not run) | 37.11 MHz | 30.74 MHz |
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| `quartus_asm` (.sof produced) | (skipped — fit failed) | (skipped — STA missed) | **Successful** |
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The Ch160 SDC profile retargets CLOCK2_50 from 20.000 ns
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(50 MHz) to 33.333 ns (30 MHz) so the fitter has positive
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slack on every report. `quartus_asm` now runs on every clean
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build, so a real `.sof` bitstream lands in
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[`output_files/de25_nano_psmct32_raster_demo_top.sof`](output_files/de25_nano_psmct32_raster_demo_top.sof).
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Worst-case path is the EE core's auto-generated 64-bit divider
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(actually the Ch43 DIVU divider, dead code in the PSMCT32 demo
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since the bootlet doesn't execute DIVU); **closed in Ch162**
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via `STRIP_HW_DIVIDER`. Programming the Ch160 `.sof` onto a
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real board where CLOCK2_50 is still wired straight through
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gives a 50 MHz chip
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clock that may setup-violate the divider path; Ch161+'s
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PLL-IP commit fixes that.
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## Ch159 fit-success state (vs Ch152 baseline)
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`make quartus_compile` runs the full syn/fit/sta flow. With
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the Ch159 BRAM-backed top:
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| Metric | Ch152 (vram_stub) | Ch159 (vram_bram_stub) |
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|-----------------------------------|-------------------------------|-------------------------------|
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| Synthesis status | Successful | Successful |
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| Synthesis ALMs estimate | 199,103 / 46,800 (425% over) | **22,704 / 46,800 (49%)** |
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| Synthesis registers | 101,457 | **36,008** |
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| **Fit status** | **FAILED** (155k / 331% over) | **Successful** (30,364 / 65%) |
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| Fit registers | 121,176 | **39,085** |
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| Fit RAM blocks | 6 / 358 | **14 / 358** |
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| **STA status** | **DID NOT RUN** | **Successful** (12 warnings) |
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| Setup slack worst (CLOCK2_50) | n/a | −6.950 ns |
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| Fmax | n/a | 37.11 MHz |
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The headline numbers: **synth ALMs −88.6 %, fit registers
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−67.7 %, +8 RAM blocks** (the `vram_bram_stub` 8 KiB dual-port
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shape that Ch154 exp_c forecast). Fit and STA both run through
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to completion. Setup slack is negative at the 50 MHz CLOCK2_50
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constraint — Fmax is currently 37.11 MHz, so timing closure
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(PLL down-clock or critical-path pipelining) is the **Ch160+**
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surface; Ch159 deliberately stops at "fits and reaches STA."
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The full chapter narrative lives in
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[`docs/contracts/gif_gs.md`](../../../docs/contracts/gif_gs.md)
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under "Board-top swap to BRAM wrapper + Quartus fit recovery
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(Ch159)". The Ch152 baseline reports are preserved under
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[`baseline_ch152/`](baseline_ch152/) for diff and audit.
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Ch150's QSF/SDC pin clock + reset + LED I/O for a real Quartus
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build, but **`VIDEO_R/G/B/HSYNC/VSYNC/DE` are intentionally left
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as virtual pins** (`VIRTUAL_PIN ON` in the QSF) — they will not
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toggle real package pins until the PHY shim chapter (Ch151+)
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maps them to a video output. Without virtualization, Quartus
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would auto-place an unassigned top-level output on an arbitrary
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package pin.
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## Files
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| File | Purpose |
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|---------------------------------------------------|----------------------------------------------------------------|
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| `files.f` | Synthesis filelist — Ch123 dep tree + Ch149 board wrapper. |
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| `de25_nano_psmct32_raster_demo_top.qsf` | **Ch150** — Quartus pin assignments + IO standards + macros. |
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| `de25_nano_psmct32_raster_demo_top.sdc` | **Ch150** — clock + reset-sync + IO false-path constraints. |
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| `README.md` | This file. |
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The Ch150 `.qsf` + `.sdc` together are PHY-light: clock / reset /
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LED pins are pinned and constrained, but video pins
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(`VIDEO_R/G/B/HSYNC/VSYNC/DE`) are **not** pin-assigned. The PHY
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shim chapter (Ch151+) maps them to a real connector.
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To validate the Quartus scaffold (.qsf + .sdc + filelist +
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fixtures) without launching Quartus:
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```
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make -C sim top_psmct32_raster_demo_quartus_scaffold_check
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```
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## Top module
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**Set Quartus's top-level entity to `de25_nano_psmct32_raster_demo_top`**
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(in [`rtl/top/de25_nano_psmct32_raster_demo_top.sv`](../../../rtl/top/de25_nano_psmct32_raster_demo_top.sv)).
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This is the Ch149 board-shaped wrapper, retargeted in **Ch159**
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to instantiate `top_psmct32_raster_demo_bram` (the BRAM-backed
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inner module from Ch155+, carrying every Ch155-Ch158 fix). It
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adds the DE25-Nano-specific plumbing — Terasic-canonical port
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names, reset-release sequencer, `core_go` pulse generator, and
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active-low LED status mapping.
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The legacy Ch146 inner module `top_psmct32_raster_demo` is kept
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on the project file list for back-compat with sim TBs that
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still target it; on Quartus only the actually-instantiated top
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is elaborated. **Do NOT set the top entity to either of the
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inner modules** (`top_psmct32_raster_demo` or
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`top_psmct32_raster_demo_bram`) — that bypasses every board
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adapter and exposes the inner module's `clk` / `rst_n` /
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`core_go` / `r/g/b/hsync/vsync/de` / status outputs directly,
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which is useful for sim and lint but not for an FPGA build.
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### Ch149 board wrapper ports (`de25_nano_psmct32_raster_demo_top`)
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| Port | Direction | Width | Role |
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|-------------------------------------|-----------|-------|------------------------------------------------------------|
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| `CLOCK0_50` / `CLOCK1_50` / `CLOCK2_50` | input | 1 ea. | DE25-Nano 50 MHz oscillators. Only `CLOCK2_50` is used. |
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| `KEY[1:0]` | input | 2 | Active-LOW push buttons. `KEY[0]` = soft reset. |
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| `SW[3:0]` | input | 4 | DIP switches; placeholder, unused. |
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| `LED[7:0]` | output | 8 | Active-LOW. `LED[2:0]` = status, `LED[7:3]` = OFF. |
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| `VIDEO_R/G/B` | output | 8 ea. | Raw 8-bit RGB; PHY shim deferred to next chapter. |
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| `VIDEO_HSYNC/VSYNC/DE` | output | 1 ea. | Raw video timing; PHY shim deferred. |
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LED mapping (active-low; signal asserted lights its LED):
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| LED | Polarity-corrected source |
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|-----------|---------------------------|
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| `LED[0]` | `~core_halt` |
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| `LED[1]` | `~dma_done_seen` |
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| `LED[2]` | `~frame_seen` |
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| `LED[7:3]`| tied HIGH (OFF) |
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### Inner module ports (`top_psmct32_raster_demo_bram`, Ch155+)
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For sim / lint use only. The board wrapper above adapts these
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to the DE25-Nano signal names; a custom integration could
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re-adapt them for a different board. The legacy Ch146 inner
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module `top_psmct32_raster_demo` exposes the same external
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port shape (just with a `vram_stub`-backed implementation
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instead of `vram_bram_stub`).
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| Port | Direction | Width | Role |
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|-----------------|-----------|-------|---------------------------------------------------------------|
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| `clk` | input | 1 | Single clock domain (see "Clock plan" below). |
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| `rst_n` | input | 1 | Active-low synchronous reset (see "Reset plan"). |
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| `core_go` | input | 1 | Pulsed high to start the EE bootlet (see "core_go strategy"). |
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| `r/g/b` | output | 8 ea. | 8-bit RGB scanout (PCRTC). |
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| `hsync/vsync/de`| output | 1 ea. | Standard video timing. |
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| `core_halt` | output | 1 | High once the EE has SYSCALL'd. |
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| `dma_done_seen` | output | 1 | Sticky: DMAC ch2 fired EV_DMA_DONE. |
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| `frame_seen` | output | 1 | Sticky: PCRTC end-of-frame fired ≥1 frame. |
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## Required preprocessor macros
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||||
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||||
Both must be set on the synthesis tool (NOT as module generics —
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||||
they're `\`define` macros per the Ch146 iverilog-12 string-
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||||
parameter forwarding workaround):
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| Macro | Value |
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|----------------------------------------------------|---------------------------------------------|
|
||||
| `TOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE` | Absolute path to `bios.mem` |
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| `TOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE` | Absolute path to `payload.mem` |
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||||
For Quartus: see the `set_global_assignment -name VERILOG_MACRO`
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||||
example in [`docs/contracts/gif_gs.md`](../../../docs/contracts/gif_gs.md)
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||||
under "Synthesis-facing macros".
|
||||
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||||
## Required `.mem` fixtures
|
||||
|
||||
Both files must exist before synthesis (Quartus's `$readmemh`
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||||
runs at elaboration; if the file is missing you get a silent
|
||||
zero-init that produces no payload at all):
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||||
|
||||
| File | Size | Produced by |
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||||
|--------------------------------------------|-----------------------|-------------|
|
||||
| `sim/data/top_psmct32_raster_demo/bios.mem` | 1024 32-bit words | `bake.py` |
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||||
| `sim/data/top_psmct32_raster_demo/payload.mem` | 256 128-bit qwords | `bake.py` |
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||||
|
||||
To produce them:
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||||
```
|
||||
make -C sim top_psmct32_raster_demo_mem
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||||
```
|
||||
|
||||
To verify both files exist + match expected sizes (and the
|
||||
synth filelist resolves cleanly):
|
||||
```
|
||||
make -C sim top_psmct32_raster_demo_synth_check
|
||||
```
|
||||
|
||||
## DE25-Nano board topology (current as of Ch151)
|
||||
|
||||
Live wiring (no longer "assumptions" — the board top
|
||||
implements it):
|
||||
|
||||
### Clock plan
|
||||
|
||||
- DE25-Nano's `CLOCK2_50` (50 MHz, PIN_BF23) is the only board
|
||||
oscillator the design uses. CLOCK0_50 / CLOCK1_50 are pin-
|
||||
assigned in the QSF for completeness but the wrapper ties
|
||||
them off internally.
|
||||
- **Ch151**: CLOCK2_50 → `de25_nano_pll_stub` (sim default,
|
||||
pass-through) or Quartus IOPLL `pll` (synth, when
|
||||
`USE_PLL_IP` is defined) → `design_clk`. Everything in the
|
||||
design (EE core, GIF, GS, PCRTC, `core_go` sequencer, all
|
||||
three status sticky-bits) is clocked on `design_clk`.
|
||||
- The PCRTC's H/V counters are parameter-driven (default 16×8)
|
||||
and do NOT model real CRTC timing — a first hardware build
|
||||
can run at any sane clock. The PLL chapter (Ch152+) will
|
||||
commit a real `outclk_0` frequency.
|
||||
- No clock gating, no derived clocks, no CDCs in the design.
|
||||
|
||||
### Reset plan
|
||||
|
||||
- **Ch151**: the reset bridge async-asserts on
|
||||
`(ninit_done | ~pll_locked)` and synchronously deasserts on
|
||||
`design_clk` through a 2-stage shift register. Both
|
||||
conditions must clear before the design leaves reset:
|
||||
1. `ninit_done` falls when FPGA initialization completes
|
||||
(real Terasic `reset_release` IP under
|
||||
`\`ifdef USE_TERASIC_RESET_RELEASE_IP`, else inline
|
||||
16-cycle stub).
|
||||
2. `pll_locked` rises when the PLL acquires lock (32-cycle
|
||||
stub warm-up; real IP timing depends on the configured
|
||||
output frequency).
|
||||
- `KEY[0]` (active-low push button) is sampled synchronously
|
||||
through the same 2-stage register — async-assert is reserved
|
||||
for the FPGA-init / PLL-lock signals.
|
||||
- The Ch146 wrapper's `rst_n` input is active-low and sampled
|
||||
inside `always_ff @(posedge clk) if (!rst_n)` — i.e.
|
||||
**synchronous** reset despite active-low polarity.
|
||||
|
||||
### `core_go` strategy
|
||||
|
||||
`ee_core_stub.go_i` is sampled **level-sensitively** in the
|
||||
core's `S_IDLE` state (see [`rtl/ee/ee_core_stub.sv:812-813`](../../../rtl/ee/ee_core_stub.sv#L812-L813)
|
||||
— `if (go_i) state <= S_IFETCH_REQ`). There is no edge
|
||||
synchronizer; the core enters `S_IDLE` after reset and
|
||||
transitions to `S_IFETCH_REQ` on the first cycle `go_i` is
|
||||
high. Two equivalent hardware paths:
|
||||
|
||||
1. **Tie `core_go` high** at the top level. After `rst_n`
|
||||
deasserts, the core enters `S_IDLE`, sees `go_i == 1`, and
|
||||
immediately starts fetching from `0xBFC0_0000`. Simplest
|
||||
wiring.
|
||||
2. **Reset-release sequencer**: a small board-level FSM that
|
||||
waits N cycles after `rst_n` deasserts (giving the PLL +
|
||||
BRAM init time to settle) then drives `core_go` high. Held-
|
||||
high or one-cycle pulse both work — only the rising-into-
|
||||
S_IDLE matters.
|
||||
|
||||
Option 2 is the **recommended hardware path** because the
|
||||
deliberate post-reset wait avoids fetching during the BRAM
|
||||
`$readmemh` settle window. A board-level synchronizer also
|
||||
gives a clean place to debounce the user push-button if
|
||||
`core_go` is also user-controllable.
|
||||
|
||||
### Video output path
|
||||
|
||||
- DE25-Nano video output is **TBD** in this chapter — the next
|
||||
chapter will wire the top's `r/g/b/hsync/vsync/de` to the
|
||||
board's chosen video PHY. Likely candidates:
|
||||
- **HDMI** via on-board ADV7513 (or equivalent). Needs an I²C
|
||||
config sequence, which adds a small bring-up state machine.
|
||||
- **VGA** via on-board ADV7123 / passive DAC. Simpler — just
|
||||
pin-wire the 8-bit RGB + sync signals.
|
||||
- **Direct GPIO** for an external PMOD video adapter
|
||||
(simplest path for a first bring-up).
|
||||
- The Ch146 wrapper's PCRTC outputs are 8-bit RGB at one cycle
|
||||
per pixel — compatible with all three options after a clock-
|
||||
rate adjustment.
|
||||
|
||||
### LEDs / status
|
||||
|
||||
The Ch146 wrapper exposes three sticky status bits the DE25-
|
||||
Nano user LEDs can show:
|
||||
|
||||
| LED | Signal | Meaning |
|
||||
|----------------|------------------|----------------------------------------|
|
||||
| User LED 0 | `core_halt` | EE has SYSCALL'd → bootlet finished. |
|
||||
| User LED 1 | `dma_done_seen` | DMAC ch2 completed transfer. |
|
||||
| User LED 2 | `frame_seen` | PCRTC has scanned out ≥1 frame. |
|
||||
|
||||
All three latch high within ~10 ms of `rst_n` deasserting on a
|
||||
typical 50 MHz clock. The actual order is **`frame_seen` first**
|
||||
(the PCRTC starts scanning empty frames as soon as reset
|
||||
deasserts), then `core_halt` (after the EE bootlet runs to
|
||||
SYSCALL), then `dma_done_seen` (after the DMAC channel-2
|
||||
transfer completes). The Ch146 wrapper's `frame_seen` is a
|
||||
"PCRTC alive" indicator — it doesn't gate on whether the frame
|
||||
holds rendered content. If you see `core_halt` low, the bootlet
|
||||
hung; if `dma_done_seen` is low, the DMAC didn't deliver the
|
||||
GIF payload; if `frame_seen` is low, the PCRTC isn't scanning
|
||||
out (PLL not locked or reset stuck asserted).
|
||||
|
||||
## What's still NOT in this chapter
|
||||
|
||||
Landed in Ch165–Ch167:
|
||||
|
||||
- **Accelerated I²C bring-up TB** — `sim/tb/top/tb_hdmi_i2c_wake_smoke.sv`
|
||||
instantiates `I2C_HDMI_Config` with `CLK_Freq=2 / I2C_Freq=1` so
|
||||
the LUT walks in microseconds, asserts (1) the 38-entry walk reaches
|
||||
`LUT_SIZE-1`, (2) `READY` rises, (3) `HDMI_TX_INT` retriggers the
|
||||
walk, (4) SDA never resolves to `'x` (no driver conflict), (5)
|
||||
Ch166 NACK watchdog stays low on the healthy bus and rises
|
||||
(sticky) when `mI2C_ACK` is forced HIGH, and **(6, Ch167) every
|
||||
one of the 38 transactions on the wire matches the FSM-intent
|
||||
payload byte-for-byte**. The byte-sequence lock uses a pullup +
|
||||
phase-aware slave-ACK bus model so released SDA bits resolve to
|
||||
1; a decoder samples SDA on each SCL rising edge between START
|
||||
and STOP and assembles each transaction as a 24-bit
|
||||
`{dev_addr, reg, data}` tuple, which is then compared against
|
||||
`u_dut.mI2C_DATA[23:0]` snapshots taken on `mI2C_GO` rising
|
||||
edges. Every transaction's dev_addr is asserted to be 8'h72
|
||||
(ADV7513 write address). At the production divider the LUT
|
||||
walk takes ~125 ms (controller-clock period ~100 µs × 33
|
||||
phases/byte × 38 bytes), so observing it inside the 5 ms board
|
||||
TB is impractical.
|
||||
|
||||
Deferred to Ch168+:
|
||||
|
||||
- Proper `set_output_delay` constraints for HDMI_TX_* once
|
||||
the ADV7513 setup/hold window is locked from the bring-up
|
||||
datasheet pass — replaces Ch164's `set_false_path -to`.
|
||||
- Make the rendered pattern bigger than Ch123's 16×8 SPRITE
|
||||
so there's something visible to admire on a real screen.
|
||||
- xfer-side T4 coverage TB (open from Ch157+).
|
||||
- `useg_shadow_mem` BRAM-shape forensics.
|
||||
|
||||
(Ch161 made the PLL hardware-real at 30 MHz. Ch162 retired
|
||||
the EE-core hardware-divider critical path via
|
||||
`STRIP_HW_DIVIDER`. Ch163 retired the PCRTC magnification
|
||||
divider via `STRIP_PCRTC_MAG_DIV` and retuned the PLL to
|
||||
50 MHz outclk_0 — the `.sof` now genuinely runs at 50 MHz
|
||||
on the DE25-Nano. Ch164 added the HDMI pin shim — pixels
|
||||
reach the DE25-Nano HDMI connector pins. Ch165 ported the
|
||||
ADV7513 wake-up FSM from Terasic's reference design — the
|
||||
chip is now configured to transmit RGB on the HDMI port,
|
||||
so the .sof should drive a real monitor for the first time.)
|
||||
|
||||
The point of Ch149 was that the **design is now board-shaped** —
|
||||
DE25-Nano signal names, Terasic-style reset-release sequencer,
|
||||
and active-low LED status mapping. Ch161 made the **PLL
|
||||
hardware-real**; Ch162+ makes the **timing closure
|
||||
hardware-real** at 50 MHz.
|
||||
|
||||
## Ch149 additions
|
||||
|
||||
| Artifact | Purpose |
|
||||
|--------------------------------------------------|----------------------------------------------------------|
|
||||
| `rtl/top/de25_nano_psmct32_raster_demo_top.sv` | DE25-Nano board wrapper: CLOCK0/1/2_50 + KEY[1:0] + SW[3:0] + LED[7:0] + raw video pins. |
|
||||
| `sim/tb/top/tb_de25_nano_psmct32_raster_demo_top.sv` | Smoke TB: drives CLOCK2_50 + KEY[0] release, asserts core_go pulses exactly once, all 3 status LEDs latch, VIDEO_DE rises. |
|
||||
|
||||
The board top instantiates `top_psmct32_raster_demo_bram` (Ch155+
|
||||
BRAM-backed inner module, retargeted in **Ch159** from the Ch146
|
||||
legacy `top_psmct32_raster_demo`) and adds:
|
||||
|
||||
- **`ninit_done` source**. Default-off `\`ifdef
|
||||
USE_TERASIC_RESET_RELEASE_IP` swaps in Terasic's `reset_release`
|
||||
IP (from
|
||||
`DE25_Nano_ResourceCD/Demonstration/FPGA/Board_Info_RTL/reset_release/`).
|
||||
When the macro is undefined (sim default), an inline 16-cycle
|
||||
counter mimics the IP's "high until BRAM init completes" shape.
|
||||
- **Reset synchronizer**. `KEY[0]` (active-low button) and
|
||||
`ninit_done` feed an async-assert/sync-deassert 2-stage shift
|
||||
register clocked by CLOCK2_50, mirroring the retroDE_nes
|
||||
pattern. Output is the design's `core_rst_n`.
|
||||
- **`core_go` sequencer**. After `core_rst_n` deasserts, waits 16
|
||||
cycles then drives `core_go` high for one cycle. Matches the
|
||||
recommended hardware path documented above (the EE core's
|
||||
`go_i` is sampled level-sensitively in S_IDLE, so a single
|
||||
pulse is sufficient).
|
||||
- **LED polarity**. DE25-Nano LEDs are active-LOW (LED HIGH =
|
||||
OFF); the three status outputs are inverted before driving
|
||||
the pins. `LED[7:3]` are tied HIGH (OFF).
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
#!/usr/bin/env bash
|
||||
# ============================================================================
|
||||
# retroDE_ps2 — Ch152 Quartus build driver for the DE25-Nano
|
||||
# top_psmct32_raster_demo board top.
|
||||
#
|
||||
# Asks the toolchain the honest question: "does this board top
|
||||
# synthesize, fit, and pass static timing analysis?" Captures resource
|
||||
# usage, warning summaries, and unconstrained-path reports so a future
|
||||
# audit can compare across chapters.
|
||||
#
|
||||
# Usage (from repo root):
|
||||
# ./synth/de25_nano/top_psmct32_raster_demo/build_quartus.sh # default flow
|
||||
# ./synth/de25_nano/top_psmct32_raster_demo/build_quartus.sh clean # wipe outputs first
|
||||
# ./synth/de25_nano/top_psmct32_raster_demo/build_quartus.sh syn-only # synthesis only (fast)
|
||||
#
|
||||
# Convenience: `make -C sim quartus_compile` wraps this.
|
||||
#
|
||||
# What this script DOES:
|
||||
# - Resolves Quartus binaries via QUARTUS_ROOTDIR or PATH.
|
||||
# - Re-bakes the .mem fixtures via the existing make target so
|
||||
# $readmemh resolves at synth time.
|
||||
# - Runs quartus_syn (synthesis) → quartus_fit (placement+routing) →
|
||||
# quartus_sta (timing analysis) → quartus_asm (bitstream). The
|
||||
# final step is gated on a clean STA so a .sof is produced only
|
||||
# when timing actually closes (Ch160).
|
||||
# - Captures stdout/stderr per step into output_files/ for audit.
|
||||
#
|
||||
# What this script does NOT do:
|
||||
# - Define USE_PLL_IP — keeps the Ch151 self-contained stub path
|
||||
# under test, per Codex's Ch152 framing.
|
||||
# ============================================================================
|
||||
|
||||
set -euo pipefail
|
||||
|
||||
PROJECT=de25_nano_psmct32_raster_demo_top
|
||||
|
||||
SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
|
||||
REPO_ROOT="$(cd "$SCRIPT_DIR/../../.." && pwd)"
|
||||
QSF_DIR="$SCRIPT_DIR"
|
||||
|
||||
# Quartus binaries.
|
||||
if [ -n "${QUARTUS_ROOTDIR:-}" ]; then
|
||||
QUARTUS="$QUARTUS_ROOTDIR/bin"
|
||||
elif command -v quartus_sh >/dev/null 2>&1; then
|
||||
QUARTUS="$(dirname "$(command -v quartus_sh)")"
|
||||
else
|
||||
echo "error: Quartus not found. Set QUARTUS_ROOTDIR or add quartus to PATH." >&2
|
||||
exit 1
|
||||
fi
|
||||
|
||||
MODE="${1:-default}"
|
||||
|
||||
# All Quartus output goes here (under the project dir).
|
||||
OUT_DIR="$QSF_DIR/output_files"
|
||||
LOG_DIR="$OUT_DIR/build_logs"
|
||||
|
||||
if [ "$MODE" = "clean" ]; then
|
||||
echo "=== Cleaning output_files / db / incremental_db ==="
|
||||
rm -rf "$OUT_DIR" "$QSF_DIR/db" "$QSF_DIR/incremental_db" \
|
||||
"$QSF_DIR/qdb" "$QSF_DIR/synthesis"
|
||||
shift
|
||||
MODE="${1:-default}"
|
||||
fi
|
||||
|
||||
mkdir -p "$LOG_DIR"
|
||||
|
||||
# Re-bake .mem fixtures so $readmemh resolves at elaboration.
|
||||
echo ""
|
||||
echo "=== Re-baking .mem fixtures ==="
|
||||
make -C "$REPO_ROOT/sim" --no-print-directory top_psmct32_raster_demo_mem
|
||||
|
||||
# Quartus runs from the repo root because the QSF references RTL via
|
||||
# repo-root-relative paths (rtl/...). The project name is the QSF
|
||||
# basename, but the $QSF_DIR/PROJECT.qsf path is the absolute file.
|
||||
# Quartus's `-project` flag wants the project base path (no .qsf
|
||||
# suffix). With Quartus Pro, we run from the project dir and the file
|
||||
# paths inside the QSF resolve via PROJECT_OUTPUT_DIRECTORY +
|
||||
# implicit project-relative search.
|
||||
#
|
||||
# Strategy: copy the QSF to a working directory at the repo root so
|
||||
# that (a) the SYSTEMVERILOG_FILE rtl/... paths resolve and (b)
|
||||
# Quartus puts its db/ and output_files/ under the project dir, not
|
||||
# the repo root.
|
||||
WORK_DIR="$QSF_DIR/work"
|
||||
mkdir -p "$WORK_DIR"
|
||||
# Symlink the QSF + SDC into the work dir (Quartus reads them from
|
||||
# the dir it's invoked in by default), then symlink the rtl/ + sim/
|
||||
# dirs so the QSF's relative paths resolve.
|
||||
ln -sfn "$QSF_DIR/$PROJECT.qsf" "$WORK_DIR/$PROJECT.qsf"
|
||||
ln -sfn "$QSF_DIR/$PROJECT.sdc" "$WORK_DIR/$PROJECT.sdc"
|
||||
ln -sfn "$REPO_ROOT/rtl" "$WORK_DIR/rtl"
|
||||
ln -sfn "$REPO_ROOT/sim" "$WORK_DIR/sim"
|
||||
# Ch161 — IOPLL `.qip` references its synth/ subdir via paths
|
||||
# relative to the .qip's own location. The QSF's QIP_FILE entry
|
||||
# uses `ip/pll/pll.qip` (relative to the work dir), so symlink
|
||||
# the synth-project's `ip/` tree into the work dir alongside
|
||||
# `rtl/` and `sim/`.
|
||||
ln -sfn "$QSF_DIR/ip" "$WORK_DIR/ip"
|
||||
|
||||
cd "$WORK_DIR"
|
||||
|
||||
run_step() {
|
||||
local step="$1"
|
||||
local cmd="$2"
|
||||
local log="$LOG_DIR/${step}.log"
|
||||
echo ""
|
||||
echo "=== [$step] ==="
|
||||
# Run; tee output to log; capture exit status. We do NOT want
|
||||
# `set -e` to abort here — the chapter contract is to capture a
|
||||
# complete report even when a step errored, and the script's
|
||||
# exit code (computed at the bottom from SYN/FIT/STA together)
|
||||
# is what the caller (make / CI) sees.
|
||||
set +e
|
||||
eval "$cmd" 2>&1 | tee "$log"
|
||||
local rc=${PIPESTATUS[0]}
|
||||
set -e
|
||||
if [ $rc -ne 0 ]; then
|
||||
echo ""
|
||||
echo "FAIL: $step exited $rc — see $log"
|
||||
echo ""
|
||||
fi
|
||||
return $rc
|
||||
}
|
||||
|
||||
# Each step's rc is captured via `if run_step ...; then RC=0; else
|
||||
# RC=$?; fi`. The earlier idiom (`run_step ... || true; RC=$?`)
|
||||
# silently masked tool failures because `$?` then captured `true`'s
|
||||
# exit (always 0). The `if ...; then` form is the correct
|
||||
# `set -e`-friendly capture: the exit status of `run_step` is what
|
||||
# `else $?` sees, and the `if` block keeps `set -e` from aborting
|
||||
# the script when a step fails (Ch160 audit High fix).
|
||||
if run_step "quartus_syn" \
|
||||
"$QUARTUS/quartus_syn --read_settings_files=on --write_settings_files=off $PROJECT -c $PROJECT"
|
||||
then
|
||||
SYN_RC=0
|
||||
else
|
||||
SYN_RC=$?
|
||||
fi
|
||||
|
||||
# 99 sentinel = "step skipped (upstream failed or syn-only mode)".
|
||||
if [ "$MODE" = "syn-only" ]; then
|
||||
FIT_RC=99
|
||||
STA_RC=99
|
||||
ASM_RC=99
|
||||
elif [ $SYN_RC -ne 0 ]; then
|
||||
# syn failed — don't bother with downstream steps.
|
||||
FIT_RC=99
|
||||
STA_RC=99
|
||||
ASM_RC=99
|
||||
else
|
||||
if run_step "quartus_fit" \
|
||||
"$QUARTUS/quartus_fit --read_settings_files=on --write_settings_files=off $PROJECT -c $PROJECT"
|
||||
then
|
||||
FIT_RC=0
|
||||
else
|
||||
FIT_RC=$?
|
||||
fi
|
||||
|
||||
if [ $FIT_RC -eq 0 ]; then
|
||||
if run_step "quartus_sta" \
|
||||
"$QUARTUS/quartus_sta $PROJECT -c $PROJECT"
|
||||
then
|
||||
STA_RC=0
|
||||
else
|
||||
STA_RC=$?
|
||||
fi
|
||||
|
||||
# Ch161 audit High #2 fix — quartus_sta exits 0 even when
|
||||
# individual timing classes (Setup / Hold / Recovery /
|
||||
# Removal / Min Pulse Width) report negative slack. Without
|
||||
# parsing the summary file, a "tool rc=0" verdict could let
|
||||
# quartus_asm run on a design with a real timing violation
|
||||
# and produce a .sof under a failing timing class. Inspect
|
||||
# the .sta.summary, fail the script if any "Slack :" line
|
||||
# is negative.
|
||||
if [ $STA_RC -eq 0 ]; then
|
||||
STA_SUMMARY="$WORK_DIR/output_files/$PROJECT.sta.summary"
|
||||
if [ -f "$STA_SUMMARY" ]; then
|
||||
NEG_SLACK_LINES=$(awk '/^Slack[[:space:]]*:/ {
|
||||
# strip "Slack : " prefix and any trailing fields.
|
||||
sub(/^Slack[[:space:]]*:[[:space:]]*/, "", $0);
|
||||
# first whitespace-separated token is the slack value.
|
||||
s=$1; if (s+0 < 0) print s
|
||||
}' "$STA_SUMMARY")
|
||||
if [ -n "$NEG_SLACK_LINES" ]; then
|
||||
echo ""
|
||||
echo "FAIL: quartus_sta tool exit was 0 but the .sta.summary"
|
||||
echo " reports negative slack(s): $NEG_SLACK_LINES"
|
||||
echo " (build_quartus.sh promotes this to a build failure)"
|
||||
echo ""
|
||||
STA_RC=2
|
||||
fi
|
||||
else
|
||||
# Ch161 audit Medium fix — a missing .sta.summary
|
||||
# disables the slack-parse gate, which is functionally
|
||||
# the same hole as "tool rc=0 but timing failed". A
|
||||
# report-path or tool-output change must not be
|
||||
# allowed to bypass the gate by deleting the artifact
|
||||
# we parse. Promote to a build failure with the same
|
||||
# STA_RC=2 used for the negative-slack case.
|
||||
echo ""
|
||||
echo "FAIL: quartus_sta tool exit was 0 but $STA_SUMMARY is missing —"
|
||||
echo " the slack-parse gate cannot run. Promoting to STA_RC=2."
|
||||
echo ""
|
||||
STA_RC=2
|
||||
fi
|
||||
fi
|
||||
else
|
||||
STA_RC=99
|
||||
fi
|
||||
|
||||
# Ch160 — bitstream generation, gated on a clean STA so a .sof
|
||||
# is produced only when timing actually closes. Ch161 audit High
|
||||
# #2 strengthens "clean STA" to also require all summary slacks
|
||||
# to be non-negative (see the .sta.summary parse above).
|
||||
if [ $FIT_RC -eq 0 ] && [ $STA_RC -eq 0 ]; then
|
||||
if run_step "quartus_asm" \
|
||||
"$QUARTUS/quartus_asm $PROJECT -c $PROJECT"
|
||||
then
|
||||
ASM_RC=0
|
||||
else
|
||||
ASM_RC=$?
|
||||
fi
|
||||
else
|
||||
ASM_RC=99
|
||||
fi
|
||||
fi
|
||||
|
||||
# Move output_files from work dir into the canonical location.
|
||||
if [ -d "$WORK_DIR/output_files" ]; then
|
||||
rsync -a --remove-source-files "$WORK_DIR/output_files/" "$OUT_DIR/" 2>/dev/null || \
|
||||
cp -a "$WORK_DIR/output_files/." "$OUT_DIR/"
|
||||
fi
|
||||
|
||||
echo ""
|
||||
echo "================================================================"
|
||||
echo " Compile summary"
|
||||
echo "================================================================"
|
||||
echo " quartus_syn : rc=$SYN_RC"
|
||||
echo " quartus_fit : rc=$FIT_RC (99 = skipped)"
|
||||
echo " quartus_sta : rc=$STA_RC (99 = skipped)"
|
||||
echo " quartus_asm : rc=${ASM_RC:-99} (99 = skipped)"
|
||||
echo " logs in : $LOG_DIR"
|
||||
echo " outputs in : $OUT_DIR"
|
||||
echo "================================================================"
|
||||
|
||||
# Final exit code:
|
||||
# syn-only mode → exit SYN_RC (only the syn step is meaningful).
|
||||
# default mode → exit the FIRST nonzero of (SYN, FIT, STA, ASM);
|
||||
# 99 sentinels are skipped-step markers and only
|
||||
# propagate when the upstream step actually
|
||||
# failed (so default mode never exits 99). Ch160
|
||||
# audit Medium fix: ASM is now part of the
|
||||
# deliverable so its rc participates here.
|
||||
if [ "$MODE" = "syn-only" ]; then
|
||||
exit $SYN_RC
|
||||
fi
|
||||
if [ $SYN_RC -ne 0 ]; then
|
||||
exit $SYN_RC
|
||||
fi
|
||||
if [ $FIT_RC -ne 0 ] && [ $FIT_RC -ne 99 ]; then
|
||||
exit $FIT_RC
|
||||
fi
|
||||
if [ $STA_RC -ne 0 ] && [ $STA_RC -ne 99 ]; then
|
||||
exit $STA_RC
|
||||
fi
|
||||
if [ $ASM_RC -ne 0 ] && [ $ASM_RC -ne 99 ]; then
|
||||
exit $ASM_RC
|
||||
fi
|
||||
exit 0
|
||||
@@ -0,0 +1,31 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2025 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
# the Altera IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Altera and sold by Altera or its authorized distributors. Please
|
||||
# refer to the Altera Software License Subscription Agreements
|
||||
# on the Quartus Prime software download page.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 25.3.1 Build 100 12/19/2025 Patches 1.02 SC Pro Edition
|
||||
# Date created = 11:04:54 May 07, 2026
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "25.3"
|
||||
DATE = "11:04:54 May 07, 2026"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "de25_nano_psmct32_raster_demo_top"
|
||||
File diff suppressed because it is too large
Load Diff
+1032
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,258 @@
|
||||
# ============================================================================
|
||||
# retroDE_ps2 — minimal SDC for the DE25-Nano top_psmct32_raster_demo
|
||||
# board wrapper (current as of Ch163 — real PLL IP retuned to 50 MHz
|
||||
# outclk_0; first .sof that genuinely runs at 50 MHz on hardware).
|
||||
# Scope: just enough constraints to close timing on the single
|
||||
# `design_clk` domain the wrapper uses, and to mark the IO false paths
|
||||
# Quartus would otherwise flag.
|
||||
#
|
||||
# Clock topology:
|
||||
# CLOCK2_50 (board pad, physical 50 MHz)
|
||||
# └─→ pll u_pll (Quartus IOPLL when USE_PLL_IP is defined;
|
||||
# de25_nano_pll_stub when not — sim-only pass-through)
|
||||
# └─→ design_clk = u_pll.outclk_0 (50 MHz under USE_PLL_IP)
|
||||
# └─→ EE core / PCRTC / GIF / etc.
|
||||
#
|
||||
# Ch161-Ch163 timing-closure journey:
|
||||
# - Ch159 BRAM-backed VRAM rescued the Ch152 fit failure but STA
|
||||
# missed the 50 MHz target by −6.95 ns of setup slack.
|
||||
# - Ch160 retargeted the SDC to a 30 MHz profile so STA could
|
||||
# close, but the PLL was still a sim stub so the .sof was
|
||||
# profile-only on hardware.
|
||||
# - **Ch161** committed a real Quartus Agilex 5 IOPLL
|
||||
# (`synth/.../ip/pll.ip` → `pll.qip`, configured for 50 MHz
|
||||
# refclk → 30 MHz outclk_0) and defined `USE_PLL_IP=1` so the
|
||||
# wrapper's `\`ifdef USE_PLL_IP` instantiates the IP-generated
|
||||
# `pll` module. The .sof now genuinely ran at 30 MHz on hardware.
|
||||
# - **Ch162** retired the EE-core auto-inferred 32-bit DIVU
|
||||
# divider via `STRIP_HW_DIVIDER` (Fmax 30.74 → 33.6 MHz).
|
||||
# - **Ch163** retired the PCRTC magnification divider via
|
||||
# `STRIP_PCRTC_MAG_DIV` (Fmax 33.6 → 81.83 MHz at the 30 MHz
|
||||
# constraint), then **retuned `pll.ip` to 50 MHz outclk_0**.
|
||||
# STA closes at the 50 MHz target with +7.500 ns setup slack
|
||||
# and Fmax 80.0 MHz; the .sof produced now genuinely runs at
|
||||
# 50 MHz on the DE25-Nano.
|
||||
#
|
||||
# Clock constraint plan:
|
||||
# - CLOCK2_50 period stays at 20.000 ns (the physical board
|
||||
# oscillator). This is the IP's refclk input.
|
||||
# - The IOPLL's auto-generated SDC (inside the .qip's pll.sdc)
|
||||
# declares the post-PLL clock at **50 MHz** via
|
||||
# `create_generated_clock` on the IP's output. Quartus picks
|
||||
# it up automatically when the .qip is included; nothing else
|
||||
# is needed here for the design_clk domain.
|
||||
#
|
||||
# Default (`USE_PLL_IP` undefined): the de25_nano_pll_stub is a sim
|
||||
# pass-through — `design_clk` follows `CLOCK2_50` cycle-for-cycle and
|
||||
# the 20 ns period below covers everything downstream.
|
||||
#
|
||||
# Reset bridge (Ch151 + Ch161 audit High #1): the rst_sync register
|
||||
# async-asserts on `(ninit_done | ~pll_locked)` and synchronously
|
||||
# deasserts on design_clk. Both async sources AND both stages of
|
||||
# the synchronizer are covered by the `set_false_path -to *rst_sync[*]`
|
||||
# line below — Ch161's audit High fix widened the wildcard from
|
||||
# `*rst_sync[0]` to `*rst_sync[*]` after a real recovery violation
|
||||
# fired on the second stage.
|
||||
#
|
||||
# Sourced from sibling retroDE_splash.sdc for false-path conventions
|
||||
# (reset synchronizers, button/SW/LED IO false paths).
|
||||
#
|
||||
# Deferred to Ch165+:
|
||||
# - ADV7513 wake-up FSM + matching `set_output_delay` constraints
|
||||
# for HDMI_TX_*. Ch164 pinned the HDMI 24-bit RGB + sync data
|
||||
# path and constrained the outputs as `set_false_path -to`
|
||||
# (see the "HDMI ADV7513 output ports" block below). Ch165
|
||||
# replaces those false-paths with real output-delay constraints
|
||||
# once the ADV7513's setup/hold window is documented from its
|
||||
# bring-up datasheet pass.
|
||||
# - LPDDR4 / SDRAM / HPS clock groups.
|
||||
# ============================================================================
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
derive_clock_uncertainty
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Board clock — CLOCK2_50 is the physical 50 MHz oscillator that
|
||||
# drives the IOPLL's refclk input. The PLL's output (`design_clk`,
|
||||
# 50 MHz under USE_PLL_IP after the Ch163 retune) is constrained
|
||||
# by the IP's auto-generated SDC inside
|
||||
# `synth/.../ip/pll/pll.qip`.
|
||||
# ----------------------------------------------------------------------------
|
||||
create_clock -name CLOCK2_50 -period 20.000 [get_ports {CLOCK2_50}]
|
||||
|
||||
# CLOCK0_50 / CLOCK1_50 are pin-assigned but unused by this design;
|
||||
# constrain them at their physical 50 MHz period so Quartus doesn't
|
||||
# synthesize unconstrained-clock warnings in case a future chapter
|
||||
# promotes them.
|
||||
create_clock -name CLOCK0_50 -period 20.000 [get_ports {CLOCK0_50}]
|
||||
create_clock -name CLOCK1_50 -period 20.000 [get_ports {CLOCK1_50}]
|
||||
|
||||
# CLOCK0_50 / CLOCK1_50 are asynchronous to CLOCK2_50 — separate
|
||||
# board oscillator pads on the DE25-Nano. Mark them so Quartus
|
||||
# doesn't try to optimize cross-paths that don't exist.
|
||||
set_clock_groups -asynchronous \
|
||||
-group [get_clocks {CLOCK0_50}] \
|
||||
-group [get_clocks {CLOCK1_50}] \
|
||||
-group [get_clocks {CLOCK2_50}]
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Reset synchronizer — async assert, sync deassert. BOTH stages of
|
||||
# `rst_sync` are async-cleared by `(ninit_done | ~pll_locked)`, not
|
||||
# by clk; mark them false-path so the recovery analysis doesn't
|
||||
# flag them under either source.
|
||||
#
|
||||
# Ch161 audit High #1 fix: the original constraint only covered
|
||||
# `*rst_sync[0]`, which left rst_sync[1] under recovery analysis.
|
||||
# Quartus reported a real recovery violation on
|
||||
# init_cnt[2] (refclk domain) → rst_sync[1].clrn (async-clear)
|
||||
# of −0.079 ns at the 30 MHz outclk0 latch clock. The endpoint is
|
||||
# an asynchronous-clear pin shared across both stages, so the
|
||||
# correct constraint is the wildcard `*rst_sync[*]`. Recovery /
|
||||
# removal analysis on the async-clear pin is masked the same way
|
||||
# `set_false_path -to <regs>` masks the data-pin setup analysis —
|
||||
# Quartus treats the reg's async-set/clear pin as a single endpoint
|
||||
# under this constraint.
|
||||
# ----------------------------------------------------------------------------
|
||||
set_false_path -to [get_registers -nowarn {*rst_sync[*]}]
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# gs_async_fifo gray-pointer CDC (Ch324). The dual-clock FIFOs (gs_z_flush_writer
|
||||
# color/Z spill, gs_lpddr_axi_master FB writer, scanout) cross design_clk (u_pll,
|
||||
# 40 ns / 25 MHz) <-> emif_clk (u_emif, 3.225 ns / 310 MHz) — a 12x ratio. With NO
|
||||
# constraint the tool timed the gray-pointer crossing against the FAST 3.225 ns
|
||||
# clock (an impossible single-cycle setup), so place&route corrupted the Z FIFO's
|
||||
# wgray_s sync (placement-unlucky) -> rempty read wrong-low -> PHANTOM pops
|
||||
# (board: z_pop/beats 1454 > z_push 987, ovf, ~2 artifact pixels). Color got lucky.
|
||||
# A gray pointer changes ONE bit per source-clock; correctness needs the gray-bus
|
||||
# arrival SKEW bounded below the period. Quartus Prime PRO has no `set_max_delay
|
||||
# -datapath_only` (that is a Standard-only option) — the Pro constraint for CDC bus
|
||||
# skew is `set_max_skew`, which is a SEPARATE analysis from setup (so it is NOT voided
|
||||
# by clock groups / false paths the way max_delay would be). Bounding the source->first-
|
||||
# sync skew well under the fast emif period (3.225 ns) forces the tool to place the gray
|
||||
# bits compactly for EVERY gs_async_fifo instance, so at most one bit is ever in flight ->
|
||||
# the 2-FF synchronizers handle metastability normally. (1.0 ns << both clock periods.)
|
||||
set_max_skew -from {*wgray[*]} -to {*wgray_s1[*]} 1.0
|
||||
set_max_skew -from {*rgray[*]} -to {*rgray_s1[*]} 1.0
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Ch352 — design fabric <-> EMIF user clock are ASYNCHRONOUS (Codex). Every
|
||||
# fabric<->emif transfer now goes through a real synchronizer: gray-pointer FIFOs
|
||||
# (max_skew above), the HPS-bridge status snapshots / toggle syncs, the
|
||||
# gs_lpddr_axi_master {arm,canary,fb_base} commit snapshot + admission-stable AXI,
|
||||
# and the video_src/scanout_lb commit-capture. So the tool must STOP timing these
|
||||
# crossings against the fast 310 MHz emif clock as if single-cycle (the source of
|
||||
# the −5.7/−7.5 ns violations). set_max_skew is a SEPARATE analysis and SURVIVES
|
||||
# clock groups, so the gray pointers stay bounded.
|
||||
#
|
||||
# SCOPE (Codex): ONLY the bridge/design fabric clocks vs the EMIF USER clock. Do
|
||||
# NOT wildcard the EMIF PHY/internal clocks — the EMIF IP constrains those itself;
|
||||
# grouping them would hide real intra-EMIF paths.
|
||||
#
|
||||
# CLOCK NAME (Codex, post-fit STA): the fabric base clock is u_pll|iopll_0_refclk,
|
||||
# NOT the CLOCK2_50 PORT. The PLL IP owns that port, so the TimeQuest clock at the
|
||||
# bridge/refclk node is named u_pll|iopll_0_refclk; get_clocks {CLOCK2_50} returned
|
||||
# an empty/1-clock collection, the group never activated, and placement burned ~76
|
||||
# min on the impossible fabric<->emif paths. The collection-size checks are now a
|
||||
# FATAL Tcl `error` (not a warning): a renamed/mistyped clock HALTS SDC immediately.
|
||||
# Ch352 DIAG — collections + fatal checks DISABLED with their constraints (orphaned otherwise).
|
||||
# set ch352_fabric_clks [get_clocks -nowarn {u_pll|iopll_0_refclk u_pll|iopll_0_outclk0}]
|
||||
# set ch352_emif_user [get_clocks -nowarn {u_emif_lpddr4b|iopll|iopll_0_outclk0}]
|
||||
# Ch352 LEAD CHANGE — false_path (both directions) INSTEAD of set_clock_groups. The clock-group declared the
|
||||
# EMIF user clock ASYNC to u_pll|iopll_0_refclk = CLOCK2_50 = the EMIF IP's OWN refclk source
|
||||
# (iopll_refclk_clk(CLOCK2_50)). Declaring a GENERATED clock asynchronous to the clock that GENERATES it is the
|
||||
# leading suspect for the fitter's pathological Place grind (June-26 placed in 19 min; the only timing-constraint
|
||||
# deltas since are this group + the gradient multicycle, and "ample RAM still stalled" ruled out congestion).
|
||||
# false_path CUTS the same fabric<->emif DATA paths — all RTL-synchronized (gray FIFOs + bridge snapshots + the
|
||||
# gs_lpddr_axi_master commit snapshot) — WITHOUT re-declaring the clock relationship the EMIF IP owns. set_max_skew
|
||||
# is a separate analysis and survives false_path, so the gray pointers stay bounded.
|
||||
# Ch352 DIAG (binary SDC-vs-RTL bisect) — fabric<->EMIF cut DISABLED. RTL CDC synchronizers make these crossings
|
||||
# safe regardless; STA will report the -5.7/-7.5ns false violations, which (like June-26's -66ns) do not block a
|
||||
# working board. Re-enable after the bisect tells us whether the SDC was the Place grind.
|
||||
# set_false_path -from $ch352_fabric_clks -to $ch352_emif_user
|
||||
# set_false_path -from $ch352_emif_user -to $ch352_fabric_clks
|
||||
# (post_message removed — it falsely claimed false_path was applied while the two lines above are commented out.)
|
||||
# DEFERRED (Codex, acknowledged NOT hidden): the Ch323/324 tile-spill/reload + writer DEBUG counters at
|
||||
# 0x080-0x0FC (spill_*_errs, dbg_z/c_*_count, feeder_addr) are read by the bridge directly from the emif
|
||||
# domain and are now inside the async group above. They are explicitly DEFERRED "stable-after-scene
|
||||
# diagnostics": INERT in the SH3 profile (GS_TILE_SPILL undefined -> the spill writers are tied off, counters
|
||||
# static 0), and in the GS_TILE_SPILL profile they are read only AFTER a render completes (writers quiescent,
|
||||
# values stable). They are NOT bundled-snapshot CDC. If a future flow polls them WHILE the spill writers are
|
||||
# active, they must be snapshotted (latch-on-quiesce, like the fill counters) before being trusted.
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# IO false paths — buttons, switches, LEDs are async to the design
|
||||
# clock (debounce/sample is handled in RTL via the rst_sync register).
|
||||
# ----------------------------------------------------------------------------
|
||||
set_false_path -from [get_ports {KEY[*]}]
|
||||
set_false_path -from [get_ports {SW[*]}]
|
||||
set_false_path -to [get_ports {LED[*]}]
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Abstract VIDEO_* ports — kept VIRTUAL_PIN ON in the QSF for
|
||||
# sim/TB compat (the Ch149 board TB references them via hierarchical
|
||||
# probe). They aren't real package pins, so a false_path is the
|
||||
# right constraint.
|
||||
# ----------------------------------------------------------------------------
|
||||
set_false_path -to [get_ports {VIDEO_R[*]}]
|
||||
set_false_path -to [get_ports {VIDEO_G[*]}]
|
||||
set_false_path -to [get_ports {VIDEO_B[*]}]
|
||||
set_false_path -to [get_ports {VIDEO_HSYNC}]
|
||||
set_false_path -to [get_ports {VIDEO_VSYNC}]
|
||||
set_false_path -to [get_ports {VIDEO_DE}]
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# HDMI ADV7513 output ports (Ch164) — real package pins. Ch164 is
|
||||
# the "get pixels off-chip" first move; proper `set_output_delay`
|
||||
# constraints with respect to a generated HDMI_TX_CLK domain land
|
||||
# alongside the Ch165+ ADV7513 I²C wake-up FSM (the chip's actual
|
||||
# setup/hold window comes out of the wake-up pass). Until then,
|
||||
# false_path keeps STA quiet on the HDMI pins.
|
||||
# ----------------------------------------------------------------------------
|
||||
set_false_path -to [get_ports {HDMI_TX_CLK}]
|
||||
set_false_path -to [get_ports {HDMI_TX_D[*]}]
|
||||
set_false_path -to [get_ports {HDMI_TX_HS}]
|
||||
set_false_path -to [get_ports {HDMI_TX_VS}]
|
||||
set_false_path -to [get_ports {HDMI_TX_DE}]
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# ADV7513 control / wake-up pins (Ch165) — clocked on the slow I²C
|
||||
# domain (~20 kHz, derived inside `I2C_HDMI_Config` from CLOCK2_50)
|
||||
# and inherently async to design_clk. The interrupt input
|
||||
# `HDMI_TX_INT` is sampled by the wake-up FSM directly. Mark them
|
||||
# false-path so STA doesn't try to time the I²C bus or the audio
|
||||
# MCLK output against the design clock; their timing is dominated
|
||||
# by the I²C SCL period (50 µs) and well below any meaningful
|
||||
# constraint on the fabric.
|
||||
# ----------------------------------------------------------------------------
|
||||
set_false_path -to [get_ports {HDMI_I2C_SCL}]
|
||||
set_false_path -to [get_ports {HDMI_I2C_SDA}]
|
||||
set_false_path -from [get_ports {HDMI_I2C_SDA}]
|
||||
set_false_path -from [get_ports {HDMI_TX_INT}]
|
||||
set_false_path -to [get_ports {HDMI_MCLK}]
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Ch352 — triangle-setup gradient divide is a MULTICYCLE path, terminated at ONE
|
||||
# result register (Codex). gs_stub's gradient solve uses one shared combinational
|
||||
# signed divide (grad_num_q[grad_step] / grad_det_q); the RTL holds the sources
|
||||
# stable for GRAD_DIV_CYCLES=4 and captures the settled quotient into grad_result_q,
|
||||
# which is then written to the selected gradient FIFO on the following (single-cycle)
|
||||
# cycle. The exception DESTINATION is grad_result_q ALONE (~32 regs) — NOT the
|
||||
# {*u_gs|fifo_d*} fields. The old fifo_d* wildcard matched 5120 destinations x 837
|
||||
# sources (~4M endpoint pairs); the timing-driven placer churned on that matrix
|
||||
# indefinitely (Place stalled <1% for 50min+). Targeting grad_result_q drops the
|
||||
# matrix ~160x. The grad_result_q -> fifo write stays an ordinary single-cycle path.
|
||||
# ----------------------------------------------------------------------------
|
||||
# Bind the collections to variables and make the DESTINATION count fatal: grad_result_q is (* preserve *)'d to
|
||||
# exactly 32 regs. If synthesis still optimizes/renames it (count != 32) the exception would silently apply to
|
||||
# NOTHING and Place would churn the -66ns divider — so HALT here (same fail-fast policy as the clock-name checks),
|
||||
# before A&S->Place, instead of discovering a dead exception 50 minutes into Place.
|
||||
# Ch352 DIAG — collections + fatal check DISABLED with the multicycle (orphaned otherwise). NOTE: the error
|
||||
# string above had a Tcl `[31:0]` command-substitution bug that fired during routing once the check tripped.
|
||||
# set grad_mc_from [get_keepers -nowarn {*u_gs|grad_num_q* *u_gs|grad_det_q* *u_gs|grad_step*}]
|
||||
# set grad_mc_to [get_keepers -nowarn {*u_gs|grad_result_q*}]
|
||||
# Ch352 DIAG (binary SDC-vs-RTL bisect) — gradient multicycle DISABLED. The RTL grad_settle holds the divide
|
||||
# for GRAD_DIV_CYCLES=4 real cycles, so the divider is FUNCTIONALLY correct without this exception; STA will
|
||||
# report the divide as a -66ns single-cycle path (false — same as June-26, which placed and ran). Re-enable
|
||||
# after the bisect tells us whether the SDC was the Place grind.
|
||||
# set_multicycle_path -setup -end 4 -from $grad_mc_from -to $grad_mc_to
|
||||
# set_multicycle_path -hold -end 3 -from $grad_mc_from -to $grad_mc_to
|
||||
+961
@@ -0,0 +1,961 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2026 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
# the Altera IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Altera and sold by Altera or its authorized distributors. Please
|
||||
# refer to the Altera Software License Subscription Agreements
|
||||
# on the Quartus Prime software download page.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 26.1.0 Build 110 03/26/2026 SC Pro Edition
|
||||
# Date created = 10:50:30 May 11, 2026
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Note:
|
||||
#
|
||||
# 1) Do not modify this file. This file was generated
|
||||
# automatically by the Quartus Prime software and is used
|
||||
# to preserve global assignments across Quartus Prime versions.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
|
||||
set_global_assignment -name IP_COMPONENT_INTERNAL Off
|
||||
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
|
||||
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
|
||||
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
|
||||
set_global_assignment -name MAX_IGNORED_ASGN_MSG 10
|
||||
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
|
||||
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
|
||||
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
|
||||
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
|
||||
set_global_assignment -name FLOW_ENABLE_EARLY_TIMING_ANALYSIS Off
|
||||
set_global_assignment -name FLOW_ENABLE_INTERACTIVE_TIMING_ANALYZER On
|
||||
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
|
||||
set_global_assignment -name HC_OUTPUT_DIR hc_output
|
||||
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
|
||||
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
|
||||
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
|
||||
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
|
||||
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
|
||||
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
|
||||
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
|
||||
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
|
||||
set_global_assignment -name ENABLE_FIT_RPT_RESOURCE_BY_ENTITY Off
|
||||
set_global_assignment -name INVALID_DESIGN_SOURCE Off
|
||||
set_global_assignment -name FLOW_ENABLE_DESIGN_ASSISTANT On -family "Agilex 5"
|
||||
set_global_assignment -name FLOW_ENABLE_DESIGN_ASSISTANT On -family "Agilex 3"
|
||||
set_global_assignment -name FLOW_ENABLE_DESIGN_ASSISTANT On -family "Agilex 7"
|
||||
set_global_assignment -name FLOW_ENABLE_DESIGN_ASSISTANT On -family "Stratix 10"
|
||||
set_global_assignment -name FLOW_ENABLE_DESIGN_ASSISTANT On -family "Liberty Mesa"
|
||||
set_global_assignment -name DESIGN_ASSISTANT_WAIVER_FILE da_drc.dawf
|
||||
set_global_assignment -name DESIGN_ASSISTANT_INCLUDE_IP_BLOCKS Off
|
||||
set_global_assignment -name DRC_RAM_INFERENCE_HIGH_FANOUT_NET_THRESHOLD 15
|
||||
set_global_assignment -name DESIGN_ASSISTANT_MAX_VIOLATIONS_PER_RULE 5000
|
||||
set_global_assignment -name FLOW_ENABLE_EDA_NETLIST_WRITER Off
|
||||
set_global_assignment -name ERROR_ON_INVALID_ENTITY_NAME Off
|
||||
set_global_assignment -name ENABLE_COMMON_IP_FILES_DIRECTORY Off
|
||||
set_global_assignment -name COMMON_IP_FILES_DIRECTORY common_ip_files
|
||||
set_global_assignment -name ENABLE_GENERATION_OUTPUT_DIRECTORY Off
|
||||
set_global_assignment -name GENERATION_OUTPUT_DIRECTORY generation_output
|
||||
set_global_assignment -name PROJECT_SOURCE_DIRECTORY src
|
||||
set_global_assignment -name PROJECT_GENERATION_DIRECTORY gen
|
||||
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
|
||||
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
|
||||
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
|
||||
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
|
||||
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
|
||||
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
|
||||
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
|
||||
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Liberty Mesa"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Agilex 5"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Agilex 3"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Agilex 7"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_SIMULTANEOUS_MULTICORNER_ANALYSIS On
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
|
||||
set_global_assignment -name STA_AUTO_DESIGN_CLOSURE_REPORT_SUMMARY On
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_CDC_VIEWER Off
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 10
|
||||
set_global_assignment -name TIMING_ANAYZER_REPORT_WORST_CASE_TIMING_PATHS_SHOW_ROUTING Off
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Agilex 7"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Agilex 3"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Liberty Mesa"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Agilex 5"
|
||||
set_global_assignment -name FLOW_ENABLE_TIMING_ANALYZER_AFTER_PLAN_STAGE Off
|
||||
set_global_assignment -name MIN_MTBF_REQUIREMENT 9
|
||||
set_global_assignment -name STA_AUTO_UPDATE_TIMING_NETLIST On
|
||||
set_global_assignment -name STA_AUTO_REPORT_SETUP_SUMMARY On
|
||||
set_global_assignment -name STA_POST_SYN_DELAY_MODEL "Average Value"
|
||||
set_global_assignment -name STA_POST_PLAN_DELAY_MODEL "Average Value"
|
||||
set_global_assignment -name STA_POST_SYN_REGISTER_PACKING Off
|
||||
set_global_assignment -name OPTIMIZATION_MODE Balanced
|
||||
set_global_assignment -name ALLOW_REGISTER_MERGING On
|
||||
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
|
||||
set_global_assignment -name ALLOW_REGISTER_RETIMING On
|
||||
set_global_assignment -name ALLOW_RAM_RETIMING On -family "Agilex 7"
|
||||
set_global_assignment -name ALLOW_RAM_RETIMING Off -family "Stratix 10"
|
||||
set_global_assignment -name ALLOW_RAM_RETIMING On -family "Agilex 3"
|
||||
set_global_assignment -name ALLOW_RAM_RETIMING On -family "Agilex 5"
|
||||
set_global_assignment -name ALLOW_DSP_RETIMING Off -family "Stratix 10"
|
||||
set_global_assignment -name ALLOW_DSP_RETIMING On -family "Agilex 7"
|
||||
set_global_assignment -name ALLOW_DSP_RETIMING On -family "Agilex 3"
|
||||
set_global_assignment -name ALLOW_DSP_RETIMING On -family "Agilex 5"
|
||||
set_global_assignment -name MUX_RESTRUCTURE Auto
|
||||
set_global_assignment -name WAIVE_GATED_CLOCK_SYNCHRONIZER_CHECK On
|
||||
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
|
||||
set_global_assignment -name SAVE_DISK_SPACE On
|
||||
set_global_assignment -name OCP_HW_EVAL Enable
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
|
||||
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
|
||||
set_global_assignment -name FAMILY "Cyclone 10 GX"
|
||||
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
|
||||
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
|
||||
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
|
||||
set_global_assignment -name SAFE_STATE_MACHINE Auto
|
||||
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
|
||||
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
|
||||
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
|
||||
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
|
||||
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
|
||||
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
|
||||
set_global_assignment -name PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name DSP_ACTION_ON_MISS Ignore
|
||||
set_global_assignment -name DSP_BLOCK_BALANCING Auto
|
||||
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
|
||||
set_global_assignment -name NOT_GATE_PUSH_BACK On
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
|
||||
set_global_assignment -name DISABLE_REGISTER_POWER_UP_INITIALIZATION Off
|
||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
|
||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
|
||||
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_SOFT_BUFFERS On
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
|
||||
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
|
||||
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
|
||||
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
|
||||
set_global_assignment -name AUTO_LCELL_INSERTION On
|
||||
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
|
||||
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
|
||||
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
|
||||
set_global_assignment -name AUTO_CASCADE_CHAINS On
|
||||
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS Off -family "Agilex 5"
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -family "Agilex 7"
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -family "Stratix 10"
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -family "Arria 10"
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -family "Cyclone 10 GX"
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
|
||||
set_global_assignment -name AUTO_ROM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_RAM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_DSP_RECOGNITION On
|
||||
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
|
||||
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name PHYSICAL_SHIFT_REGISTER_INFERENCE Off -family "Liberty Mesa"
|
||||
set_global_assignment -name PHYSICAL_SHIFT_REGISTER_INFERENCE On -family "Agilex 5"
|
||||
set_global_assignment -name PHYSICAL_SHIFT_REGISTER_INFERENCE On -family "Agilex 3"
|
||||
set_global_assignment -name PHYSICAL_SHIFT_REGISTER_INFERENCE On -family "Stratix 10"
|
||||
set_global_assignment -name PHYSICAL_SHIFT_REGISTER_INFERENCE On -family "Agilex 7"
|
||||
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
|
||||
set_global_assignment -name STRICT_RAM_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
|
||||
set_global_assignment -name FORCE_SYNCH_CLEAR Off
|
||||
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
|
||||
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
|
||||
set_global_assignment -name AUTO_RESOURCE_SHARING Off
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
|
||||
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
|
||||
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
|
||||
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix 10"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Liberty Mesa"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 GX"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
|
||||
set_global_assignment -name REPORT_CONSTRAINT_PROPAGATION On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
|
||||
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
|
||||
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
|
||||
set_global_assignment -name MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED 3 -family "Liberty Mesa"
|
||||
set_global_assignment -name MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED 3 -family "Agilex 5"
|
||||
set_global_assignment -name MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED 3 -family "Agilex 3"
|
||||
set_global_assignment -name MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED 3 -family "Arria 10"
|
||||
set_global_assignment -name MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED 3 -family "Agilex 7"
|
||||
set_global_assignment -name MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED 3 -family "Stratix 10"
|
||||
set_global_assignment -name MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED 3 -family "Cyclone 10 GX"
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
|
||||
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
|
||||
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
|
||||
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
|
||||
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_OPTIMIZED_AWAY_HIERARCHIES_REPORTED 100
|
||||
set_global_assignment -name NUMBER_OF_TOP_ROOT_CAUSES_REPORTED 10
|
||||
set_global_assignment -name GROUP_IDENTICAL_HIERARCHIES On
|
||||
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
|
||||
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
|
||||
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
|
||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
|
||||
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
|
||||
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
|
||||
set_global_assignment -name SYNTH_CONSTRAINT_OPTIMIZATION_PRECEDENCE "Prioritize Optimization"
|
||||
set_global_assignment -name SYNTHESIS_EFFORT Auto
|
||||
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
|
||||
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 GX"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Agilex 3"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Agilex 5"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix 10"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Agilex 7"
|
||||
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
|
||||
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
|
||||
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
|
||||
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name PRPOF_ID Off
|
||||
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS_TO_ASCII_PRO On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_TO_ASCII_PRO On
|
||||
set_global_assignment -name REPORT_ENTITY_UTILIZATION_TO_ASCII_PRO On
|
||||
set_global_assignment -name SIZE_OF_LATCH_REPORT 100
|
||||
set_global_assignment -name ENABLE_VHDL_STATIC_ASSERTIONS Off
|
||||
set_global_assignment -name ENABLE_SV_STATIC_ASSERTIONS Off
|
||||
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE On
|
||||
set_global_assignment -name VERILOG_ALLOW_RAM_INFERRED_IN_GENERATE_LOOP Off
|
||||
set_global_assignment -name ENABLE_FORMAL_VERIFICATION Off
|
||||
set_global_assignment -name SIZE_OF_PR_INITIAL_CONDITIONS_REPORT 100
|
||||
set_global_assignment -name SIZE_OF_IGNORED_POWER_UP_REPORT 500
|
||||
set_global_assignment -name REPORT_PR_INITIAL_VALUES_AS_ERROR Off
|
||||
set_global_assignment -name FRACTAL_SYNTHESIS Off
|
||||
set_global_assignment -name AGGRESSIVE_MUX_AREA_OPTIMIZATION Auto
|
||||
set_global_assignment -name CONVERT_6LUT_TO_EXTENDED_MODE Auto
|
||||
set_global_assignment -name SYNTHESIS_AVAILABLE_RESOURCE_MULTIPLIER 1
|
||||
set_global_assignment -name UNCONNECTED_OUTPUT_PORT_MESSAGE_LEVEL Warning
|
||||
set_global_assignment -name ENABLE_FPGA_TAMPER_DETECTION Off
|
||||
set_global_assignment -name BARRELSHIFTER_CARRY_CHAIN_PACKING Auto
|
||||
set_global_assignment -name INIT_ENUM_TO_X Off
|
||||
set_global_assignment -name ENABLE_DYNAMIC_REPORT Off
|
||||
set_global_assignment -name USE_COMPRESSOR_IMPLEMENTATION Auto
|
||||
set_global_assignment -name DOWNGRADE_ERROR_ON_DUPLICATE_ATTRIBUTE Off
|
||||
set_global_assignment -name ENABLE_VERILOG_NETLIST_READER Off
|
||||
set_global_assignment -name SHOW_COLLAPSIBLE_ROWS_IN_ASCII_REPORT_FOR_WARNING_SUMMARY_REPORT On
|
||||
set_global_assignment -name ENFORCE_CLK_ENABLE_INFERENCING_IN_M20KS On
|
||||
set_global_assignment -name RTL_ANALYSIS_DEBUG_MODE Off
|
||||
set_global_assignment -name ENABLE_FAST_HIERARCHY_DISPLAY On
|
||||
set_global_assignment -name DISABLE_ANSI_SEARCH_INCLUDE_DIR Off
|
||||
set_global_assignment -name ENABLE_DEFENSIVE_SYNTHESIS Waive
|
||||
set_global_assignment -name ENABLE_ARRAY_INSTANCES_FOR_LPARAM Off
|
||||
set_global_assignment -name ENABLE_RELAXED_CHECKING_MODE Off
|
||||
set_global_assignment -name ENABLE_CREATE_NAME_FOR_UNNAMED_GEN_BLOCK Off
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
|
||||
set_global_assignment -name AUTO_MERGE_PLLS On
|
||||
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
|
||||
set_global_assignment -name TXPMA_SLEW_RATE Low
|
||||
set_global_assignment -name ADCE_ENABLED Auto
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS On -family "Agilex 3"
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS On -family "Agilex 5"
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS Off -family "Cyclone 10 GX"
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS Off -family "Arria 10"
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS On -family "Stratix 10"
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS On -family "Agilex 7"
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS Off -family "Liberty Mesa"
|
||||
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
|
||||
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
|
||||
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
|
||||
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
|
||||
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
|
||||
set_global_assignment -name STRATIX_UPDATE_MODE Standard
|
||||
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
|
||||
set_global_assignment -name CVP_MODE Off
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Internal Configuration" -family "Liberty Mesa"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone 10 GX"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x4" -family "eASIC N5X"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x4" -family "Agilex 7"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x4" -family "Stratix 10"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x4" -family "Agilex 3"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x4" -family "Agilex 5"
|
||||
set_global_assignment -name VID_OPERATION_MODE "PMBus Master"
|
||||
set_global_assignment -name USE_CONF_DONE Off
|
||||
set_global_assignment -name USE_PWRMGT_SCL Off
|
||||
set_global_assignment -name USE_PWRMGT_SDA Off
|
||||
set_global_assignment -name USE_PWRMGT_ALERT Off
|
||||
set_global_assignment -name USE_INIT_DONE Off
|
||||
set_global_assignment -name USE_CVP_CONFDONE Off
|
||||
set_global_assignment -name USE_SEU_ERROR Off
|
||||
set_global_assignment -name USE_HPS_COLD_RESET Off
|
||||
set_global_assignment -name USE_HPS_WARM_RESET Off
|
||||
set_global_assignment -name HPS_WARM_RESET_PIN_MODE BIDIRECTIONAL
|
||||
set_global_assignment -name HPS_COLD_RESET_PIN_MODE BIDIRECTIONAL
|
||||
set_global_assignment -name USE_UIB_CATTRIP Off
|
||||
set_global_assignment -name USE_NCATTRIP Off
|
||||
set_global_assignment -name USE_ANTI_TAMPER Off
|
||||
set_global_assignment -name USE_TAMPER_DETECT Off
|
||||
set_global_assignment -name ANTI_TAMPER_RESPONSE_FAILED Off
|
||||
set_global_assignment -name SDM_PCIE_CALIB_START Off
|
||||
set_global_assignment -name SDM_DIRECT_TO_FACTORY_IMAGE Off
|
||||
set_global_assignment -name USE_DATA_UNLOCK Off
|
||||
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name USER_START_UP_CLOCK Off
|
||||
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
|
||||
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off -family "Cyclone 10 GX"
|
||||
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL On -family "Agilex 3"
|
||||
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off -family "Arria 10"
|
||||
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL On -family "Liberty Mesa"
|
||||
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL On -family "Agilex 5"
|
||||
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off -family "Agilex 7"
|
||||
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off -family "Stratix 10"
|
||||
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
|
||||
set_global_assignment -name ALLOW_VCCR_VCCT_PER_BANK Off
|
||||
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -family "Agilex 3"
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -family "Agilex 5"
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -family "eASIC N5X"
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -family "Cyclone 10 GX"
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -family "Arria 10"
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -family "Stratix 10"
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -family "Agilex 7"
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -family "Liberty Mesa"
|
||||
set_global_assignment -name ENABLE_VREFA_PIN Off
|
||||
set_global_assignment -name ENABLE_VREFB_PIN Off
|
||||
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
|
||||
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
|
||||
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
|
||||
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
|
||||
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
|
||||
set_global_assignment -name ENABLE_NCE_PIN Off
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN Off
|
||||
set_global_assignment -name CRC_ERROR_CHECKING Off
|
||||
set_global_assignment -name MINIMUM_SEU_INTERVAL 10000
|
||||
set_global_assignment -name INTERNAL_SCRUBBING Off
|
||||
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
|
||||
set_global_assignment -name PR_READY_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CVP_CONFDONE Off
|
||||
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Agilex 3"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 GX"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Agilex 7"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix 10"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Liberty Mesa"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Agilex 5"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Liberty Mesa"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Agilex 7"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix 10"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Agilex 3"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Agilex 5"
|
||||
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
|
||||
set_global_assignment -name REPORT_DSP_PACKED_REGISTER_NAMES On
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Cyclone 10 GX"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
|
||||
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
|
||||
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
|
||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
|
||||
set_global_assignment -name SKIP_DSP_SKEW_OPT Off
|
||||
set_global_assignment -name ENABLE_DSP_REGISTER_UNPACKING On
|
||||
set_global_assignment -name IGNORE_SDC_CONSTRAINTS_FOR_REGISTER_PACKING On
|
||||
set_global_assignment -name ENABLE_INFERRED_SHIFT_REG_COUNTER_DUPLICATION On
|
||||
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
|
||||
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
|
||||
set_global_assignment -name FITTER_DENSITY_PACKING_EFFORT Normal
|
||||
set_global_assignment -name SEED 1
|
||||
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
|
||||
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
|
||||
set_global_assignment -name SLOW_SLEW_RATE Off
|
||||
set_global_assignment -name PCI_IO Off
|
||||
set_global_assignment -name TURBO_BIT On
|
||||
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
|
||||
set_global_assignment -name WEAK_PULL_DOWN_RESISTOR Off
|
||||
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
|
||||
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
|
||||
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
|
||||
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
|
||||
set_global_assignment -name NORMAL_LCELL_INSERT On
|
||||
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Liberty Mesa"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 GX"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix 10"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Agilex 7"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Agilex 3"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Agilex 5"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
|
||||
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
|
||||
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
|
||||
set_global_assignment -name AUTO_TURBO_BIT ON
|
||||
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
|
||||
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
|
||||
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
|
||||
set_global_assignment -name FITTER_EFFORT "Auto Fit"
|
||||
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
|
||||
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
|
||||
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE On
|
||||
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
|
||||
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
|
||||
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
|
||||
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
|
||||
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
|
||||
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
|
||||
set_global_assignment -name AUTO_ANALYZE_METASTABILITY Off
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone 10 GX"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
|
||||
set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Agilex 5"
|
||||
set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Agilex 3"
|
||||
set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Stratix 10"
|
||||
set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Agilex 7"
|
||||
set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Liberty Mesa"
|
||||
set_global_assignment -name ALLOW_SEU_FAULT_INJECTION Off -family "Liberty Mesa"
|
||||
set_global_assignment -name ALLOW_SEU_FAULT_INJECTION Off -family "Agilex 7"
|
||||
set_global_assignment -name ALLOW_SEU_FAULT_INJECTION Off -family "Stratix 10"
|
||||
set_global_assignment -name ALLOW_SEU_FAULT_INJECTION Off -family "Agilex 5"
|
||||
set_global_assignment -name ALLOW_SEU_FAULT_INJECTION Off -family "Agilex 3"
|
||||
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone 10 GX"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "eASIC N5X"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Agilex 3"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Liberty Mesa"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Agilex 5"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Agilex 7"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Stratix 10"
|
||||
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
|
||||
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
|
||||
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
|
||||
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
|
||||
set_global_assignment -name PR_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name NCEO_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
|
||||
set_global_assignment -name ENABLE_PR_PINS Off
|
||||
set_global_assignment -name RESERVE_PR_PINS Off
|
||||
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
|
||||
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
|
||||
set_global_assignment -name CLAMPING_DIODE Off
|
||||
set_global_assignment -name TRI_STATE_SPI_PINS Off
|
||||
set_global_assignment -name UNUSED_TSD_PINS_GND Off
|
||||
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
|
||||
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On
|
||||
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
|
||||
set_global_assignment -name SEU_FIT_REPORT Off
|
||||
set_global_assignment -name GLOBAL_PLACEMENT_EFFORT Normal
|
||||
set_global_assignment -name OPTIMIZE_PERSONA_ROUTABILITY Off
|
||||
set_global_assignment -name NUMBER_OF_EXAMPLE_NODES_REPORTED 50
|
||||
set_global_assignment -name PR_SECURITY_VALIDATION Off
|
||||
set_global_assignment -name ENABLE_INTERMEDIATE_SNAPSHOTS Off
|
||||
set_global_assignment -name FITTER_EARLY_RETIMING On -family "Agilex 3"
|
||||
set_global_assignment -name FITTER_EARLY_RETIMING On -family "Agilex 5"
|
||||
set_global_assignment -name FITTER_EARLY_RETIMING On -family "Stratix 10"
|
||||
set_global_assignment -name FITTER_EARLY_RETIMING On -family "Agilex 7"
|
||||
set_global_assignment -name FITTER_EARLY_RETIMING Off -family "Liberty Mesa"
|
||||
set_global_assignment -name SCHMITT_TRIGGER On
|
||||
set_global_assignment -name ENABLE_TIME_BORROWING_OPTIMIZATION Off -family "Cyclone 10 GX"
|
||||
set_global_assignment -name ENABLE_TIME_BORROWING_OPTIMIZATION Off -family "Arria 10"
|
||||
set_global_assignment -name ENABLE_TIME_BORROWING_OPTIMIZATION On -family "Agilex 7"
|
||||
set_global_assignment -name ENABLE_TIME_BORROWING_OPTIMIZATION Off -family "Stratix 10"
|
||||
set_global_assignment -name ENABLE_TIME_BORROWING_OPTIMIZATION On -family "Agilex 3"
|
||||
set_global_assignment -name ENABLE_TIME_BORROWING_OPTIMIZATION On -family "Agilex 5"
|
||||
set_global_assignment -name GLOBAL_SIGNAL_PROMOTION_FANOUT_THRESHOLD 50
|
||||
set_global_assignment -name PHYSICAL_RAM_RPT_MAX_ROW 500
|
||||
set_global_assignment -name WIRELUT_REMOVAL_SETUP_GUARD_BAND 100
|
||||
set_global_assignment -name WIRELUT_REMOVAL_HOLD_GUARD_BAND 100
|
||||
set_global_assignment -name FORCE_AVST_DUAL_MODE_PINS_FOR_PR Off
|
||||
set_global_assignment -name USE_ADDITIONAL_QSPI_FLASH Off
|
||||
set_global_assignment -name NOC_COMMON_ADDRESS_RANGE_SECURITY_CHECK Off
|
||||
set_global_assignment -name NOC_ADDRESS_CONSISTENCY_CHECK Off
|
||||
set_global_assignment -name S10_FIX_XCVR_PORT_MAPPING Off
|
||||
set_global_assignment -name FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD Off -family "Agilex 7"
|
||||
set_global_assignment -name FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD Off -family "Stratix 10"
|
||||
set_global_assignment -name FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD Off -family "Agilex 3"
|
||||
set_global_assignment -name FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD Off -family "Agilex 5"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ON_HIERARCHY On -family "Agilex 5"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ON_HIERARCHY On -family "Agilex 3"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ON_HIERARCHY On -family "Agilex 7"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ON_HIERARCHY On -family "Stratix 10"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_CUT_ALL_CLOCK_TRANSFERS On
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
|
||||
set_global_assignment -name CRITICAL_CHAIN_VIEWER On
|
||||
set_global_assignment -name HYPER_RETIMER_ENABLE_ADD_PIPELINING On
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (Verilog)"
|
||||
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING On -family "Agilex 3"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -family "Cyclone 10 GX"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING On -family "Agilex 7"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -family "Stratix 10"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING On -family "Agilex 5"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING On -family "Liberty Mesa"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -family "Arria 10"
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -family "Cyclone 10 GX"
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 5p0 -family "Agilex 7"
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -family "Stratix 10"
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -family "Arria 10"
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 5p0 -family "Agilex 3"
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 5p0 -family "Agilex 5"
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 5p0 -family "Liberty Mesa"
|
||||
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
|
||||
set_global_assignment -name COMPRESSION_MODE Off
|
||||
set_global_assignment -name CLOCK_SOURCE Internal
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
|
||||
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
|
||||
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
|
||||
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
|
||||
set_global_assignment -name SECURITY_BIT Off
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name PWRMGT_TABLE_VERSION 1
|
||||
set_global_assignment -name PWRMGT_ADV_VOLTAGE_STABLE_DELAY 10
|
||||
set_global_assignment -name PWRMGT_ADV_FPGA_RELEASE_DELAY 10
|
||||
set_global_assignment -name PWRMGT_ADV_INITIAL_DELAY 0
|
||||
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHz"
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTM4677
|
||||
set_global_assignment -name PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE 00
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 00
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00
|
||||
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
|
||||
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N 0
|
||||
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT Volts
|
||||
set_global_assignment -name PWRMGT_VID_FORMAT_BASE_VOLTAGE 0
|
||||
set_global_assignment -name PWRMGT_VID_FORMAT_STEP_SIZE 0
|
||||
set_global_assignment -name PWRMGT_ADV_DATA_SETUP_TIME 0
|
||||
set_global_assignment -name PWRMGT_ADV_DATA_HOLD_TIME 0
|
||||
set_global_assignment -name PWRMGT_ADV_CLOCK_DATA_FALL_TIME 0
|
||||
set_global_assignment -name PWRMGT_ADV_CLOCK_DATA_RISE_TIME 0
|
||||
set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE Off
|
||||
set_global_assignment -name PWRMGT_ADV_VOUT_READING_ERR_MARGIN 8
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
|
||||
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name GENERATE_TTF_FILE Off
|
||||
set_global_assignment -name GENERATE_RBF_FILE Off
|
||||
set_global_assignment -name GENERATE_PR_RBF_FILE On -family "Agilex 5"
|
||||
set_global_assignment -name GENERATE_PR_RBF_FILE On -family "Agilex 3"
|
||||
set_global_assignment -name GENERATE_PR_RBF_FILE On -family "Agilex 7"
|
||||
set_global_assignment -name GENERATE_PR_RBF_FILE On -family "Stratix 10"
|
||||
set_global_assignment -name GENERATE_PR_RBF_FILE Off -family "Arria 10"
|
||||
set_global_assignment -name GENERATE_PR_RBF_FILE Off -family "Cyclone 10 GX"
|
||||
set_global_assignment -name GENERATE_HEX_FILE Off
|
||||
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
|
||||
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
|
||||
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
|
||||
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
|
||||
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
|
||||
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off
|
||||
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
|
||||
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
|
||||
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
|
||||
set_global_assignment -name POR_SCHEME "Instant ON"
|
||||
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
|
||||
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
|
||||
set_global_assignment -name POF_VERIFY_PROTECT Off
|
||||
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
|
||||
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
|
||||
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
|
||||
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
|
||||
set_global_assignment -name GENERATE_PMSF_FILES On
|
||||
set_global_assignment -name RBF_FILE_GENERATION_FOR_SUPR On
|
||||
set_global_assignment -name ENABLE_PR_POF_ID On
|
||||
set_global_assignment -name HPS_INITIALIZATION "After INIT_DONE" -family "eASIC N5X"
|
||||
set_global_assignment -name HPS_INITIALIZATION "After INIT_DONE" -family "Agilex 7"
|
||||
set_global_assignment -name HPS_INITIALIZATION "After INIT_DONE" -family "Stratix 10"
|
||||
set_global_assignment -name HPS_INITIALIZATION "After INIT_DONE" -family "Agilex 3"
|
||||
set_global_assignment -name HPS_INITIALIZATION "After INIT_DONE" -family "Agilex 5"
|
||||
set_global_assignment -name HPS_DAP_SPLIT_MODE Disabled
|
||||
set_global_assignment -name PRIORITY_SEU_AREA Off
|
||||
set_global_assignment -name ENCRYPT_PROGRAMMING_BITSTREAM Off
|
||||
set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT "Quad SPI flash" -family "Agilex 3"
|
||||
set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT "Battery Backup RAM" -family "Agilex 5"
|
||||
set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT eFuses -family "eASIC N5X"
|
||||
set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT "Battery Backup RAM" -family "Agilex 7"
|
||||
set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT "Battery Backup RAM" -family "Stratix 10"
|
||||
set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_UPDATE_RATIO 0
|
||||
set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_CNOC_SCRAMBLING Off
|
||||
set_global_assignment -name HPS_DAP_NO_CERTIFICATE Off
|
||||
set_global_assignment -name RSU_MAX_RETRY_COUNT 1
|
||||
set_global_assignment -name SECU_OPTION_DISABLE_JTAG OFF
|
||||
set_global_assignment -name SECU_OPTION_FORCE_SDM_CLOCK_TO_INT_OSC OFF
|
||||
set_global_assignment -name SECU_OPTION_FORCE_ENCRYPTION_KEY_UPDATE OFF
|
||||
set_global_assignment -name SECU_OPTION_DISABLE_VIRTUAL_EFUSES OFF
|
||||
set_global_assignment -name SECU_OPTION_LOCK_SECURITY_EFUSES OFF
|
||||
set_global_assignment -name SECU_OPTION_DISABLE_HPS_DEBUG OFF
|
||||
set_global_assignment -name SECU_OPTION_DISABLE_ENCRYPTION_KEY_IN_EFUSES OFF
|
||||
set_global_assignment -name SECU_OPTION_DISABLE_ENCRYPTION_KEY_IN_BBRAM OFF
|
||||
set_global_assignment -name SECU_OPTION_DISABLE_PUF_WRAPPED_ENCRYPTION_KEY OFF
|
||||
set_global_assignment -name ENABLE_FREQUENCY_TAMPER_DETECTION Off
|
||||
set_global_assignment -name ENABLE_TEMPERATURE_TAMPER_DETECTION Off
|
||||
set_global_assignment -name ENABLE_VOLTAGE_TAMPER_DETECTION Off
|
||||
set_global_assignment -name ANTI_TAMPER_RESPONSE DISABLED
|
||||
set_global_assignment -name FREQUENCY_TAMPER_DETECTION_RANGE 35
|
||||
set_global_assignment -name TEMPERATURE_TAMPER_UPPER_BOUND 110
|
||||
set_global_assignment -name TEMPERATURE_TAMPER_LOWER_BOUND "-40"
|
||||
set_global_assignment -name ENABLE_VCCL_VOLTAGE_TAMPER_DETECTION Off
|
||||
set_global_assignment -name ENABLE_VCCL_SDM_VOLTAGE_TAMPER_DETECTION Off
|
||||
set_global_assignment -name ENABLE_VCCL_HPS_VOLTAGE_TAMPER_DETECTION Off
|
||||
set_global_assignment -name VOLTAGE_TAMPER_DETECTION_TRIGGER 15
|
||||
set_global_assignment -name VCCL_VOLTAGE_DIFFERENCE_TRIGGER 0
|
||||
set_global_assignment -name VCCL_SDM_VOLTAGE_DIFFERENCE_TRIGGER 0
|
||||
set_global_assignment -name RUN_CONFIG_CPU_FROM_INT_OSC Off
|
||||
set_global_assignment -name REPAIR_CLK_DIV_VAL 0
|
||||
set_global_assignment -name LOW_VOLTAGE_MODE Off
|
||||
set_global_assignment -name XCVR32_ACJTAG_CONFIG 46
|
||||
set_global_assignment -name GENERATE_COMPRESSED_SOF On
|
||||
set_global_assignment -name HPS_RETAIN_DDR_CONTENT Off
|
||||
set_global_assignment -name PWRMGT_PAGE_COMMAND_PAYLOAD 255
|
||||
set_global_assignment -name ENABLE_PARTIAL_RECONFIGURATION_BITSTREAM_ENCRYPTION Off
|
||||
set_global_assignment -name USE_ALIAS_L1 Off
|
||||
set_global_assignment -name ENABLE_S10_ATTESTATION_COMMANDS Off
|
||||
set_global_assignment -name ENABLE_MULTI_AUTHORITY Off
|
||||
set_global_assignment -name ENABLE_FREQUENCY_TAMPER_DEVICE_SELF_KILL Off
|
||||
set_global_assignment -name ENABLE_TEMPERATURE_TAMPER_DEVICE_SELF_KILL Off
|
||||
set_global_assignment -name ENABLE_VOLTAGE_TAMPER_DEVICE_SELF_KILL Off
|
||||
set_global_assignment -name ENABLE_FPGA_TAMPER_DEVICE_SELF_KILL Off
|
||||
set_global_assignment -name ENABLE_EXTERNAL_VOLTAGE_REFERENCE Off
|
||||
set_global_assignment -name GENERATE_PROGRAMMING_FILES Off
|
||||
set_global_assignment -name NUMBER_OF_SLAVE_DEVICE 1
|
||||
set_global_assignment -name SECU_OPTION_DISABLE_ALIAS_L1 OFF
|
||||
set_global_assignment -name SECU_OPTION_DISABLE_BETA OFF
|
||||
set_global_assignment -name TEMPERATURE_THRESHOLD_VALUE 120
|
||||
set_global_assignment -name ENABLE_EXTERNAL_SCRUBBING Off
|
||||
set_global_assignment -name ENABLE_STATUS_BYTE On
|
||||
set_global_assignment -name DISABLE_VID Off
|
||||
set_global_assignment -name ENABLE_PMF_DIAGNOSTIC Off
|
||||
set_global_assignment -name SEU_DETECTED_PIN_BEHAVIOR "Only uncorrectable"
|
||||
set_global_assignment -name ENABLE_OWNERSHIP_TRANSFER Off
|
||||
set_global_assignment -name FIPS_MODE Non_FIPS
|
||||
set_global_assignment -name ENABLE_SPDM_SECURE_MESSAGE_ROUTING Off
|
||||
set_global_assignment -name ENABLE_CRAM_INTEGRITY_CHECK Off
|
||||
set_global_assignment -name VR_VOLTAGE_MONITOR_SOURCE "Voltage Regulator"
|
||||
set_global_assignment -name QSPI_OWNERSHIP SDM
|
||||
set_global_assignment -name SIGNATURE_ALGORITHM ECDSA
|
||||
set_global_assignment -name NUMBER_OF_INTENDED_KEY_CHAINS 1
|
||||
set_global_assignment -name NUMBER_OF_INTENDED_PUBLIC_KEY_ENTRIES 3
|
||||
set_global_assignment -name START_TIME 0ns
|
||||
set_global_assignment -name SIMULATION_MODE TIMING
|
||||
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
|
||||
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION Off
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
|
||||
set_global_assignment -name CHECK_OUTPUTS Off
|
||||
set_global_assignment -name SIMULATION_COVERAGE On
|
||||
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name GLITCH_DETECTION Off
|
||||
set_global_assignment -name GLITCH_INTERVAL 1ns
|
||||
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
|
||||
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
|
||||
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
|
||||
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
|
||||
set_global_assignment -name DRC_TOP_FANOUT 50
|
||||
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
|
||||
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
|
||||
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
|
||||
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
|
||||
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
|
||||
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
|
||||
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
|
||||
set_global_assignment -name MERGE_HEX_FILE Off
|
||||
set_global_assignment -name GENERATE_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
|
||||
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
|
||||
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
|
||||
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
|
||||
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
|
||||
set_global_assignment -name PRESERVE_FOR_DEBUG_ENABLE Off
|
||||
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_USE_PVA On
|
||||
set_global_assignment -name POWER_USE_INPUT_FILES Off
|
||||
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
|
||||
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
|
||||
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL -family "Arria 10"
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM -family "Stratix 10"
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM -family "Agilex 7"
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL -family "Cyclone 10 GX"
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM -family "Agilex 5"
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM -family "Agilex 3"
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM -family "Liberty Mesa"
|
||||
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -family "Arria 10"
|
||||
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -family "Cyclone 10 GX"
|
||||
set_global_assignment -name POWER_TJ_VALUE 25
|
||||
set_global_assignment -name POWER_USE_TA_VALUE 50
|
||||
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
|
||||
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
|
||||
set_global_assignment -name POWER_COOLING_FOR_MAX_TJ Off
|
||||
set_global_assignment -name POWER_MAX_TJ_VALUE 100
|
||||
set_global_assignment -name POWER_PSI_CA_VALUE 0.5
|
||||
set_global_assignment -name POWER_USER_LIFE_VALUE 11.4
|
||||
set_global_assignment -name POWER_APPLY_THERMAL_MARGIN OFF
|
||||
set_global_assignment -name POWER_ADDITIONAL_MARGIN_PERCENTAGE 0.0
|
||||
set_global_assignment -name POWER_TEMPERATURE_MEASUREMENT_METHOD DTS
|
||||
set_global_assignment -name POWER_HPS_ENABLE Off
|
||||
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
|
||||
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
|
||||
set_global_assignment -name EARLY_POWER_ESTIMATOR_EXPORT_FILE $active_revision_early_pwr.csv
|
||||
set_global_assignment -name POWER_AND_THERMAL_ANALYZER_EXPORT_FILE $active_revision.qpta
|
||||
set_global_assignment -name POWER_PERCENT_HEAT_THROUGH_TOP_OF_PACKAGE 100
|
||||
set_global_assignment -name IGNORE_PARTITIONS Off
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
|
||||
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
|
||||
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
|
||||
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_BBOX_MERGE On
|
||||
set_global_assignment -name EQC_LVDS_MERGE On
|
||||
set_global_assignment -name EQC_RAM_UNMERGING On
|
||||
set_global_assignment -name EQC_DFF_SS_EMULATION On
|
||||
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
|
||||
set_global_assignment -name EQC_STRUCTURE_MATCHING On
|
||||
set_global_assignment -name EQC_AUTO_BREAK_CONE On
|
||||
set_global_assignment -name EQC_POWER_UP_COMPARE Off
|
||||
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
|
||||
set_global_assignment -name EQC_AUTO_INVERSION On
|
||||
set_global_assignment -name EQC_AUTO_TERMINATE On
|
||||
set_global_assignment -name EQC_SUB_CONE_REPORT Off
|
||||
set_global_assignment -name EQC_RENAMING_RULES On
|
||||
set_global_assignment -name EQC_PARAMETER_CHECK On
|
||||
set_global_assignment -name EQC_AUTO_PORTSWAP On
|
||||
set_global_assignment -name EQC_DETECT_DONT_CARES On
|
||||
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
|
||||
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
|
||||
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
|
||||
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
|
||||
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
|
||||
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
|
||||
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY On -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_GENERATE_SCRIPT_ONLY Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_USE_RELATIVE_PATH Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_START_WITH_CLEAN_DIR On -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_TYPE RTL -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_STAGE_FOR_GATE_LEVEL MOST_RECENT -section_id ?
|
||||
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
|
||||
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
|
||||
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_RTL_SIM_MODE TEST_BENCH_MODE -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_SDF_FOR_POWER Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
|
||||
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
|
||||
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
|
||||
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
|
||||
set_global_assignment -name EDA_FORCE_GATE_LEVEL_REG_INIT_X Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_AMI Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_PRE_SYNTH Off -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
|
||||
set_global_assignment -name PLL_REFCLK_INPUT_TYPE DIRECT -entity ?
|
||||
set_global_assignment -name HPS_EMIF_BANK_LOCATION PRIMARY -entity ?
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING On -entity ? -family "Agilex 3"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -entity ? -family "Cyclone 10 GX"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING On -entity ? -family "Agilex 7"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -entity ? -family "Stratix 10"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING On -entity ? -family "Agilex 5"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING On -entity ? -family "Liberty Mesa"
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -entity ? -family "Arria 10"
|
||||
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
|
||||
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
|
||||
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
|
||||
@@ -0,0 +1,115 @@
|
||||
# retroDE_ps2 — Ch148 (Ch159 retargeted) synthesis filelist for the
|
||||
# DE25-Nano PSMCT32 raster demo.
|
||||
#
|
||||
# This filelist contains ONLY the modules in the Ch123 dependency tree
|
||||
# (audited in Ch144) plus the Ch155+ BRAM wrapper additions. Synthesis
|
||||
# tools (Quartus / Vivado) accept this as a `-F filelist.f` argument
|
||||
# or import it directly.
|
||||
#
|
||||
# Ch159 swap: the board-shaped wrapper now instantiates
|
||||
# `top_psmct32_raster_demo_bram` (vram_bram_stub-backed) instead of
|
||||
# the legacy `top_psmct32_raster_demo` (vram_stub-backed). Both top
|
||||
# wrappers are kept compiled below so the file list is forward-
|
||||
# compatible with either board-top instantiation; Quartus only
|
||||
# elaborates the wrapper actually instantiated by
|
||||
# `de25_nano_psmct32_raster_demo_top.sv`.
|
||||
#
|
||||
# Path convention: relative to the repo root. Tools should be invoked
|
||||
# from the repo root, or paths can be made absolute by the project file.
|
||||
#
|
||||
# To validate the filelist + fixture presence without running synthesis:
|
||||
# make -C sim top_psmct32_raster_demo_synth_check
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# Common debug + trace package (compiled first; type aliases used
|
||||
# below).
|
||||
# ---------------------------------------------------------------------
|
||||
rtl/debug/trace_pkg.sv
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# Memory blocks (BIOS ROM + EE RAM + EE memory map).
|
||||
# ---------------------------------------------------------------------
|
||||
rtl/memory/bios_rom_stub.sv
|
||||
rtl/memory/ee_ram_stub.sv
|
||||
rtl/memory/ee_memory_map_stub.sv
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# EE core + GS-priv MMIO bridge.
|
||||
# ---------------------------------------------------------------------
|
||||
rtl/ee/ee_core_stub.sv
|
||||
rtl/gif_gs/ee_gs_priv_bridge_stub.sv
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# DMAC channel-2 (NORMAL transfer; DMAC reads RAM, streams to GIF).
|
||||
# ---------------------------------------------------------------------
|
||||
rtl/dmac/dmac_reg_stub.sv
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# GIF + GS data plane.
|
||||
#
|
||||
# Ch159 — both VRAM shapes are kept on the file list:
|
||||
# * `vram_stub` (legacy byte-addressable + per-bit RMW; used
|
||||
# by the Ch146 wrapper and every legacy sim TB)
|
||||
# * `vram_bram_stub` (Ch154 BRAM-friendly, 2048×32-bit, sync-read,
|
||||
# byte-WE only; used by the Ch155+ wrapper and
|
||||
# inferred as M20K by Quartus)
|
||||
# * `vram_normalize_pkg` (Ch155 pure-comb writer-side normalization)
|
||||
# Quartus only elaborates whichever VRAM the actually-instantiated top
|
||||
# wrapper depends on; the unused module is trimmed at hierarchy
|
||||
# resolution.
|
||||
# ---------------------------------------------------------------------
|
||||
rtl/gif_gs/gif_packed_stub.sv
|
||||
rtl/gif_gs/gs_stub.sv
|
||||
rtl/gif_gs/gif_image_xfer_stub.sv
|
||||
rtl/gif_gs/vram_normalize_pkg.sv
|
||||
rtl/gif_gs/vram_stub.sv
|
||||
rtl/gif_gs/vram_bram_stub.sv
|
||||
rtl/gif_gs/gs_pcrtc_stub.sv
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# Swizzle math primitives. The PSMCT32 demo only enables PSMCT32_SWIZZLE,
|
||||
# but gs_pcrtc_stub / gif_image_xfer_stub / gs_stub unconditionally
|
||||
# *instantiate* all four swizzle modules (the per-PSM muxer just
|
||||
# doesn't select them when their gate is 0). Quartus requires every
|
||||
# instantiated module to have a definition even when its outputs are
|
||||
# unused; the unused instances trim cleanly at fitter so the resource
|
||||
# cost is zero. iverilog (sim) trimmed them silently before; Quartus
|
||||
# (Ch152) made the dependency explicit.
|
||||
# ---------------------------------------------------------------------
|
||||
rtl/gif_gs/gs_swizzle_psmct32_stub.sv
|
||||
rtl/gif_gs/gs_swizzle_psmct16_stub.sv
|
||||
rtl/gif_gs/gs_swizzle_psmt8_stub.sv
|
||||
rtl/gif_gs/gs_swizzle_psmt4_stub.sv
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# Board-agnostic top wrappers.
|
||||
# * `top_psmct32_raster_demo` — Ch146 legacy vram_stub-backed
|
||||
# * `top_psmct32_raster_demo_bram` — Ch155+ BRAM-backed
|
||||
# (Ch159 board-top swap target)
|
||||
# ---------------------------------------------------------------------
|
||||
rtl/top/top_psmct32_raster_demo.sv
|
||||
rtl/top/top_psmct32_raster_demo_bram.sv
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# Ch165 — Terasic-derived ADV7513 I²C wake-up FSM + the bit-bang
|
||||
# I²C controller it drives. Plain Verilog (not SystemVerilog); the
|
||||
# wake-up walks a 38-entry LUT of canonical ADV7513 register writes
|
||||
# to bring the chip out of standby.
|
||||
# ---------------------------------------------------------------------
|
||||
rtl/platform/I2C_Controller.v
|
||||
rtl/platform/I2C_HDMI_Config.v
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# DE25-Nano PLL sim stub (Ch151) — pass-through clock + lock counter.
|
||||
# Mimics Quartus's IOPLL "pll" module signature so synthesis can swap
|
||||
# in the real IP via `\`ifdef USE_PLL_IP` without changing RTL.
|
||||
# ---------------------------------------------------------------------
|
||||
rtl/top/de25_nano_pll_stub.sv
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# DE25-Nano board-shaped wrapper (Ch149+Ch151) — board signal names,
|
||||
# PLL + reset-release sequencer, status LEDs, raw video pass-through.
|
||||
# Board pin assignments (.qsf), PLL .ip enablement, and PHY shim are
|
||||
# deferred to later chapters.
|
||||
# ---------------------------------------------------------------------
|
||||
rtl/top/de25_nano_psmct32_raster_demo_top.sv
|
||||
File diff suppressed because it is too large
Load Diff
+702
@@ -0,0 +1,702 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2025 Altera Corporation. All rights reserved.
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
the Altera IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Altera and sold by Altera or its authorized distributors. Please
|
||||
refer to the Altera Software License Subscription Agreements
|
||||
on the Quartus Prime software download page.
|
||||
*/
|
||||
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(text "arvalid" (rect 226 521 494 1052)(font "SansSerif" (color 0 0 0)))
|
||||
(text "aruser" (rect 226 546 488 1102)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arprot" (rect 226 571 488 1152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arready" (rect 226 596 494 1202)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wdata" (rect 226 621 482 1252)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wstrb" (rect 226 646 482 1302)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wlast" (rect 226 671 482 1352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wvalid" (rect 226 696 488 1402)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wready" (rect 226 721 488 1452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bready" (rect 226 746 488 1502)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bid" (rect 226 771 470 1552)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bresp" (rect 226 796 482 1602)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bvalid" (rect 226 821 488 1652)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rready" (rect 226 846 488 1702)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rdata" (rect 226 871 482 1752)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rid" (rect 226 896 470 1802)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rlast" (rect 226 921 482 1852)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rresp" (rect 226 946 482 1902)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rvalid" (rect 226 971 488 1952)(font "SansSerif" (color 0 0 0)))
|
||||
(text "emif_lpddr4b_s0_axi4lite_clock" (rect 38 996 256 2005)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 226 1021 470 2052)(font "SansSerif" (color 0 0 0)))
|
||||
(text "emif_lpddr4b_s0_axi4lite_reset_n" (rect 22 1046 236 2105)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "reset_n" (rect 226 1071 494 2152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "emif_lpddr4b_s0_axi4lite" (rect 75 1096 294 2205)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "awaddr" (rect 226 1121 488 2252)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awprot" (rect 226 1146 488 2302)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awvalid" (rect 226 1171 494 2352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awready" (rect 226 1196 494 2402)(font "SansSerif" (color 0 0 0)))
|
||||
(text "araddr" (rect 226 1221 488 2452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arprot" (rect 226 1246 488 2502)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arvalid" (rect 226 1271 494 2552)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arready" (rect 226 1296 494 2602)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wdata" (rect 226 1321 482 2652)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wstrb" (rect 226 1346 482 2702)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wvalid" (rect 226 1371 488 2752)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wready" (rect 226 1396 488 2802)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bready" (rect 226 1421 488 2852)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bresp" (rect 226 1446 482 2902)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bvalid" (rect 226 1471 488 2952)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rready" (rect 226 1496 488 3002)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rdata" (rect 226 1521 482 3052)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rresp" (rect 226 1546 482 3102)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rvalid" (rect 226 1571 488 3152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "emif_lpddr4b_mem" (rect 108 1596 312 3205)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "mem_cs" (rect 226 1621 488 3252)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_ca" (rect 226 1646 488 3302)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_cke" (rect 226 1671 494 3352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dq" (rect 226 1696 488 3402)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dqs_t" (rect 226 1721 506 3452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dqs_c" (rect 226 1746 506 3502)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dmi" (rect 226 1771 494 3552)(font "SansSerif" (color 0 0 0)))
|
||||
(text "emif_lpddr4b_mem_ck" (rect 87 1796 288 3605)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "mem_ck_t" (rect 226 1821 500 3652)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_ck_c" (rect 226 1846 500 3702)(font "SansSerif" (color 0 0 0)))
|
||||
(text "emif_lpddr4b_mem_reset_n" (rect 55 1871 254 3755)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "mem_reset_n" (rect 226 1896 518 3802)(font "SansSerif" (color 0 0 0)))
|
||||
(text "emif_lpddr4b_oct" (rect 120 1921 336 3855)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "oct_rzqin" (rect 226 1946 506 3902)(font "SansSerif" (color 0 0 0)))
|
||||
(text "emif_lpddr4b_ref_clk" (rect 96 1971 312 3955)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 226 1996 470 4002)(font "SansSerif" (color 0 0 0)))
|
||||
(text "iopll_refclk" (rect 158 2021 388 4055)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 226 2046 470 4102)(font "SansSerif" (color 0 0 0)))
|
||||
(text "iopll_locked" (rect 341 146 754 305)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 310 171 656 352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "iopll_reset" (rect 161 2071 388 4155)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "reset" (rect 226 2096 482 4202)(font "SansSerif" (color 0 0 0)))
|
||||
(text "iopll_outclk_axi4_lite" (rect 341 196 814 405)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 325 221 668 452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "reset" (rect 192 2121 414 4255)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "reset_n" (rect 226 2146 494 4302)(font "SansSerif" (color 0 0 0)))
|
||||
(text " system " (rect 526 2176 1100 4362)(font "SansSerif" ))
|
||||
(line (pt 221 34)(pt 340 34)(line_width 1))
|
||||
(line (pt 340 34)(pt 340 2176)(line_width 1))
|
||||
(line (pt 221 2176)(pt 340 2176)(line_width 1))
|
||||
(line (pt 221 34)(pt 221 2176)(line_width 1))
|
||||
(line (pt 339 55)(pt 339 80)(line_width 1))
|
||||
(line (pt 338 55)(pt 338 80)(line_width 1))
|
||||
(line (pt 339 105)(pt 339 130)(line_width 1))
|
||||
(line (pt 338 105)(pt 338 130)(line_width 1))
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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(line (pt 222 1005)(pt 222 1030)(line_width 1))
|
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(line (pt 223 1005)(pt 223 1030)(line_width 1))
|
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(line (pt 222 1055)(pt 222 1080)(line_width 1))
|
||||
(line (pt 223 1055)(pt 223 1080)(line_width 1))
|
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(line (pt 560 1201)(pt 221 1201)(line_width 1))
|
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(line (pt 560 1301)(pt 221 1301)(line_width 1))
|
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(line (pt 560 1401)(pt 221 1401)(line_width 1))
|
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(line (pt 560 1451)(pt 221 1451)(line_width 3))
|
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(line (pt 560 1476)(pt 221 1476)(line_width 1))
|
||||
(line (pt 560 1526)(pt 221 1526)(line_width 3))
|
||||
(line (pt 560 1551)(pt 221 1551)(line_width 3))
|
||||
(line (pt 560 1576)(pt 221 1576)(line_width 1))
|
||||
(line (pt 222 1105)(pt 222 1580)(line_width 1))
|
||||
(line (pt 223 1105)(pt 223 1580)(line_width 1))
|
||||
(line (pt 560 1626)(pt 221 1626)(line_width 1))
|
||||
(line (pt 560 1651)(pt 221 1651)(line_width 3))
|
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(line (pt 560 1676)(pt 221 1676)(line_width 1))
|
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(line (pt 222 1605)(pt 222 1780)(line_width 1))
|
||||
(line (pt 223 1605)(pt 223 1780)(line_width 1))
|
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(line (pt 560 1826)(pt 221 1826)(line_width 1))
|
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(line (pt 560 1851)(pt 221 1851)(line_width 1))
|
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(line (pt 222 1805)(pt 222 1855)(line_width 1))
|
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(line (pt 223 1805)(pt 223 1855)(line_width 1))
|
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(line (pt 560 1901)(pt 221 1901)(line_width 1))
|
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(line (pt 222 1880)(pt 222 1905)(line_width 1))
|
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(line (pt 223 1880)(pt 223 1905)(line_width 1))
|
||||
(line (pt 222 1930)(pt 222 1955)(line_width 1))
|
||||
(line (pt 223 1930)(pt 223 1955)(line_width 1))
|
||||
(line (pt 222 1980)(pt 222 2005)(line_width 1))
|
||||
(line (pt 223 1980)(pt 223 2005)(line_width 1))
|
||||
(line (pt 222 2030)(pt 222 2055)(line_width 1))
|
||||
(line (pt 223 2030)(pt 223 2055)(line_width 1))
|
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(line (pt 339 155)(pt 339 180)(line_width 1))
|
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(line (pt 338 155)(pt 338 180)(line_width 1))
|
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(line (pt 222 2080)(pt 222 2105)(line_width 1))
|
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(line (pt 223 2080)(pt 223 2105)(line_width 1))
|
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(line (pt 339 205)(pt 339 230)(line_width 1))
|
||||
(line (pt 338 205)(pt 338 230)(line_width 1))
|
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(line (pt 222 2130)(pt 222 2155)(line_width 1))
|
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(line (pt 223 2130)(pt 223 2155)(line_width 1))
|
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|
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|
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(line (pt 0 2193)(pt 560 2193)(line_width 1))
|
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(line (pt 0 0)(pt 0 2193)(line_width 1))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,82 @@
|
||||
component EMIF_Qsys is
|
||||
port (
|
||||
clock_310m_out_clk_clk : out std_logic; -- clk
|
||||
emif_lpddr4b_s0_axi4_ctrl_ready_reset_n : out std_logic; -- reset_n
|
||||
emif_lpddr4b_s0_axi4_awaddr : in std_logic_vector(29 downto 0) := (others => 'X'); -- awaddr
|
||||
emif_lpddr4b_s0_axi4_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst
|
||||
emif_lpddr4b_s0_axi4_awid : in std_logic_vector(6 downto 0) := (others => 'X'); -- awid
|
||||
emif_lpddr4b_s0_axi4_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- awlen
|
||||
emif_lpddr4b_s0_axi4_awlock : in std_logic := 'X'; -- awlock
|
||||
emif_lpddr4b_s0_axi4_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- awqos
|
||||
emif_lpddr4b_s0_axi4_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize
|
||||
emif_lpddr4b_s0_axi4_awvalid : in std_logic := 'X'; -- awvalid
|
||||
emif_lpddr4b_s0_axi4_awuser : in std_logic_vector(13 downto 0) := (others => 'X'); -- awuser
|
||||
emif_lpddr4b_s0_axi4_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
|
||||
emif_lpddr4b_s0_axi4_awready : out std_logic; -- awready
|
||||
emif_lpddr4b_s0_axi4_araddr : in std_logic_vector(29 downto 0) := (others => 'X'); -- araddr
|
||||
emif_lpddr4b_s0_axi4_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst
|
||||
emif_lpddr4b_s0_axi4_arid : in std_logic_vector(6 downto 0) := (others => 'X'); -- arid
|
||||
emif_lpddr4b_s0_axi4_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- arlen
|
||||
emif_lpddr4b_s0_axi4_arlock : in std_logic := 'X'; -- arlock
|
||||
emif_lpddr4b_s0_axi4_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- arqos
|
||||
emif_lpddr4b_s0_axi4_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize
|
||||
emif_lpddr4b_s0_axi4_arvalid : in std_logic := 'X'; -- arvalid
|
||||
emif_lpddr4b_s0_axi4_aruser : in std_logic_vector(13 downto 0) := (others => 'X'); -- aruser
|
||||
emif_lpddr4b_s0_axi4_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
|
||||
emif_lpddr4b_s0_axi4_arready : out std_logic; -- arready
|
||||
emif_lpddr4b_s0_axi4_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- wdata
|
||||
emif_lpddr4b_s0_axi4_wstrb : in std_logic_vector(31 downto 0) := (others => 'X'); -- wstrb
|
||||
emif_lpddr4b_s0_axi4_wlast : in std_logic := 'X'; -- wlast
|
||||
emif_lpddr4b_s0_axi4_wvalid : in std_logic := 'X'; -- wvalid
|
||||
emif_lpddr4b_s0_axi4_wready : out std_logic; -- wready
|
||||
emif_lpddr4b_s0_axi4_bready : in std_logic := 'X'; -- bready
|
||||
emif_lpddr4b_s0_axi4_bid : out std_logic_vector(6 downto 0); -- bid
|
||||
emif_lpddr4b_s0_axi4_bresp : out std_logic_vector(1 downto 0); -- bresp
|
||||
emif_lpddr4b_s0_axi4_bvalid : out std_logic; -- bvalid
|
||||
emif_lpddr4b_s0_axi4_rready : in std_logic := 'X'; -- rready
|
||||
emif_lpddr4b_s0_axi4_rdata : out std_logic_vector(255 downto 0); -- rdata
|
||||
emif_lpddr4b_s0_axi4_rid : out std_logic_vector(6 downto 0); -- rid
|
||||
emif_lpddr4b_s0_axi4_rlast : out std_logic; -- rlast
|
||||
emif_lpddr4b_s0_axi4_rresp : out std_logic_vector(1 downto 0); -- rresp
|
||||
emif_lpddr4b_s0_axi4_rvalid : out std_logic; -- rvalid
|
||||
emif_lpddr4b_s0_axi4lite_clock_clk : in std_logic := 'X'; -- clk
|
||||
emif_lpddr4b_s0_axi4lite_reset_n_reset_n : in std_logic := 'X'; -- reset_n
|
||||
emif_lpddr4b_s0_axi4lite_awaddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- awaddr
|
||||
emif_lpddr4b_s0_axi4lite_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
|
||||
emif_lpddr4b_s0_axi4lite_awvalid : in std_logic := 'X'; -- awvalid
|
||||
emif_lpddr4b_s0_axi4lite_awready : out std_logic; -- awready
|
||||
emif_lpddr4b_s0_axi4lite_araddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- araddr
|
||||
emif_lpddr4b_s0_axi4lite_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
|
||||
emif_lpddr4b_s0_axi4lite_arvalid : in std_logic := 'X'; -- arvalid
|
||||
emif_lpddr4b_s0_axi4lite_arready : out std_logic; -- arready
|
||||
emif_lpddr4b_s0_axi4lite_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata
|
||||
emif_lpddr4b_s0_axi4lite_wstrb : in std_logic_vector(3 downto 0) := (others => 'X'); -- wstrb
|
||||
emif_lpddr4b_s0_axi4lite_wvalid : in std_logic := 'X'; -- wvalid
|
||||
emif_lpddr4b_s0_axi4lite_wready : out std_logic; -- wready
|
||||
emif_lpddr4b_s0_axi4lite_bready : in std_logic := 'X'; -- bready
|
||||
emif_lpddr4b_s0_axi4lite_bresp : out std_logic_vector(1 downto 0); -- bresp
|
||||
emif_lpddr4b_s0_axi4lite_bvalid : out std_logic; -- bvalid
|
||||
emif_lpddr4b_s0_axi4lite_rready : in std_logic := 'X'; -- rready
|
||||
emif_lpddr4b_s0_axi4lite_rdata : out std_logic_vector(31 downto 0); -- rdata
|
||||
emif_lpddr4b_s0_axi4lite_rresp : out std_logic_vector(1 downto 0); -- rresp
|
||||
emif_lpddr4b_s0_axi4lite_rvalid : out std_logic; -- rvalid
|
||||
emif_lpddr4b_mem_mem_cs : out std_logic_vector(0 downto 0); -- mem_cs
|
||||
emif_lpddr4b_mem_mem_ca : out std_logic_vector(5 downto 0); -- mem_ca
|
||||
emif_lpddr4b_mem_mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
|
||||
emif_lpddr4b_mem_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
|
||||
emif_lpddr4b_mem_mem_dqs_t : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_t
|
||||
emif_lpddr4b_mem_mem_dqs_c : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_c
|
||||
emif_lpddr4b_mem_mem_dmi : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dmi
|
||||
emif_lpddr4b_mem_ck_mem_ck_t : out std_logic_vector(0 downto 0); -- mem_ck_t
|
||||
emif_lpddr4b_mem_ck_mem_ck_c : out std_logic_vector(0 downto 0); -- mem_ck_c
|
||||
emif_lpddr4b_mem_reset_n_mem_reset_n : out std_logic; -- mem_reset_n
|
||||
emif_lpddr4b_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
|
||||
emif_lpddr4b_ref_clk_clk : in std_logic := 'X'; -- clk
|
||||
iopll_refclk_clk : in std_logic := 'X'; -- clk
|
||||
iopll_locked_export : out std_logic; -- export
|
||||
iopll_reset_reset : in std_logic := 'X'; -- reset
|
||||
iopll_outclk_axi4_lite_clk : out std_logic; -- clk
|
||||
reset_reset_n : in std_logic := 'X' -- reset_n
|
||||
);
|
||||
end component EMIF_Qsys;
|
||||
|
||||
+289
@@ -0,0 +1,289 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for EMIF_Qsys</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">EMIF_Qsys</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.03.02.19:16:03</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_emif_lpddr4b"><b>emif_lpddr4b</b>
|
||||
</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">s0_axi4 </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">s0_axi4lite </td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_clock_310m"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>clock_310m</h2>altera_clock_bridge v19.2.0
|
||||
<br/>
|
||||
<div class="greydiv">
|
||||
<table class="connectionboxes">
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_iopll">iopll</a>
|
||||
</td>
|
||||
<td class="from">outclk0  </td>
|
||||
<td class="main" rowspan="2">clock_310m</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  in_clk</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_emif_lpddr4b"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>emif_lpddr4b</h2>emif_io96b_lpddr4 v4.0.0
|
||||
<br/>
|
||||
<div class="greydiv">
|
||||
<table class="connectionboxes">
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_iopll">iopll</a>
|
||||
</td>
|
||||
<td class="from">outclk0  </td>
|
||||
<td class="main" rowspan="5">emif_lpddr4b</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  s0_axi4_clock_in</td>
|
||||
</tr>
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_reset_in">reset_in</a>
|
||||
</td>
|
||||
<td class="from">out_reset  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  core_init_n</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_iopll"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>iopll</h2>altera_iopll v20.0.0
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_reset_in"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>reset_in</h2>altera_reset_bridge v19.2.0
|
||||
<br/>
|
||||
<div class="greydiv">
|
||||
<table class="connectionboxes">
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_iopll">iopll</a>
|
||||
</td>
|
||||
<td class="from">outclk0  </td>
|
||||
<td class="main" rowspan="4">reset_in</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  clk</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">out_reset  </td>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_emif_lpddr4b">emif_lpddr4b</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  core_init_n</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.02 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
+4160
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,59 @@
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_TOOL_VERSION "25.3.1"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -library "EMIF_Qsys" -name SOPCINFO_FILE [file join $::quartus(qip_path) "EMIF_Qsys.sopcinfo"]
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name SLD_INFO "QSYS_NAME EMIF_Qsys HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "EMIF_Qsys" -name MISC_FILE [file join $::quartus(qip_path) "EMIF_Qsys.cmp"]
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_TARGETED_PART_TRAIT "part.DEVICE_IOBANK_REVISION::IO96B_REVB1"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_TARGETED_PART_TRAIT "DEVICE_SPEEDGRADE::4"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_TARGETED_PART_TRAIT "BASE_DEVICE::SM4REVB"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_TARGETED_PART_TRAIT "part.DEVICE_POWER_MODEL::STANDARD_POWER_FIXED"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_TARGETED_PART_TRAIT "part.DEVICE_TEMPERATURE_GRADE::EXTENDED"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_TARGETED_PART_TRAIT "part.SUPPORTS_VID::0"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_QSYS_MODE "SYSTEM"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "EMIF_Qsys" -name MISC_FILE [file join $::quartus(qip_path) "../EMIF_Qsys.qsys"]
|
||||
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2Nsb2NrX2JyaWRnZV8w"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_DISPLAY_NAME "R2VuZXJpYyBDb21wb25lbnQ="
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_DESCRIPTION "QSBkeW5hbWljIGNvbXBvbmVudCB3aGVyZSB5b3UgY2FuIGFkZCwgbW9kaWZ5IG9yIHJlbW92ZSBpbnRlcmZhY2VzIGFuZCBwb3J0cyBvbiB0aGUgZmx5"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_GROUP "R2VuZXJpYyBDb21wb25lbnQ="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMA=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_DISPLAY_NAME "R2VuZXJpYyBDb21wb25lbnQ="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_DESCRIPTION "QSBkeW5hbWljIGNvbXBvbmVudCB3aGVyZSB5b3UgY2FuIGFkZCwgbW9kaWZ5IG9yIHJlbW92ZSBpbnRlcmZhY2VzIGFuZCBwb3J0cyBvbiB0aGUgZmx5"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_GROUP "R2VuZXJpYyBDb21wb25lbnQ="
|
||||
set_global_assignment -entity "EMIF_Qsys_iopll_0" -library "EMIF_Qsys_iopll_0" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2lvcGxsXzA="
|
||||
set_global_assignment -entity "EMIF_Qsys_iopll_0" -library "EMIF_Qsys_iopll_0" -name IP_COMPONENT_DISPLAY_NAME "R2VuZXJpYyBDb21wb25lbnQ="
|
||||
set_global_assignment -entity "EMIF_Qsys_iopll_0" -library "EMIF_Qsys_iopll_0" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_iopll_0" -library "EMIF_Qsys_iopll_0" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_iopll_0" -library "EMIF_Qsys_iopll_0" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "EMIF_Qsys_iopll_0" -library "EMIF_Qsys_iopll_0" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "EMIF_Qsys_iopll_0" -library "EMIF_Qsys_iopll_0" -name IP_COMPONENT_DESCRIPTION "QSBkeW5hbWljIGNvbXBvbmVudCB3aGVyZSB5b3UgY2FuIGFkZCwgbW9kaWZ5IG9yIHJlbW92ZSBpbnRlcmZhY2VzIGFuZCBwb3J0cyBvbiB0aGUgZmx5"
|
||||
set_global_assignment -entity "EMIF_Qsys_iopll_0" -library "EMIF_Qsys_iopll_0" -name IP_COMPONENT_GROUP "R2VuZXJpYyBDb21wb25lbnQ="
|
||||
set_global_assignment -entity "EMIF_Qsys_reset_in" -library "EMIF_Qsys_reset_in" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX3Jlc2V0X2lu"
|
||||
set_global_assignment -entity "EMIF_Qsys_reset_in" -library "EMIF_Qsys_reset_in" -name IP_COMPONENT_DISPLAY_NAME "R2VuZXJpYyBDb21wb25lbnQ="
|
||||
set_global_assignment -entity "EMIF_Qsys_reset_in" -library "EMIF_Qsys_reset_in" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_reset_in" -library "EMIF_Qsys_reset_in" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_reset_in" -library "EMIF_Qsys_reset_in" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "EMIF_Qsys_reset_in" -library "EMIF_Qsys_reset_in" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "EMIF_Qsys_reset_in" -library "EMIF_Qsys_reset_in" -name IP_COMPONENT_DESCRIPTION "QSBkeW5hbWljIGNvbXBvbmVudCB3aGVyZSB5b3UgY2FuIGFkZCwgbW9kaWZ5IG9yIHJlbW92ZSBpbnRlcmZhY2VzIGFuZCBwb3J0cyBvbiB0aGUgZmx5"
|
||||
set_global_assignment -entity "EMIF_Qsys_reset_in" -library "EMIF_Qsys_reset_in" -name IP_COMPONENT_GROUP "R2VuZXJpYyBDb21wb25lbnQ="
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_COMPONENT_NAME "RU1JRl9Rc3lz"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_COMPONENT_DISPLAY_NAME "RU1JRl9Rc3lz"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys" -library "EMIF_Qsys" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "EMIF_Qsys" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/EMIF_Qsys.v"]
|
||||
|
||||
+7022
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,81 @@
|
||||
module EMIF_Qsys (
|
||||
output wire clock_310m_out_clk_clk, // clock_310m_out_clk.clk
|
||||
output wire emif_lpddr4b_s0_axi4_ctrl_ready_reset_n, // emif_lpddr4b_s0_axi4_ctrl_ready.reset_n
|
||||
input wire [29:0] emif_lpddr4b_s0_axi4_awaddr, // emif_lpddr4b_s0_axi4.awaddr
|
||||
input wire [1:0] emif_lpddr4b_s0_axi4_awburst, // .awburst
|
||||
input wire [6:0] emif_lpddr4b_s0_axi4_awid, // .awid
|
||||
input wire [7:0] emif_lpddr4b_s0_axi4_awlen, // .awlen
|
||||
input wire emif_lpddr4b_s0_axi4_awlock, // .awlock
|
||||
input wire [3:0] emif_lpddr4b_s0_axi4_awqos, // .awqos
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4_awsize, // .awsize
|
||||
input wire emif_lpddr4b_s0_axi4_awvalid, // .awvalid
|
||||
input wire [13:0] emif_lpddr4b_s0_axi4_awuser, // .awuser
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4_awprot, // .awprot
|
||||
output wire emif_lpddr4b_s0_axi4_awready, // .awready
|
||||
input wire [29:0] emif_lpddr4b_s0_axi4_araddr, // .araddr
|
||||
input wire [1:0] emif_lpddr4b_s0_axi4_arburst, // .arburst
|
||||
input wire [6:0] emif_lpddr4b_s0_axi4_arid, // .arid
|
||||
input wire [7:0] emif_lpddr4b_s0_axi4_arlen, // .arlen
|
||||
input wire emif_lpddr4b_s0_axi4_arlock, // .arlock
|
||||
input wire [3:0] emif_lpddr4b_s0_axi4_arqos, // .arqos
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4_arsize, // .arsize
|
||||
input wire emif_lpddr4b_s0_axi4_arvalid, // .arvalid
|
||||
input wire [13:0] emif_lpddr4b_s0_axi4_aruser, // .aruser
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4_arprot, // .arprot
|
||||
output wire emif_lpddr4b_s0_axi4_arready, // .arready
|
||||
input wire [255:0] emif_lpddr4b_s0_axi4_wdata, // .wdata
|
||||
input wire [31:0] emif_lpddr4b_s0_axi4_wstrb, // .wstrb
|
||||
input wire emif_lpddr4b_s0_axi4_wlast, // .wlast
|
||||
input wire emif_lpddr4b_s0_axi4_wvalid, // .wvalid
|
||||
output wire emif_lpddr4b_s0_axi4_wready, // .wready
|
||||
input wire emif_lpddr4b_s0_axi4_bready, // .bready
|
||||
output wire [6:0] emif_lpddr4b_s0_axi4_bid, // .bid
|
||||
output wire [1:0] emif_lpddr4b_s0_axi4_bresp, // .bresp
|
||||
output wire emif_lpddr4b_s0_axi4_bvalid, // .bvalid
|
||||
input wire emif_lpddr4b_s0_axi4_rready, // .rready
|
||||
output wire [255:0] emif_lpddr4b_s0_axi4_rdata, // .rdata
|
||||
output wire [6:0] emif_lpddr4b_s0_axi4_rid, // .rid
|
||||
output wire emif_lpddr4b_s0_axi4_rlast, // .rlast
|
||||
output wire [1:0] emif_lpddr4b_s0_axi4_rresp, // .rresp
|
||||
output wire emif_lpddr4b_s0_axi4_rvalid, // .rvalid
|
||||
input wire emif_lpddr4b_s0_axi4lite_clock_clk, // emif_lpddr4b_s0_axi4lite_clock.clk
|
||||
input wire emif_lpddr4b_s0_axi4lite_reset_n_reset_n, // emif_lpddr4b_s0_axi4lite_reset_n.reset_n
|
||||
input wire [26:0] emif_lpddr4b_s0_axi4lite_awaddr, // emif_lpddr4b_s0_axi4lite.awaddr
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4lite_awprot, // .awprot
|
||||
input wire emif_lpddr4b_s0_axi4lite_awvalid, // .awvalid
|
||||
output wire emif_lpddr4b_s0_axi4lite_awready, // .awready
|
||||
input wire [26:0] emif_lpddr4b_s0_axi4lite_araddr, // .araddr
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4lite_arprot, // .arprot
|
||||
input wire emif_lpddr4b_s0_axi4lite_arvalid, // .arvalid
|
||||
output wire emif_lpddr4b_s0_axi4lite_arready, // .arready
|
||||
input wire [31:0] emif_lpddr4b_s0_axi4lite_wdata, // .wdata
|
||||
input wire [3:0] emif_lpddr4b_s0_axi4lite_wstrb, // .wstrb
|
||||
input wire emif_lpddr4b_s0_axi4lite_wvalid, // .wvalid
|
||||
output wire emif_lpddr4b_s0_axi4lite_wready, // .wready
|
||||
input wire emif_lpddr4b_s0_axi4lite_bready, // .bready
|
||||
output wire [1:0] emif_lpddr4b_s0_axi4lite_bresp, // .bresp
|
||||
output wire emif_lpddr4b_s0_axi4lite_bvalid, // .bvalid
|
||||
input wire emif_lpddr4b_s0_axi4lite_rready, // .rready
|
||||
output wire [31:0] emif_lpddr4b_s0_axi4lite_rdata, // .rdata
|
||||
output wire [1:0] emif_lpddr4b_s0_axi4lite_rresp, // .rresp
|
||||
output wire emif_lpddr4b_s0_axi4lite_rvalid, // .rvalid
|
||||
output wire [0:0] emif_lpddr4b_mem_mem_cs, // emif_lpddr4b_mem.mem_cs
|
||||
output wire [5:0] emif_lpddr4b_mem_mem_ca, // .mem_ca
|
||||
output wire [0:0] emif_lpddr4b_mem_mem_cke, // .mem_cke
|
||||
inout wire [31:0] emif_lpddr4b_mem_mem_dq, // .mem_dq
|
||||
inout wire [3:0] emif_lpddr4b_mem_mem_dqs_t, // .mem_dqs_t
|
||||
inout wire [3:0] emif_lpddr4b_mem_mem_dqs_c, // .mem_dqs_c
|
||||
inout wire [3:0] emif_lpddr4b_mem_mem_dmi, // .mem_dmi
|
||||
output wire [0:0] emif_lpddr4b_mem_ck_mem_ck_t, // emif_lpddr4b_mem_ck.mem_ck_t
|
||||
output wire [0:0] emif_lpddr4b_mem_ck_mem_ck_c, // .mem_ck_c
|
||||
output wire emif_lpddr4b_mem_reset_n_mem_reset_n, // emif_lpddr4b_mem_reset_n.mem_reset_n
|
||||
input wire emif_lpddr4b_oct_oct_rzqin, // emif_lpddr4b_oct.oct_rzqin
|
||||
input wire emif_lpddr4b_ref_clk_clk, // emif_lpddr4b_ref_clk.clk
|
||||
input wire iopll_refclk_clk, // iopll_refclk.clk
|
||||
output wire iopll_locked_export, // iopll_locked.export
|
||||
input wire iopll_reset_reset, // iopll_reset.reset
|
||||
output wire iopll_outclk_axi4_lite_clk, // iopll_outclk_axi4_lite.clk
|
||||
input wire reset_reset_n // reset.reset_n
|
||||
);
|
||||
endmodule
|
||||
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/EMIF_Qsys.qsys --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/EMIF_Qsys --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Progress: Loading emif_lpddr4b/EMIF_Qsys.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Parameterizing module clock_310m
|
||||
Progress: Parameterizing module emif_lpddr4b
|
||||
Progress: Parameterizing module iopll
|
||||
Progress: Parameterizing module reset_in
|
||||
Progress: Building connections
|
||||
Progress: Parameterizing connections
|
||||
Progress: Validating
|
||||
Progress: Done reading input file
|
||||
Info: EMIF_Qsys: "Transforming system: EMIF_Qsys"
|
||||
Info: EMIF_Qsys: "Naming system components in system: EMIF_Qsys"
|
||||
Info: EMIF_Qsys: "Processing generation queue"
|
||||
Info: EMIF_Qsys: "Generating: EMIF_Qsys"
|
||||
Info: EMIF_Qsys: "Generating: EMIF_Qsys_clock_bridge_0"
|
||||
Info: EMIF_Qsys: "Generating: EMIF_Qsys_emif_ddr4a_0"
|
||||
Info: EMIF_Qsys: "Generating: EMIF_Qsys_iopll_0"
|
||||
Info: EMIF_Qsys: "Generating: EMIF_Qsys_reset_in"
|
||||
Info: EMIF_Qsys: Done "EMIF_Qsys" with 5 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,80 @@
|
||||
EMIF_Qsys u0 (
|
||||
.clock_310m_out_clk_clk (_connected_to_clock_310m_out_clk_clk_), // output, width = 1, clock_310m_out_clk.clk
|
||||
.emif_lpddr4b_s0_axi4_ctrl_ready_reset_n (_connected_to_emif_lpddr4b_s0_axi4_ctrl_ready_reset_n_), // output, width = 1, emif_lpddr4b_s0_axi4_ctrl_ready.reset_n
|
||||
.emif_lpddr4b_s0_axi4_awaddr (_connected_to_emif_lpddr4b_s0_axi4_awaddr_), // input, width = 30, emif_lpddr4b_s0_axi4.awaddr
|
||||
.emif_lpddr4b_s0_axi4_awburst (_connected_to_emif_lpddr4b_s0_axi4_awburst_), // input, width = 2, .awburst
|
||||
.emif_lpddr4b_s0_axi4_awid (_connected_to_emif_lpddr4b_s0_axi4_awid_), // input, width = 7, .awid
|
||||
.emif_lpddr4b_s0_axi4_awlen (_connected_to_emif_lpddr4b_s0_axi4_awlen_), // input, width = 8, .awlen
|
||||
.emif_lpddr4b_s0_axi4_awlock (_connected_to_emif_lpddr4b_s0_axi4_awlock_), // input, width = 1, .awlock
|
||||
.emif_lpddr4b_s0_axi4_awqos (_connected_to_emif_lpddr4b_s0_axi4_awqos_), // input, width = 4, .awqos
|
||||
.emif_lpddr4b_s0_axi4_awsize (_connected_to_emif_lpddr4b_s0_axi4_awsize_), // input, width = 3, .awsize
|
||||
.emif_lpddr4b_s0_axi4_awvalid (_connected_to_emif_lpddr4b_s0_axi4_awvalid_), // input, width = 1, .awvalid
|
||||
.emif_lpddr4b_s0_axi4_awuser (_connected_to_emif_lpddr4b_s0_axi4_awuser_), // input, width = 14, .awuser
|
||||
.emif_lpddr4b_s0_axi4_awprot (_connected_to_emif_lpddr4b_s0_axi4_awprot_), // input, width = 3, .awprot
|
||||
.emif_lpddr4b_s0_axi4_awready (_connected_to_emif_lpddr4b_s0_axi4_awready_), // output, width = 1, .awready
|
||||
.emif_lpddr4b_s0_axi4_araddr (_connected_to_emif_lpddr4b_s0_axi4_araddr_), // input, width = 30, .araddr
|
||||
.emif_lpddr4b_s0_axi4_arburst (_connected_to_emif_lpddr4b_s0_axi4_arburst_), // input, width = 2, .arburst
|
||||
.emif_lpddr4b_s0_axi4_arid (_connected_to_emif_lpddr4b_s0_axi4_arid_), // input, width = 7, .arid
|
||||
.emif_lpddr4b_s0_axi4_arlen (_connected_to_emif_lpddr4b_s0_axi4_arlen_), // input, width = 8, .arlen
|
||||
.emif_lpddr4b_s0_axi4_arlock (_connected_to_emif_lpddr4b_s0_axi4_arlock_), // input, width = 1, .arlock
|
||||
.emif_lpddr4b_s0_axi4_arqos (_connected_to_emif_lpddr4b_s0_axi4_arqos_), // input, width = 4, .arqos
|
||||
.emif_lpddr4b_s0_axi4_arsize (_connected_to_emif_lpddr4b_s0_axi4_arsize_), // input, width = 3, .arsize
|
||||
.emif_lpddr4b_s0_axi4_arvalid (_connected_to_emif_lpddr4b_s0_axi4_arvalid_), // input, width = 1, .arvalid
|
||||
.emif_lpddr4b_s0_axi4_aruser (_connected_to_emif_lpddr4b_s0_axi4_aruser_), // input, width = 14, .aruser
|
||||
.emif_lpddr4b_s0_axi4_arprot (_connected_to_emif_lpddr4b_s0_axi4_arprot_), // input, width = 3, .arprot
|
||||
.emif_lpddr4b_s0_axi4_arready (_connected_to_emif_lpddr4b_s0_axi4_arready_), // output, width = 1, .arready
|
||||
.emif_lpddr4b_s0_axi4_wdata (_connected_to_emif_lpddr4b_s0_axi4_wdata_), // input, width = 256, .wdata
|
||||
.emif_lpddr4b_s0_axi4_wstrb (_connected_to_emif_lpddr4b_s0_axi4_wstrb_), // input, width = 32, .wstrb
|
||||
.emif_lpddr4b_s0_axi4_wlast (_connected_to_emif_lpddr4b_s0_axi4_wlast_), // input, width = 1, .wlast
|
||||
.emif_lpddr4b_s0_axi4_wvalid (_connected_to_emif_lpddr4b_s0_axi4_wvalid_), // input, width = 1, .wvalid
|
||||
.emif_lpddr4b_s0_axi4_wready (_connected_to_emif_lpddr4b_s0_axi4_wready_), // output, width = 1, .wready
|
||||
.emif_lpddr4b_s0_axi4_bready (_connected_to_emif_lpddr4b_s0_axi4_bready_), // input, width = 1, .bready
|
||||
.emif_lpddr4b_s0_axi4_bid (_connected_to_emif_lpddr4b_s0_axi4_bid_), // output, width = 7, .bid
|
||||
.emif_lpddr4b_s0_axi4_bresp (_connected_to_emif_lpddr4b_s0_axi4_bresp_), // output, width = 2, .bresp
|
||||
.emif_lpddr4b_s0_axi4_bvalid (_connected_to_emif_lpddr4b_s0_axi4_bvalid_), // output, width = 1, .bvalid
|
||||
.emif_lpddr4b_s0_axi4_rready (_connected_to_emif_lpddr4b_s0_axi4_rready_), // input, width = 1, .rready
|
||||
.emif_lpddr4b_s0_axi4_rdata (_connected_to_emif_lpddr4b_s0_axi4_rdata_), // output, width = 256, .rdata
|
||||
.emif_lpddr4b_s0_axi4_rid (_connected_to_emif_lpddr4b_s0_axi4_rid_), // output, width = 7, .rid
|
||||
.emif_lpddr4b_s0_axi4_rlast (_connected_to_emif_lpddr4b_s0_axi4_rlast_), // output, width = 1, .rlast
|
||||
.emif_lpddr4b_s0_axi4_rresp (_connected_to_emif_lpddr4b_s0_axi4_rresp_), // output, width = 2, .rresp
|
||||
.emif_lpddr4b_s0_axi4_rvalid (_connected_to_emif_lpddr4b_s0_axi4_rvalid_), // output, width = 1, .rvalid
|
||||
.emif_lpddr4b_s0_axi4lite_clock_clk (_connected_to_emif_lpddr4b_s0_axi4lite_clock_clk_), // input, width = 1, emif_lpddr4b_s0_axi4lite_clock.clk
|
||||
.emif_lpddr4b_s0_axi4lite_reset_n_reset_n (_connected_to_emif_lpddr4b_s0_axi4lite_reset_n_reset_n_), // input, width = 1, emif_lpddr4b_s0_axi4lite_reset_n.reset_n
|
||||
.emif_lpddr4b_s0_axi4lite_awaddr (_connected_to_emif_lpddr4b_s0_axi4lite_awaddr_), // input, width = 27, emif_lpddr4b_s0_axi4lite.awaddr
|
||||
.emif_lpddr4b_s0_axi4lite_awprot (_connected_to_emif_lpddr4b_s0_axi4lite_awprot_), // input, width = 3, .awprot
|
||||
.emif_lpddr4b_s0_axi4lite_awvalid (_connected_to_emif_lpddr4b_s0_axi4lite_awvalid_), // input, width = 1, .awvalid
|
||||
.emif_lpddr4b_s0_axi4lite_awready (_connected_to_emif_lpddr4b_s0_axi4lite_awready_), // output, width = 1, .awready
|
||||
.emif_lpddr4b_s0_axi4lite_araddr (_connected_to_emif_lpddr4b_s0_axi4lite_araddr_), // input, width = 27, .araddr
|
||||
.emif_lpddr4b_s0_axi4lite_arprot (_connected_to_emif_lpddr4b_s0_axi4lite_arprot_), // input, width = 3, .arprot
|
||||
.emif_lpddr4b_s0_axi4lite_arvalid (_connected_to_emif_lpddr4b_s0_axi4lite_arvalid_), // input, width = 1, .arvalid
|
||||
.emif_lpddr4b_s0_axi4lite_arready (_connected_to_emif_lpddr4b_s0_axi4lite_arready_), // output, width = 1, .arready
|
||||
.emif_lpddr4b_s0_axi4lite_wdata (_connected_to_emif_lpddr4b_s0_axi4lite_wdata_), // input, width = 32, .wdata
|
||||
.emif_lpddr4b_s0_axi4lite_wstrb (_connected_to_emif_lpddr4b_s0_axi4lite_wstrb_), // input, width = 4, .wstrb
|
||||
.emif_lpddr4b_s0_axi4lite_wvalid (_connected_to_emif_lpddr4b_s0_axi4lite_wvalid_), // input, width = 1, .wvalid
|
||||
.emif_lpddr4b_s0_axi4lite_wready (_connected_to_emif_lpddr4b_s0_axi4lite_wready_), // output, width = 1, .wready
|
||||
.emif_lpddr4b_s0_axi4lite_bready (_connected_to_emif_lpddr4b_s0_axi4lite_bready_), // input, width = 1, .bready
|
||||
.emif_lpddr4b_s0_axi4lite_bresp (_connected_to_emif_lpddr4b_s0_axi4lite_bresp_), // output, width = 2, .bresp
|
||||
.emif_lpddr4b_s0_axi4lite_bvalid (_connected_to_emif_lpddr4b_s0_axi4lite_bvalid_), // output, width = 1, .bvalid
|
||||
.emif_lpddr4b_s0_axi4lite_rready (_connected_to_emif_lpddr4b_s0_axi4lite_rready_), // input, width = 1, .rready
|
||||
.emif_lpddr4b_s0_axi4lite_rdata (_connected_to_emif_lpddr4b_s0_axi4lite_rdata_), // output, width = 32, .rdata
|
||||
.emif_lpddr4b_s0_axi4lite_rresp (_connected_to_emif_lpddr4b_s0_axi4lite_rresp_), // output, width = 2, .rresp
|
||||
.emif_lpddr4b_s0_axi4lite_rvalid (_connected_to_emif_lpddr4b_s0_axi4lite_rvalid_), // output, width = 1, .rvalid
|
||||
.emif_lpddr4b_mem_mem_cs (_connected_to_emif_lpddr4b_mem_mem_cs_), // output, width = 1, emif_lpddr4b_mem.mem_cs
|
||||
.emif_lpddr4b_mem_mem_ca (_connected_to_emif_lpddr4b_mem_mem_ca_), // output, width = 6, .mem_ca
|
||||
.emif_lpddr4b_mem_mem_cke (_connected_to_emif_lpddr4b_mem_mem_cke_), // output, width = 1, .mem_cke
|
||||
.emif_lpddr4b_mem_mem_dq (_connected_to_emif_lpddr4b_mem_mem_dq_), // inout, width = 32, .mem_dq
|
||||
.emif_lpddr4b_mem_mem_dqs_t (_connected_to_emif_lpddr4b_mem_mem_dqs_t_), // inout, width = 4, .mem_dqs_t
|
||||
.emif_lpddr4b_mem_mem_dqs_c (_connected_to_emif_lpddr4b_mem_mem_dqs_c_), // inout, width = 4, .mem_dqs_c
|
||||
.emif_lpddr4b_mem_mem_dmi (_connected_to_emif_lpddr4b_mem_mem_dmi_), // inout, width = 4, .mem_dmi
|
||||
.emif_lpddr4b_mem_ck_mem_ck_t (_connected_to_emif_lpddr4b_mem_ck_mem_ck_t_), // output, width = 1, emif_lpddr4b_mem_ck.mem_ck_t
|
||||
.emif_lpddr4b_mem_ck_mem_ck_c (_connected_to_emif_lpddr4b_mem_ck_mem_ck_c_), // output, width = 1, .mem_ck_c
|
||||
.emif_lpddr4b_mem_reset_n_mem_reset_n (_connected_to_emif_lpddr4b_mem_reset_n_mem_reset_n_), // output, width = 1, emif_lpddr4b_mem_reset_n.mem_reset_n
|
||||
.emif_lpddr4b_oct_oct_rzqin (_connected_to_emif_lpddr4b_oct_oct_rzqin_), // input, width = 1, emif_lpddr4b_oct.oct_rzqin
|
||||
.emif_lpddr4b_ref_clk_clk (_connected_to_emif_lpddr4b_ref_clk_clk_), // input, width = 1, emif_lpddr4b_ref_clk.clk
|
||||
.iopll_refclk_clk (_connected_to_iopll_refclk_clk_), // input, width = 1, iopll_refclk.clk
|
||||
.iopll_locked_export (_connected_to_iopll_locked_export_), // output, width = 1, iopll_locked.export
|
||||
.iopll_reset_reset (_connected_to_iopll_reset_reset_), // input, width = 1, iopll_reset.reset
|
||||
.iopll_outclk_axi4_lite_clk (_connected_to_iopll_outclk_axi4_lite_clk_), // output, width = 1, iopll_outclk_axi4_lite.clk
|
||||
.reset_reset_n (_connected_to_reset_reset_n_) // input, width = 1, reset.reset_n
|
||||
);
|
||||
|
||||
@@ -0,0 +1,163 @@
|
||||
component EMIF_Qsys is
|
||||
port (
|
||||
clock_310m_out_clk_clk : out std_logic; -- clk
|
||||
emif_lpddr4b_s0_axi4_ctrl_ready_reset_n : out std_logic; -- reset_n
|
||||
emif_lpddr4b_s0_axi4_awaddr : in std_logic_vector(29 downto 0) := (others => 'X'); -- awaddr
|
||||
emif_lpddr4b_s0_axi4_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst
|
||||
emif_lpddr4b_s0_axi4_awid : in std_logic_vector(6 downto 0) := (others => 'X'); -- awid
|
||||
emif_lpddr4b_s0_axi4_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- awlen
|
||||
emif_lpddr4b_s0_axi4_awlock : in std_logic := 'X'; -- awlock
|
||||
emif_lpddr4b_s0_axi4_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- awqos
|
||||
emif_lpddr4b_s0_axi4_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize
|
||||
emif_lpddr4b_s0_axi4_awvalid : in std_logic := 'X'; -- awvalid
|
||||
emif_lpddr4b_s0_axi4_awuser : in std_logic_vector(13 downto 0) := (others => 'X'); -- awuser
|
||||
emif_lpddr4b_s0_axi4_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
|
||||
emif_lpddr4b_s0_axi4_awready : out std_logic; -- awready
|
||||
emif_lpddr4b_s0_axi4_araddr : in std_logic_vector(29 downto 0) := (others => 'X'); -- araddr
|
||||
emif_lpddr4b_s0_axi4_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst
|
||||
emif_lpddr4b_s0_axi4_arid : in std_logic_vector(6 downto 0) := (others => 'X'); -- arid
|
||||
emif_lpddr4b_s0_axi4_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- arlen
|
||||
emif_lpddr4b_s0_axi4_arlock : in std_logic := 'X'; -- arlock
|
||||
emif_lpddr4b_s0_axi4_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- arqos
|
||||
emif_lpddr4b_s0_axi4_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize
|
||||
emif_lpddr4b_s0_axi4_arvalid : in std_logic := 'X'; -- arvalid
|
||||
emif_lpddr4b_s0_axi4_aruser : in std_logic_vector(13 downto 0) := (others => 'X'); -- aruser
|
||||
emif_lpddr4b_s0_axi4_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
|
||||
emif_lpddr4b_s0_axi4_arready : out std_logic; -- arready
|
||||
emif_lpddr4b_s0_axi4_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- wdata
|
||||
emif_lpddr4b_s0_axi4_wstrb : in std_logic_vector(31 downto 0) := (others => 'X'); -- wstrb
|
||||
emif_lpddr4b_s0_axi4_wlast : in std_logic := 'X'; -- wlast
|
||||
emif_lpddr4b_s0_axi4_wvalid : in std_logic := 'X'; -- wvalid
|
||||
emif_lpddr4b_s0_axi4_wready : out std_logic; -- wready
|
||||
emif_lpddr4b_s0_axi4_bready : in std_logic := 'X'; -- bready
|
||||
emif_lpddr4b_s0_axi4_bid : out std_logic_vector(6 downto 0); -- bid
|
||||
emif_lpddr4b_s0_axi4_bresp : out std_logic_vector(1 downto 0); -- bresp
|
||||
emif_lpddr4b_s0_axi4_bvalid : out std_logic; -- bvalid
|
||||
emif_lpddr4b_s0_axi4_rready : in std_logic := 'X'; -- rready
|
||||
emif_lpddr4b_s0_axi4_rdata : out std_logic_vector(255 downto 0); -- rdata
|
||||
emif_lpddr4b_s0_axi4_rid : out std_logic_vector(6 downto 0); -- rid
|
||||
emif_lpddr4b_s0_axi4_rlast : out std_logic; -- rlast
|
||||
emif_lpddr4b_s0_axi4_rresp : out std_logic_vector(1 downto 0); -- rresp
|
||||
emif_lpddr4b_s0_axi4_rvalid : out std_logic; -- rvalid
|
||||
emif_lpddr4b_s0_axi4lite_clock_clk : in std_logic := 'X'; -- clk
|
||||
emif_lpddr4b_s0_axi4lite_reset_n_reset_n : in std_logic := 'X'; -- reset_n
|
||||
emif_lpddr4b_s0_axi4lite_awaddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- awaddr
|
||||
emif_lpddr4b_s0_axi4lite_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
|
||||
emif_lpddr4b_s0_axi4lite_awvalid : in std_logic := 'X'; -- awvalid
|
||||
emif_lpddr4b_s0_axi4lite_awready : out std_logic; -- awready
|
||||
emif_lpddr4b_s0_axi4lite_araddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- araddr
|
||||
emif_lpddr4b_s0_axi4lite_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
|
||||
emif_lpddr4b_s0_axi4lite_arvalid : in std_logic := 'X'; -- arvalid
|
||||
emif_lpddr4b_s0_axi4lite_arready : out std_logic; -- arready
|
||||
emif_lpddr4b_s0_axi4lite_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata
|
||||
emif_lpddr4b_s0_axi4lite_wstrb : in std_logic_vector(3 downto 0) := (others => 'X'); -- wstrb
|
||||
emif_lpddr4b_s0_axi4lite_wvalid : in std_logic := 'X'; -- wvalid
|
||||
emif_lpddr4b_s0_axi4lite_wready : out std_logic; -- wready
|
||||
emif_lpddr4b_s0_axi4lite_bready : in std_logic := 'X'; -- bready
|
||||
emif_lpddr4b_s0_axi4lite_bresp : out std_logic_vector(1 downto 0); -- bresp
|
||||
emif_lpddr4b_s0_axi4lite_bvalid : out std_logic; -- bvalid
|
||||
emif_lpddr4b_s0_axi4lite_rready : in std_logic := 'X'; -- rready
|
||||
emif_lpddr4b_s0_axi4lite_rdata : out std_logic_vector(31 downto 0); -- rdata
|
||||
emif_lpddr4b_s0_axi4lite_rresp : out std_logic_vector(1 downto 0); -- rresp
|
||||
emif_lpddr4b_s0_axi4lite_rvalid : out std_logic; -- rvalid
|
||||
emif_lpddr4b_mem_mem_cs : out std_logic_vector(0 downto 0); -- mem_cs
|
||||
emif_lpddr4b_mem_mem_ca : out std_logic_vector(5 downto 0); -- mem_ca
|
||||
emif_lpddr4b_mem_mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
|
||||
emif_lpddr4b_mem_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
|
||||
emif_lpddr4b_mem_mem_dqs_t : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_t
|
||||
emif_lpddr4b_mem_mem_dqs_c : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_c
|
||||
emif_lpddr4b_mem_mem_dmi : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dmi
|
||||
emif_lpddr4b_mem_ck_mem_ck_t : out std_logic_vector(0 downto 0); -- mem_ck_t
|
||||
emif_lpddr4b_mem_ck_mem_ck_c : out std_logic_vector(0 downto 0); -- mem_ck_c
|
||||
emif_lpddr4b_mem_reset_n_mem_reset_n : out std_logic; -- mem_reset_n
|
||||
emif_lpddr4b_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
|
||||
emif_lpddr4b_ref_clk_clk : in std_logic := 'X'; -- clk
|
||||
iopll_refclk_clk : in std_logic := 'X'; -- clk
|
||||
iopll_locked_export : out std_logic; -- export
|
||||
iopll_reset_reset : in std_logic := 'X'; -- reset
|
||||
iopll_outclk_axi4_lite_clk : out std_logic; -- clk
|
||||
reset_reset_n : in std_logic := 'X' -- reset_n
|
||||
);
|
||||
end component EMIF_Qsys;
|
||||
|
||||
u0 : component EMIF_Qsys
|
||||
port map (
|
||||
clock_310m_out_clk_clk => CONNECTED_TO_clock_310m_out_clk_clk, -- clock_310m_out_clk.clk
|
||||
emif_lpddr4b_s0_axi4_ctrl_ready_reset_n => CONNECTED_TO_emif_lpddr4b_s0_axi4_ctrl_ready_reset_n, -- emif_lpddr4b_s0_axi4_ctrl_ready.reset_n
|
||||
emif_lpddr4b_s0_axi4_awaddr => CONNECTED_TO_emif_lpddr4b_s0_axi4_awaddr, -- emif_lpddr4b_s0_axi4.awaddr
|
||||
emif_lpddr4b_s0_axi4_awburst => CONNECTED_TO_emif_lpddr4b_s0_axi4_awburst, -- .awburst
|
||||
emif_lpddr4b_s0_axi4_awid => CONNECTED_TO_emif_lpddr4b_s0_axi4_awid, -- .awid
|
||||
emif_lpddr4b_s0_axi4_awlen => CONNECTED_TO_emif_lpddr4b_s0_axi4_awlen, -- .awlen
|
||||
emif_lpddr4b_s0_axi4_awlock => CONNECTED_TO_emif_lpddr4b_s0_axi4_awlock, -- .awlock
|
||||
emif_lpddr4b_s0_axi4_awqos => CONNECTED_TO_emif_lpddr4b_s0_axi4_awqos, -- .awqos
|
||||
emif_lpddr4b_s0_axi4_awsize => CONNECTED_TO_emif_lpddr4b_s0_axi4_awsize, -- .awsize
|
||||
emif_lpddr4b_s0_axi4_awvalid => CONNECTED_TO_emif_lpddr4b_s0_axi4_awvalid, -- .awvalid
|
||||
emif_lpddr4b_s0_axi4_awuser => CONNECTED_TO_emif_lpddr4b_s0_axi4_awuser, -- .awuser
|
||||
emif_lpddr4b_s0_axi4_awprot => CONNECTED_TO_emif_lpddr4b_s0_axi4_awprot, -- .awprot
|
||||
emif_lpddr4b_s0_axi4_awready => CONNECTED_TO_emif_lpddr4b_s0_axi4_awready, -- .awready
|
||||
emif_lpddr4b_s0_axi4_araddr => CONNECTED_TO_emif_lpddr4b_s0_axi4_araddr, -- .araddr
|
||||
emif_lpddr4b_s0_axi4_arburst => CONNECTED_TO_emif_lpddr4b_s0_axi4_arburst, -- .arburst
|
||||
emif_lpddr4b_s0_axi4_arid => CONNECTED_TO_emif_lpddr4b_s0_axi4_arid, -- .arid
|
||||
emif_lpddr4b_s0_axi4_arlen => CONNECTED_TO_emif_lpddr4b_s0_axi4_arlen, -- .arlen
|
||||
emif_lpddr4b_s0_axi4_arlock => CONNECTED_TO_emif_lpddr4b_s0_axi4_arlock, -- .arlock
|
||||
emif_lpddr4b_s0_axi4_arqos => CONNECTED_TO_emif_lpddr4b_s0_axi4_arqos, -- .arqos
|
||||
emif_lpddr4b_s0_axi4_arsize => CONNECTED_TO_emif_lpddr4b_s0_axi4_arsize, -- .arsize
|
||||
emif_lpddr4b_s0_axi4_arvalid => CONNECTED_TO_emif_lpddr4b_s0_axi4_arvalid, -- .arvalid
|
||||
emif_lpddr4b_s0_axi4_aruser => CONNECTED_TO_emif_lpddr4b_s0_axi4_aruser, -- .aruser
|
||||
emif_lpddr4b_s0_axi4_arprot => CONNECTED_TO_emif_lpddr4b_s0_axi4_arprot, -- .arprot
|
||||
emif_lpddr4b_s0_axi4_arready => CONNECTED_TO_emif_lpddr4b_s0_axi4_arready, -- .arready
|
||||
emif_lpddr4b_s0_axi4_wdata => CONNECTED_TO_emif_lpddr4b_s0_axi4_wdata, -- .wdata
|
||||
emif_lpddr4b_s0_axi4_wstrb => CONNECTED_TO_emif_lpddr4b_s0_axi4_wstrb, -- .wstrb
|
||||
emif_lpddr4b_s0_axi4_wlast => CONNECTED_TO_emif_lpddr4b_s0_axi4_wlast, -- .wlast
|
||||
emif_lpddr4b_s0_axi4_wvalid => CONNECTED_TO_emif_lpddr4b_s0_axi4_wvalid, -- .wvalid
|
||||
emif_lpddr4b_s0_axi4_wready => CONNECTED_TO_emif_lpddr4b_s0_axi4_wready, -- .wready
|
||||
emif_lpddr4b_s0_axi4_bready => CONNECTED_TO_emif_lpddr4b_s0_axi4_bready, -- .bready
|
||||
emif_lpddr4b_s0_axi4_bid => CONNECTED_TO_emif_lpddr4b_s0_axi4_bid, -- .bid
|
||||
emif_lpddr4b_s0_axi4_bresp => CONNECTED_TO_emif_lpddr4b_s0_axi4_bresp, -- .bresp
|
||||
emif_lpddr4b_s0_axi4_bvalid => CONNECTED_TO_emif_lpddr4b_s0_axi4_bvalid, -- .bvalid
|
||||
emif_lpddr4b_s0_axi4_rready => CONNECTED_TO_emif_lpddr4b_s0_axi4_rready, -- .rready
|
||||
emif_lpddr4b_s0_axi4_rdata => CONNECTED_TO_emif_lpddr4b_s0_axi4_rdata, -- .rdata
|
||||
emif_lpddr4b_s0_axi4_rid => CONNECTED_TO_emif_lpddr4b_s0_axi4_rid, -- .rid
|
||||
emif_lpddr4b_s0_axi4_rlast => CONNECTED_TO_emif_lpddr4b_s0_axi4_rlast, -- .rlast
|
||||
emif_lpddr4b_s0_axi4_rresp => CONNECTED_TO_emif_lpddr4b_s0_axi4_rresp, -- .rresp
|
||||
emif_lpddr4b_s0_axi4_rvalid => CONNECTED_TO_emif_lpddr4b_s0_axi4_rvalid, -- .rvalid
|
||||
emif_lpddr4b_s0_axi4lite_clock_clk => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_clock_clk, -- emif_lpddr4b_s0_axi4lite_clock.clk
|
||||
emif_lpddr4b_s0_axi4lite_reset_n_reset_n => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_reset_n_reset_n, -- emif_lpddr4b_s0_axi4lite_reset_n.reset_n
|
||||
emif_lpddr4b_s0_axi4lite_awaddr => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_awaddr, -- emif_lpddr4b_s0_axi4lite.awaddr
|
||||
emif_lpddr4b_s0_axi4lite_awprot => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_awprot, -- .awprot
|
||||
emif_lpddr4b_s0_axi4lite_awvalid => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_awvalid, -- .awvalid
|
||||
emif_lpddr4b_s0_axi4lite_awready => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_awready, -- .awready
|
||||
emif_lpddr4b_s0_axi4lite_araddr => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_araddr, -- .araddr
|
||||
emif_lpddr4b_s0_axi4lite_arprot => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_arprot, -- .arprot
|
||||
emif_lpddr4b_s0_axi4lite_arvalid => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_arvalid, -- .arvalid
|
||||
emif_lpddr4b_s0_axi4lite_arready => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_arready, -- .arready
|
||||
emif_lpddr4b_s0_axi4lite_wdata => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_wdata, -- .wdata
|
||||
emif_lpddr4b_s0_axi4lite_wstrb => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_wstrb, -- .wstrb
|
||||
emif_lpddr4b_s0_axi4lite_wvalid => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_wvalid, -- .wvalid
|
||||
emif_lpddr4b_s0_axi4lite_wready => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_wready, -- .wready
|
||||
emif_lpddr4b_s0_axi4lite_bready => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_bready, -- .bready
|
||||
emif_lpddr4b_s0_axi4lite_bresp => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_bresp, -- .bresp
|
||||
emif_lpddr4b_s0_axi4lite_bvalid => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_bvalid, -- .bvalid
|
||||
emif_lpddr4b_s0_axi4lite_rready => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_rready, -- .rready
|
||||
emif_lpddr4b_s0_axi4lite_rdata => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_rdata, -- .rdata
|
||||
emif_lpddr4b_s0_axi4lite_rresp => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_rresp, -- .rresp
|
||||
emif_lpddr4b_s0_axi4lite_rvalid => CONNECTED_TO_emif_lpddr4b_s0_axi4lite_rvalid, -- .rvalid
|
||||
emif_lpddr4b_mem_mem_cs => CONNECTED_TO_emif_lpddr4b_mem_mem_cs, -- emif_lpddr4b_mem.mem_cs
|
||||
emif_lpddr4b_mem_mem_ca => CONNECTED_TO_emif_lpddr4b_mem_mem_ca, -- .mem_ca
|
||||
emif_lpddr4b_mem_mem_cke => CONNECTED_TO_emif_lpddr4b_mem_mem_cke, -- .mem_cke
|
||||
emif_lpddr4b_mem_mem_dq => CONNECTED_TO_emif_lpddr4b_mem_mem_dq, -- .mem_dq
|
||||
emif_lpddr4b_mem_mem_dqs_t => CONNECTED_TO_emif_lpddr4b_mem_mem_dqs_t, -- .mem_dqs_t
|
||||
emif_lpddr4b_mem_mem_dqs_c => CONNECTED_TO_emif_lpddr4b_mem_mem_dqs_c, -- .mem_dqs_c
|
||||
emif_lpddr4b_mem_mem_dmi => CONNECTED_TO_emif_lpddr4b_mem_mem_dmi, -- .mem_dmi
|
||||
emif_lpddr4b_mem_ck_mem_ck_t => CONNECTED_TO_emif_lpddr4b_mem_ck_mem_ck_t, -- emif_lpddr4b_mem_ck.mem_ck_t
|
||||
emif_lpddr4b_mem_ck_mem_ck_c => CONNECTED_TO_emif_lpddr4b_mem_ck_mem_ck_c, -- .mem_ck_c
|
||||
emif_lpddr4b_mem_reset_n_mem_reset_n => CONNECTED_TO_emif_lpddr4b_mem_reset_n_mem_reset_n, -- emif_lpddr4b_mem_reset_n.mem_reset_n
|
||||
emif_lpddr4b_oct_oct_rzqin => CONNECTED_TO_emif_lpddr4b_oct_oct_rzqin, -- emif_lpddr4b_oct.oct_rzqin
|
||||
emif_lpddr4b_ref_clk_clk => CONNECTED_TO_emif_lpddr4b_ref_clk_clk, -- emif_lpddr4b_ref_clk.clk
|
||||
iopll_refclk_clk => CONNECTED_TO_iopll_refclk_clk, -- iopll_refclk.clk
|
||||
iopll_locked_export => CONNECTED_TO_iopll_locked_export, -- iopll_locked.export
|
||||
iopll_reset_reset => CONNECTED_TO_iopll_reset_reset, -- iopll_reset.reset
|
||||
iopll_outclk_axi4_lite_clk => CONNECTED_TO_iopll_outclk_axi4_lite_clk, -- iopll_outclk_axi4_lite.clk
|
||||
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
|
||||
);
|
||||
|
||||
+184
@@ -0,0 +1,184 @@
|
||||
// EMIF_Qsys.v
|
||||
|
||||
// Generated using ACDS version 25.3.1 100
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module EMIF_Qsys (
|
||||
output wire clock_310m_out_clk_clk, // clock_310m_out_clk.clk
|
||||
output wire emif_lpddr4b_s0_axi4_ctrl_ready_reset_n, // emif_lpddr4b_s0_axi4_ctrl_ready.reset_n
|
||||
input wire [29:0] emif_lpddr4b_s0_axi4_awaddr, // emif_lpddr4b_s0_axi4.awaddr
|
||||
input wire [1:0] emif_lpddr4b_s0_axi4_awburst, // .awburst
|
||||
input wire [6:0] emif_lpddr4b_s0_axi4_awid, // .awid
|
||||
input wire [7:0] emif_lpddr4b_s0_axi4_awlen, // .awlen
|
||||
input wire emif_lpddr4b_s0_axi4_awlock, // .awlock
|
||||
input wire [3:0] emif_lpddr4b_s0_axi4_awqos, // .awqos
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4_awsize, // .awsize
|
||||
input wire emif_lpddr4b_s0_axi4_awvalid, // .awvalid
|
||||
input wire [13:0] emif_lpddr4b_s0_axi4_awuser, // .awuser
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4_awprot, // .awprot
|
||||
output wire emif_lpddr4b_s0_axi4_awready, // .awready
|
||||
input wire [29:0] emif_lpddr4b_s0_axi4_araddr, // .araddr
|
||||
input wire [1:0] emif_lpddr4b_s0_axi4_arburst, // .arburst
|
||||
input wire [6:0] emif_lpddr4b_s0_axi4_arid, // .arid
|
||||
input wire [7:0] emif_lpddr4b_s0_axi4_arlen, // .arlen
|
||||
input wire emif_lpddr4b_s0_axi4_arlock, // .arlock
|
||||
input wire [3:0] emif_lpddr4b_s0_axi4_arqos, // .arqos
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4_arsize, // .arsize
|
||||
input wire emif_lpddr4b_s0_axi4_arvalid, // .arvalid
|
||||
input wire [13:0] emif_lpddr4b_s0_axi4_aruser, // .aruser
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4_arprot, // .arprot
|
||||
output wire emif_lpddr4b_s0_axi4_arready, // .arready
|
||||
input wire [255:0] emif_lpddr4b_s0_axi4_wdata, // .wdata
|
||||
input wire [31:0] emif_lpddr4b_s0_axi4_wstrb, // .wstrb
|
||||
input wire emif_lpddr4b_s0_axi4_wlast, // .wlast
|
||||
input wire emif_lpddr4b_s0_axi4_wvalid, // .wvalid
|
||||
output wire emif_lpddr4b_s0_axi4_wready, // .wready
|
||||
input wire emif_lpddr4b_s0_axi4_bready, // .bready
|
||||
output wire [6:0] emif_lpddr4b_s0_axi4_bid, // .bid
|
||||
output wire [1:0] emif_lpddr4b_s0_axi4_bresp, // .bresp
|
||||
output wire emif_lpddr4b_s0_axi4_bvalid, // .bvalid
|
||||
input wire emif_lpddr4b_s0_axi4_rready, // .rready
|
||||
output wire [255:0] emif_lpddr4b_s0_axi4_rdata, // .rdata
|
||||
output wire [6:0] emif_lpddr4b_s0_axi4_rid, // .rid
|
||||
output wire emif_lpddr4b_s0_axi4_rlast, // .rlast
|
||||
output wire [1:0] emif_lpddr4b_s0_axi4_rresp, // .rresp
|
||||
output wire emif_lpddr4b_s0_axi4_rvalid, // .rvalid
|
||||
input wire emif_lpddr4b_s0_axi4lite_clock_clk, // emif_lpddr4b_s0_axi4lite_clock.clk
|
||||
input wire emif_lpddr4b_s0_axi4lite_reset_n_reset_n, // emif_lpddr4b_s0_axi4lite_reset_n.reset_n
|
||||
input wire [26:0] emif_lpddr4b_s0_axi4lite_awaddr, // emif_lpddr4b_s0_axi4lite.awaddr
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4lite_awprot, // .awprot
|
||||
input wire emif_lpddr4b_s0_axi4lite_awvalid, // .awvalid
|
||||
output wire emif_lpddr4b_s0_axi4lite_awready, // .awready
|
||||
input wire [26:0] emif_lpddr4b_s0_axi4lite_araddr, // .araddr
|
||||
input wire [2:0] emif_lpddr4b_s0_axi4lite_arprot, // .arprot
|
||||
input wire emif_lpddr4b_s0_axi4lite_arvalid, // .arvalid
|
||||
output wire emif_lpddr4b_s0_axi4lite_arready, // .arready
|
||||
input wire [31:0] emif_lpddr4b_s0_axi4lite_wdata, // .wdata
|
||||
input wire [3:0] emif_lpddr4b_s0_axi4lite_wstrb, // .wstrb
|
||||
input wire emif_lpddr4b_s0_axi4lite_wvalid, // .wvalid
|
||||
output wire emif_lpddr4b_s0_axi4lite_wready, // .wready
|
||||
input wire emif_lpddr4b_s0_axi4lite_bready, // .bready
|
||||
output wire [1:0] emif_lpddr4b_s0_axi4lite_bresp, // .bresp
|
||||
output wire emif_lpddr4b_s0_axi4lite_bvalid, // .bvalid
|
||||
input wire emif_lpddr4b_s0_axi4lite_rready, // .rready
|
||||
output wire [31:0] emif_lpddr4b_s0_axi4lite_rdata, // .rdata
|
||||
output wire [1:0] emif_lpddr4b_s0_axi4lite_rresp, // .rresp
|
||||
output wire emif_lpddr4b_s0_axi4lite_rvalid, // .rvalid
|
||||
output wire [0:0] emif_lpddr4b_mem_mem_cs, // emif_lpddr4b_mem.mem_cs
|
||||
output wire [5:0] emif_lpddr4b_mem_mem_ca, // .mem_ca
|
||||
output wire [0:0] emif_lpddr4b_mem_mem_cke, // .mem_cke
|
||||
inout wire [31:0] emif_lpddr4b_mem_mem_dq, // .mem_dq
|
||||
inout wire [3:0] emif_lpddr4b_mem_mem_dqs_t, // .mem_dqs_t
|
||||
inout wire [3:0] emif_lpddr4b_mem_mem_dqs_c, // .mem_dqs_c
|
||||
inout wire [3:0] emif_lpddr4b_mem_mem_dmi, // .mem_dmi
|
||||
output wire [0:0] emif_lpddr4b_mem_ck_mem_ck_t, // emif_lpddr4b_mem_ck.mem_ck_t
|
||||
output wire [0:0] emif_lpddr4b_mem_ck_mem_ck_c, // .mem_ck_c
|
||||
output wire emif_lpddr4b_mem_reset_n_mem_reset_n, // emif_lpddr4b_mem_reset_n.mem_reset_n
|
||||
input wire emif_lpddr4b_oct_oct_rzqin, // emif_lpddr4b_oct.oct_rzqin
|
||||
input wire emif_lpddr4b_ref_clk_clk, // emif_lpddr4b_ref_clk.clk
|
||||
input wire iopll_refclk_clk, // iopll_refclk.clk
|
||||
output wire iopll_locked_export, // iopll_locked.export
|
||||
input wire iopll_reset_reset, // iopll_reset.reset
|
||||
output wire iopll_outclk_axi4_lite_clk, // iopll_outclk_axi4_lite.clk
|
||||
input wire reset_reset_n // reset.reset_n
|
||||
);
|
||||
|
||||
wire iopll_outclk0_clk; // iopll:outclk_0 -> [clock_310m:in_clk, emif_lpddr4b:s0_axi4_clock_in, reset_in:clk]
|
||||
wire reset_in_out_reset_reset; // reset_in:out_reset_n -> emif_lpddr4b:core_init_n
|
||||
|
||||
EMIF_Qsys_clock_bridge_0 clock_310m (
|
||||
.in_clk (iopll_outclk0_clk), // input, width = 1, in_clk.clk
|
||||
.out_clk (clock_310m_out_clk_clk) // output, width = 1, out_clk.clk
|
||||
);
|
||||
|
||||
EMIF_Qsys_emif_ddr4a_0 emif_lpddr4b (
|
||||
.s0_axi4_clock_in (iopll_outclk0_clk), // input, width = 1, s0_axi4_clock_in.clk
|
||||
.core_init_n (reset_in_out_reset_reset), // input, width = 1, core_init_n.reset_n
|
||||
.s0_axi4_reset_n (emif_lpddr4b_s0_axi4_ctrl_ready_reset_n), // output, width = 1, s0_axi4_ctrl_ready.reset_n
|
||||
.s0_axi4_awaddr (emif_lpddr4b_s0_axi4_awaddr), // input, width = 30, s0_axi4.awaddr
|
||||
.s0_axi4_awburst (emif_lpddr4b_s0_axi4_awburst), // input, width = 2, .awburst
|
||||
.s0_axi4_awid (emif_lpddr4b_s0_axi4_awid), // input, width = 7, .awid
|
||||
.s0_axi4_awlen (emif_lpddr4b_s0_axi4_awlen), // input, width = 8, .awlen
|
||||
.s0_axi4_awlock (emif_lpddr4b_s0_axi4_awlock), // input, width = 1, .awlock
|
||||
.s0_axi4_awqos (emif_lpddr4b_s0_axi4_awqos), // input, width = 4, .awqos
|
||||
.s0_axi4_awsize (emif_lpddr4b_s0_axi4_awsize), // input, width = 3, .awsize
|
||||
.s0_axi4_awvalid (emif_lpddr4b_s0_axi4_awvalid), // input, width = 1, .awvalid
|
||||
.s0_axi4_awuser (emif_lpddr4b_s0_axi4_awuser), // input, width = 14, .awuser
|
||||
.s0_axi4_awprot (emif_lpddr4b_s0_axi4_awprot), // input, width = 3, .awprot
|
||||
.s0_axi4_awready (emif_lpddr4b_s0_axi4_awready), // output, width = 1, .awready
|
||||
.s0_axi4_araddr (emif_lpddr4b_s0_axi4_araddr), // input, width = 30, .araddr
|
||||
.s0_axi4_arburst (emif_lpddr4b_s0_axi4_arburst), // input, width = 2, .arburst
|
||||
.s0_axi4_arid (emif_lpddr4b_s0_axi4_arid), // input, width = 7, .arid
|
||||
.s0_axi4_arlen (emif_lpddr4b_s0_axi4_arlen), // input, width = 8, .arlen
|
||||
.s0_axi4_arlock (emif_lpddr4b_s0_axi4_arlock), // input, width = 1, .arlock
|
||||
.s0_axi4_arqos (emif_lpddr4b_s0_axi4_arqos), // input, width = 4, .arqos
|
||||
.s0_axi4_arsize (emif_lpddr4b_s0_axi4_arsize), // input, width = 3, .arsize
|
||||
.s0_axi4_arvalid (emif_lpddr4b_s0_axi4_arvalid), // input, width = 1, .arvalid
|
||||
.s0_axi4_aruser (emif_lpddr4b_s0_axi4_aruser), // input, width = 14, .aruser
|
||||
.s0_axi4_arprot (emif_lpddr4b_s0_axi4_arprot), // input, width = 3, .arprot
|
||||
.s0_axi4_arready (emif_lpddr4b_s0_axi4_arready), // output, width = 1, .arready
|
||||
.s0_axi4_wdata (emif_lpddr4b_s0_axi4_wdata), // input, width = 256, .wdata
|
||||
.s0_axi4_wstrb (emif_lpddr4b_s0_axi4_wstrb), // input, width = 32, .wstrb
|
||||
.s0_axi4_wlast (emif_lpddr4b_s0_axi4_wlast), // input, width = 1, .wlast
|
||||
.s0_axi4_wvalid (emif_lpddr4b_s0_axi4_wvalid), // input, width = 1, .wvalid
|
||||
.s0_axi4_wready (emif_lpddr4b_s0_axi4_wready), // output, width = 1, .wready
|
||||
.s0_axi4_bready (emif_lpddr4b_s0_axi4_bready), // input, width = 1, .bready
|
||||
.s0_axi4_bid (emif_lpddr4b_s0_axi4_bid), // output, width = 7, .bid
|
||||
.s0_axi4_bresp (emif_lpddr4b_s0_axi4_bresp), // output, width = 2, .bresp
|
||||
.s0_axi4_bvalid (emif_lpddr4b_s0_axi4_bvalid), // output, width = 1, .bvalid
|
||||
.s0_axi4_rready (emif_lpddr4b_s0_axi4_rready), // input, width = 1, .rready
|
||||
.s0_axi4_rdata (emif_lpddr4b_s0_axi4_rdata), // output, width = 256, .rdata
|
||||
.s0_axi4_rid (emif_lpddr4b_s0_axi4_rid), // output, width = 7, .rid
|
||||
.s0_axi4_rlast (emif_lpddr4b_s0_axi4_rlast), // output, width = 1, .rlast
|
||||
.s0_axi4_rresp (emif_lpddr4b_s0_axi4_rresp), // output, width = 2, .rresp
|
||||
.s0_axi4_rvalid (emif_lpddr4b_s0_axi4_rvalid), // output, width = 1, .rvalid
|
||||
.s0_axi4lite_clock (emif_lpddr4b_s0_axi4lite_clock_clk), // input, width = 1, s0_axi4lite_clock.clk
|
||||
.s0_axi4lite_reset_n (emif_lpddr4b_s0_axi4lite_reset_n_reset_n), // input, width = 1, s0_axi4lite_reset_n.reset_n
|
||||
.s0_axi4lite_awaddr (emif_lpddr4b_s0_axi4lite_awaddr), // input, width = 27, s0_axi4lite.awaddr
|
||||
.s0_axi4lite_awprot (emif_lpddr4b_s0_axi4lite_awprot), // input, width = 3, .awprot
|
||||
.s0_axi4lite_awvalid (emif_lpddr4b_s0_axi4lite_awvalid), // input, width = 1, .awvalid
|
||||
.s0_axi4lite_awready (emif_lpddr4b_s0_axi4lite_awready), // output, width = 1, .awready
|
||||
.s0_axi4lite_araddr (emif_lpddr4b_s0_axi4lite_araddr), // input, width = 27, .araddr
|
||||
.s0_axi4lite_arprot (emif_lpddr4b_s0_axi4lite_arprot), // input, width = 3, .arprot
|
||||
.s0_axi4lite_arvalid (emif_lpddr4b_s0_axi4lite_arvalid), // input, width = 1, .arvalid
|
||||
.s0_axi4lite_arready (emif_lpddr4b_s0_axi4lite_arready), // output, width = 1, .arready
|
||||
.s0_axi4lite_wdata (emif_lpddr4b_s0_axi4lite_wdata), // input, width = 32, .wdata
|
||||
.s0_axi4lite_wstrb (emif_lpddr4b_s0_axi4lite_wstrb), // input, width = 4, .wstrb
|
||||
.s0_axi4lite_wvalid (emif_lpddr4b_s0_axi4lite_wvalid), // input, width = 1, .wvalid
|
||||
.s0_axi4lite_wready (emif_lpddr4b_s0_axi4lite_wready), // output, width = 1, .wready
|
||||
.s0_axi4lite_bready (emif_lpddr4b_s0_axi4lite_bready), // input, width = 1, .bready
|
||||
.s0_axi4lite_bresp (emif_lpddr4b_s0_axi4lite_bresp), // output, width = 2, .bresp
|
||||
.s0_axi4lite_bvalid (emif_lpddr4b_s0_axi4lite_bvalid), // output, width = 1, .bvalid
|
||||
.s0_axi4lite_rready (emif_lpddr4b_s0_axi4lite_rready), // input, width = 1, .rready
|
||||
.s0_axi4lite_rdata (emif_lpddr4b_s0_axi4lite_rdata), // output, width = 32, .rdata
|
||||
.s0_axi4lite_rresp (emif_lpddr4b_s0_axi4lite_rresp), // output, width = 2, .rresp
|
||||
.s0_axi4lite_rvalid (emif_lpddr4b_s0_axi4lite_rvalid), // output, width = 1, .rvalid
|
||||
.mem_0_cs (emif_lpddr4b_mem_mem_cs), // output, width = 1, mem_0.mem_cs
|
||||
.mem_0_ca (emif_lpddr4b_mem_mem_ca), // output, width = 6, .mem_ca
|
||||
.mem_0_cke (emif_lpddr4b_mem_mem_cke), // output, width = 1, .mem_cke
|
||||
.mem_0_dq (emif_lpddr4b_mem_mem_dq), // inout, width = 32, .mem_dq
|
||||
.mem_0_dqs_t (emif_lpddr4b_mem_mem_dqs_t), // inout, width = 4, .mem_dqs_t
|
||||
.mem_0_dqs_c (emif_lpddr4b_mem_mem_dqs_c), // inout, width = 4, .mem_dqs_c
|
||||
.mem_0_dmi (emif_lpddr4b_mem_mem_dmi), // inout, width = 4, .mem_dmi
|
||||
.mem_0_ck_t (emif_lpddr4b_mem_ck_mem_ck_t), // output, width = 1, mem_ck_0.mem_ck_t
|
||||
.mem_0_ck_c (emif_lpddr4b_mem_ck_mem_ck_c), // output, width = 1, .mem_ck_c
|
||||
.mem_0_reset_n (emif_lpddr4b_mem_reset_n_mem_reset_n), // output, width = 1, mem_reset_n.mem_reset_n
|
||||
.oct_rzqin_0 (emif_lpddr4b_oct_oct_rzqin), // input, width = 1, oct_0.oct_rzqin
|
||||
.ref_clk (emif_lpddr4b_ref_clk_clk) // input, width = 1, ref_clk.clk
|
||||
);
|
||||
|
||||
EMIF_Qsys_iopll_0 iopll (
|
||||
.refclk (iopll_refclk_clk), // input, width = 1, refclk.clk
|
||||
.locked (iopll_locked_export), // output, width = 1, locked.export
|
||||
.rst (iopll_reset_reset), // input, width = 1, reset.reset
|
||||
.outclk_0 (iopll_outclk0_clk), // output, width = 1, outclk0.clk
|
||||
.outclk_1 (iopll_outclk_axi4_lite_clk) // output, width = 1, outclk1.clk
|
||||
);
|
||||
|
||||
EMIF_Qsys_reset_in reset_in (
|
||||
.clk (iopll_outclk0_clk), // input, width = 1, clk.clk
|
||||
.in_reset_n (reset_reset_n), // input, width = 1, in_reset.reset_n
|
||||
.out_reset_n (reset_in_out_reset_reset) // output, width = 1, out_reset.reset_n
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,2 @@
|
||||
// This file was automatically generated and it is used for board migration. Do not make changes to this file.
|
||||
default
|
||||
Executable
+371
@@ -0,0 +1,371 @@
|
||||
<?xml version="1.0" ?>
|
||||
<!--Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.-->
|
||||
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
|
||||
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
||||
<ipxact:library>EMIF_Qsys_clock_bridge_0</ipxact:library>
|
||||
<ipxact:name>clock_bridge_0</ipxact:name>
|
||||
<ipxact:version>19.2.0</ipxact:version>
|
||||
<ipxact:busInterfaces>
|
||||
<ipxact:busInterface>
|
||||
<ipxact:name>in_clk</ipxact:name>
|
||||
<ipxact:busType vendor="intel" library="intel" name="clock" version="25.3"></ipxact:busType>
|
||||
<ipxact:abstractionTypes>
|
||||
<ipxact:abstractionType>
|
||||
<ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="25.3"></ipxact:abstractionRef>
|
||||
<ipxact:portMaps>
|
||||
<ipxact:portMap>
|
||||
<ipxact:logicalPort>
|
||||
<ipxact:name>clk</ipxact:name>
|
||||
</ipxact:logicalPort>
|
||||
<ipxact:physicalPort>
|
||||
<ipxact:name>in_clk</ipxact:name>
|
||||
</ipxact:physicalPort>
|
||||
</ipxact:portMap>
|
||||
</ipxact:portMaps>
|
||||
</ipxact:abstractionType>
|
||||
</ipxact:abstractionTypes>
|
||||
<ipxact:slave></ipxact:slave>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="clockRate" type="longint">
|
||||
<ipxact:name>clockRate</ipxact:name>
|
||||
<ipxact:displayName>Clock rate</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="externallyDriven" type="bit">
|
||||
<ipxact:name>externallyDriven</ipxact:name>
|
||||
<ipxact:displayName>Externally driven</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="ptfSchematicName" type="string">
|
||||
<ipxact:name>ptfSchematicName</ipxact:name>
|
||||
<ipxact:displayName>PTF schematic name</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</ipxact:busInterface>
|
||||
<ipxact:busInterface>
|
||||
<ipxact:name>out_clk</ipxact:name>
|
||||
<ipxact:busType vendor="intel" library="intel" name="clock" version="25.3"></ipxact:busType>
|
||||
<ipxact:abstractionTypes>
|
||||
<ipxact:abstractionType>
|
||||
<ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="25.3"></ipxact:abstractionRef>
|
||||
<ipxact:portMaps>
|
||||
<ipxact:portMap>
|
||||
<ipxact:logicalPort>
|
||||
<ipxact:name>clk</ipxact:name>
|
||||
</ipxact:logicalPort>
|
||||
<ipxact:physicalPort>
|
||||
<ipxact:name>out_clk</ipxact:name>
|
||||
</ipxact:physicalPort>
|
||||
</ipxact:portMap>
|
||||
</ipxact:portMaps>
|
||||
</ipxact:abstractionType>
|
||||
</ipxact:abstractionTypes>
|
||||
<ipxact:master></ipxact:master>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="associatedDirectClock" type="string">
|
||||
<ipxact:name>associatedDirectClock</ipxact:name>
|
||||
<ipxact:displayName>Associated direct clock</ipxact:displayName>
|
||||
<ipxact:value>in_clk</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="clockRate" type="longint">
|
||||
<ipxact:name>clockRate</ipxact:name>
|
||||
<ipxact:displayName>Clock rate</ipxact:displayName>
|
||||
<ipxact:value>310000000</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="clockRateKnown" type="bit">
|
||||
<ipxact:name>clockRateKnown</ipxact:name>
|
||||
<ipxact:displayName>Clock rate known</ipxact:displayName>
|
||||
<ipxact:value>true</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="externallyDriven" type="bit">
|
||||
<ipxact:name>externallyDriven</ipxact:name>
|
||||
<ipxact:displayName>Externally driven</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="ptfSchematicName" type="string">
|
||||
<ipxact:name>ptfSchematicName</ipxact:name>
|
||||
<ipxact:displayName>PTF schematic name</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</ipxact:busInterface>
|
||||
</ipxact:busInterfaces>
|
||||
<ipxact:model>
|
||||
<ipxact:views>
|
||||
<ipxact:view>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
|
||||
<ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
|
||||
</ipxact:view>
|
||||
</ipxact:views>
|
||||
<ipxact:instantiations>
|
||||
<ipxact:componentInstantiation>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:moduleName>altera_clock_bridge</ipxact:moduleName>
|
||||
<ipxact:fileSetRef>
|
||||
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
|
||||
</ipxact:fileSetRef>
|
||||
<ipxact:parameters></ipxact:parameters>
|
||||
</ipxact:componentInstantiation>
|
||||
</ipxact:instantiations>
|
||||
<ipxact:ports>
|
||||
<ipxact:port>
|
||||
<ipxact:name>in_clk</ipxact:name>
|
||||
<ipxact:wire>
|
||||
<ipxact:direction>in</ipxact:direction>
|
||||
<ipxact:vectors></ipxact:vectors>
|
||||
<ipxact:wireTypeDefs>
|
||||
<ipxact:wireTypeDef>
|
||||
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
|
||||
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
|
||||
</ipxact:wireTypeDef>
|
||||
</ipxact:wireTypeDefs>
|
||||
</ipxact:wire>
|
||||
</ipxact:port>
|
||||
<ipxact:port>
|
||||
<ipxact:name>out_clk</ipxact:name>
|
||||
<ipxact:wire>
|
||||
<ipxact:direction>out</ipxact:direction>
|
||||
<ipxact:vectors></ipxact:vectors>
|
||||
<ipxact:wireTypeDefs>
|
||||
<ipxact:wireTypeDef>
|
||||
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
|
||||
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
|
||||
</ipxact:wireTypeDef>
|
||||
</ipxact:wireTypeDefs>
|
||||
</ipxact:wire>
|
||||
</ipxact:port>
|
||||
</ipxact:ports>
|
||||
</ipxact:model>
|
||||
<ipxact:vendorExtensions>
|
||||
<altera:entity_info>
|
||||
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
||||
<ipxact:library>EMIF_Qsys_clock_bridge_0</ipxact:library>
|
||||
<ipxact:name>altera_clock_bridge</ipxact:name>
|
||||
<ipxact:version>19.2.0</ipxact:version>
|
||||
</altera:entity_info>
|
||||
<altera:altera_module_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="DERIVED_CLOCK_RATE" type="longint">
|
||||
<ipxact:name>DERIVED_CLOCK_RATE</ipxact:name>
|
||||
<ipxact:displayName>Derived clock rate</ipxact:displayName>
|
||||
<ipxact:value>310000000</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="EXPLICIT_CLOCK_RATE" type="longint">
|
||||
<ipxact:name>EXPLICIT_CLOCK_RATE</ipxact:name>
|
||||
<ipxact:displayName>Explicit clock rate</ipxact:displayName>
|
||||
<ipxact:value>310000000</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="NUM_CLOCK_OUTPUTS" type="int">
|
||||
<ipxact:name>NUM_CLOCK_OUTPUTS</ipxact:name>
|
||||
<ipxact:displayName>Number of Clock Outputs</ipxact:displayName>
|
||||
<ipxact:value>1</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_module_parameters>
|
||||
<altera:altera_system_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="board" type="string">
|
||||
<ipxact:name>board</ipxact:name>
|
||||
<ipxact:displayName>Board</ipxact:displayName>
|
||||
<ipxact:value>default</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="device" type="string">
|
||||
<ipxact:name>device</ipxact:name>
|
||||
<ipxact:displayName>Device</ipxact:displayName>
|
||||
<ipxact:value>A5EB013BB23BE4SCS</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceFamily" type="string">
|
||||
<ipxact:name>deviceFamily</ipxact:name>
|
||||
<ipxact:displayName>Device family</ipxact:displayName>
|
||||
<ipxact:value>Agilex 5</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
|
||||
<ipxact:name>deviceSpeedGrade</ipxact:name>
|
||||
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
|
||||
<ipxact:value>4</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="generationId" type="int">
|
||||
<ipxact:name>generationId</ipxact:name>
|
||||
<ipxact:displayName>Generation Id</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="bonusData" type="string">
|
||||
<ipxact:name>bonusData</ipxact:name>
|
||||
<ipxact:displayName>bonusData</ipxact:displayName>
|
||||
<ipxact:value>bonusData
|
||||
{
|
||||
element $system
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Agilex 5";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element clock_bridge_0
|
||||
{
|
||||
}
|
||||
}
|
||||
</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
|
||||
<ipxact:name>hideFromIPCatalog</ipxact:name>
|
||||
<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
|
||||
<ipxact:name>lockedInterfaceDefinition</ipxact:name>
|
||||
<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
|
||||
<ipxact:value><boundaryDefinition>
|
||||
<interfaces>
|
||||
<interface>
|
||||
<name>in_clk</name>
|
||||
<type>clock</type>
|
||||
<isStart>false</isStart>
|
||||
<ports>
|
||||
<port>
|
||||
<name>in_clk</name>
|
||||
<role>clk</role>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<lowerBound>0</lowerBound>
|
||||
<vhdlType>STD_LOGIC</vhdlType>
|
||||
<terminationValue>0</terminationValue>
|
||||
</port>
|
||||
</ports>
|
||||
<assignments>
|
||||
<assignmentValueMap/>
|
||||
</assignments>
|
||||
<parameters>
|
||||
<parameterValueMap>
|
||||
<entry>
|
||||
<key>clockRate</key>
|
||||
<value>0</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>externallyDriven</key>
|
||||
<value>false</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>ptfSchematicName</key>
|
||||
</entry>
|
||||
</parameterValueMap>
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface>
|
||||
<name>out_clk</name>
|
||||
<type>clock</type>
|
||||
<isStart>true</isStart>
|
||||
<ports>
|
||||
<port>
|
||||
<name>out_clk</name>
|
||||
<role>clk</role>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<lowerBound>0</lowerBound>
|
||||
<vhdlType>STD_LOGIC</vhdlType>
|
||||
<terminationValue>0</terminationValue>
|
||||
</port>
|
||||
</ports>
|
||||
<assignments>
|
||||
<assignmentValueMap/>
|
||||
</assignments>
|
||||
<parameters>
|
||||
<parameterValueMap>
|
||||
<entry>
|
||||
<key>associatedDirectClock</key>
|
||||
<value>in_clk</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>clockRate</key>
|
||||
<value>310000000</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>clockRateKnown</key>
|
||||
<value>true</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>externallyDriven</key>
|
||||
<value>false</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>ptfSchematicName</key>
|
||||
</entry>
|
||||
</parameterValueMap>
|
||||
</parameters>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</boundaryDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="systemInfos" type="string">
|
||||
<ipxact:name>systemInfos</ipxact:name>
|
||||
<ipxact:displayName>systemInfos</ipxact:displayName>
|
||||
<ipxact:value><systemInfosDefinition>
|
||||
<connPtSystemInfos>
|
||||
<entry>
|
||||
<key>in_clk</key>
|
||||
<value>
|
||||
<connectionPointName>in_clk</connectionPointName>
|
||||
<suppliedSystemInfos>
|
||||
<entry>
|
||||
<key>CLOCK_RATE</key>
|
||||
<value>310000000</value>
|
||||
</entry>
|
||||
</suppliedSystemInfos>
|
||||
<consumedSystemInfos/>
|
||||
</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>out_clk</key>
|
||||
<value>
|
||||
<connectionPointName>out_clk</connectionPointName>
|
||||
<suppliedSystemInfos/>
|
||||
<consumedSystemInfos>
|
||||
<entry>
|
||||
<key>CLOCK_RATE</key>
|
||||
<value>310000000</value>
|
||||
</entry>
|
||||
</consumedSystemInfos>
|
||||
</value>
|
||||
</entry>
|
||||
</connPtSystemInfos>
|
||||
</systemInfosDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="dflBitArray" type="string">
|
||||
<ipxact:name>dflBitArray</ipxact:name>
|
||||
<ipxact:displayName>dflBitArray</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="cpuInfo" type="string">
|
||||
<ipxact:name>cpuInfo</ipxact:name>
|
||||
<ipxact:displayName>cpuInfo</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_system_parameters>
|
||||
<altera:altera_interface_boundary>
|
||||
<altera:interface_mapping altera:name="in_clk" altera:internal="clock_bridge_0.in_clk" altera:type="clock" altera:dir="end">
|
||||
<altera:port_mapping altera:name="in_clk" altera:internal="in_clk"></altera:port_mapping>
|
||||
</altera:interface_mapping>
|
||||
<altera:interface_mapping altera:name="out_clk" altera:internal="clock_bridge_0.out_clk" altera:type="clock" altera:dir="start">
|
||||
<altera:port_mapping altera:name="out_clk" altera:internal="out_clk"></altera:port_mapping>
|
||||
</altera:interface_mapping>
|
||||
</altera:altera_interface_boundary>
|
||||
<altera:altera_has_warnings>false</altera:altera_has_warnings>
|
||||
<altera:altera_has_errors>false</altera:altera_has_errors>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:component>
|
||||
+7
@@ -0,0 +1,7 @@
|
||||
component EMIF_Qsys_clock_bridge_0 is
|
||||
port (
|
||||
in_clk : in std_logic := 'X'; -- clk
|
||||
out_clk : out std_logic -- clk
|
||||
);
|
||||
end component EMIF_Qsys_clock_bridge_0;
|
||||
|
||||
+145
@@ -0,0 +1,145 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for EMIF_Qsys_clock_bridge_0</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">EMIF_Qsys_clock_bridge_0</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.03.02.19:16:02</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_clock_bridge_0"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>clock_bridge_0</h2>altera_clock_bridge v19.2.0
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">DERIVED_CLOCK_RATE</td>
|
||||
<td class="parametervalue">310000000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EXPLICIT_CLOCK_RATE</td>
|
||||
<td class="parametervalue">310000000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">NUM_CLOCK_OUTPUTS</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.01 seconds</td>
|
||||
<td class="r">rendering took 0.02 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
+44
@@ -0,0 +1,44 @@
|
||||
<?xml version="1.0" ?>
|
||||
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
|
||||
<instanceKey xsi:type="xs:string">EMIF_Qsys_clock_bridge_0</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters></parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>EMIF_Qsys_clock_bridge_0</className>
|
||||
<version>1.0</version>
|
||||
<name>EMIF_Qsys_clock_bridge_0</name>
|
||||
<uniqueName>EMIF_Qsys_clock_bridge_0</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
</instanceData>
|
||||
<children>
|
||||
<node>
|
||||
<instanceKey xsi:type="xs:string">clock_bridge_0</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters>
|
||||
<parameter>
|
||||
<name>DERIVED_CLOCK_RATE</name>
|
||||
<value>310000000</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>EXPLICIT_CLOCK_RATE</name>
|
||||
<value>310000000</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>NUM_CLOCK_OUTPUTS</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
</parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>altera_clock_bridge</className>
|
||||
<version>19.2.0</version>
|
||||
<name>clock_bridge_0</name>
|
||||
<uniqueName>EMIF_Qsys_clock_bridge_0_altera_clock_bridge_1920_njakcna</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
<path>EMIF_Qsys_clock_bridge_0.clock_bridge_0</path>
|
||||
</instanceData>
|
||||
<children></children>
|
||||
</node>
|
||||
</children>
|
||||
</node>
|
||||
+29
@@ -0,0 +1,29 @@
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TOOL_VERSION "25.3.1"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_clock_bridge"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name PRE_COMPILED_MODULE "ON"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name OCS_IP_FILE [file join $::quartus(qip_path) "../EMIF_Qsys_clock_bridge_0.ip"]
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name OCS_IP_TYPE "altera_clock_bridge"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name OCS_IP_VERSION "19.2.0"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name OCS_IP_HASH "njakcna"
|
||||
set_global_assignment -library "EMIF_Qsys_clock_bridge_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "EMIF_Qsys_clock_bridge_0.sopcinfo"]
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name SLD_INFO "QSYS_NAME EMIF_Qsys_clock_bridge_0 HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "EMIF_Qsys_clock_bridge_0" -name MISC_FILE [file join $::quartus(qip_path) "EMIF_Qsys_clock_bridge_0.cmp"]
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "EMIF_Qsys_clock_bridge_0" -name MISC_FILE [file join $::quartus(qip_path) "../EMIF_Qsys_clock_bridge_0.ip"]
|
||||
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2Nsb2NrX2JyaWRnZV8w"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "EMIF_Qsys_clock_bridge_0" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/EMIF_Qsys_clock_bridge_0.v"]
|
||||
|
||||
+320
@@ -0,0 +1,320 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport
|
||||
name="EMIF_Qsys_clock_bridge_0"
|
||||
kind="EMIF_Qsys_clock_bridge_0"
|
||||
version="1.0"
|
||||
fabric="QSYS">
|
||||
<!-- Format version 25.3.1 100 (Future versions may contain additional information.) -->
|
||||
<!-- 2026.03.02.19:16:02 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_UNIQUE_ID">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE">
|
||||
<type>java.lang.String</type>
|
||||
<value>A5EB013BB23BE4SCS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
||||
<type>java.lang.String</type>
|
||||
<value>4</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_BOARD">
|
||||
<type>java.lang.String</type>
|
||||
<value>default</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>BOARD</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_RATE">
|
||||
<type>java.lang.Long</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_DOMAIN">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_RESET_DOMAIN">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="clock_bridge_0"
|
||||
kind="altera_clock_bridge"
|
||||
version="19.2.0"
|
||||
path="clock_bridge_0"
|
||||
className="altera_clock_bridge">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="DERIVED_CLOCK_RATE">
|
||||
<type>long</type>
|
||||
<value>310000000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="EXPLICIT_CLOCK_RATE">
|
||||
<type>long</type>
|
||||
<value>310000000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="NUM_CLOCK_OUTPUTS">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="in_clk" kind="clock_sink" version="25.3">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRateKnown">
|
||||
<type>java.lang.Boolean</type>
|
||||
<value>true</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRate">
|
||||
<type>java.lang.Long</type>
|
||||
<value>310000000</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<span>0</span>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>in_clk</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="out_clk" kind="clock_source" version="25.3">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedDirectClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>in_clk</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRate">
|
||||
<type>long</type>
|
||||
<value>310000000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRateKnown">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<span>0</span>
|
||||
<isStart>true</isStart>
|
||||
<port>
|
||||
<name>out_clk</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altera_clock_bridge</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>Clock Bridge IP</displayName>
|
||||
<version>19.2.0</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Clock Input</displayName>
|
||||
<version>25.3</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_source</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Clock Output</displayName>
|
||||
<version>25.3</version>
|
||||
</plugin>
|
||||
<reportVersion>25.3.1 100</reportVersion>
|
||||
<uniqueIdentifier></uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.03.02.19:16:02"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_clock_bridge_0/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5EB013BB23BE4SCS"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="4"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_CLOCK_RATE"
|
||||
type="Long"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_CLOCK_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_RESET_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="in_clk" kind="clock" start="0">
|
||||
<property name="clockRate" value="0" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="in_clk" direction="input" role="clk" width="1" />
|
||||
</interface>
|
||||
<interface name="out_clk" kind="clock" start="1">
|
||||
<property name="associatedDirectClock" value="in_clk" />
|
||||
<property name="clockRate" value="310000000" />
|
||||
<property name="clockRateKnown" value="true" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="out_clk" direction="output" role="clk" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity
|
||||
kind="EMIF_Qsys_clock_bridge_0"
|
||||
version="1.0"
|
||||
name="EMIF_Qsys_clock_bridge_0">
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_IN_CLK_RESET_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_DOMAIN" value="-1" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_clock_bridge_0/synth/EMIF_Qsys_clock_bridge_0.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_clock_bridge_0/synth/EMIF_Qsys_clock_bridge_0.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_clock_bridge_0.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<messages>
|
||||
<message level="Info" culprit="EMIF_Qsys_clock_bridge_0">"Generating: EMIF_Qsys_clock_bridge_0"</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
module EMIF_Qsys_clock_bridge_0 (
|
||||
input wire in_clk, // in_clk.clk, Clock Input
|
||||
output wire out_clk // out_clk.clk, Clock Output
|
||||
);
|
||||
endmodule
|
||||
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_clock_bridge_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_clock_bridge_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: EMIF_Qsys_clock_bridge_0: "Transforming system: EMIF_Qsys_clock_bridge_0"
|
||||
Info: EMIF_Qsys_clock_bridge_0: "Naming system components in system: EMIF_Qsys_clock_bridge_0"
|
||||
Info: EMIF_Qsys_clock_bridge_0: "Processing generation queue"
|
||||
Info: EMIF_Qsys_clock_bridge_0: "Generating: EMIF_Qsys_clock_bridge_0"
|
||||
Info: EMIF_Qsys_clock_bridge_0: Done "EMIF_Qsys_clock_bridge_0" with 1 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
EMIF_Qsys_clock_bridge_0 u0 (
|
||||
.in_clk (_connected_to_in_clk_), // input, width = 1, in_clk.clk
|
||||
.out_clk (_connected_to_out_clk_) // output, width = 1, out_clk.clk
|
||||
);
|
||||
|
||||
+13
@@ -0,0 +1,13 @@
|
||||
component EMIF_Qsys_clock_bridge_0 is
|
||||
port (
|
||||
in_clk : in std_logic := 'X'; -- clk
|
||||
out_clk : out std_logic -- clk
|
||||
);
|
||||
end component EMIF_Qsys_clock_bridge_0;
|
||||
|
||||
u0 : component EMIF_Qsys_clock_bridge_0
|
||||
port map (
|
||||
in_clk => CONNECTED_TO_in_clk, -- in_clk.clk
|
||||
out_clk => CONNECTED_TO_out_clk -- out_clk.clk
|
||||
);
|
||||
|
||||
+13
@@ -0,0 +1,13 @@
|
||||
// EMIF_Qsys_clock_bridge_0.v
|
||||
|
||||
// Generated using ACDS version 25.3.1 100
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module EMIF_Qsys_clock_bridge_0 (
|
||||
input wire in_clk, // in_clk.clk, Clock Input
|
||||
output wire out_clk // out_clk.clk, Clock Output
|
||||
);
|
||||
|
||||
assign out_clk = in_clk;
|
||||
|
||||
endmodule
|
||||
Executable
+4552
File diff suppressed because it is too large
Load Diff
+658
@@ -0,0 +1,658 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2026 Altera Corporation. All rights reserved.
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
the Altera IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Altera and sold by Altera or its authorized distributors. Please
|
||||
refer to the Altera Software License Subscription Agreements
|
||||
on the Quartus Prime software download page.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 384 2136)
|
||||
(text "EMIF_Qsys_emif_ddr4a_0" (rect 106 0 221 12)(font "SansSerif" (font_size 11)))
|
||||
(text "inst" (rect 8 2120 20 2132)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 76)
|
||||
(input)
|
||||
(text "s0_axi4_clock_in" (rect 0 0 69 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_clock_in" (rect 4 65 100 76)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 76)(pt 136 76)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 126)
|
||||
(input)
|
||||
(text "core_init_n" (rect 0 0 43 12)(font "SansSerif" (font_size 8)))
|
||||
(text "core_init_n" (rect 4 115 70 126)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 126)(pt 136 126)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 176)
|
||||
(input)
|
||||
(text "s0_axi4_awaddr[29..0]" (rect 0 0 90 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awaddr[29..0]" (rect 4 165 130 176)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 176)(pt 136 176)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 201)
|
||||
(input)
|
||||
(text "s0_axi4_awburst[1..0]" (rect 0 0 87 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awburst[1..0]" (rect 4 190 130 201)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 201)(pt 136 201)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 226)
|
||||
(input)
|
||||
(text "s0_axi4_awid[6..0]" (rect 0 0 74 12)(font "SansSerif" (font_size 8)))
|
||||
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|
||||
(text "s0_axi4lite_arready" (rect 4 1390 118 1401)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1501)
|
||||
(output)
|
||||
(text "s0_axi4lite_wready" (rect 0 0 76 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4lite_wready" (rect 4 1490 112 1501)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1551)
|
||||
(output)
|
||||
(text "s0_axi4lite_bresp[1..0]" (rect 0 0 88 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4lite_bresp[1..0]" (rect 4 1540 142 1551)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1576)
|
||||
(output)
|
||||
(text "s0_axi4lite_bvalid" (rect 0 0 69 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4lite_bvalid" (rect 4 1565 112 1576)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1626)
|
||||
(output)
|
||||
(text "s0_axi4lite_rdata[31..0]" (rect 0 0 90 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4lite_rdata[31..0]" (rect 4 1615 148 1626)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1651)
|
||||
(output)
|
||||
(text "s0_axi4lite_rresp[1..0]" (rect 0 0 87 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4lite_rresp[1..0]" (rect 4 1640 142 1651)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1676)
|
||||
(output)
|
||||
(text "s0_axi4lite_rvalid" (rect 0 0 68 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4lite_rvalid" (rect 4 1665 112 1676)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1726)
|
||||
(output)
|
||||
(text "mem_0_cs" (rect 0 0 47 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_cs" (rect 4 1715 52 1726)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1751)
|
||||
(output)
|
||||
(text "mem_0_ca[5..0]" (rect 0 0 67 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_ca[5..0]" (rect 4 1740 88 1751)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1776)
|
||||
(output)
|
||||
(text "mem_0_cke" (rect 0 0 51 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_cke" (rect 4 1765 58 1776)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1926)
|
||||
(output)
|
||||
(text "mem_0_ck_t" (rect 0 0 55 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_ck_t" (rect 4 1915 64 1926)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1951)
|
||||
(output)
|
||||
(text "mem_0_ck_c" (rect 0 0 57 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_ck_c" (rect 4 1940 64 1951)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 2001)
|
||||
(output)
|
||||
(text "mem_0_reset_n" (rect 0 0 68 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_reset_n" (rect 4 1990 82 2001)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1801)
|
||||
(bidir)
|
||||
(text "mem_0_dq[31..0]" (rect 0 0 70 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_dq[31..0]" (rect 4 1790 94 1801)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1801)(pt 136 1801)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1826)
|
||||
(bidir)
|
||||
(text "mem_0_dqs_t[3..0]" (rect 0 0 80 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_dqs_t[3..0]" (rect 4 1815 106 1826)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1826)(pt 136 1826)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1851)
|
||||
(bidir)
|
||||
(text "mem_0_dqs_c[3..0]" (rect 0 0 82 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_dqs_c[3..0]" (rect 4 1840 106 1851)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1851)(pt 136 1851)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1876)
|
||||
(bidir)
|
||||
(text "mem_0_dmi[3..0]" (rect 0 0 71 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_dmi[3..0]" (rect 4 1865 94 1876)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1876)(pt 136 1876)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "s0_axi4_clock_in" (rect 37 46 170 105)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 141 71 300 152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "core_init_n" (rect 72 96 210 205)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "reset_n" (rect 141 121 324 252)(font "SansSerif" (color 0 0 0)))
|
||||
(text "s0_axi4_ctrl_ready" (rect 256 46 620 105)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "reset_n" (rect 219 71 480 152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "s0_axi4" (rect 92 146 226 305)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "awaddr" (rect 141 171 318 352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awburst" (rect 141 196 324 402)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awid" (rect 141 221 306 452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awlen" (rect 141 246 312 502)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awlock" (rect 141 271 318 552)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awqos" (rect 141 296 312 602)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awsize" (rect 141 321 318 652)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awvalid" (rect 141 346 324 702)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awuser" (rect 141 371 318 752)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awprot" (rect 141 396 318 802)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awready" (rect 141 421 324 852)(font "SansSerif" (color 0 0 0)))
|
||||
(text "araddr" (rect 141 446 318 902)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arburst" (rect 141 471 324 952)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arid" (rect 141 496 306 1002)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arlen" (rect 141 521 312 1052)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arlock" (rect 141 546 318 1102)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arqos" (rect 141 571 312 1152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arsize" (rect 141 596 318 1202)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arvalid" (rect 141 621 324 1252)(font "SansSerif" (color 0 0 0)))
|
||||
(text "aruser" (rect 141 646 318 1302)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arprot" (rect 141 671 318 1352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arready" (rect 141 696 324 1402)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wdata" (rect 141 721 312 1452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wstrb" (rect 141 746 312 1502)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wlast" (rect 141 771 312 1552)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wvalid" (rect 141 796 318 1602)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wready" (rect 141 821 318 1652)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bready" (rect 141 846 318 1702)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bid" (rect 141 871 300 1752)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bresp" (rect 141 896 312 1802)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bvalid" (rect 141 921 318 1852)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rready" (rect 141 946 318 1902)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rdata" (rect 141 971 312 1952)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rid" (rect 141 996 300 2002)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rlast" (rect 141 1021 312 2052)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rresp" (rect 141 1046 312 2102)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rvalid" (rect 141 1071 318 2152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "s0_axi4lite_clock" (rect 38 1096 178 2205)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 141 1121 300 2252)(font "SansSerif" (color 0 0 0)))
|
||||
(text "s0_axi4lite_reset_n" (rect 22 1146 158 2305)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "reset_n" (rect 141 1171 324 2352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "s0_axi4lite" (rect 75 1196 216 2405)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "awaddr" (rect 141 1221 318 2452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awprot" (rect 141 1246 318 2502)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awvalid" (rect 141 1271 324 2552)(font "SansSerif" (color 0 0 0)))
|
||||
(text "awready" (rect 141 1296 324 2602)(font "SansSerif" (color 0 0 0)))
|
||||
(text "araddr" (rect 141 1321 318 2652)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arprot" (rect 141 1346 318 2702)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arvalid" (rect 141 1371 324 2752)(font "SansSerif" (color 0 0 0)))
|
||||
(text "arready" (rect 141 1396 324 2802)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wdata" (rect 141 1421 312 2852)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wstrb" (rect 141 1446 312 2902)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wvalid" (rect 141 1471 318 2952)(font "SansSerif" (color 0 0 0)))
|
||||
(text "wready" (rect 141 1496 318 3002)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bready" (rect 141 1521 318 3052)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bresp" (rect 141 1546 312 3102)(font "SansSerif" (color 0 0 0)))
|
||||
(text "bvalid" (rect 141 1571 318 3152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rready" (rect 141 1596 318 3202)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rdata" (rect 141 1621 312 3252)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rresp" (rect 141 1646 312 3302)(font "SansSerif" (color 0 0 0)))
|
||||
(text "rvalid" (rect 141 1671 318 3352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_0" (rect 93 1696 216 3405)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "mem_cs" (rect 141 1721 318 3452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_ca" (rect 141 1746 318 3502)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_cke" (rect 141 1771 324 3552)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dq" (rect 141 1796 318 3602)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dqs_t" (rect 141 1821 336 3652)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dqs_c" (rect 141 1846 336 3702)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dmi" (rect 141 1871 324 3752)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_ck_0" (rect 72 1896 192 3805)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "mem_ck_t" (rect 141 1921 330 3852)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_ck_c" (rect 141 1946 330 3902)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_reset_n" (rect 55 1971 176 3955)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "mem_reset_n" (rect 141 1996 348 4002)(font "SansSerif" (color 0 0 0)))
|
||||
(text "oct_0" (rect 105 2021 240 4055)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "oct_rzqin" (rect 141 2046 336 4102)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ref_clk" (rect 96 2071 234 4155)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 141 2096 300 4202)(font "SansSerif" (color 0 0 0)))
|
||||
(text " EMIF_Qsys_emif_ddr4a_0 " (rect 268 2126 680 4262)(font "SansSerif" ))
|
||||
(line (pt 136 34)(pt 255 34)(line_width 1))
|
||||
(line (pt 255 34)(pt 255 2126)(line_width 1))
|
||||
(line (pt 136 2126)(pt 255 2126)(line_width 1))
|
||||
(line (pt 136 34)(pt 136 2126)(line_width 1))
|
||||
(line (pt 137 55)(pt 137 80)(line_width 1))
|
||||
(line (pt 138 55)(pt 138 80)(line_width 1))
|
||||
(line (pt 137 105)(pt 137 130)(line_width 1))
|
||||
(line (pt 138 105)(pt 138 130)(line_width 1))
|
||||
(line (pt 254 55)(pt 254 80)(line_width 1))
|
||||
(line (pt 253 55)(pt 253 80)(line_width 1))
|
||||
(line (pt 384 426)(pt 136 426)(line_width 1))
|
||||
(line (pt 384 701)(pt 136 701)(line_width 1))
|
||||
(line (pt 384 826)(pt 136 826)(line_width 1))
|
||||
(line (pt 384 876)(pt 136 876)(line_width 3))
|
||||
(line (pt 384 901)(pt 136 901)(line_width 3))
|
||||
(line (pt 384 926)(pt 136 926)(line_width 1))
|
||||
(line (pt 384 976)(pt 136 976)(line_width 3))
|
||||
(line (pt 384 1001)(pt 136 1001)(line_width 3))
|
||||
(line (pt 384 1026)(pt 136 1026)(line_width 1))
|
||||
(line (pt 384 1051)(pt 136 1051)(line_width 3))
|
||||
(line (pt 384 1076)(pt 136 1076)(line_width 1))
|
||||
(line (pt 137 155)(pt 137 1080)(line_width 1))
|
||||
(line (pt 138 155)(pt 138 1080)(line_width 1))
|
||||
(line (pt 137 1105)(pt 137 1130)(line_width 1))
|
||||
(line (pt 138 1105)(pt 138 1130)(line_width 1))
|
||||
(line (pt 137 1155)(pt 137 1180)(line_width 1))
|
||||
(line (pt 138 1155)(pt 138 1180)(line_width 1))
|
||||
(line (pt 384 1301)(pt 136 1301)(line_width 1))
|
||||
(line (pt 384 1401)(pt 136 1401)(line_width 1))
|
||||
(line (pt 384 1501)(pt 136 1501)(line_width 1))
|
||||
(line (pt 384 1551)(pt 136 1551)(line_width 3))
|
||||
(line (pt 384 1576)(pt 136 1576)(line_width 1))
|
||||
(line (pt 384 1626)(pt 136 1626)(line_width 3))
|
||||
(line (pt 384 1651)(pt 136 1651)(line_width 3))
|
||||
(line (pt 384 1676)(pt 136 1676)(line_width 1))
|
||||
(line (pt 137 1205)(pt 137 1680)(line_width 1))
|
||||
(line (pt 138 1205)(pt 138 1680)(line_width 1))
|
||||
(line (pt 384 1726)(pt 136 1726)(line_width 1))
|
||||
(line (pt 384 1751)(pt 136 1751)(line_width 3))
|
||||
(line (pt 384 1776)(pt 136 1776)(line_width 1))
|
||||
(line (pt 137 1705)(pt 137 1880)(line_width 1))
|
||||
(line (pt 138 1705)(pt 138 1880)(line_width 1))
|
||||
(line (pt 384 1926)(pt 136 1926)(line_width 1))
|
||||
(line (pt 384 1951)(pt 136 1951)(line_width 1))
|
||||
(line (pt 137 1905)(pt 137 1955)(line_width 1))
|
||||
(line (pt 138 1905)(pt 138 1955)(line_width 1))
|
||||
(line (pt 384 2001)(pt 136 2001)(line_width 1))
|
||||
(line (pt 137 1980)(pt 137 2005)(line_width 1))
|
||||
(line (pt 138 1980)(pt 138 2005)(line_width 1))
|
||||
(line (pt 137 2030)(pt 137 2055)(line_width 1))
|
||||
(line (pt 138 2030)(pt 138 2055)(line_width 1))
|
||||
(line (pt 137 2080)(pt 137 2105)(line_width 1))
|
||||
(line (pt 138 2080)(pt 138 2105)(line_width 1))
|
||||
(line (pt 0 0)(pt 384 0)(line_width 1))
|
||||
(line (pt 384 0)(pt 384 2143)(line_width 1))
|
||||
(line (pt 0 2143)(pt 384 2143)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 2143)(line_width 1))
|
||||
)
|
||||
)
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
component EMIF_Qsys_emif_ddr4a_0 is
|
||||
port (
|
||||
s0_axi4_clock_in : in std_logic := 'X'; -- clk
|
||||
core_init_n : in std_logic := 'X'; -- reset_n
|
||||
s0_axi4_reset_n : out std_logic; -- reset_n
|
||||
s0_axi4_awaddr : in std_logic_vector(29 downto 0) := (others => 'X'); -- awaddr
|
||||
s0_axi4_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst
|
||||
s0_axi4_awid : in std_logic_vector(6 downto 0) := (others => 'X'); -- awid
|
||||
s0_axi4_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- awlen
|
||||
s0_axi4_awlock : in std_logic := 'X'; -- awlock
|
||||
s0_axi4_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- awqos
|
||||
s0_axi4_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize
|
||||
s0_axi4_awvalid : in std_logic := 'X'; -- awvalid
|
||||
s0_axi4_awuser : in std_logic_vector(13 downto 0) := (others => 'X'); -- awuser
|
||||
s0_axi4_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
|
||||
s0_axi4_awready : out std_logic; -- awready
|
||||
s0_axi4_araddr : in std_logic_vector(29 downto 0) := (others => 'X'); -- araddr
|
||||
s0_axi4_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst
|
||||
s0_axi4_arid : in std_logic_vector(6 downto 0) := (others => 'X'); -- arid
|
||||
s0_axi4_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- arlen
|
||||
s0_axi4_arlock : in std_logic := 'X'; -- arlock
|
||||
s0_axi4_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- arqos
|
||||
s0_axi4_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize
|
||||
s0_axi4_arvalid : in std_logic := 'X'; -- arvalid
|
||||
s0_axi4_aruser : in std_logic_vector(13 downto 0) := (others => 'X'); -- aruser
|
||||
s0_axi4_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
|
||||
s0_axi4_arready : out std_logic; -- arready
|
||||
s0_axi4_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- wdata
|
||||
s0_axi4_wstrb : in std_logic_vector(31 downto 0) := (others => 'X'); -- wstrb
|
||||
s0_axi4_wlast : in std_logic := 'X'; -- wlast
|
||||
s0_axi4_wvalid : in std_logic := 'X'; -- wvalid
|
||||
s0_axi4_wready : out std_logic; -- wready
|
||||
s0_axi4_bready : in std_logic := 'X'; -- bready
|
||||
s0_axi4_bid : out std_logic_vector(6 downto 0); -- bid
|
||||
s0_axi4_bresp : out std_logic_vector(1 downto 0); -- bresp
|
||||
s0_axi4_bvalid : out std_logic; -- bvalid
|
||||
s0_axi4_rready : in std_logic := 'X'; -- rready
|
||||
s0_axi4_rdata : out std_logic_vector(255 downto 0); -- rdata
|
||||
s0_axi4_rid : out std_logic_vector(6 downto 0); -- rid
|
||||
s0_axi4_rlast : out std_logic; -- rlast
|
||||
s0_axi4_rresp : out std_logic_vector(1 downto 0); -- rresp
|
||||
s0_axi4_rvalid : out std_logic; -- rvalid
|
||||
s0_axi4lite_clock : in std_logic := 'X'; -- clk
|
||||
s0_axi4lite_reset_n : in std_logic := 'X'; -- reset_n
|
||||
s0_axi4lite_awaddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- awaddr
|
||||
s0_axi4lite_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
|
||||
s0_axi4lite_awvalid : in std_logic := 'X'; -- awvalid
|
||||
s0_axi4lite_awready : out std_logic; -- awready
|
||||
s0_axi4lite_araddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- araddr
|
||||
s0_axi4lite_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
|
||||
s0_axi4lite_arvalid : in std_logic := 'X'; -- arvalid
|
||||
s0_axi4lite_arready : out std_logic; -- arready
|
||||
s0_axi4lite_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata
|
||||
s0_axi4lite_wstrb : in std_logic_vector(3 downto 0) := (others => 'X'); -- wstrb
|
||||
s0_axi4lite_wvalid : in std_logic := 'X'; -- wvalid
|
||||
s0_axi4lite_wready : out std_logic; -- wready
|
||||
s0_axi4lite_bready : in std_logic := 'X'; -- bready
|
||||
s0_axi4lite_bresp : out std_logic_vector(1 downto 0); -- bresp
|
||||
s0_axi4lite_bvalid : out std_logic; -- bvalid
|
||||
s0_axi4lite_rready : in std_logic := 'X'; -- rready
|
||||
s0_axi4lite_rdata : out std_logic_vector(31 downto 0); -- rdata
|
||||
s0_axi4lite_rresp : out std_logic_vector(1 downto 0); -- rresp
|
||||
s0_axi4lite_rvalid : out std_logic; -- rvalid
|
||||
mem_0_cs : out std_logic_vector(0 downto 0); -- mem_cs
|
||||
mem_0_ca : out std_logic_vector(5 downto 0); -- mem_ca
|
||||
mem_0_cke : out std_logic_vector(0 downto 0); -- mem_cke
|
||||
mem_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
|
||||
mem_0_dqs_t : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_t
|
||||
mem_0_dqs_c : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_c
|
||||
mem_0_dmi : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dmi
|
||||
mem_0_ck_t : out std_logic_vector(0 downto 0); -- mem_ck_t
|
||||
mem_0_ck_c : out std_logic_vector(0 downto 0); -- mem_ck_c
|
||||
mem_0_reset_n : out std_logic; -- mem_reset_n
|
||||
oct_rzqin_0 : in std_logic := 'X'; -- oct_rzqin
|
||||
ref_clk : in std_logic := 'X' -- clk
|
||||
);
|
||||
end component EMIF_Qsys_emif_ddr4a_0;
|
||||
|
||||
+188
@@ -0,0 +1,188 @@
|
||||
# system info EMIF_Qsys_emif_ddr4a_0 on 2026.04.08.11:54:31
|
||||
system_info:
|
||||
name,value
|
||||
DEVICE,A5EB013BB23BE4SCS
|
||||
DEVICE_FAMILY,Agilex 5
|
||||
GENERATION_ID,0
|
||||
#
|
||||
#
|
||||
# Files generated for EMIF_Qsys_emif_ddr4a_0 on 2026.04.08.11:54:31
|
||||
files:
|
||||
filepath,kind,attributes,module,is_top
|
||||
sim/EMIF_Qsys_emif_ddr4a_0.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,EMIF_Qsys_emif_ddr4a_0,true
|
||||
emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_arch_top.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/altera_std_synchronizer_nocut.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh,SYSTEM_VERILOG_INCLUDE,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/emif_io96b_lib.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/emif_io96b_clk_div.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_jedec_params.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pin_locations.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_byte.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_byte_ctrl.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_cpa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_c2p_hmc.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_p2c_hmc.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_c2p_lane.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_p2c_lane.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_noc.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_hmc_wide.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_hmc_slim.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pll.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_bufs_mem.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_mc_wide_seq_pt_sim.hex,HEX,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_mc_wide_seq_pt_sim.txt,OTHER,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_bufs_mem.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_byte.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_byte_ctrl.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_cpa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_noc.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_hmc_wide.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_hmc_slim.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_pa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_pll.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_reftree.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_hmc.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_lane.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_fbr_axi_adapter_wide.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_fbr_axi_adapter_slim.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_io96b_top.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
|
||||
emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby,false
|
||||
emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_fa_c2p_ssm.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_fa_p2c_ssm.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_iossm.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_seq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/iossm_cal_boot.hex,HEX,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/iossm_cal.hex,HEX,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_arbitrator.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_top.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_iossm.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_seq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_fa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_comp.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/cal_io96b_interface.svh,SYSTEM_VERILOG_INCLUDE,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/altera_emif_cal_gearbox.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/altera_emif_cal_gearbox_bidir.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_translator_1931_d46vvwa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_reset_controller.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_avalon_st_bytes_to_packets.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_avalon_packets_to_master.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_master_ni_1962_2kryw2a.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_merlin_reorder_memory.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_7ekoqry.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_1921_bk6lvda.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_channel_adapter_1921_fkajlia.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_jy53pgi.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_ctb2miq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_7b7u3ni.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_252f2xa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/rd_pri_mux_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/rd_comp_sel_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_channel_adapter_1921_5wnzrci.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_avalon_st_pipeline_stage_1930_bv2ucky.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_avalon_st_packets_to_bytes.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/wr_sipo_plus_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/wr_response_mem_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/wr_comp_sel_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/rd_response_mem_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/wr_sipo_plus_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/wr_comp_sel_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/rd_sipo_plus_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/rd_sipo_plus_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_vnonqiy.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_alj3kza.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_ysgnmwa.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/compare_eq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/wr_response_mem_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/rd_response_mem_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/rd_pri_mux_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/rd_comp_sel_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_o34766q.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_1971_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_1971_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/wr_pri_mux_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/wr_pri_mux_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_h6wexfa.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_cgpn6xq.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_avalon_sc_fifo_1931_fzgstwy.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_width_adapter_1933_2qdsena.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_master_agent_1921_2inlndi.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_rcor4va.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_ekcygpi.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_c2mlp5i.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_width_adapter_1933_sqfzewq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1931_glj62si.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_adapter_uncmpr.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_adapter_new.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_burst_adapter_1931_hbsisni.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_wrap_burst_converter.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_adapter_13_1.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_incr_burst_converter.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_default_burst_converter.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_timing_adapter_1940_5ju4ddy.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/intel_axi4lite_injector_dcfifo_s.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/intel_axi4lite_injector_util.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/intel_axi4lite_injector_ph2.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_intel_axi4lite_injector_100_2yowc3a.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_hs_clk_xer_1940_hvja46q.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_hs_clk_xer_1940_4s7hdhy.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_mm_interconnect_1920_jmzr6ly.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_mm_interconnect_1920_5sovoyi.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_master_translator_192_lykd4la.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_std_synchronizer_nocut.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_reset_synchronizer.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/altera_avalon_st_clock_crosser.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_vbaxzva.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_nxsnrbi.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_irryw4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_wqohhgi.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_4ytgf2y.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_2jqun3q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
|
||||
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa,false
|
||||
alt_mem_if_jtag_master_191/sim/EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.v,VERILOG,,altera_avalon_st_jtag_interface,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_jtag_dc_streaming.v,VERILOG,,altera_avalon_st_jtag_interface,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_jtag_sld_node.v,VERILOG,,altera_avalon_st_jtag_interface,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_jtag_streaming.v,VERILOG,,altera_avalon_st_jtag_interface,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_avalon_st_clock_crosser.v,VERILOG,,altera_avalon_st_jtag_interface,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_reset_synchronizer.v,VERILOG,,altera_avalon_st_jtag_interface,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_std_synchronizer_nocut.v,VERILOG,,altera_avalon_st_jtag_interface,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_base.v,VERILOG,,altera_avalon_st_jtag_interface,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_remover.v,VERILOG,,altera_avalon_st_jtag_interface,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_inserter.v,VERILOG,,altera_avalon_st_jtag_interface,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_stage.sv,SYSTEM_VERILOG,,altera_avalon_st_jtag_interface,false
|
||||
altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.sdc,SDC_ENTITY,NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION,altera_avalon_st_jtag_interface,false
|
||||
timing_adapter_1950/sim/EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq,false
|
||||
altera_avalon_sc_fifo_1932/sim/EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq.v,VERILOG,,EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq,false
|
||||
altera_avalon_st_bytes_to_packets_1922/sim/altera_avalon_st_bytes_to_packets.v,VERILOG,,altera_avalon_st_bytes_to_packets,false
|
||||
altera_avalon_st_packets_to_bytes_1922/sim/altera_avalon_st_packets_to_bytes.v,VERILOG,,altera_avalon_st_packets_to_bytes,false
|
||||
altera_avalon_packets_to_master_1922/sim/altera_avalon_packets_to_master.v,VERILOG,,altera_avalon_packets_to_master,false
|
||||
channel_adapter_1922/sim/EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy,false
|
||||
channel_adapter_1922/sim/EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a,false
|
||||
altera_reset_controller_1924/sim/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
|
||||
altera_reset_controller_1924/sim/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
|
||||
altera_reset_controller_1924/sim/altera_reset_controller.sdc,SDC_ENTITY,NO_SDC_PROMOTION,altera_reset_controller,false
|
||||
#
|
||||
# Map from instance-path to kind of module
|
||||
instances:
|
||||
instancePath,module
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb,EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.jtag_phy_embedded_in_jtag_master,altera_avalon_st_jtag_interface
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.timing_adt,EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.fifo,EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.b2p,altera_avalon_st_bytes_to_packets
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.p2b,altera_avalon_st_packets_to_bytes
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.transacto,altera_avalon_packets_to_master
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.b2p_adapter,EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.p2b_adapter,EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a
|
||||
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.rst_controller,altera_reset_controller
|
||||
|
+857
@@ -0,0 +1,857 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for EMIF_Qsys_emif_ddr4a_0</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">EMIF_Qsys_emif_ddr4a_0</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.04.08.11:54:34</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
<td class="mastermodule" colspan="1">
|
||||
<a href="#module_EMIF_Qsys_emif_ddr4a_0_cal_0"><b>EMIF_Qsys_emif_ddr4a_0_cal_0</b>
|
||||
</a>
|
||||
</td>
|
||||
<td class="mastermodule" colspan="1">
|
||||
<a href="#module_EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0"><b>EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0</b>
|
||||
</a>
|
||||
</td>
|
||||
<td class="mastermodule" colspan="1">
|
||||
<a href="#module_EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0_jamb"><b>EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0_jamb</b>
|
||||
</a>
|
||||
</td>
|
||||
<td class="mastermodule" colspan="1">
|
||||
<a href="#module_EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0_jamb_jamb"><b>EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0_jamb_jamb</b>
|
||||
</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="masterlr"> m0_axi4lite</td>
|
||||
<td class="masterlr"> m0_axi4lite</td>
|
||||
<td class="masterlr"> master</td>
|
||||
<td class="masterlr"> master</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_EMIF_Qsys_emif_ddr4a_0"><b>EMIF_Qsys_emif_ddr4a_0</b>
|
||||
</a>
|
||||
</td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">s0_axi4 </td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">s0_axi4lite </td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_EMIF_Qsys_emif_ddr4a_0_cal_0"><b>EMIF_Qsys_emif_ddr4a_0_cal_0</b>
|
||||
</a>
|
||||
</td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">s0_axi4lite </td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">s0_noc_axi4lite </td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">s0_noc_axi4litenoc </td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0"><b>EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0</b>
|
||||
</a>
|
||||
</td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">s0_axi4lite </td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">s0_noc_axi4lite </td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">s0_noc_axi4litenoc </td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_EMIF_Qsys_emif_ddr4a_0"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>EMIF_Qsys_emif_ddr4a_0</h2>emif_io96b_lpddr4 v4.2.0
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">MEM_NUM_CHANNELS</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_CHANNEL_DATA_DQ_WIDTH</td>
|
||||
<td class="parametervalue">32</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_DIE_DENSITY_GBITS</td>
|
||||
<td class="parametervalue">4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_CHANNEL_CS_WIDTH</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_OPERATING_FREQ_MHZ_AUTOSET_EN</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_OPERATING_FREQ_MHZ</td>
|
||||
<td class="parametervalue">1066.667</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CTRL_ECC_INLINE_EN</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CTRL_DM_EN</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CTRL_WR_DBI_EN</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CTRL_RD_DBI_EN</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CTRL_PERFORMANCE_PROFILE</td>
|
||||
<td class="parametervalue">SEQ</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CTRL_AUTO_PRECHARGE_EN</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">DIAG_HMC_ADDR_SWAP_EN</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CTRL_PLACEMENT_EN</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CTRL_ALL_STRB_EN</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CTRL_FIXED_PRIORITY_EN</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">TURNAROUND_R2W_SAMECS_CYC</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">TURNAROUND_R2R_SAMECS_CYC</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">TURNAROUND_W2W_SAMECS_CYC</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">TURNAROUND_W2R_SAMECS_CYC</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_REFCLK_FREQ_MHZ_AUTOSET_EN</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_REFCLK_ADVANCED_SELECT_EN</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_REFCLK_FREQ_MHZ</td>
|
||||
<td class="parametervalue">166.6667</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_AC_PLACEMENT</td>
|
||||
<td class="parametervalue">BOT</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_MAINBAND_ACCESS_MODE</td>
|
||||
<td class="parametervalue">ASYNC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_SIDEBAND_ACCESS_MODE</td>
|
||||
<td class="parametervalue">FABRIC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_SWIZZLE_MAP</td>
|
||||
<td class="parametervalue">PIN_SWIZZLE_CH0_DQS0=0,1,6,7,2,4,5,3;PIN_SWIZZLE_CH0_DQS1=15,14,8,9,13,12,10,11;PIN_SWIZZLE_CH0_DQS2=18,17,21,19,20,16,22,23;PIN_SWIZZLE_CH0_DQS3=26,28,27,29,25,24,31,30;</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">DEBUG_TOOLS_EN</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">INSTANCE_ID</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">ADV_CAL_ENABLE_MARGIN</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_CL_CYC</td>
|
||||
<td class="parametervalue">22</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_CWL_CYC</td>
|
||||
<td class="parametervalue">18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_RD_POSTAMBLE_CYC</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_WR_POSTAMBLE_CYC</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TSR_NS</td>
|
||||
<td class="parametervalue">15.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TRFCAB_NS</td>
|
||||
<td class="parametervalue">180.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TRFCPB_NS</td>
|
||||
<td class="parametervalue">90.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TXSR_NS</td>
|
||||
<td class="parametervalue">187.5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TXP_NS</td>
|
||||
<td class="parametervalue">7.5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TCCD_NS</td>
|
||||
<td class="parametervalue">16.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TRTP_NS</td>
|
||||
<td class="parametervalue">7.5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TRCD_NS</td>
|
||||
<td class="parametervalue">18.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TRPPB_NS</td>
|
||||
<td class="parametervalue">18.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TRPAB_NS</td>
|
||||
<td class="parametervalue">21.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TRAS_NS</td>
|
||||
<td class="parametervalue">42.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TWR_NS</td>
|
||||
<td class="parametervalue">18.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TWTR_NS</td>
|
||||
<td class="parametervalue">10.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TRRD_NS</td>
|
||||
<td class="parametervalue">10.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TPPD_CYC</td>
|
||||
<td class="parametervalue">4.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TFAW_NS</td>
|
||||
<td class="parametervalue">40.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TRC_NS</td>
|
||||
<td class="parametervalue">63.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TREFW_NS</td>
|
||||
<td class="parametervalue">3.2E7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_MINNUMREFSREQ</td>
|
||||
<td class="parametervalue">8192.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TREFI_NS</td>
|
||||
<td class="parametervalue">3904.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TCKE_NS</td>
|
||||
<td class="parametervalue">7.5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TCMDCKE_NS</td>
|
||||
<td class="parametervalue">2.81</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TCKELCK_NS</td>
|
||||
<td class="parametervalue">5.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TCSCKE_NS</td>
|
||||
<td class="parametervalue">1.75</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TCKCKEH_NS</td>
|
||||
<td class="parametervalue">2.81</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TCSCKEH_NS</td>
|
||||
<td class="parametervalue">1.75</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TMRWCKEL_NS</td>
|
||||
<td class="parametervalue">14.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TZQCKE_NS</td>
|
||||
<td class="parametervalue">2.81</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TMRR_NS</td>
|
||||
<td class="parametervalue">7.5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TMRW_NS</td>
|
||||
<td class="parametervalue">10.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TMRD_NS</td>
|
||||
<td class="parametervalue">14.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TESCKE_NS</td>
|
||||
<td class="parametervalue">2.81</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TZQCAL_NS</td>
|
||||
<td class="parametervalue">1000.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TZQLAT_NS</td>
|
||||
<td class="parametervalue">30.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TDQSCK_MAX_NS</td>
|
||||
<td class="parametervalue">3.5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TDQSCK_MIN_NS</td>
|
||||
<td class="parametervalue">1.5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TCKCKEL_NS</td>
|
||||
<td class="parametervalue">5.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TCKELCMD_NS</td>
|
||||
<td class="parametervalue">5.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_TCKEHCMD_NS</td>
|
||||
<td class="parametervalue">7.5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">JEDEC_OVERRIDE_TABLE_PARAM_NAME</td>
|
||||
<td class="parametervalue">MEM_TRFCPB_NS,MEM_TCCD_NS,MEM_TCMDCKE_NS,MEM_TCKCKEH_NS,MEM_TZQCKE_NS,MEM_TESCKE_NS,MEM_RD_POSTAMBLE_CYC,MEM_WR_POSTAMBLE_CYC,MEM_TRFCAB_NS</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EX_DESIGN_HDL_FORMAT</td>
|
||||
<td class="parametervalue">VERILOG</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EX_DESIGN_GEN_SYNTH</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EX_DESIGN_GEN_SIM</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EX_DESIGN_TG_CSR_ACCESS_MODE</td>
|
||||
<td class="parametervalue">JTAG</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EX_DESIGN_TG_PROGRAM</td>
|
||||
<td class="parametervalue">MEDIUM</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EX_DESIGN_TG_WIDE_IF</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ</td>
|
||||
<td class="parametervalue">275.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ</td>
|
||||
<td class="parametervalue">100.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EX_DESIGN_PMON_CH0_EN</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_TERM_X_R_S_AC_OUTPUT_OHM</td>
|
||||
<td class="parametervalue">SERIES_40_OHM_CAL</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_TERM_X_R_S_CK_OUTPUT_OHM</td>
|
||||
<td class="parametervalue">SERIES_40_OHM_CAL</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_TERM_X_R_S_DQ_OUTPUT_OHM</td>
|
||||
<td class="parametervalue">SERIES_40_OHM_CAL</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_TERM_X_DQ_SLEW_RATE</td>
|
||||
<td class="parametervalue">FASTEST</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_TERM_X_AC_SLEW_RATE</td>
|
||||
<td class="parametervalue">FASTEST</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_TERM_X_CK_SLEW_RATE</td>
|
||||
<td class="parametervalue">FASTEST</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_TERM_X_R_T_DQ_INPUT_OHM</td>
|
||||
<td class="parametervalue">RT_50_OHM_CAL</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_TERM_X_DQ_VREF</td>
|
||||
<td class="parametervalue">17.5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_TERM_X_R_T_REFCLK_INPUT_OHM</td>
|
||||
<td class="parametervalue">RT_DIFF</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_AC_TX_EQUALIZATION</td>
|
||||
<td class="parametervalue">OFF</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_CK_TX_EQUALIZATION</td>
|
||||
<td class="parametervalue">OFF</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PHY_DQ_TX_EQUALIZATION</td>
|
||||
<td class="parametervalue">OFF</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_ODT_DQ_X_TGT_WR</td>
|
||||
<td class="parametervalue">5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_ODT_DQ_X_IDLE</td>
|
||||
<td class="parametervalue">off</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_ODT_DQ_X_RON</td>
|
||||
<td class="parametervalue">6</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_VREF_DQ_X_RANGE</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_VREF_DQ_X_VALUE</td>
|
||||
<td class="parametervalue">18.0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_ODT_CA_X_CA_COMM</td>
|
||||
<td class="parametervalue">3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_ODT_CA_X_CA_ENABLE</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_ODT_CA_X_CS_ENABLE</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_ODT_CA_X_CK_ENABLE</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_VREF_CA_X_CA_RANGE</td>
|
||||
<td class="parametervalue">2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MEM_VREF_CA_X_CA_VALUE</td>
|
||||
<td class="parametervalue">27.2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">ANALOG_PARAM_DERIVATION_PARAM_NAME</td>
|
||||
<td class="parametervalue"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_EMIF_Qsys_emif_ddr4a_0_cal_0"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>EMIF_Qsys_emif_ddr4a_0_cal_0</h2>emif_io96b_lpddr4_emif_io96b_cal v4.2.0
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">INSTANCE_ID</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">NUM_CALBUS_PERIPHS</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">NUM_CALBUS_PLLS</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PORT_S_AXIL_MODE</td>
|
||||
<td class="parametervalue">FABRIC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0</h2>emif_io96b_cal v2.3.2
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">INSTANCE_ID</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">NUM_CALBUS_PERIPHS</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">NUM_CALBUS_PLLS</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PORT_S_AXIL_MODE</td>
|
||||
<td class="parametervalue">FABRIC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0_jamb"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0_jamb</h2>emif_io96b_cal_alt_mem_if_jtag_master v2.3.2
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">USE_PLI</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PLI_PORT</td>
|
||||
<td class="parametervalue">50000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">FAST_VER</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">FIFO_DEPTHS</td>
|
||||
<td class="parametervalue">2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0_jamb_jamb"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>EMIF_Qsys_emif_ddr4a_0_cal_0_cal_0_jamb_jamb</h2>alt_mem_if_jtag_master v19.1
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">USE_PLI</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PLI_PORT</td>
|
||||
<td class="parametervalue">50000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">FAST_VER</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">FIFO_DEPTHS</td>
|
||||
<td class="parametervalue">2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.01 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
+3829
File diff suppressed because it is too large
Load Diff
+3829
File diff suppressed because it is too large
Load Diff
+635
@@ -0,0 +1,635 @@
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_TOOL_VENDOR_NAME "Altera Corporation"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_TOP_LEVEL_COMPONENT_NAME "emif_io96b_lpddr4"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name PRE_COMPILED_MODULE "ON"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name OCS_IP_FILE [file join $::quartus(qip_path) "../EMIF_Qsys_emif_ddr4a_0.ip"]
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name OCS_IP_TYPE "emif_io96b_lpddr4"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name OCS_IP_VERSION "4.2.0"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name OCS_IP_HASH "ddgvvei"
|
||||
set_global_assignment -library "EMIF_Qsys_emif_ddr4a_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "EMIF_Qsys_emif_ddr4a_0.sopcinfo"]
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name SLD_INFO "QSYS_NAME EMIF_Qsys_emif_ddr4a_0 HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "EMIF_Qsys_emif_ddr4a_0" -name MISC_FILE [file join $::quartus(qip_path) "EMIF_Qsys_emif_ddr4a_0.cmp"]
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_TARGETED_PART_TRAIT "part.DEVICE_TEMPERATURE_GRADE::EXTENDED"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_TARGETED_PART_TRAIT "part.DEVICE_POWER_MODEL::STANDARD_POWER_FIXED"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_TARGETED_PART_TRAIT "part.SUPPORTS_VID::0"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_TARGETED_PART_TRAIT "part.DEVICE_IOBANK_REVISION::IO96B_REVB1"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_TARGETED_PART_TRAIT "BASE_DEVICE::SM4REVB"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "EMIF_Qsys_emif_ddr4a_0" -name MISC_FILE [file join $::quartus(qip_path) "../EMIF_Qsys_emif_ddr4a_0.ip"]
|
||||
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9qdGFnX2ludGVyZmFjZQ=="
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEpUQUcgSW50ZXJmYWNl"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name IP_COMPONENT_INTERNAL "On"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name IP_COMPONENT_VERSION "MTkuMQ=="
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name IP_COMPONENT_GROUP "SW50ZXJmYWNlIFByb3RvY29scy9TZXJpYWw="
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvaGIvbmlvczIvcXRzX3FpaTU1MDA4LnBkZg=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMF90aW1pbmdfYWRhcHRlcl8xOTUwX2JianQ2a3E="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIFN0cmVhbWluZyBUaW1pbmcgQWRhcHRlciBJUA=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_COMPONENT_VERSION "MTkuNS4w"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_COMPONENT_DESCRIPTION "VXNlZCB0byBjb25uZWN0IEF2YWxvbiBTdHJlYW1pbmcgU291cmNlIGFuZCBTaW5rIHdoaWNoIGhhdmUgbWlzbWF0Y2ggaW4gcmVhZHkgbGF0ZW5jeSBwcm9wZXJ0eQ=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0JyaWRnZXMgYW5kIEFkYXB0b3JzL0F2YWxvbiBTdHJlYW1pbmc="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL213aDE0MDk5NjAxODE2NDEvbXdoMTQwOTk1ODgyODczMg=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MjE2OTgwNDIwODcvaGNvMTQyMTY5ODAxMzQwOA=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMF9hbHRlcmFfYXZhbG9uX3NjX2ZpZm9fMTkzMl9vbnBjb3Vx"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIFN0cmVhbWluZyBTaW5nbGUgQ2xvY2sgRklGTyBJUA=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_VERSION "MTkuMy4y"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_DESCRIPTION "U2luZ2xlIENsb2NrIEZJRk8gd2l0aCBBdmFsb24gU3RyZWFtaW5nIEludGVyZmFjZXM="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL09uIENoaXAgTWVtb3J5"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL3NmbzE0MDA3ODc5NTI5MzIvaWdhMTQwMTM5NTU2Mzc3OQ=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MjE2OTgwNDIwODcvaGNvMTQyMTY5NzY4OTMwMA=="
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9ieXRlc190b19wYWNrZXRz"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEJ5dGVzIHRvIFBhY2tldHMgQ29udmVydGVyIElQ"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_COMPONENT_VERSION "MTkuMi4y"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uLVNUIEJ5dGVzIHRvIFBhY2tldHMgQ29udmVydGVy"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0JyaWRnZXMgYW5kIEFkYXB0b3JzL1N0cmVhbWluZw=="
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvaGIvbmlvczIvcXRzX3FpaTU1MDEyLnBkZg=="
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3N0LWJ5dGVzLXRvLXBhY2tldHMtYW5kLXBhY2tldHMtdG8tYnl0ZXMtMzAxNzkuaHRtbA=="
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3N0LWJ5dGVzLXRvLXBhY2tldHMtYW5kLXBhY2tldHMtdG8tYnl0ZXMtMzI1ODIuaHRtbA=="
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9wYWNrZXRzX3RvX2J5dGVz"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIFBhY2tldHMgdG8gQnl0ZXMgQ29udmVydGVyIElQ"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_COMPONENT_VERSION "MTkuMi4y"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_COMPONENT_DESCRIPTION "VGhlIEF2YWxvbsKuIC1TVCBQYWNrZXRzIHRvIEJ5dGVzIENvbnZlcnRlciBjb3JlIHJlY2VpdmVzIHBhY2tldGl6ZWQgZGF0YSBhbmQgdHJhbnNmb3JtcyB0aGUgcGFja2V0cyB0byBieXRlc3RyZWFtcy4="
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0JyaWRnZXMgYW5kIEFkYXB0b3JzL1N0cmVhbWluZw=="
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvaGIvbmlvczIvcXRzX3FpaTU1MDEyLnBkZg=="
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3N0LWJ5dGVzLXRvLXBhY2tldHMtYW5kLXBhY2tldHMtdG8tYnl0ZXMtMzAxNzkuaHRtbA=="
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3N0LWJ5dGVzLXRvLXBhY2tldHMtYW5kLXBhY2tldHMtdG8tYnl0ZXMtMzI1ODIuaHRtbA=="
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9wYWNrZXRzX3RvX21hc3Rlcg=="
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIFBhY2tldHMgdG8gVHJhbnNhY3Rpb24gQ29udmVydGVyIElQ"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_COMPONENT_VERSION "MTkuMi4y"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uIFBhY2tldHMgdG8gVHJhbnNhY3Rpb24gQ29udmVydGVy"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0JyaWRnZXMgYW5kIEFkYXB0b3JzL1N0cmVhbWluZw=="
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvaGIvbmlvczIvcXRzX3FpaTU1MDEzLnBkZg=="
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3BhY2tldHMtdG8tdHJhbnNhY3Rpb25zLWNvbnZlcnRlci1jb3JlLTYxOTg4Lmh0bWw="
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3BhY2tldHMtdG8tdHJhbnNhY3Rpb25zLWNvbnZlcnRlci1jb3JlLTYzOTUzLmh0bWw="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMF9jaGFubmVsX2FkYXB0ZXJfMTkyMl9yZDU2dWZ5"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIFN0cmVhbWluZyBDaGFubmVsIEFkYXB0ZXIgSVA="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_COMPONENT_VERSION "MTkuMi4y"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_COMPONENT_DESCRIPTION "VXNlZCB0byBjb25uZWN0IEF2YWxvbiBTdHJlYW1pbmcgU291cmNlIGFuZCBTaW5rIHRoYXQgaGF2ZSBtaXNtYXRjaGVzIGluIENoYW5uZWwgc2lnbmFsIHByb3BlcnRpZXM="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0JyaWRnZXMgYW5kIEFkYXB0b3JzL0F2YWxvbiBTdHJlYW1pbmc="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL213aDE0MDk5NjAxODE2NDEvbXdoMTQwOTk1ODgyODczMg=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MjE2OTgwNDIwODcvaGNvMTQyMTY5ODAxMzQwOA=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMF9jaGFubmVsX2FkYXB0ZXJfMTkyMl81dnAzZDVh"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIFN0cmVhbWluZyBDaGFubmVsIEFkYXB0ZXIgSVA="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_COMPONENT_VERSION "MTkuMi4y"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_COMPONENT_DESCRIPTION "VXNlZCB0byBjb25uZWN0IEF2YWxvbiBTdHJlYW1pbmcgU291cmNlIGFuZCBTaW5rIHRoYXQgaGF2ZSBtaXNtYXRjaGVzIGluIENoYW5uZWwgc2lnbmFsIHByb3BlcnRpZXM="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0JyaWRnZXMgYW5kIEFkYXB0b3JzL0F2YWxvbiBTdHJlYW1pbmc="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL213aDE0MDk5NjAxODE2NDEvbXdoMTQwOTk1ODgyODczMg=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MjE2OTgwNDIwODcvaGNvMTQyMTY5ODAxMzQwOA=="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_NAME "YWx0ZXJhX3Jlc2V0X2NvbnRyb2xsZXI="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_DISPLAY_NAME "TWVybGluIFJlc2V0IENvbnRyb2xsZXIgSVA="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_VERSION "MTkuMi40"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_DESCRIPTION "Rm9yIHN5c3RlbXMgd2l0aCBtdWx0aXBsZSByZXNldCBpbnB1dHMsIHRoZSBNZXJsaW4gUmVzZXQgQ29udHJvbGxlciBPUnMgYWxsIHJlc2V0IGlucHV0cyBhbmQgZ2VuZXJhdGVzIGEgc2luZ2xlIHJlc2V0IG91dHB1dC4="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0Nsb2NrczsgUExMcyBhbmQgUmVzZXRz"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3pjbjE1MTM5ODcyODI5MzUuaHRtbCNtd2gxNDA5OTU4ODI4NzMy"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi" -library "alt_mem_if_jtag_master_191" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMF9hbHRfbWVtX2lmX2p0YWdfbWFzdGVyXzE5MV8yeGJmcmJp"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi" -library "alt_mem_if_jtag_master_191" -name IP_COMPONENT_DISPLAY_NAME "YWx0X21lbV9pZiBKVEFHIHRvIEF2YWxvbiBNYXN0ZXIgQnJpZGdl"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi" -library "alt_mem_if_jtag_master_191" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi" -library "alt_mem_if_jtag_master_191" -name IP_COMPONENT_INTERNAL "On"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi" -library "alt_mem_if_jtag_master_191" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi" -library "alt_mem_if_jtag_master_191" -name IP_COMPONENT_VERSION "MTkuMQ=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi" -library "alt_mem_if_jtag_master_191" -name IP_COMPONENT_GROUP "QnJpZGdlcyBhbmQgQWRhcHRlcnMvTWVtb3J5IE1hcHBlZA=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi" -library "alt_mem_if_jtag_master_191" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvaGIvbmlvczIvcXRzX3FpaTU1MDExLnBkZg=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa" -library "emif_io96b_cal_232" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMF9lbWlmX2lvOTZiX2NhbF9hbHRfbWVtX2lmX2p0YWdfbWFzdGVyXzIzMl9jaDY1cHNh"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa" -library "emif_io96b_cal_232" -name IP_COMPONENT_DISPLAY_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMF9lbWlmX2lvOTZiX2NhbF9hbHRfbWVtX2lmX2p0YWdfbWFzdGVyXzIzMl9jaDY1cHNh"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa" -library "emif_io96b_cal_232" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa" -library "emif_io96b_cal_232" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa" -library "emif_io96b_cal_232" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa" -library "emif_io96b_cal_232" -name IP_COMPONENT_VERSION "Mi4zLjI="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMF9lbWlmX2lvOTZiX2NhbF8yMzJfbDRndXFjcQ=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_DISPLAY_NAME "RU1JRiBDYWxpYnJhdGlvbiBJUA=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_VERSION "Mi4zLjI="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIEV4dGVybmFsIE1lbW9yeSBJbnRlcmZhY2UgQ2FsaWJyYXRpb24gQ29tcG9uZW50"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_GROUP "TWVtb3J5IEludGVyZmFjZXMgYW5kIENvbnRyb2xsZXJz"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzc3MjUzOC5odG1s"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzc3MjYzNS5odG1s"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzgxNzQ2Ny5odG1s"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzgxNzM5Ni5odG1s"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMF9lbWlmX2lvOTZiX2xwZGRyNF9lbWlmX2lvOTZiX2NhbF80MjBfeW00MnRieQ=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_DISPLAY_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMF9lbWlmX2lvOTZiX2xwZGRyNF9lbWlmX2lvOTZiX2NhbF80MjBfeW00MnRieQ=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_VERSION "NC4yLjA="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMF9lbWlmX2lvOTZiX2xwZGRyNF80MjBfZGRndnZlaQ=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_DISPLAY_NAME "TFBERFI0IEV4dGVybmFsIE1lbW9yeSBJbnRlcmZhY2VzIChFTUlGKSBJUA=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_VERSION "NC4yLjA="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIEV4dGVybmFsIE1lbW9yeSBJbnRlcmZhY2VzIElQIGZvciBMUEREUjQgRFJBTXM="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_GROUP "TWVtb3J5IEludGVyZmFjZXMgYW5kIENvbnRyb2xsZXJz"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzgxNzQ2Ny5odG1s"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzgxNzM5NC5odG1s"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzgxNzM5Ni5odG1s"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzg0NzQ1OC5odG1s"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzg0ODA3OS5odG1s"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2VtaWZfZGRyNGFfMA=="
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0" -library "EMIF_Qsys_emif_ddr4a_0" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_cs"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_cs"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_cs"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_ca[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_ca[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_ca[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_ca[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_ca[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_ca[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_ca[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_ca[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_ca[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_ca[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_ca[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_ca[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_ca[4]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_ca[4]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_ca[4]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_ca[5]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_ca[5]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_ca[5]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_cke"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_cke"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_cke"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[4]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[4]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[4]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[4]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[4]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[5]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[5]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[5]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[5]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[5]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[6]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[6]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[6]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[6]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[6]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[7]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[7]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[7]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[7]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[7]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[8]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[8]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[8]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[8]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[8]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[9]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[9]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[9]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[9]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[9]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[10]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[10]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[10]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[10]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[10]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[11]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[11]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[11]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[11]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[11]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[12]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[12]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[12]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[12]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[12]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[13]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[13]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[13]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[13]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[13]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[14]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[14]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[14]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[14]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[14]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[15]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[15]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[15]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[15]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[15]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[16]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[16]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[16]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[16]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[16]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[17]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[17]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[17]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[17]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[17]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[18]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[18]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[18]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[18]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[18]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[19]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[19]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[19]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[19]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[19]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[20]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[20]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[20]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[20]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[20]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[21]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[21]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[21]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[21]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[21]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[22]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[22]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[22]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[22]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[22]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[23]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[23]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[23]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[23]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[23]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[24]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[24]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[24]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[24]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[24]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[25]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[25]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[25]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[25]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[25]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[26]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[26]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[26]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[26]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[26]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[27]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[27]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[27]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[27]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[27]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[28]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[28]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[28]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[28]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[28]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[29]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[29]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[29]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[29]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[29]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[30]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[30]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[30]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[30]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[30]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dq[31]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dq[31]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[31]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dq[31]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dq[31]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "Differential 1.1-V LVSTL" -to "mem_0_dqs_t[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dqs_t[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_t[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dqs_t[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_t[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "Differential 1.1-V LVSTL" -to "mem_0_dqs_t[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dqs_t[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_t[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dqs_t[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_t[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "Differential 1.1-V LVSTL" -to "mem_0_dqs_t[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dqs_t[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_t[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dqs_t[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_t[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "Differential 1.1-V LVSTL" -to "mem_0_dqs_t[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dqs_t[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_t[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dqs_t[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_t[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "Differential 1.1-V LVSTL" -to "mem_0_dqs_c[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dqs_c[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_c[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dqs_c[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_c[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "Differential 1.1-V LVSTL" -to "mem_0_dqs_c[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dqs_c[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_c[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dqs_c[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_c[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "Differential 1.1-V LVSTL" -to "mem_0_dqs_c[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dqs_c[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_c[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dqs_c[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_c[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "Differential 1.1-V LVSTL" -to "mem_0_dqs_c[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dqs_c[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_c[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dqs_c[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dqs_c[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dmi[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dmi[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dmi[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dmi[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dmi[0]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dmi[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dmi[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dmi[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dmi[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dmi[1]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dmi[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dmi[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dmi[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dmi[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dmi[2]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_dmi[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "PARALLEL_50_OHM_WITH_CALIBRATION" -to "mem_0_dmi[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dmi[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_dmi[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_dmi[3]"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "Differential 1.1-V LVSTL" -to "mem_0_ck_t"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_ck_t"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_ck_t"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "Differential 1.1-V LVSTL" -to "mem_0_ck_c"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_ck_c"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_ck_c"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V LVSTL" -to "mem_0_reset_n"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name OUTPUT_TERMINATION "SERIES_40_OHM_WITH_CALIBRATION" -to "mem_0_reset_n"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_GROUP EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "mem_0_reset_n"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name RZQ_PIN_GROUP_NAME EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_EMIF_RZQ_GROUP_1_CH0 -to "oct_rzqin_0"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V" -to "oct_rzqin_0"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "OFF" -to "oct_rzqin_0"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_STANDARD "1.1-V True Differential Signaling" -to "ref_clk"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name INPUT_TERMINATION "DIFFERENTIAL" -to "ref_clk"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IO_RELATIVE_LOCATION_ASSIGNMENT IOPLL-A -to "*arch_0|wrapper_pll|pll"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name PLL_REFCLK_INPUT_TYPE NOT_BALANCED -to "*arch_*|wrapper_pll|pll"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name REQUIRE_PLL_INITIALIZATION_CLOCK ON -to "*arch_*|wrapper_pll|pll"
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -to "*lock_sync_inst|din_s1" -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS
|
||||
|
||||
set_global_assignment -library "altera_jtag_dc_streaming_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v"]
|
||||
set_global_assignment -library "altera_jtag_dc_streaming_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v"]
|
||||
set_global_assignment -library "altera_jtag_dc_streaming_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v"]
|
||||
set_global_assignment -library "altera_jtag_dc_streaming_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v"]
|
||||
set_global_assignment -library "altera_jtag_dc_streaming_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v"]
|
||||
set_global_assignment -library "altera_jtag_dc_streaming_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v"]
|
||||
set_global_assignment -library "altera_jtag_dc_streaming_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v"]
|
||||
set_global_assignment -library "altera_jtag_dc_streaming_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v"]
|
||||
set_global_assignment -library "altera_jtag_dc_streaming_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v"]
|
||||
set_global_assignment -library "altera_jtag_dc_streaming_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v"]
|
||||
set_global_assignment -library "altera_jtag_dc_streaming_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv"]
|
||||
set_instance_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name SDC_ENTITY_FILE [file join $::quartus(qip_path) "altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.sdc"] -no_sdc_promotion -no_auto_inst_discovery
|
||||
set_global_assignment -library "timing_adapter_1950" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "timing_adapter_1950/synth/EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq.sv"]
|
||||
set_global_assignment -library "altera_avalon_sc_fifo_1932" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_sc_fifo_1932/synth/EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq.v"]
|
||||
set_global_assignment -library "altera_avalon_st_bytes_to_packets_1922" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v"]
|
||||
set_global_assignment -library "altera_avalon_st_packets_to_bytes_1922" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v"]
|
||||
set_global_assignment -library "altera_avalon_packets_to_master_1922" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v"]
|
||||
set_global_assignment -library "channel_adapter_1922" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "channel_adapter_1922/synth/EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy.sv"]
|
||||
set_global_assignment -library "channel_adapter_1922" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "channel_adapter_1922/synth/EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a.sv"]
|
||||
set_global_assignment -library "altera_reset_controller_1924" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_reset_controller_1924/synth/altera_reset_controller.v"]
|
||||
set_global_assignment -library "altera_reset_controller_1924" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_reset_controller_1924/synth/altera_reset_synchronizer.v"]
|
||||
set_instance_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name SDC_ENTITY_FILE [file join $::quartus(qip_path) "altera_reset_controller_1924/synth/altera_reset_controller.sdc"] -no_sdc_promotion
|
||||
set_global_assignment -library "alt_mem_if_jtag_master_191" -name VERILOG_FILE [file join $::quartus(qip_path) "alt_mem_if_jtag_master_191/synth/EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name VERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_fa_c2p_ssm.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_fa_p2c_ssm.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_iossm.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_seq.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SOURCE_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/iossm_cal_boot.hex"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SOURCE_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/iossm_cal.hex"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_arbitrator.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_top.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_iossm.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_seq.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_fa.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_comp.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name MISC_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/cal_io96b_interface.svh"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/altera_emif_cal_gearbox.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/altera_emif_cal_gearbox_bidir.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_axi_translator_1931_d46vvwa.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_reset_controller.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_avalon_st_bytes_to_packets.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_avalon_packets_to_master.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_axi_master_ni_1962_2kryw2a.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_merlin_reorder_memory.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_7ekoqry.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_1921_bk6lvda.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_channel_adapter_1921_fkajlia.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_jy53pgi.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_ctb2miq.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_7b7u3ni.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_252f2xa.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_merlin_arbitrator.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/rd_pri_mux_cwyib4q.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/rd_comp_sel_kt2puei.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_channel_adapter_1921_5wnzrci.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_avalon_st_pipeline_stage_1930_bv2ucky.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_avalon_st_packets_to_bytes.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/wr_sipo_plus_kt2puei.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/wr_response_mem_kt2puei.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/wr_comp_sel_kt2puei.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/rd_response_mem_kt2puei.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/wr_sipo_plus_cwyib4q.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/wr_comp_sel_cwyib4q.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/rd_sipo_plus_kt2puei.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/rd_sipo_plus_cwyib4q.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_vnonqiy.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_alj3kza.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_ysgnmwa.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/compare_eq.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/wr_response_mem_cwyib4q.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/rd_response_mem_cwyib4q.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/rd_pri_mux_kt2puei.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/rd_comp_sel_cwyib4q.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_o34766q.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_1971_kt2puei.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_1971_cwyib4q.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/wr_pri_mux_kt2puei.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/wr_pri_mux_cwyib4q.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_h6wexfa.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_cgpn6xq.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_avalon_sc_fifo_1931_fzgstwy.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_merlin_burst_uncompressor.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_width_adapter_1933_2qdsena.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_master_agent_1921_2inlndi.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_rcor4va.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_ekcygpi.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_c2mlp5i.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_merlin_address_alignment.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_width_adapter_1933_sqfzewq.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1931_glj62si.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_merlin_burst_adapter_uncmpr.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_merlin_burst_adapter_new.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_burst_adapter_1931_hbsisni.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_wrap_burst_converter.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_merlin_burst_adapter_13_1.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_incr_burst_converter.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_default_burst_converter.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_timing_adapter_1940_5ju4ddy.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/intel_axi4lite_injector_dcfifo_s.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/intel_axi4lite_injector_util.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/intel_axi4lite_injector_ph2.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_intel_axi4lite_injector_100_2yowc3a.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_hs_clk_xer_1940_hvja46q.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_hs_clk_xer_1940_4s7hdhy.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_mm_interconnect_1920_jmzr6ly.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_mm_interconnect_1920_5sovoyi.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_master_translator_192_lykd4la.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_std_synchronizer_nocut.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_reset_synchronizer.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_avalon_st_pipeline_base.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/altera_avalon_st_clock_crosser.v"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_vbaxzva.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_nxsnrbi.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_irryw4q.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_wqohhgi.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_4ytgf2y.sv"]
|
||||
set_global_assignment -library "emif_io96b_cal_232" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_cal_232/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_2jqun3q.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name VERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby.v"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_arch_top.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/altera_std_synchronizer_nocut.v"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name MISC_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/emif_io96b_interface.svh"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/emif_io96b_lib.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/emif_io96b_clk_div.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_jedec_params.sv"]
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_timing_parameters.tcl"]
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name SDC_ENTITY_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei.sdc"] -no_sdc_promotion -no_auto_inst_discovery
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_timing_pins.tcl"]
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_timing_utils.tcl"]
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_report_timing_core.tcl"]
|
||||
set_instance_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_report_timing.tcl"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pin_locations.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_byte.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_byte_ctrl.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_cpa.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_c2p_hmc.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_p2c_hmc.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_c2p_lane.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_p2c_lane.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_noc.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_hmc_wide.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_hmc_slim.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pa.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pll.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_bufs_mem.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SOURCE_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_mc_wide_seq_pt_synth.hex"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SOURCE_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_mc_wide_seq_pt_synth.txt"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_bufs_mem.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_byte.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_byte_ctrl.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_cpa.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_noc.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_hmc_wide.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_hmc_slim.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_pa.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_pll.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_reftree.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_hmc.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_lane.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_fbr_axi_adapter_wide.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_fbr_axi_adapter_slim.sv"]
|
||||
set_global_assignment -library "emif_io96b_lpddr4_420" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "emif_io96b_lpddr4_420/synth/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_io96b_top.sv"]
|
||||
set_global_assignment -library "EMIF_Qsys_emif_ddr4a_0" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/EMIF_Qsys_emif_ddr4a_0.v"]
|
||||
|
||||
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_TOOL_NAME "emif_io96b_lpddr4"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_TOOL_VERSION "4.2.0"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei" -library "emif_io96b_lpddr4_420" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_TOOL_NAME "emif_io96b_cal"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_TOOL_VERSION "2.3.2"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq" -library "emif_io96b_cal_232" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi" -library "alt_mem_if_jtag_master_191" -name IP_TOOL_NAME "alt_mem_if_jtag_master"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi" -library "alt_mem_if_jtag_master_191" -name IP_TOOL_VERSION "19.1"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi" -library "alt_mem_if_jtag_master_191" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_TOOL_NAME "altera_reset_controller"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_TOOL_VERSION "19.2.4"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_TOOL_NAME "channel_adapter"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_TOOL_VERSION "19.2.2"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a" -library "channel_adapter_1922" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_TOOL_NAME "channel_adapter"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_TOOL_VERSION "19.2.2"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy" -library "channel_adapter_1922" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_TOOL_NAME "altera_avalon_packets_to_master"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_TOOL_VERSION "19.2.2"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "altera_avalon_packets_to_master_1922" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_TOOL_NAME "altera_avalon_st_packets_to_bytes"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_TOOL_VERSION "19.2.2"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "altera_avalon_st_packets_to_bytes_1922" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_TOOL_NAME "altera_avalon_st_bytes_to_packets"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_TOOL_VERSION "19.2.2"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "altera_avalon_st_bytes_to_packets_1922" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_TOOL_NAME "altera_avalon_sc_fifo"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_TOOL_VERSION "19.3.2"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq" -library "altera_avalon_sc_fifo_1932" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_TOOL_NAME "timing_adapter"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_TOOL_VERSION "19.5.0"
|
||||
set_global_assignment -entity "EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq" -library "timing_adapter_1950" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name IP_TOOL_NAME "altera_jtag_dc_streaming"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name IP_TOOL_VERSION "19.1"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "altera_jtag_dc_streaming_191" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
|
||||
+8687
File diff suppressed because it is too large
Load Diff
+900
@@ -0,0 +1,900 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<simPackage>
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.v"
|
||||
type="VERILOG"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_jtag_dc_streaming.v"
|
||||
type="VERILOG"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_jtag_sld_node.v"
|
||||
type="VERILOG"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_jtag_streaming.v"
|
||||
type="VERILOG"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_avalon_st_clock_crosser.v"
|
||||
type="VERILOG"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_reset_synchronizer.v"
|
||||
type="VERILOG"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_std_synchronizer_nocut.v"
|
||||
type="VERILOG"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_base.v"
|
||||
type="VERILOG"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_remover.v"
|
||||
type="VERILOG"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_inserter.v"
|
||||
type="VERILOG"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_stage.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.sdc"
|
||||
type="SDC_ENTITY"
|
||||
library="altera_jtag_dc_streaming_191" />
|
||||
<file
|
||||
path="timing_adapter_1950/sim/EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="timing_adapter_1950" />
|
||||
<file
|
||||
path="altera_avalon_sc_fifo_1932/sim/EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq.v"
|
||||
type="VERILOG"
|
||||
library="altera_avalon_sc_fifo_1932" />
|
||||
<file
|
||||
path="altera_avalon_st_bytes_to_packets_1922/sim/altera_avalon_st_bytes_to_packets.v"
|
||||
type="VERILOG"
|
||||
library="altera_avalon_st_bytes_to_packets_1922" />
|
||||
<file
|
||||
path="altera_avalon_st_packets_to_bytes_1922/sim/altera_avalon_st_packets_to_bytes.v"
|
||||
type="VERILOG"
|
||||
library="altera_avalon_st_packets_to_bytes_1922" />
|
||||
<file
|
||||
path="altera_avalon_packets_to_master_1922/sim/altera_avalon_packets_to_master.v"
|
||||
type="VERILOG"
|
||||
library="altera_avalon_packets_to_master_1922" />
|
||||
<file
|
||||
path="channel_adapter_1922/sim/EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="channel_adapter_1922" />
|
||||
<file
|
||||
path="channel_adapter_1922/sim/EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="channel_adapter_1922" />
|
||||
<file
|
||||
path="altera_reset_controller_1924/sim/altera_reset_controller.v"
|
||||
type="VERILOG"
|
||||
library="altera_reset_controller_1924" />
|
||||
<file
|
||||
path="altera_reset_controller_1924/sim/altera_reset_synchronizer.v"
|
||||
type="VERILOG"
|
||||
library="altera_reset_controller_1924" />
|
||||
<file
|
||||
path="altera_reset_controller_1924/sim/altera_reset_controller.sdc"
|
||||
type="SDC_ENTITY"
|
||||
library="altera_reset_controller_1924" />
|
||||
<file
|
||||
path="alt_mem_if_jtag_master_191/sim/EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi.v"
|
||||
type="VERILOG"
|
||||
library="alt_mem_if_jtag_master_191"
|
||||
hasInlineConfiguration="true" />
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa.v"
|
||||
type="VERILOG"
|
||||
library="emif_io96b_cal_232"
|
||||
hasInlineConfiguration="true" />
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_fa_c2p_ssm.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_fa_p2c_ssm.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_iossm.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_seq.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/iossm_cal_boot.hex"
|
||||
type="HEX"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/iossm_cal.hex"
|
||||
type="HEX"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_arbitrator.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_top.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_iossm.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_seq.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_fa.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_comp.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/altera_emif_cal_gearbox.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/altera_emif_cal_gearbox_bidir.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_translator_1931_d46vvwa.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_reset_controller.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_avalon_st_bytes_to_packets.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_avalon_packets_to_master.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_master_ni_1962_2kryw2a.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_merlin_reorder_memory.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_7ekoqry.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_1921_bk6lvda.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_channel_adapter_1921_fkajlia.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_jy53pgi.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_ctb2miq.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_7b7u3ni.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_252f2xa.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_merlin_arbitrator.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/rd_pri_mux_cwyib4q.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/rd_comp_sel_kt2puei.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_channel_adapter_1921_5wnzrci.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_avalon_st_pipeline_stage_1930_bv2ucky.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_avalon_st_packets_to_bytes.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/wr_sipo_plus_kt2puei.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/wr_response_mem_kt2puei.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/wr_comp_sel_kt2puei.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/rd_response_mem_kt2puei.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/wr_sipo_plus_cwyib4q.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/wr_comp_sel_cwyib4q.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/rd_sipo_plus_kt2puei.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/rd_sipo_plus_cwyib4q.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_vnonqiy.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_alj3kza.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_ysgnmwa.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/compare_eq.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/wr_response_mem_cwyib4q.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/rd_response_mem_cwyib4q.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/rd_pri_mux_kt2puei.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/rd_comp_sel_cwyib4q.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_o34766q.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_1971_kt2puei.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_1971_cwyib4q.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/wr_pri_mux_kt2puei.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/wr_pri_mux_cwyib4q.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_h6wexfa.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_cgpn6xq.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_avalon_sc_fifo_1931_fzgstwy.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_uncompressor.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_width_adapter_1933_2qdsena.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_master_agent_1921_2inlndi.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_rcor4va.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_ekcygpi.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_c2mlp5i.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_merlin_address_alignment.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_width_adapter_1933_sqfzewq.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1931_glj62si.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_adapter_uncmpr.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_adapter_new.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_burst_adapter_1931_hbsisni.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_wrap_burst_converter.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_adapter_13_1.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_incr_burst_converter.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_default_burst_converter.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_timing_adapter_1940_5ju4ddy.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/intel_axi4lite_injector_dcfifo_s.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/intel_axi4lite_injector_util.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/intel_axi4lite_injector_ph2.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_intel_axi4lite_injector_100_2yowc3a.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_hs_clk_xer_1940_hvja46q.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_hs_clk_xer_1940_4s7hdhy.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_mm_interconnect_1920_jmzr6ly.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_mm_interconnect_1920_5sovoyi.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_master_translator_192_lykd4la.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_std_synchronizer_nocut.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_reset_synchronizer.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_avalon_st_pipeline_base.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/altera_avalon_st_clock_crosser.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_vbaxzva.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_nxsnrbi.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_irryw4q.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_wqohhgi.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_4ytgf2y.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_2jqun3q.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_cal_232">
|
||||
<include path="emif_io96b_cal_232/sim/cal_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby.v"
|
||||
type="VERILOG"
|
||||
library="emif_io96b_lpddr4_420"
|
||||
hasInlineConfiguration="true" />
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_arch_top.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/altera_std_synchronizer_nocut.v"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/emif_io96b_lib.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/emif_io96b_clk_div.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_jedec_params.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pin_locations.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_byte.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_byte_ctrl.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_cpa.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_c2p_hmc.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_p2c_hmc.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_c2p_lane.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_p2c_lane.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_noc.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_hmc_wide.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_hmc_slim.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pa.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pll.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_bufs_mem.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_mc_wide_seq_pt_sim.hex"
|
||||
type="HEX"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_mc_wide_seq_pt_sim.txt"
|
||||
type="OTHER"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_bufs_mem.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_byte.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_byte_ctrl.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_cpa.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_noc.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_hmc_wide.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_hmc_slim.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_pa.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_pll.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_reftree.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_hmc.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_lane.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_fbr_axi_adapter_wide.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_fbr_axi_adapter_slim.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_io96b_top.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="emif_io96b_lpddr4_420">
|
||||
<include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
|
||||
</file>
|
||||
<file
|
||||
path="sim/EMIF_Qsys_emif_ddr4a_0.v"
|
||||
type="VERILOG"
|
||||
library="EMIF_Qsys_emif_ddr4a_0"
|
||||
hasInlineConfiguration="true" />
|
||||
<topLevel name="EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0" />
|
||||
<deviceFamily name="agilex5" />
|
||||
<device name="A5EB013BB23BE4SCS" />
|
||||
</simPackage>
|
||||
+23959
File diff suppressed because it is too large
Load Diff
+77
@@ -0,0 +1,77 @@
|
||||
module EMIF_Qsys_emif_ddr4a_0 (
|
||||
input wire s0_axi4_clock_in, // s0_axi4_clock_in.clk, User clock for mainband axi. Input clock to the EMIF IP, no relationship to PHY clock.
|
||||
input wire core_init_n, // core_init_n.reset_n, Core init signal going into EMIF. Used to generate the reset signal on the core-EMIF interface in fabric modes. When high, indicates core initialization is complete. The Reset Release IP should be used to generate the core initialization complete signal.
|
||||
output wire s0_axi4_reset_n, // s0_axi4_ctrl_ready.reset_n, Output signal from EMIF IP (primary I/O bank), indicating that Calibration of the channels in this I/O bank is complete, and controllers in this I/O bank are ready for use.
|
||||
input wire [29:0] s0_axi4_awaddr, // s0_axi4.awaddr, Write Address , channel 0.
|
||||
input wire [1:0] s0_axi4_awburst, // .awburst, Write Burst Type, channel 0.
|
||||
input wire [6:0] s0_axi4_awid, // .awid, Write Address ID, channel 0.
|
||||
input wire [7:0] s0_axi4_awlen, // .awlen, Write Burst Length, channel 0.
|
||||
input wire s0_axi4_awlock, // .awlock, Write Lock Type, channel 0.
|
||||
input wire [3:0] s0_axi4_awqos, // .awqos, Write Quality of Service, channel 0.
|
||||
input wire [2:0] s0_axi4_awsize, // .awsize, Write Burst Size, channel 0.
|
||||
input wire s0_axi4_awvalid, // .awvalid, Write Address Valid, channel 0.
|
||||
input wire [13:0] s0_axi4_awuser, // .awuser, Write Address User Signal, channel 0.
|
||||
input wire [2:0] s0_axi4_awprot, // .awprot, Write Protection Type, channel 0.
|
||||
output wire s0_axi4_awready, // .awready, Write Address Ready, channel 0.
|
||||
input wire [29:0] s0_axi4_araddr, // .araddr, Read Address , channel 0.
|
||||
input wire [1:0] s0_axi4_arburst, // .arburst, Read Burst Type, channel 0.
|
||||
input wire [6:0] s0_axi4_arid, // .arid, Read Address ID, channel 0.
|
||||
input wire [7:0] s0_axi4_arlen, // .arlen, Read Burst Length, channel 0.
|
||||
input wire s0_axi4_arlock, // .arlock, Read Lock Type, channel 0.
|
||||
input wire [3:0] s0_axi4_arqos, // .arqos, Read Quality of Service, channel 0.
|
||||
input wire [2:0] s0_axi4_arsize, // .arsize, Read Burst Size, channel 0.
|
||||
input wire s0_axi4_arvalid, // .arvalid, Read Address Valid, channel 0.
|
||||
input wire [13:0] s0_axi4_aruser, // .aruser, Read Address User Signal, channel 0.
|
||||
input wire [2:0] s0_axi4_arprot, // .arprot, Read Protection Type, channel 0.
|
||||
output wire s0_axi4_arready, // .arready, Read Address Ready, channel 0.
|
||||
input wire [255:0] s0_axi4_wdata, // .wdata, Write Data , channel 0.
|
||||
input wire [31:0] s0_axi4_wstrb, // .wstrb, Write Strobes, channel 0.
|
||||
input wire s0_axi4_wlast, // .wlast, Write Last, channel 0.
|
||||
input wire s0_axi4_wvalid, // .wvalid, Write Valid, channel 0.
|
||||
output wire s0_axi4_wready, // .wready, Write Ready, channel 0.
|
||||
input wire s0_axi4_bready, // .bready, Write Response Ready, channel 0.
|
||||
output wire [6:0] s0_axi4_bid, // .bid, Write Response ID, channel 0.
|
||||
output wire [1:0] s0_axi4_bresp, // .bresp, Write Response , channel 0.
|
||||
output wire s0_axi4_bvalid, // .bvalid, Write Response Valid, channel 0.
|
||||
input wire s0_axi4_rready, // .rready, Read Ready, channel 0.
|
||||
output wire [255:0] s0_axi4_rdata, // .rdata, Read Data, channel 0.
|
||||
output wire [6:0] s0_axi4_rid, // .rid, Read ID , channel 0.
|
||||
output wire s0_axi4_rlast, // .rlast, Read Last, channel 0.
|
||||
output wire [1:0] s0_axi4_rresp, // .rresp, Read Response, channel 0.
|
||||
output wire s0_axi4_rvalid, // .rvalid, Read Valid, channel 0.
|
||||
input wire s0_axi4lite_clock, // s0_axi4lite_clock.clk, Axi-Lite clock, to primary IOSSM.
|
||||
input wire s0_axi4lite_reset_n, // s0_axi4lite_reset_n.reset_n, Axi-Lite reset_n, to primary IOSSM.
|
||||
input wire [26:0] s0_axi4lite_awaddr, // s0_axi4lite.awaddr, Axi-Lite Write Address, to primary IOSSM.
|
||||
input wire [2:0] s0_axi4lite_awprot, // .awprot, Axi-Lite Write Address Protection Signal, to primary IOSSM.
|
||||
input wire s0_axi4lite_awvalid, // .awvalid, Axi-Lite Write Address Valid, to primary IOSSM.
|
||||
output wire s0_axi4lite_awready, // .awready, Axi-Lite Write Address Ready, to primary IOSSM.
|
||||
input wire [26:0] s0_axi4lite_araddr, // .araddr, Axi-Lite Read Address, to primary IOSSM.
|
||||
input wire [2:0] s0_axi4lite_arprot, // .arprot, Axi-Lite Read Address Protection Signal, to primary IOSSM.
|
||||
input wire s0_axi4lite_arvalid, // .arvalid, Axi-Lite Read Address Valid, to primary IOSSM.
|
||||
output wire s0_axi4lite_arready, // .arready, Axi-Lite Read Address Ready, to primary IOSSM.
|
||||
input wire [31:0] s0_axi4lite_wdata, // .wdata, Axi-Lite Write Data, to primary IOSSM.
|
||||
input wire [3:0] s0_axi4lite_wstrb, // .wstrb, Axi-Lite Write Strobe, to primary IOSSM.
|
||||
input wire s0_axi4lite_wvalid, // .wvalid, Axi-Lite Write Valid, to primary IOSSM.
|
||||
output wire s0_axi4lite_wready, // .wready, Axi-Lite Write Ready, to primary IOSSM.
|
||||
input wire s0_axi4lite_bready, // .bready, Axi-Lite Write Response Ready, to primary IOSSM.
|
||||
output wire [1:0] s0_axi4lite_bresp, // .bresp, Axi-Lite Write Response, to primary IOSSM.
|
||||
output wire s0_axi4lite_bvalid, // .bvalid, Axi-Lite Write Response Valid, to primary IOSSM.
|
||||
input wire s0_axi4lite_rready, // .rready, Axi-Lite Read Ready, to primary IOSSM.
|
||||
output wire [31:0] s0_axi4lite_rdata, // .rdata, Axi-Lite Read Data, to primary IOSSM.
|
||||
output wire [1:0] s0_axi4lite_rresp, // .rresp, Axi-Lite Read Response, to primary IOSSM.
|
||||
output wire s0_axi4lite_rvalid, // .rvalid, Axi-Lite Read Valid, to primary IOSSM.
|
||||
output wire [0:0] mem_0_cs, // mem_0.mem_cs, Chip Select channel 0.
|
||||
output wire [5:0] mem_0_ca, // .mem_ca, Command/Address Bus channel 0.
|
||||
output wire [0:0] mem_0_cke, // .mem_cke, Clock Enable channel 0.
|
||||
inout wire [31:0] mem_0_dq, // .mem_dq, Data (read/write) channel 0.
|
||||
inout wire [3:0] mem_0_dqs_t, // .mem_dqs_t, Data Strobe (true) channel 0.
|
||||
inout wire [3:0] mem_0_dqs_c, // .mem_dqs_c, Data Strobe (complement) channel 0.
|
||||
inout wire [3:0] mem_0_dmi, // .mem_dmi, Data Mask/Data Inversion channel 0.
|
||||
output wire [0:0] mem_0_ck_t, // mem_ck_0.mem_ck_t, CK Clock (true) channel 0.
|
||||
output wire [0:0] mem_0_ck_c, // .mem_ck_c, CK Clock (complement) channel 0.
|
||||
output wire mem_0_reset_n, // mem_reset_n.mem_reset_n, Asynchronous Reset channel 0.
|
||||
input wire oct_rzqin_0, // oct_0.oct_rzqin, Calibrated On-Chip Termination (OCT) input pin channel 0.
|
||||
input wire ref_clk // ref_clk.clk, PLL reference clock input.
|
||||
);
|
||||
endmodule
|
||||
|
||||
+88
@@ -0,0 +1,88 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create simulation model
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0: Configuring this IP for device A5EB013BB23BE4SCS (Agilex 5). This device has speedgrade 4.
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Transforming system: EMIF_Qsys_emif_ddr4a_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Naming system components in system: EMIF_Qsys_emif_ddr4a_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Processing generation queue"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei"
|
||||
Info: cal_0: "Generating: cal_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq"
|
||||
Info: jamb: "Generating: jamb"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_jtag_interface"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_bytes_to_packets"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_packets_to_bytes"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_packets_to_master"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_reset_controller"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: Done "EMIF_Qsys_emif_ddr4a_0" with 15 modules, 159 files
|
||||
Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for specified device family. Use VCS-MX or another supported simulator.
|
||||
Info: Generating the following file(s) for MODELSIM simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
|
||||
Info: common/modelsim_files.tcl
|
||||
Info: Generating the following file(s) for RIVIERA simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
|
||||
Info: common/riviera_files.tcl
|
||||
Info: Generating the following file(s) for VCSMX simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
|
||||
Info: common/vcsmx_files.tcl
|
||||
Info: Generating the following file(s) for XCELIUM simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
|
||||
Info: common/xcelium_files.tcl
|
||||
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/.
|
||||
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
|
||||
Info: Finished: Create simulation model
|
||||
Info: Starting: Create simulation script
|
||||
Info: sim-script-gen --system-file=/home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ --use-relative-paths=true
|
||||
Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for specified device family. Use VCS-MX or another supported simulator.
|
||||
Info: Generating the following file(s) for MODELSIM simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
|
||||
Info: mentor/msim_setup.tcl
|
||||
Info: mentor/run_msim_setup.tcl
|
||||
Info: Generating the following file(s) for RIVIERA simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
|
||||
Info: aldec/rivierapro_setup.tcl
|
||||
Info: aldec/run_rivierapro_setup.tcl
|
||||
Info: Generating the following file(s) for VCSMX simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
|
||||
Info: synopsys/vcsmx/_device_synopsys_sim.setup
|
||||
Info: synopsys/vcsmx/synopsys_sim.setup
|
||||
Info: synopsys/vcsmx/vcsmx_setup.sh
|
||||
Info: Generating the following file(s) for XCELIUM simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
|
||||
Info: xcelium/cds.lib
|
||||
Info: xcelium/hdl.var
|
||||
Info: xcelium/xcelium_setup.sh
|
||||
Info: 13 .cds.lib files in xcelium/cds_libs/ directory
|
||||
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/.
|
||||
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
|
||||
Info: Finished: Create simulation script
|
||||
Info: Starting: Create block symbol file (.bsf)
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip --block-symbol-file --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0: Configuring this IP for device A5EB013BB23BE4SCS (Agilex 5). This device has speedgrade 4.
|
||||
Info: Finished: Create block symbol file (.bsf)
|
||||
Info:
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0: Configuring this IP for device A5EB013BB23BE4SCS (Agilex 5). This device has speedgrade 4.
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Transforming system: EMIF_Qsys_emif_ddr4a_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Naming system components in system: EMIF_Qsys_emif_ddr4a_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Processing generation queue"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei"
|
||||
Info: cal_0: "Generating: cal_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq"
|
||||
Info: jamb: "Generating: jamb"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_jtag_interface"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_bytes_to_packets"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_packets_to_bytes"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_packets_to_master"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_reset_controller"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: Done "EMIF_Qsys_emif_ddr4a_0" with 15 modules, 165 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0: Configuring this IP for device A5EB013BB23BE4SCS (Agilex 5). This device has speedgrade 4.
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Transforming system: EMIF_Qsys_emif_ddr4a_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Naming system components in system: EMIF_Qsys_emif_ddr4a_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Processing generation queue"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_411_5rak7ri"
|
||||
Info: cal_0: "Generating: cal_0"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_411_yhgkgsq"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_231_ihlvdea"
|
||||
Info: jamb: "Generating: jamb"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_231_7ir2qwq"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_jtag_interface"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_bytes_to_packets"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_packets_to_bytes"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_packets_to_master"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_reset_controller"
|
||||
Info: EMIF_Qsys_emif_ddr4a_0: Done "EMIF_Qsys_emif_ddr4a_0" with 15 modules, 165 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
+76
@@ -0,0 +1,76 @@
|
||||
EMIF_Qsys_emif_ddr4a_0 u0 (
|
||||
.s0_axi4_clock_in (_connected_to_s0_axi4_clock_in_), // input, width = 1, s0_axi4_clock_in.clk
|
||||
.core_init_n (_connected_to_core_init_n_), // input, width = 1, core_init_n.reset_n
|
||||
.s0_axi4_reset_n (_connected_to_s0_axi4_reset_n_), // output, width = 1, s0_axi4_ctrl_ready.reset_n
|
||||
.s0_axi4_awaddr (_connected_to_s0_axi4_awaddr_), // input, width = 30, s0_axi4.awaddr
|
||||
.s0_axi4_awburst (_connected_to_s0_axi4_awburst_), // input, width = 2, .awburst
|
||||
.s0_axi4_awid (_connected_to_s0_axi4_awid_), // input, width = 7, .awid
|
||||
.s0_axi4_awlen (_connected_to_s0_axi4_awlen_), // input, width = 8, .awlen
|
||||
.s0_axi4_awlock (_connected_to_s0_axi4_awlock_), // input, width = 1, .awlock
|
||||
.s0_axi4_awqos (_connected_to_s0_axi4_awqos_), // input, width = 4, .awqos
|
||||
.s0_axi4_awsize (_connected_to_s0_axi4_awsize_), // input, width = 3, .awsize
|
||||
.s0_axi4_awvalid (_connected_to_s0_axi4_awvalid_), // input, width = 1, .awvalid
|
||||
.s0_axi4_awuser (_connected_to_s0_axi4_awuser_), // input, width = 14, .awuser
|
||||
.s0_axi4_awprot (_connected_to_s0_axi4_awprot_), // input, width = 3, .awprot
|
||||
.s0_axi4_awready (_connected_to_s0_axi4_awready_), // output, width = 1, .awready
|
||||
.s0_axi4_araddr (_connected_to_s0_axi4_araddr_), // input, width = 30, .araddr
|
||||
.s0_axi4_arburst (_connected_to_s0_axi4_arburst_), // input, width = 2, .arburst
|
||||
.s0_axi4_arid (_connected_to_s0_axi4_arid_), // input, width = 7, .arid
|
||||
.s0_axi4_arlen (_connected_to_s0_axi4_arlen_), // input, width = 8, .arlen
|
||||
.s0_axi4_arlock (_connected_to_s0_axi4_arlock_), // input, width = 1, .arlock
|
||||
.s0_axi4_arqos (_connected_to_s0_axi4_arqos_), // input, width = 4, .arqos
|
||||
.s0_axi4_arsize (_connected_to_s0_axi4_arsize_), // input, width = 3, .arsize
|
||||
.s0_axi4_arvalid (_connected_to_s0_axi4_arvalid_), // input, width = 1, .arvalid
|
||||
.s0_axi4_aruser (_connected_to_s0_axi4_aruser_), // input, width = 14, .aruser
|
||||
.s0_axi4_arprot (_connected_to_s0_axi4_arprot_), // input, width = 3, .arprot
|
||||
.s0_axi4_arready (_connected_to_s0_axi4_arready_), // output, width = 1, .arready
|
||||
.s0_axi4_wdata (_connected_to_s0_axi4_wdata_), // input, width = 256, .wdata
|
||||
.s0_axi4_wstrb (_connected_to_s0_axi4_wstrb_), // input, width = 32, .wstrb
|
||||
.s0_axi4_wlast (_connected_to_s0_axi4_wlast_), // input, width = 1, .wlast
|
||||
.s0_axi4_wvalid (_connected_to_s0_axi4_wvalid_), // input, width = 1, .wvalid
|
||||
.s0_axi4_wready (_connected_to_s0_axi4_wready_), // output, width = 1, .wready
|
||||
.s0_axi4_bready (_connected_to_s0_axi4_bready_), // input, width = 1, .bready
|
||||
.s0_axi4_bid (_connected_to_s0_axi4_bid_), // output, width = 7, .bid
|
||||
.s0_axi4_bresp (_connected_to_s0_axi4_bresp_), // output, width = 2, .bresp
|
||||
.s0_axi4_bvalid (_connected_to_s0_axi4_bvalid_), // output, width = 1, .bvalid
|
||||
.s0_axi4_rready (_connected_to_s0_axi4_rready_), // input, width = 1, .rready
|
||||
.s0_axi4_rdata (_connected_to_s0_axi4_rdata_), // output, width = 256, .rdata
|
||||
.s0_axi4_rid (_connected_to_s0_axi4_rid_), // output, width = 7, .rid
|
||||
.s0_axi4_rlast (_connected_to_s0_axi4_rlast_), // output, width = 1, .rlast
|
||||
.s0_axi4_rresp (_connected_to_s0_axi4_rresp_), // output, width = 2, .rresp
|
||||
.s0_axi4_rvalid (_connected_to_s0_axi4_rvalid_), // output, width = 1, .rvalid
|
||||
.s0_axi4lite_clock (_connected_to_s0_axi4lite_clock_), // input, width = 1, s0_axi4lite_clock.clk
|
||||
.s0_axi4lite_reset_n (_connected_to_s0_axi4lite_reset_n_), // input, width = 1, s0_axi4lite_reset_n.reset_n
|
||||
.s0_axi4lite_awaddr (_connected_to_s0_axi4lite_awaddr_), // input, width = 27, s0_axi4lite.awaddr
|
||||
.s0_axi4lite_awprot (_connected_to_s0_axi4lite_awprot_), // input, width = 3, .awprot
|
||||
.s0_axi4lite_awvalid (_connected_to_s0_axi4lite_awvalid_), // input, width = 1, .awvalid
|
||||
.s0_axi4lite_awready (_connected_to_s0_axi4lite_awready_), // output, width = 1, .awready
|
||||
.s0_axi4lite_araddr (_connected_to_s0_axi4lite_araddr_), // input, width = 27, .araddr
|
||||
.s0_axi4lite_arprot (_connected_to_s0_axi4lite_arprot_), // input, width = 3, .arprot
|
||||
.s0_axi4lite_arvalid (_connected_to_s0_axi4lite_arvalid_), // input, width = 1, .arvalid
|
||||
.s0_axi4lite_arready (_connected_to_s0_axi4lite_arready_), // output, width = 1, .arready
|
||||
.s0_axi4lite_wdata (_connected_to_s0_axi4lite_wdata_), // input, width = 32, .wdata
|
||||
.s0_axi4lite_wstrb (_connected_to_s0_axi4lite_wstrb_), // input, width = 4, .wstrb
|
||||
.s0_axi4lite_wvalid (_connected_to_s0_axi4lite_wvalid_), // input, width = 1, .wvalid
|
||||
.s0_axi4lite_wready (_connected_to_s0_axi4lite_wready_), // output, width = 1, .wready
|
||||
.s0_axi4lite_bready (_connected_to_s0_axi4lite_bready_), // input, width = 1, .bready
|
||||
.s0_axi4lite_bresp (_connected_to_s0_axi4lite_bresp_), // output, width = 2, .bresp
|
||||
.s0_axi4lite_bvalid (_connected_to_s0_axi4lite_bvalid_), // output, width = 1, .bvalid
|
||||
.s0_axi4lite_rready (_connected_to_s0_axi4lite_rready_), // input, width = 1, .rready
|
||||
.s0_axi4lite_rdata (_connected_to_s0_axi4lite_rdata_), // output, width = 32, .rdata
|
||||
.s0_axi4lite_rresp (_connected_to_s0_axi4lite_rresp_), // output, width = 2, .rresp
|
||||
.s0_axi4lite_rvalid (_connected_to_s0_axi4lite_rvalid_), // output, width = 1, .rvalid
|
||||
.mem_0_cs (_connected_to_mem_0_cs_), // output, width = 1, mem_0.mem_cs
|
||||
.mem_0_ca (_connected_to_mem_0_ca_), // output, width = 6, .mem_ca
|
||||
.mem_0_cke (_connected_to_mem_0_cke_), // output, width = 1, .mem_cke
|
||||
.mem_0_dq (_connected_to_mem_0_dq_), // inout, width = 32, .mem_dq
|
||||
.mem_0_dqs_t (_connected_to_mem_0_dqs_t_), // inout, width = 4, .mem_dqs_t
|
||||
.mem_0_dqs_c (_connected_to_mem_0_dqs_c_), // inout, width = 4, .mem_dqs_c
|
||||
.mem_0_dmi (_connected_to_mem_0_dmi_), // inout, width = 4, .mem_dmi
|
||||
.mem_0_ck_t (_connected_to_mem_0_ck_t_), // output, width = 1, mem_ck_0.mem_ck_t
|
||||
.mem_0_ck_c (_connected_to_mem_0_ck_c_), // output, width = 1, .mem_ck_c
|
||||
.mem_0_reset_n (_connected_to_mem_0_reset_n_), // output, width = 1, mem_reset_n.mem_reset_n
|
||||
.oct_rzqin_0 (_connected_to_oct_rzqin_0_), // input, width = 1, oct_0.oct_rzqin
|
||||
.ref_clk (_connected_to_ref_clk_) // input, width = 1, ref_clk.clk
|
||||
);
|
||||
|
||||
+155
@@ -0,0 +1,155 @@
|
||||
component EMIF_Qsys_emif_ddr4a_0 is
|
||||
port (
|
||||
s0_axi4_clock_in : in std_logic := 'X'; -- clk
|
||||
core_init_n : in std_logic := 'X'; -- reset_n
|
||||
s0_axi4_reset_n : out std_logic; -- reset_n
|
||||
s0_axi4_awaddr : in std_logic_vector(29 downto 0) := (others => 'X'); -- awaddr
|
||||
s0_axi4_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst
|
||||
s0_axi4_awid : in std_logic_vector(6 downto 0) := (others => 'X'); -- awid
|
||||
s0_axi4_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- awlen
|
||||
s0_axi4_awlock : in std_logic := 'X'; -- awlock
|
||||
s0_axi4_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- awqos
|
||||
s0_axi4_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize
|
||||
s0_axi4_awvalid : in std_logic := 'X'; -- awvalid
|
||||
s0_axi4_awuser : in std_logic_vector(13 downto 0) := (others => 'X'); -- awuser
|
||||
s0_axi4_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
|
||||
s0_axi4_awready : out std_logic; -- awready
|
||||
s0_axi4_araddr : in std_logic_vector(29 downto 0) := (others => 'X'); -- araddr
|
||||
s0_axi4_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst
|
||||
s0_axi4_arid : in std_logic_vector(6 downto 0) := (others => 'X'); -- arid
|
||||
s0_axi4_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- arlen
|
||||
s0_axi4_arlock : in std_logic := 'X'; -- arlock
|
||||
s0_axi4_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- arqos
|
||||
s0_axi4_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize
|
||||
s0_axi4_arvalid : in std_logic := 'X'; -- arvalid
|
||||
s0_axi4_aruser : in std_logic_vector(13 downto 0) := (others => 'X'); -- aruser
|
||||
s0_axi4_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
|
||||
s0_axi4_arready : out std_logic; -- arready
|
||||
s0_axi4_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- wdata
|
||||
s0_axi4_wstrb : in std_logic_vector(31 downto 0) := (others => 'X'); -- wstrb
|
||||
s0_axi4_wlast : in std_logic := 'X'; -- wlast
|
||||
s0_axi4_wvalid : in std_logic := 'X'; -- wvalid
|
||||
s0_axi4_wready : out std_logic; -- wready
|
||||
s0_axi4_bready : in std_logic := 'X'; -- bready
|
||||
s0_axi4_bid : out std_logic_vector(6 downto 0); -- bid
|
||||
s0_axi4_bresp : out std_logic_vector(1 downto 0); -- bresp
|
||||
s0_axi4_bvalid : out std_logic; -- bvalid
|
||||
s0_axi4_rready : in std_logic := 'X'; -- rready
|
||||
s0_axi4_rdata : out std_logic_vector(255 downto 0); -- rdata
|
||||
s0_axi4_rid : out std_logic_vector(6 downto 0); -- rid
|
||||
s0_axi4_rlast : out std_logic; -- rlast
|
||||
s0_axi4_rresp : out std_logic_vector(1 downto 0); -- rresp
|
||||
s0_axi4_rvalid : out std_logic; -- rvalid
|
||||
s0_axi4lite_clock : in std_logic := 'X'; -- clk
|
||||
s0_axi4lite_reset_n : in std_logic := 'X'; -- reset_n
|
||||
s0_axi4lite_awaddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- awaddr
|
||||
s0_axi4lite_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
|
||||
s0_axi4lite_awvalid : in std_logic := 'X'; -- awvalid
|
||||
s0_axi4lite_awready : out std_logic; -- awready
|
||||
s0_axi4lite_araddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- araddr
|
||||
s0_axi4lite_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
|
||||
s0_axi4lite_arvalid : in std_logic := 'X'; -- arvalid
|
||||
s0_axi4lite_arready : out std_logic; -- arready
|
||||
s0_axi4lite_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata
|
||||
s0_axi4lite_wstrb : in std_logic_vector(3 downto 0) := (others => 'X'); -- wstrb
|
||||
s0_axi4lite_wvalid : in std_logic := 'X'; -- wvalid
|
||||
s0_axi4lite_wready : out std_logic; -- wready
|
||||
s0_axi4lite_bready : in std_logic := 'X'; -- bready
|
||||
s0_axi4lite_bresp : out std_logic_vector(1 downto 0); -- bresp
|
||||
s0_axi4lite_bvalid : out std_logic; -- bvalid
|
||||
s0_axi4lite_rready : in std_logic := 'X'; -- rready
|
||||
s0_axi4lite_rdata : out std_logic_vector(31 downto 0); -- rdata
|
||||
s0_axi4lite_rresp : out std_logic_vector(1 downto 0); -- rresp
|
||||
s0_axi4lite_rvalid : out std_logic; -- rvalid
|
||||
mem_0_cs : out std_logic_vector(0 downto 0); -- mem_cs
|
||||
mem_0_ca : out std_logic_vector(5 downto 0); -- mem_ca
|
||||
mem_0_cke : out std_logic_vector(0 downto 0); -- mem_cke
|
||||
mem_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
|
||||
mem_0_dqs_t : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_t
|
||||
mem_0_dqs_c : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_c
|
||||
mem_0_dmi : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dmi
|
||||
mem_0_ck_t : out std_logic_vector(0 downto 0); -- mem_ck_t
|
||||
mem_0_ck_c : out std_logic_vector(0 downto 0); -- mem_ck_c
|
||||
mem_0_reset_n : out std_logic; -- mem_reset_n
|
||||
oct_rzqin_0 : in std_logic := 'X'; -- oct_rzqin
|
||||
ref_clk : in std_logic := 'X' -- clk
|
||||
);
|
||||
end component EMIF_Qsys_emif_ddr4a_0;
|
||||
|
||||
u0 : component EMIF_Qsys_emif_ddr4a_0
|
||||
port map (
|
||||
s0_axi4_clock_in => CONNECTED_TO_s0_axi4_clock_in, -- s0_axi4_clock_in.clk
|
||||
core_init_n => CONNECTED_TO_core_init_n, -- core_init_n.reset_n
|
||||
s0_axi4_reset_n => CONNECTED_TO_s0_axi4_reset_n, -- s0_axi4_ctrl_ready.reset_n
|
||||
s0_axi4_awaddr => CONNECTED_TO_s0_axi4_awaddr, -- s0_axi4.awaddr
|
||||
s0_axi4_awburst => CONNECTED_TO_s0_axi4_awburst, -- .awburst
|
||||
s0_axi4_awid => CONNECTED_TO_s0_axi4_awid, -- .awid
|
||||
s0_axi4_awlen => CONNECTED_TO_s0_axi4_awlen, -- .awlen
|
||||
s0_axi4_awlock => CONNECTED_TO_s0_axi4_awlock, -- .awlock
|
||||
s0_axi4_awqos => CONNECTED_TO_s0_axi4_awqos, -- .awqos
|
||||
s0_axi4_awsize => CONNECTED_TO_s0_axi4_awsize, -- .awsize
|
||||
s0_axi4_awvalid => CONNECTED_TO_s0_axi4_awvalid, -- .awvalid
|
||||
s0_axi4_awuser => CONNECTED_TO_s0_axi4_awuser, -- .awuser
|
||||
s0_axi4_awprot => CONNECTED_TO_s0_axi4_awprot, -- .awprot
|
||||
s0_axi4_awready => CONNECTED_TO_s0_axi4_awready, -- .awready
|
||||
s0_axi4_araddr => CONNECTED_TO_s0_axi4_araddr, -- .araddr
|
||||
s0_axi4_arburst => CONNECTED_TO_s0_axi4_arburst, -- .arburst
|
||||
s0_axi4_arid => CONNECTED_TO_s0_axi4_arid, -- .arid
|
||||
s0_axi4_arlen => CONNECTED_TO_s0_axi4_arlen, -- .arlen
|
||||
s0_axi4_arlock => CONNECTED_TO_s0_axi4_arlock, -- .arlock
|
||||
s0_axi4_arqos => CONNECTED_TO_s0_axi4_arqos, -- .arqos
|
||||
s0_axi4_arsize => CONNECTED_TO_s0_axi4_arsize, -- .arsize
|
||||
s0_axi4_arvalid => CONNECTED_TO_s0_axi4_arvalid, -- .arvalid
|
||||
s0_axi4_aruser => CONNECTED_TO_s0_axi4_aruser, -- .aruser
|
||||
s0_axi4_arprot => CONNECTED_TO_s0_axi4_arprot, -- .arprot
|
||||
s0_axi4_arready => CONNECTED_TO_s0_axi4_arready, -- .arready
|
||||
s0_axi4_wdata => CONNECTED_TO_s0_axi4_wdata, -- .wdata
|
||||
s0_axi4_wstrb => CONNECTED_TO_s0_axi4_wstrb, -- .wstrb
|
||||
s0_axi4_wlast => CONNECTED_TO_s0_axi4_wlast, -- .wlast
|
||||
s0_axi4_wvalid => CONNECTED_TO_s0_axi4_wvalid, -- .wvalid
|
||||
s0_axi4_wready => CONNECTED_TO_s0_axi4_wready, -- .wready
|
||||
s0_axi4_bready => CONNECTED_TO_s0_axi4_bready, -- .bready
|
||||
s0_axi4_bid => CONNECTED_TO_s0_axi4_bid, -- .bid
|
||||
s0_axi4_bresp => CONNECTED_TO_s0_axi4_bresp, -- .bresp
|
||||
s0_axi4_bvalid => CONNECTED_TO_s0_axi4_bvalid, -- .bvalid
|
||||
s0_axi4_rready => CONNECTED_TO_s0_axi4_rready, -- .rready
|
||||
s0_axi4_rdata => CONNECTED_TO_s0_axi4_rdata, -- .rdata
|
||||
s0_axi4_rid => CONNECTED_TO_s0_axi4_rid, -- .rid
|
||||
s0_axi4_rlast => CONNECTED_TO_s0_axi4_rlast, -- .rlast
|
||||
s0_axi4_rresp => CONNECTED_TO_s0_axi4_rresp, -- .rresp
|
||||
s0_axi4_rvalid => CONNECTED_TO_s0_axi4_rvalid, -- .rvalid
|
||||
s0_axi4lite_clock => CONNECTED_TO_s0_axi4lite_clock, -- s0_axi4lite_clock.clk
|
||||
s0_axi4lite_reset_n => CONNECTED_TO_s0_axi4lite_reset_n, -- s0_axi4lite_reset_n.reset_n
|
||||
s0_axi4lite_awaddr => CONNECTED_TO_s0_axi4lite_awaddr, -- s0_axi4lite.awaddr
|
||||
s0_axi4lite_awprot => CONNECTED_TO_s0_axi4lite_awprot, -- .awprot
|
||||
s0_axi4lite_awvalid => CONNECTED_TO_s0_axi4lite_awvalid, -- .awvalid
|
||||
s0_axi4lite_awready => CONNECTED_TO_s0_axi4lite_awready, -- .awready
|
||||
s0_axi4lite_araddr => CONNECTED_TO_s0_axi4lite_araddr, -- .araddr
|
||||
s0_axi4lite_arprot => CONNECTED_TO_s0_axi4lite_arprot, -- .arprot
|
||||
s0_axi4lite_arvalid => CONNECTED_TO_s0_axi4lite_arvalid, -- .arvalid
|
||||
s0_axi4lite_arready => CONNECTED_TO_s0_axi4lite_arready, -- .arready
|
||||
s0_axi4lite_wdata => CONNECTED_TO_s0_axi4lite_wdata, -- .wdata
|
||||
s0_axi4lite_wstrb => CONNECTED_TO_s0_axi4lite_wstrb, -- .wstrb
|
||||
s0_axi4lite_wvalid => CONNECTED_TO_s0_axi4lite_wvalid, -- .wvalid
|
||||
s0_axi4lite_wready => CONNECTED_TO_s0_axi4lite_wready, -- .wready
|
||||
s0_axi4lite_bready => CONNECTED_TO_s0_axi4lite_bready, -- .bready
|
||||
s0_axi4lite_bresp => CONNECTED_TO_s0_axi4lite_bresp, -- .bresp
|
||||
s0_axi4lite_bvalid => CONNECTED_TO_s0_axi4lite_bvalid, -- .bvalid
|
||||
s0_axi4lite_rready => CONNECTED_TO_s0_axi4lite_rready, -- .rready
|
||||
s0_axi4lite_rdata => CONNECTED_TO_s0_axi4lite_rdata, -- .rdata
|
||||
s0_axi4lite_rresp => CONNECTED_TO_s0_axi4lite_rresp, -- .rresp
|
||||
s0_axi4lite_rvalid => CONNECTED_TO_s0_axi4lite_rvalid, -- .rvalid
|
||||
mem_0_cs => CONNECTED_TO_mem_0_cs, -- mem_0.mem_cs
|
||||
mem_0_ca => CONNECTED_TO_mem_0_ca, -- .mem_ca
|
||||
mem_0_cke => CONNECTED_TO_mem_0_cke, -- .mem_cke
|
||||
mem_0_dq => CONNECTED_TO_mem_0_dq, -- .mem_dq
|
||||
mem_0_dqs_t => CONNECTED_TO_mem_0_dqs_t, -- .mem_dqs_t
|
||||
mem_0_dqs_c => CONNECTED_TO_mem_0_dqs_c, -- .mem_dqs_c
|
||||
mem_0_dmi => CONNECTED_TO_mem_0_dmi, -- .mem_dmi
|
||||
mem_0_ck_t => CONNECTED_TO_mem_0_ck_t, -- mem_ck_0.mem_ck_t
|
||||
mem_0_ck_c => CONNECTED_TO_mem_0_ck_c, -- .mem_ck_c
|
||||
mem_0_reset_n => CONNECTED_TO_mem_0_reset_n, -- mem_reset_n.mem_reset_n
|
||||
oct_rzqin_0 => CONNECTED_TO_oct_rzqin_0, -- oct_0.oct_rzqin
|
||||
ref_clk => CONNECTED_TO_ref_clk -- ref_clk.clk
|
||||
);
|
||||
|
||||
+366
@@ -0,0 +1,366 @@
|
||||
// EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi.v
|
||||
|
||||
// This file was auto-generated from alt_mem_if_jtag_master_hw.tcl. If you edit it your changes
|
||||
// will probably be lost.
|
||||
//
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi #(
|
||||
parameter USE_PLI = 0,
|
||||
parameter PLI_PORT = 50000,
|
||||
parameter FIFO_DEPTHS = 2
|
||||
) (
|
||||
input wire clk_clk, // clk.clk, Clock Input
|
||||
input wire clk_reset_reset, // clk_reset.reset, Reset Input
|
||||
output wire master_reset_reset, // master_reset.reset, Reset Output
|
||||
output wire [31:0] master_address, // master.address, Address output of Avalon Memory Mapped Host
|
||||
input wire [31:0] master_readdata, // .readdata, Read Data input to Avalon Memory Mapped Host
|
||||
output wire master_read, // .read, Read command from Avalon Memory Mapped Host
|
||||
output wire master_write, // .write, Write command from Avalon Memory Mapped Host
|
||||
output wire [31:0] master_writedata, // .writedata, Write Data from Avalon Memory Mapped Host
|
||||
input wire master_waitrequest, // .waitrequest, Wait request from Avalon Memory Mapped Agent, indicates agent is not ready
|
||||
input wire master_readdatavalid, // .readdatavalid, Valid read data indication from Avalon Memory Mapped Agent
|
||||
output wire [3:0] master_byteenable // .byteenable, Indicates valid write data/read data location
|
||||
);
|
||||
|
||||
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
|
||||
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
|
||||
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
|
||||
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
|
||||
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
|
||||
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
|
||||
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
|
||||
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
|
||||
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
|
||||
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
|
||||
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
|
||||
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
|
||||
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
|
||||
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
|
||||
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
|
||||
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
|
||||
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
|
||||
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
|
||||
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
|
||||
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
|
||||
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
|
||||
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
|
||||
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
|
||||
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
|
||||
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
|
||||
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
|
||||
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
|
||||
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
|
||||
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
|
||||
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
|
||||
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
|
||||
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
|
||||
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
|
||||
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
|
||||
|
||||
generate
|
||||
// If any of the display statements (or deliberately broken
|
||||
// instantiations) within this generate block triggers then this module
|
||||
// has been instantiated this module with a set of parameters different
|
||||
// from those it was generated for. This will usually result in a
|
||||
// non-functioning system.
|
||||
if (USE_PLI != 0)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
use_pli_check ( .error(1'b1) );
|
||||
end
|
||||
if (PLI_PORT != 50000)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
pli_port_check ( .error(1'b1) );
|
||||
end
|
||||
if (FIFO_DEPTHS != 2)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
fifo_depths_check ( .error(1'b1) );
|
||||
end
|
||||
endgenerate
|
||||
|
||||
altera_avalon_st_jtag_interface #(
|
||||
.PURPOSE (1),
|
||||
.UPSTREAM_FIFO_SIZE (0),
|
||||
.DOWNSTREAM_FIFO_SIZE (64),
|
||||
.MGMT_CHANNEL_WIDTH (-1),
|
||||
.EXPORT_JTAG (0),
|
||||
.USE_PLI (0),
|
||||
.PLI_PORT (50000)
|
||||
) jtag_phy_embedded_in_jtag_master (
|
||||
.clk (clk_clk), // input, width = 1, clock.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clock_reset.reset_n
|
||||
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // output, width = 8, src.data
|
||||
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // output, width = 1, .valid
|
||||
.sink_data (p2b_out_bytes_stream_data), // input, width = 8, sink.data
|
||||
.sink_valid (p2b_out_bytes_stream_valid), // input, width = 1, .valid
|
||||
.sink_ready (p2b_out_bytes_stream_ready), // output, width = 1, .ready
|
||||
.resetrequest (master_reset_reset), // output, width = 1, resetrequest.reset
|
||||
.source_ready (1'b1), // (terminated),
|
||||
.mgmt_valid (), // (terminated),
|
||||
.mgmt_channel (), // (terminated),
|
||||
.mgmt_data (), // (terminated),
|
||||
.jtag_tck (1'b0), // (terminated),
|
||||
.jtag_tms (1'b0), // (terminated),
|
||||
.jtag_tdi (1'b0), // (terminated),
|
||||
.jtag_tdo (), // (terminated),
|
||||
.jtag_ena (1'b0), // (terminated),
|
||||
.jtag_usr1 (1'b0), // (terminated),
|
||||
.jtag_clr (1'b0), // (terminated),
|
||||
.jtag_clrn (1'b0), // (terminated),
|
||||
.jtag_state_tlr (1'b0), // (terminated),
|
||||
.jtag_state_rti (1'b0), // (terminated),
|
||||
.jtag_state_sdrs (1'b0), // (terminated),
|
||||
.jtag_state_cdr (1'b0), // (terminated),
|
||||
.jtag_state_sdr (1'b0), // (terminated),
|
||||
.jtag_state_e1dr (1'b0), // (terminated),
|
||||
.jtag_state_pdr (1'b0), // (terminated),
|
||||
.jtag_state_e2dr (1'b0), // (terminated),
|
||||
.jtag_state_udr (1'b0), // (terminated),
|
||||
.jtag_state_sirs (1'b0), // (terminated),
|
||||
.jtag_state_cir (1'b0), // (terminated),
|
||||
.jtag_state_sir (1'b0), // (terminated),
|
||||
.jtag_state_e1ir (1'b0), // (terminated),
|
||||
.jtag_state_pir (1'b0), // (terminated),
|
||||
.jtag_state_e2ir (1'b0), // (terminated),
|
||||
.jtag_state_uir (1'b0), // (terminated),
|
||||
.jtag_ir_in (3'b000), // (terminated),
|
||||
.jtag_irq (), // (terminated),
|
||||
.jtag_ir_out () // (terminated),
|
||||
);
|
||||
|
||||
EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq #(
|
||||
.SYNC_RESET (0),
|
||||
.FIFO_MEM_TYPE (0)
|
||||
) timing_adt (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
|
||||
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // input, width = 8, in.data
|
||||
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // input, width = 1, .valid
|
||||
.out_data (timing_adt_out_data), // output, width = 8, out.data
|
||||
.out_valid (timing_adt_out_valid), // output, width = 1, .valid
|
||||
.out_ready (timing_adt_out_ready) // input, width = 1, .ready
|
||||
);
|
||||
|
||||
EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq #(
|
||||
.SYMBOLS_PER_BEAT (1),
|
||||
.BITS_PER_SYMBOL (8),
|
||||
.FIFO_DEPTH (64),
|
||||
.CHANNEL_WIDTH (0),
|
||||
.ERROR_WIDTH (0),
|
||||
.USE_PACKETS (0),
|
||||
.USE_FILL_LEVEL (0),
|
||||
.EMPTY_LATENCY (3),
|
||||
.USE_MEMORY_BLOCKS (1),
|
||||
.USE_STORE_FORWARD (0),
|
||||
.USE_ALMOST_FULL_IF (0),
|
||||
.USE_ALMOST_EMPTY_IF (0),
|
||||
.EMPTY_WIDTH (1),
|
||||
.MEM_TYPE ("M20K"),
|
||||
.SYNC_RESET (0)
|
||||
) fifo (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset (rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset
|
||||
.in_data (timing_adt_out_data), // input, width = 8, in.data
|
||||
.in_valid (timing_adt_out_valid), // input, width = 1, .valid
|
||||
.in_ready (timing_adt_out_ready), // output, width = 1, .ready
|
||||
.out_data (fifo_out_data), // output, width = 8, out.data
|
||||
.out_valid (fifo_out_valid), // output, width = 1, .valid
|
||||
.out_ready (fifo_out_ready), // input, width = 1, .ready
|
||||
.csr_address (2'b00), // (terminated),
|
||||
.csr_read (1'b0), // (terminated),
|
||||
.csr_write (1'b0), // (terminated),
|
||||
.csr_readdata (), // (terminated),
|
||||
.csr_writedata (32'b00000000000000000000000000000000), // (terminated),
|
||||
.almost_full_data (), // (terminated),
|
||||
.almost_empty_data (), // (terminated),
|
||||
.in_startofpacket (1'b0), // (terminated),
|
||||
.in_endofpacket (1'b0), // (terminated),
|
||||
.out_startofpacket (), // (terminated),
|
||||
.out_endofpacket (), // (terminated),
|
||||
.in_empty (1'b0), // (terminated),
|
||||
.out_empty (), // (terminated),
|
||||
.in_error (1'b0), // (terminated),
|
||||
.out_error (), // (terminated),
|
||||
.in_channel (1'b0), // (terminated),
|
||||
.out_channel () // (terminated),
|
||||
);
|
||||
|
||||
altera_avalon_st_bytes_to_packets #(
|
||||
.CHANNEL_WIDTH (8),
|
||||
.ENCODING (0)
|
||||
) b2p (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
|
||||
.out_channel (b2p_out_packets_stream_channel), // output, width = 8, out_packets_stream.channel
|
||||
.out_ready (b2p_out_packets_stream_ready), // input, width = 1, .ready
|
||||
.out_valid (b2p_out_packets_stream_valid), // output, width = 1, .valid
|
||||
.out_data (b2p_out_packets_stream_data), // output, width = 8, .data
|
||||
.out_startofpacket (b2p_out_packets_stream_startofpacket), // output, width = 1, .startofpacket
|
||||
.out_endofpacket (b2p_out_packets_stream_endofpacket), // output, width = 1, .endofpacket
|
||||
.in_ready (fifo_out_ready), // output, width = 1, in_bytes_stream.ready
|
||||
.in_valid (fifo_out_valid), // input, width = 1, .valid
|
||||
.in_data (fifo_out_data) // input, width = 8, .data
|
||||
);
|
||||
|
||||
altera_avalon_st_packets_to_bytes #(
|
||||
.CHANNEL_WIDTH (8),
|
||||
.ENCODING (0)
|
||||
) p2b (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
|
||||
.in_ready (p2b_adapter_out_ready), // output, width = 1, in_packets_stream.ready
|
||||
.in_valid (p2b_adapter_out_valid), // input, width = 1, .valid
|
||||
.in_data (p2b_adapter_out_data), // input, width = 8, .data
|
||||
.in_channel (p2b_adapter_out_channel), // input, width = 8, .channel
|
||||
.in_startofpacket (p2b_adapter_out_startofpacket), // input, width = 1, .startofpacket
|
||||
.in_endofpacket (p2b_adapter_out_endofpacket), // input, width = 1, .endofpacket
|
||||
.out_ready (p2b_out_bytes_stream_ready), // input, width = 1, out_bytes_stream.ready
|
||||
.out_valid (p2b_out_bytes_stream_valid), // output, width = 1, .valid
|
||||
.out_data (p2b_out_bytes_stream_data) // output, width = 8, .data
|
||||
);
|
||||
|
||||
altera_avalon_packets_to_master #(
|
||||
.FAST_VER (0),
|
||||
.FIFO_DEPTHS (2),
|
||||
.FIFO_WIDTHU (1)
|
||||
) transacto (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
|
||||
.out_ready (transacto_out_stream_ready), // input, width = 1, out_stream.ready
|
||||
.out_valid (transacto_out_stream_valid), // output, width = 1, .valid
|
||||
.out_data (transacto_out_stream_data), // output, width = 8, .data
|
||||
.out_startofpacket (transacto_out_stream_startofpacket), // output, width = 1, .startofpacket
|
||||
.out_endofpacket (transacto_out_stream_endofpacket), // output, width = 1, .endofpacket
|
||||
.in_ready (b2p_adapter_out_ready), // output, width = 1, in_stream.ready
|
||||
.in_valid (b2p_adapter_out_valid), // input, width = 1, .valid
|
||||
.in_data (b2p_adapter_out_data), // input, width = 8, .data
|
||||
.in_startofpacket (b2p_adapter_out_startofpacket), // input, width = 1, .startofpacket
|
||||
.in_endofpacket (b2p_adapter_out_endofpacket), // input, width = 1, .endofpacket
|
||||
.address (master_address), // output, width = 32, avalon_master.address
|
||||
.readdata (master_readdata), // input, width = 32, .readdata
|
||||
.read (master_read), // output, width = 1, .read
|
||||
.write (master_write), // output, width = 1, .write
|
||||
.writedata (master_writedata), // output, width = 32, .writedata
|
||||
.waitrequest (master_waitrequest), // input, width = 1, .waitrequest
|
||||
.readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
|
||||
.byteenable (master_byteenable) // output, width = 4, .byteenable
|
||||
);
|
||||
|
||||
EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy b2p_adapter (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
|
||||
.in_data (b2p_out_packets_stream_data), // input, width = 8, in.data
|
||||
.in_valid (b2p_out_packets_stream_valid), // input, width = 1, .valid
|
||||
.in_ready (b2p_out_packets_stream_ready), // output, width = 1, .ready
|
||||
.in_startofpacket (b2p_out_packets_stream_startofpacket), // input, width = 1, .startofpacket
|
||||
.in_endofpacket (b2p_out_packets_stream_endofpacket), // input, width = 1, .endofpacket
|
||||
.in_channel (b2p_out_packets_stream_channel), // input, width = 8, .channel
|
||||
.out_data (b2p_adapter_out_data), // output, width = 8, out.data
|
||||
.out_valid (b2p_adapter_out_valid), // output, width = 1, .valid
|
||||
.out_ready (b2p_adapter_out_ready), // input, width = 1, .ready
|
||||
.out_startofpacket (b2p_adapter_out_startofpacket), // output, width = 1, .startofpacket
|
||||
.out_endofpacket (b2p_adapter_out_endofpacket) // output, width = 1, .endofpacket
|
||||
);
|
||||
|
||||
EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a p2b_adapter (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
|
||||
.in_data (transacto_out_stream_data), // input, width = 8, in.data
|
||||
.in_valid (transacto_out_stream_valid), // input, width = 1, .valid
|
||||
.in_ready (transacto_out_stream_ready), // output, width = 1, .ready
|
||||
.in_startofpacket (transacto_out_stream_startofpacket), // input, width = 1, .startofpacket
|
||||
.in_endofpacket (transacto_out_stream_endofpacket), // input, width = 1, .endofpacket
|
||||
.out_data (p2b_adapter_out_data), // output, width = 8, out.data
|
||||
.out_valid (p2b_adapter_out_valid), // output, width = 1, .valid
|
||||
.out_ready (p2b_adapter_out_ready), // input, width = 1, .ready
|
||||
.out_startofpacket (p2b_adapter_out_startofpacket), // output, width = 1, .startofpacket
|
||||
.out_endofpacket (p2b_adapter_out_endofpacket), // output, width = 1, .endofpacket
|
||||
.out_channel (p2b_adapter_out_channel) // output, width = 8, .channel
|
||||
);
|
||||
|
||||
altera_reset_controller #(
|
||||
.NUM_RESET_INPUTS (1),
|
||||
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
||||
.SYNC_DEPTH (2),
|
||||
.RESET_REQUEST_PRESENT (0),
|
||||
.RESET_REQ_WAIT_TIME (1),
|
||||
.MIN_RST_ASSERTION_TIME (3),
|
||||
.RESET_REQ_EARLY_DSRT_TIME (1),
|
||||
.USE_RESET_REQUEST_IN0 (0),
|
||||
.USE_RESET_REQUEST_IN1 (0),
|
||||
.USE_RESET_REQUEST_IN2 (0),
|
||||
.USE_RESET_REQUEST_IN3 (0),
|
||||
.USE_RESET_REQUEST_IN4 (0),
|
||||
.USE_RESET_REQUEST_IN5 (0),
|
||||
.USE_RESET_REQUEST_IN6 (0),
|
||||
.USE_RESET_REQUEST_IN7 (0),
|
||||
.USE_RESET_REQUEST_IN8 (0),
|
||||
.USE_RESET_REQUEST_IN9 (0),
|
||||
.USE_RESET_REQUEST_IN10 (0),
|
||||
.USE_RESET_REQUEST_IN11 (0),
|
||||
.USE_RESET_REQUEST_IN12 (0),
|
||||
.USE_RESET_REQUEST_IN13 (0),
|
||||
.USE_RESET_REQUEST_IN14 (0),
|
||||
.USE_RESET_REQUEST_IN15 (0),
|
||||
.ADAPT_RESET_REQUEST (0)
|
||||
) rst_controller (
|
||||
.reset_in0 (clk_reset_reset), // input, width = 1, reset_in0.reset
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_out (rst_controller_reset_out_reset), // output, width = 1, reset_out.reset
|
||||
.reset_req (), // (terminated),
|
||||
.reset_req_in0 (1'b0), // (terminated),
|
||||
.reset_in1 (1'b0), // (terminated),
|
||||
.reset_req_in1 (1'b0), // (terminated),
|
||||
.reset_in2 (1'b0), // (terminated),
|
||||
.reset_req_in2 (1'b0), // (terminated),
|
||||
.reset_in3 (1'b0), // (terminated),
|
||||
.reset_req_in3 (1'b0), // (terminated),
|
||||
.reset_in4 (1'b0), // (terminated),
|
||||
.reset_req_in4 (1'b0), // (terminated),
|
||||
.reset_in5 (1'b0), // (terminated),
|
||||
.reset_req_in5 (1'b0), // (terminated),
|
||||
.reset_in6 (1'b0), // (terminated),
|
||||
.reset_req_in6 (1'b0), // (terminated),
|
||||
.reset_in7 (1'b0), // (terminated),
|
||||
.reset_req_in7 (1'b0), // (terminated),
|
||||
.reset_in8 (1'b0), // (terminated),
|
||||
.reset_req_in8 (1'b0), // (terminated),
|
||||
.reset_in9 (1'b0), // (terminated),
|
||||
.reset_req_in9 (1'b0), // (terminated),
|
||||
.reset_in10 (1'b0), // (terminated),
|
||||
.reset_req_in10 (1'b0), // (terminated),
|
||||
.reset_in11 (1'b0), // (terminated),
|
||||
.reset_req_in11 (1'b0), // (terminated),
|
||||
.reset_in12 (1'b0), // (terminated),
|
||||
.reset_req_in12 (1'b0), // (terminated),
|
||||
.reset_in13 (1'b0), // (terminated),
|
||||
.reset_req_in13 (1'b0), // (terminated),
|
||||
.reset_in14 (1'b0), // (terminated),
|
||||
.reset_req_in14 (1'b0), // (terminated),
|
||||
.reset_in15 (1'b0), // (terminated),
|
||||
.reset_req_in15 (1'b0) // (terminated),
|
||||
);
|
||||
|
||||
endmodule
|
||||
+366
@@ -0,0 +1,366 @@
|
||||
// EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi.v
|
||||
|
||||
// This file was auto-generated from alt_mem_if_jtag_master_hw.tcl. If you edit it your changes
|
||||
// will probably be lost.
|
||||
//
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi #(
|
||||
parameter USE_PLI = 0,
|
||||
parameter PLI_PORT = 50000,
|
||||
parameter FIFO_DEPTHS = 2
|
||||
) (
|
||||
input wire clk_clk, // clk.clk, Clock Input
|
||||
input wire clk_reset_reset, // clk_reset.reset, Reset Input
|
||||
output wire master_reset_reset, // master_reset.reset, Reset Output
|
||||
output wire [31:0] master_address, // master.address, Address output of Avalon Memory Mapped Host
|
||||
input wire [31:0] master_readdata, // .readdata, Read Data input to Avalon Memory Mapped Host
|
||||
output wire master_read, // .read, Read command from Avalon Memory Mapped Host
|
||||
output wire master_write, // .write, Write command from Avalon Memory Mapped Host
|
||||
output wire [31:0] master_writedata, // .writedata, Write Data from Avalon Memory Mapped Host
|
||||
input wire master_waitrequest, // .waitrequest, Wait request from Avalon Memory Mapped Agent, indicates agent is not ready
|
||||
input wire master_readdatavalid, // .readdatavalid, Valid read data indication from Avalon Memory Mapped Agent
|
||||
output wire [3:0] master_byteenable // .byteenable, Indicates valid write data/read data location
|
||||
);
|
||||
|
||||
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
|
||||
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
|
||||
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
|
||||
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
|
||||
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
|
||||
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
|
||||
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
|
||||
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
|
||||
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
|
||||
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
|
||||
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
|
||||
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
|
||||
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
|
||||
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
|
||||
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
|
||||
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
|
||||
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
|
||||
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
|
||||
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
|
||||
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
|
||||
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
|
||||
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
|
||||
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
|
||||
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
|
||||
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
|
||||
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
|
||||
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
|
||||
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
|
||||
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
|
||||
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
|
||||
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
|
||||
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
|
||||
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
|
||||
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
|
||||
|
||||
generate
|
||||
// If any of the display statements (or deliberately broken
|
||||
// instantiations) within this generate block triggers then this module
|
||||
// has been instantiated this module with a set of parameters different
|
||||
// from those it was generated for. This will usually result in a
|
||||
// non-functioning system.
|
||||
if (USE_PLI != 0)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
use_pli_check ( .error(1'b1) );
|
||||
end
|
||||
if (PLI_PORT != 50000)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
pli_port_check ( .error(1'b1) );
|
||||
end
|
||||
if (FIFO_DEPTHS != 2)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
fifo_depths_check ( .error(1'b1) );
|
||||
end
|
||||
endgenerate
|
||||
|
||||
altera_avalon_st_jtag_interface #(
|
||||
.PURPOSE (1),
|
||||
.UPSTREAM_FIFO_SIZE (0),
|
||||
.DOWNSTREAM_FIFO_SIZE (64),
|
||||
.MGMT_CHANNEL_WIDTH (-1),
|
||||
.EXPORT_JTAG (0),
|
||||
.USE_PLI (0),
|
||||
.PLI_PORT (50000)
|
||||
) jtag_phy_embedded_in_jtag_master (
|
||||
.clk (clk_clk), // input, width = 1, clock.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clock_reset.reset_n
|
||||
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // output, width = 8, src.data
|
||||
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // output, width = 1, .valid
|
||||
.sink_data (p2b_out_bytes_stream_data), // input, width = 8, sink.data
|
||||
.sink_valid (p2b_out_bytes_stream_valid), // input, width = 1, .valid
|
||||
.sink_ready (p2b_out_bytes_stream_ready), // output, width = 1, .ready
|
||||
.resetrequest (master_reset_reset), // output, width = 1, resetrequest.reset
|
||||
.source_ready (1'b1), // (terminated),
|
||||
.mgmt_valid (), // (terminated),
|
||||
.mgmt_channel (), // (terminated),
|
||||
.mgmt_data (), // (terminated),
|
||||
.jtag_tck (1'b0), // (terminated),
|
||||
.jtag_tms (1'b0), // (terminated),
|
||||
.jtag_tdi (1'b0), // (terminated),
|
||||
.jtag_tdo (), // (terminated),
|
||||
.jtag_ena (1'b0), // (terminated),
|
||||
.jtag_usr1 (1'b0), // (terminated),
|
||||
.jtag_clr (1'b0), // (terminated),
|
||||
.jtag_clrn (1'b0), // (terminated),
|
||||
.jtag_state_tlr (1'b0), // (terminated),
|
||||
.jtag_state_rti (1'b0), // (terminated),
|
||||
.jtag_state_sdrs (1'b0), // (terminated),
|
||||
.jtag_state_cdr (1'b0), // (terminated),
|
||||
.jtag_state_sdr (1'b0), // (terminated),
|
||||
.jtag_state_e1dr (1'b0), // (terminated),
|
||||
.jtag_state_pdr (1'b0), // (terminated),
|
||||
.jtag_state_e2dr (1'b0), // (terminated),
|
||||
.jtag_state_udr (1'b0), // (terminated),
|
||||
.jtag_state_sirs (1'b0), // (terminated),
|
||||
.jtag_state_cir (1'b0), // (terminated),
|
||||
.jtag_state_sir (1'b0), // (terminated),
|
||||
.jtag_state_e1ir (1'b0), // (terminated),
|
||||
.jtag_state_pir (1'b0), // (terminated),
|
||||
.jtag_state_e2ir (1'b0), // (terminated),
|
||||
.jtag_state_uir (1'b0), // (terminated),
|
||||
.jtag_ir_in (3'b000), // (terminated),
|
||||
.jtag_irq (), // (terminated),
|
||||
.jtag_ir_out () // (terminated),
|
||||
);
|
||||
|
||||
EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq #(
|
||||
.SYNC_RESET (0),
|
||||
.FIFO_MEM_TYPE (0)
|
||||
) timing_adt (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
|
||||
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // input, width = 8, in.data
|
||||
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // input, width = 1, .valid
|
||||
.out_data (timing_adt_out_data), // output, width = 8, out.data
|
||||
.out_valid (timing_adt_out_valid), // output, width = 1, .valid
|
||||
.out_ready (timing_adt_out_ready) // input, width = 1, .ready
|
||||
);
|
||||
|
||||
EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq #(
|
||||
.SYMBOLS_PER_BEAT (1),
|
||||
.BITS_PER_SYMBOL (8),
|
||||
.FIFO_DEPTH (64),
|
||||
.CHANNEL_WIDTH (0),
|
||||
.ERROR_WIDTH (0),
|
||||
.USE_PACKETS (0),
|
||||
.USE_FILL_LEVEL (0),
|
||||
.EMPTY_LATENCY (3),
|
||||
.USE_MEMORY_BLOCKS (1),
|
||||
.USE_STORE_FORWARD (0),
|
||||
.USE_ALMOST_FULL_IF (0),
|
||||
.USE_ALMOST_EMPTY_IF (0),
|
||||
.EMPTY_WIDTH (1),
|
||||
.MEM_TYPE ("M20K"),
|
||||
.SYNC_RESET (0)
|
||||
) fifo (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset (rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset
|
||||
.in_data (timing_adt_out_data), // input, width = 8, in.data
|
||||
.in_valid (timing_adt_out_valid), // input, width = 1, .valid
|
||||
.in_ready (timing_adt_out_ready), // output, width = 1, .ready
|
||||
.out_data (fifo_out_data), // output, width = 8, out.data
|
||||
.out_valid (fifo_out_valid), // output, width = 1, .valid
|
||||
.out_ready (fifo_out_ready), // input, width = 1, .ready
|
||||
.csr_address (2'b00), // (terminated),
|
||||
.csr_read (1'b0), // (terminated),
|
||||
.csr_write (1'b0), // (terminated),
|
||||
.csr_readdata (), // (terminated),
|
||||
.csr_writedata (32'b00000000000000000000000000000000), // (terminated),
|
||||
.almost_full_data (), // (terminated),
|
||||
.almost_empty_data (), // (terminated),
|
||||
.in_startofpacket (1'b0), // (terminated),
|
||||
.in_endofpacket (1'b0), // (terminated),
|
||||
.out_startofpacket (), // (terminated),
|
||||
.out_endofpacket (), // (terminated),
|
||||
.in_empty (1'b0), // (terminated),
|
||||
.out_empty (), // (terminated),
|
||||
.in_error (1'b0), // (terminated),
|
||||
.out_error (), // (terminated),
|
||||
.in_channel (1'b0), // (terminated),
|
||||
.out_channel () // (terminated),
|
||||
);
|
||||
|
||||
altera_avalon_st_bytes_to_packets #(
|
||||
.CHANNEL_WIDTH (8),
|
||||
.ENCODING (0)
|
||||
) b2p (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
|
||||
.out_channel (b2p_out_packets_stream_channel), // output, width = 8, out_packets_stream.channel
|
||||
.out_ready (b2p_out_packets_stream_ready), // input, width = 1, .ready
|
||||
.out_valid (b2p_out_packets_stream_valid), // output, width = 1, .valid
|
||||
.out_data (b2p_out_packets_stream_data), // output, width = 8, .data
|
||||
.out_startofpacket (b2p_out_packets_stream_startofpacket), // output, width = 1, .startofpacket
|
||||
.out_endofpacket (b2p_out_packets_stream_endofpacket), // output, width = 1, .endofpacket
|
||||
.in_ready (fifo_out_ready), // output, width = 1, in_bytes_stream.ready
|
||||
.in_valid (fifo_out_valid), // input, width = 1, .valid
|
||||
.in_data (fifo_out_data) // input, width = 8, .data
|
||||
);
|
||||
|
||||
altera_avalon_st_packets_to_bytes #(
|
||||
.CHANNEL_WIDTH (8),
|
||||
.ENCODING (0)
|
||||
) p2b (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
|
||||
.in_ready (p2b_adapter_out_ready), // output, width = 1, in_packets_stream.ready
|
||||
.in_valid (p2b_adapter_out_valid), // input, width = 1, .valid
|
||||
.in_data (p2b_adapter_out_data), // input, width = 8, .data
|
||||
.in_channel (p2b_adapter_out_channel), // input, width = 8, .channel
|
||||
.in_startofpacket (p2b_adapter_out_startofpacket), // input, width = 1, .startofpacket
|
||||
.in_endofpacket (p2b_adapter_out_endofpacket), // input, width = 1, .endofpacket
|
||||
.out_ready (p2b_out_bytes_stream_ready), // input, width = 1, out_bytes_stream.ready
|
||||
.out_valid (p2b_out_bytes_stream_valid), // output, width = 1, .valid
|
||||
.out_data (p2b_out_bytes_stream_data) // output, width = 8, .data
|
||||
);
|
||||
|
||||
altera_avalon_packets_to_master #(
|
||||
.FAST_VER (0),
|
||||
.FIFO_DEPTHS (2),
|
||||
.FIFO_WIDTHU (1)
|
||||
) transacto (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
|
||||
.out_ready (transacto_out_stream_ready), // input, width = 1, out_stream.ready
|
||||
.out_valid (transacto_out_stream_valid), // output, width = 1, .valid
|
||||
.out_data (transacto_out_stream_data), // output, width = 8, .data
|
||||
.out_startofpacket (transacto_out_stream_startofpacket), // output, width = 1, .startofpacket
|
||||
.out_endofpacket (transacto_out_stream_endofpacket), // output, width = 1, .endofpacket
|
||||
.in_ready (b2p_adapter_out_ready), // output, width = 1, in_stream.ready
|
||||
.in_valid (b2p_adapter_out_valid), // input, width = 1, .valid
|
||||
.in_data (b2p_adapter_out_data), // input, width = 8, .data
|
||||
.in_startofpacket (b2p_adapter_out_startofpacket), // input, width = 1, .startofpacket
|
||||
.in_endofpacket (b2p_adapter_out_endofpacket), // input, width = 1, .endofpacket
|
||||
.address (master_address), // output, width = 32, avalon_master.address
|
||||
.readdata (master_readdata), // input, width = 32, .readdata
|
||||
.read (master_read), // output, width = 1, .read
|
||||
.write (master_write), // output, width = 1, .write
|
||||
.writedata (master_writedata), // output, width = 32, .writedata
|
||||
.waitrequest (master_waitrequest), // input, width = 1, .waitrequest
|
||||
.readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
|
||||
.byteenable (master_byteenable) // output, width = 4, .byteenable
|
||||
);
|
||||
|
||||
EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy b2p_adapter (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
|
||||
.in_data (b2p_out_packets_stream_data), // input, width = 8, in.data
|
||||
.in_valid (b2p_out_packets_stream_valid), // input, width = 1, .valid
|
||||
.in_ready (b2p_out_packets_stream_ready), // output, width = 1, .ready
|
||||
.in_startofpacket (b2p_out_packets_stream_startofpacket), // input, width = 1, .startofpacket
|
||||
.in_endofpacket (b2p_out_packets_stream_endofpacket), // input, width = 1, .endofpacket
|
||||
.in_channel (b2p_out_packets_stream_channel), // input, width = 8, .channel
|
||||
.out_data (b2p_adapter_out_data), // output, width = 8, out.data
|
||||
.out_valid (b2p_adapter_out_valid), // output, width = 1, .valid
|
||||
.out_ready (b2p_adapter_out_ready), // input, width = 1, .ready
|
||||
.out_startofpacket (b2p_adapter_out_startofpacket), // output, width = 1, .startofpacket
|
||||
.out_endofpacket (b2p_adapter_out_endofpacket) // output, width = 1, .endofpacket
|
||||
);
|
||||
|
||||
EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a p2b_adapter (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
|
||||
.in_data (transacto_out_stream_data), // input, width = 8, in.data
|
||||
.in_valid (transacto_out_stream_valid), // input, width = 1, .valid
|
||||
.in_ready (transacto_out_stream_ready), // output, width = 1, .ready
|
||||
.in_startofpacket (transacto_out_stream_startofpacket), // input, width = 1, .startofpacket
|
||||
.in_endofpacket (transacto_out_stream_endofpacket), // input, width = 1, .endofpacket
|
||||
.out_data (p2b_adapter_out_data), // output, width = 8, out.data
|
||||
.out_valid (p2b_adapter_out_valid), // output, width = 1, .valid
|
||||
.out_ready (p2b_adapter_out_ready), // input, width = 1, .ready
|
||||
.out_startofpacket (p2b_adapter_out_startofpacket), // output, width = 1, .startofpacket
|
||||
.out_endofpacket (p2b_adapter_out_endofpacket), // output, width = 1, .endofpacket
|
||||
.out_channel (p2b_adapter_out_channel) // output, width = 8, .channel
|
||||
);
|
||||
|
||||
altera_reset_controller #(
|
||||
.NUM_RESET_INPUTS (1),
|
||||
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
||||
.SYNC_DEPTH (2),
|
||||
.RESET_REQUEST_PRESENT (0),
|
||||
.RESET_REQ_WAIT_TIME (1),
|
||||
.MIN_RST_ASSERTION_TIME (3),
|
||||
.RESET_REQ_EARLY_DSRT_TIME (1),
|
||||
.USE_RESET_REQUEST_IN0 (0),
|
||||
.USE_RESET_REQUEST_IN1 (0),
|
||||
.USE_RESET_REQUEST_IN2 (0),
|
||||
.USE_RESET_REQUEST_IN3 (0),
|
||||
.USE_RESET_REQUEST_IN4 (0),
|
||||
.USE_RESET_REQUEST_IN5 (0),
|
||||
.USE_RESET_REQUEST_IN6 (0),
|
||||
.USE_RESET_REQUEST_IN7 (0),
|
||||
.USE_RESET_REQUEST_IN8 (0),
|
||||
.USE_RESET_REQUEST_IN9 (0),
|
||||
.USE_RESET_REQUEST_IN10 (0),
|
||||
.USE_RESET_REQUEST_IN11 (0),
|
||||
.USE_RESET_REQUEST_IN12 (0),
|
||||
.USE_RESET_REQUEST_IN13 (0),
|
||||
.USE_RESET_REQUEST_IN14 (0),
|
||||
.USE_RESET_REQUEST_IN15 (0),
|
||||
.ADAPT_RESET_REQUEST (0)
|
||||
) rst_controller (
|
||||
.reset_in0 (clk_reset_reset), // input, width = 1, reset_in0.reset
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_out (rst_controller_reset_out_reset), // output, width = 1, reset_out.reset
|
||||
.reset_req (), // (terminated),
|
||||
.reset_req_in0 (1'b0), // (terminated),
|
||||
.reset_in1 (1'b0), // (terminated),
|
||||
.reset_req_in1 (1'b0), // (terminated),
|
||||
.reset_in2 (1'b0), // (terminated),
|
||||
.reset_req_in2 (1'b0), // (terminated),
|
||||
.reset_in3 (1'b0), // (terminated),
|
||||
.reset_req_in3 (1'b0), // (terminated),
|
||||
.reset_in4 (1'b0), // (terminated),
|
||||
.reset_req_in4 (1'b0), // (terminated),
|
||||
.reset_in5 (1'b0), // (terminated),
|
||||
.reset_req_in5 (1'b0), // (terminated),
|
||||
.reset_in6 (1'b0), // (terminated),
|
||||
.reset_req_in6 (1'b0), // (terminated),
|
||||
.reset_in7 (1'b0), // (terminated),
|
||||
.reset_req_in7 (1'b0), // (terminated),
|
||||
.reset_in8 (1'b0), // (terminated),
|
||||
.reset_req_in8 (1'b0), // (terminated),
|
||||
.reset_in9 (1'b0), // (terminated),
|
||||
.reset_req_in9 (1'b0), // (terminated),
|
||||
.reset_in10 (1'b0), // (terminated),
|
||||
.reset_req_in10 (1'b0), // (terminated),
|
||||
.reset_in11 (1'b0), // (terminated),
|
||||
.reset_req_in11 (1'b0), // (terminated),
|
||||
.reset_in12 (1'b0), // (terminated),
|
||||
.reset_req_in12 (1'b0), // (terminated),
|
||||
.reset_in13 (1'b0), // (terminated),
|
||||
.reset_req_in13 (1'b0), // (terminated),
|
||||
.reset_in14 (1'b0), // (terminated),
|
||||
.reset_req_in14 (1'b0), // (terminated),
|
||||
.reset_in15 (1'b0), // (terminated),
|
||||
.reset_req_in15 (1'b0) // (terminated),
|
||||
);
|
||||
|
||||
endmodule
|
||||
+1244
File diff suppressed because it is too large
Load Diff
+1244
File diff suppressed because it is too large
Load Diff
+1392
File diff suppressed because it is too large
Load Diff
+1392
File diff suppressed because it is too large
Load Diff
+213
@@ -0,0 +1,213 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Bytes to Packet
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_bytes_to_packets
|
||||
//if ENCODING ==0, CHANNEL_WIDTH must be 8
|
||||
//else CHANNEL_WIDTH can be from 0 to 127
|
||||
#( parameter CHANNEL_WIDTH = 8,
|
||||
parameter ENCODING = 0 )
|
||||
(
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST out with packets
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data,
|
||||
output reg [CHANNEL_WIDTH-1: 0] out_channel,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc, received_channel, received_varchannel;
|
||||
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
|
||||
|
||||
// data out mux.
|
||||
// we need it twice (data & channel out), so use a wire here
|
||||
wire [7:0] data_out;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign sop_char = (in_data == 8'h7a);
|
||||
assign eop_char = (in_data == 8'h7b);
|
||||
assign channel_char = (in_data == 8'h7c);
|
||||
assign escape_char = (in_data == 8'h7d);
|
||||
|
||||
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
|
||||
|
||||
generate
|
||||
if (CHANNEL_WIDTH == 0) begin
|
||||
// Synchorous block -- reset and registers
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end else begin
|
||||
// we take data when in_valid and in_ready
|
||||
if (in_valid & in_ready) begin
|
||||
if (received_esc) begin
|
||||
//if we got esc char, after next byte is consumed, quit esc mode
|
||||
if (out_ready) received_esc <= 0;
|
||||
end else begin
|
||||
if (escape_char) received_esc <= 1;
|
||||
if (sop_char) out_startofpacket <= 1;
|
||||
if (eop_char) out_endofpacket <= 1;
|
||||
end
|
||||
if (out_ready & out_valid) begin
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Combinational block for in_ready and out_valid
|
||||
always @* begin
|
||||
//we choose not to pipeline here. We can process special characters when
|
||||
//in_ready, but in a chain of microcores, backpressure path is usually
|
||||
//time critical, so we keep it simple here.
|
||||
in_ready = out_ready;
|
||||
|
||||
//out_valid when in_valid, except when we are processing the special
|
||||
//characters. However, if we are in escape received mode, then we are
|
||||
//valid
|
||||
out_valid = 0;
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
out_valid = 1;
|
||||
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
|
||||
end
|
||||
out_data = data_out;
|
||||
end
|
||||
|
||||
end else begin
|
||||
assign varchannelesc_char = in_data[7];
|
||||
// Synchorous block -- reset and registers
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
received_channel <= 0;
|
||||
received_varchannel <= 0;
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end else begin
|
||||
// we take data when in_valid and in_ready
|
||||
if (in_valid & in_ready) begin
|
||||
if (received_esc) begin
|
||||
//if we got esc char, after next byte is consumed, quit esc mode
|
||||
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
|
||||
end else begin
|
||||
if (escape_char) received_esc <= 1;
|
||||
if (sop_char) out_startofpacket <= 1;
|
||||
if (eop_char) out_endofpacket <= 1;
|
||||
if (channel_char & ENCODING ) received_varchannel <= 1;
|
||||
if (channel_char & ~ENCODING) received_channel <= 1;
|
||||
end
|
||||
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
|
||||
received_channel <= 0;
|
||||
end
|
||||
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
|
||||
received_varchannel <= 0;
|
||||
end
|
||||
if (out_ready & out_valid) begin
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Combinational block for in_ready and out_valid
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = 0;
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
out_valid = 1;
|
||||
if (received_esc) begin
|
||||
if (received_channel | received_varchannel) out_valid = 0;
|
||||
end else begin
|
||||
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
|
||||
end
|
||||
end
|
||||
out_data = data_out;
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
// Channel block
|
||||
generate
|
||||
if (CHANNEL_WIDTH == 0) begin
|
||||
always @(posedge clk) begin
|
||||
out_channel <= 'h0;
|
||||
end
|
||||
|
||||
end else if (CHANNEL_WIDTH < 8) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
out_channel <= 'h0;
|
||||
end else begin
|
||||
if (in_ready & in_valid) begin
|
||||
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
|
||||
out_channel <= 'h0;
|
||||
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
|
||||
// Shifting out only the required bits
|
||||
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
out_channel <= 'h0;
|
||||
end else begin
|
||||
if (in_ready & in_valid) begin
|
||||
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
|
||||
out_channel <= data_out;
|
||||
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
|
||||
// Variable Channel Encoding always setting to 0 before begin to shift the channel in
|
||||
out_channel <= 'h0;
|
||||
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
|
||||
// Shifting out the lower 7 bits
|
||||
out_channel <= out_channel <<7;
|
||||
out_channel[6:0] <= data_out[6:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3ToCi97F+O4Jtd7lyb3HX6P4erEvg2ALdvMtyo/GHuQ/3I7pLrfwffqBLzWXXFs+6LextEIKaErTIQtRI5NPblwu4T4zWVtUAvzj5xOcu8gxOUxITJg1JZu+hgblTes2OH1rZVOYEc0eF6RV6M6mu1E0UjegEjjIH8WWlbRMFzdxz1MD+/1DOZKc2X+0imGI5dm+g8REigzqPK2bFQ27ymsU332zAZHeycYzNJZHNdp4UR/78MkHalkV8QT8ArFIuR8WyWGAcupKZKTKZDQDkHR68+dbi95JnS5K2TO0ztqaqbDaf+2QVKSQJPXXVst31OaRxADe5QDF+gWz6G2CGvrh9brNfZvLSIZIq0RDVcRDDWS9wykYAHrdn7oaVfa7Ocv3ZDY7SQC/MrrrmS7+EAwIxzdtdsmo69WDKjrhL7ao98J9L0HeZ35yJn4tmTjEgevmu0Pd++DbtOec2XvEvqoiObWXn1Ez0VgwNU0wYDLKlVz7bBTb3mS9dHgjyfaienlH7CJVn1dLF4TzwJbL1D0bmQWRhgjGJNwgPEO9iqaXZyUEDXTP6gVXMMdxaDz0GZsdz300XMv5zqF+qo557ZSiJ0QxsOcSxuNw/WvzP2stoPcFXwc0saeVFmka2V3RXgBKax4pG6q0+/KW6rpO8xAQ8EsXo8FdGHsW/FygMpuPqtz7/TFsXjrm9eJTLeTjS+bxhFsupTQd9HMcfTpXgiOk5Z4hPDwhwwe5/h7U5W/swzbB8EgT5oF/i14xZVWes6eqE3Jy3EZgj3vnUJyYO8OG7N4DNlBHxIYTfcCyegMVe5Q5+ZuX6J3X1CbMzwmWcu3T6JxSiezjpbS9gOOZ1l4i9903qMP1opGRzv8ngX55HNkAwpD3G7mshzVBGRG9BlUlq4GPpHwNHMVzXY1m12hDrSsAv9FQUOLqlKkgwsPXJYdp4oGejAaw/C0MZuVGZl8CKozUoaXUCLf3ejkN55fpY5hwHQIQEp/7otAd68JvUDbawCY8SJwht0NDxWww"
|
||||
`endif
|
||||
+213
@@ -0,0 +1,213 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Bytes to Packet
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_bytes_to_packets
|
||||
//if ENCODING ==0, CHANNEL_WIDTH must be 8
|
||||
//else CHANNEL_WIDTH can be from 0 to 127
|
||||
#( parameter CHANNEL_WIDTH = 8,
|
||||
parameter ENCODING = 0 )
|
||||
(
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST out with packets
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data,
|
||||
output reg [CHANNEL_WIDTH-1: 0] out_channel,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc, received_channel, received_varchannel;
|
||||
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
|
||||
|
||||
// data out mux.
|
||||
// we need it twice (data & channel out), so use a wire here
|
||||
wire [7:0] data_out;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign sop_char = (in_data == 8'h7a);
|
||||
assign eop_char = (in_data == 8'h7b);
|
||||
assign channel_char = (in_data == 8'h7c);
|
||||
assign escape_char = (in_data == 8'h7d);
|
||||
|
||||
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
|
||||
|
||||
generate
|
||||
if (CHANNEL_WIDTH == 0) begin
|
||||
// Synchorous block -- reset and registers
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end else begin
|
||||
// we take data when in_valid and in_ready
|
||||
if (in_valid & in_ready) begin
|
||||
if (received_esc) begin
|
||||
//if we got esc char, after next byte is consumed, quit esc mode
|
||||
if (out_ready) received_esc <= 0;
|
||||
end else begin
|
||||
if (escape_char) received_esc <= 1;
|
||||
if (sop_char) out_startofpacket <= 1;
|
||||
if (eop_char) out_endofpacket <= 1;
|
||||
end
|
||||
if (out_ready & out_valid) begin
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Combinational block for in_ready and out_valid
|
||||
always @* begin
|
||||
//we choose not to pipeline here. We can process special characters when
|
||||
//in_ready, but in a chain of microcores, backpressure path is usually
|
||||
//time critical, so we keep it simple here.
|
||||
in_ready = out_ready;
|
||||
|
||||
//out_valid when in_valid, except when we are processing the special
|
||||
//characters. However, if we are in escape received mode, then we are
|
||||
//valid
|
||||
out_valid = 0;
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
out_valid = 1;
|
||||
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
|
||||
end
|
||||
out_data = data_out;
|
||||
end
|
||||
|
||||
end else begin
|
||||
assign varchannelesc_char = in_data[7];
|
||||
// Synchorous block -- reset and registers
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
received_channel <= 0;
|
||||
received_varchannel <= 0;
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end else begin
|
||||
// we take data when in_valid and in_ready
|
||||
if (in_valid & in_ready) begin
|
||||
if (received_esc) begin
|
||||
//if we got esc char, after next byte is consumed, quit esc mode
|
||||
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
|
||||
end else begin
|
||||
if (escape_char) received_esc <= 1;
|
||||
if (sop_char) out_startofpacket <= 1;
|
||||
if (eop_char) out_endofpacket <= 1;
|
||||
if (channel_char & ENCODING ) received_varchannel <= 1;
|
||||
if (channel_char & ~ENCODING) received_channel <= 1;
|
||||
end
|
||||
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
|
||||
received_channel <= 0;
|
||||
end
|
||||
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
|
||||
received_varchannel <= 0;
|
||||
end
|
||||
if (out_ready & out_valid) begin
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Combinational block for in_ready and out_valid
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = 0;
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
out_valid = 1;
|
||||
if (received_esc) begin
|
||||
if (received_channel | received_varchannel) out_valid = 0;
|
||||
end else begin
|
||||
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
|
||||
end
|
||||
end
|
||||
out_data = data_out;
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
// Channel block
|
||||
generate
|
||||
if (CHANNEL_WIDTH == 0) begin
|
||||
always @(posedge clk) begin
|
||||
out_channel <= 'h0;
|
||||
end
|
||||
|
||||
end else if (CHANNEL_WIDTH < 8) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
out_channel <= 'h0;
|
||||
end else begin
|
||||
if (in_ready & in_valid) begin
|
||||
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
|
||||
out_channel <= 'h0;
|
||||
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
|
||||
// Shifting out only the required bits
|
||||
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
out_channel <= 'h0;
|
||||
end else begin
|
||||
if (in_ready & in_valid) begin
|
||||
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
|
||||
out_channel <= data_out;
|
||||
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
|
||||
// Variable Channel Encoding always setting to 0 before begin to shift the channel in
|
||||
out_channel <= 'h0;
|
||||
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
|
||||
// Shifting out the lower 7 bits
|
||||
out_channel <= out_channel <<7;
|
||||
out_channel[6:0] <= data_out[6:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3ToCi97F+O4Jtd7lyb3HX6P4erEvg2ALdvMtyo/GHuQ/3I7pLrfwffqBLzWXXFs+6LextEIKaErTIQtRI5NPblwu4T4zWVtUAvzj5xOcu8gxOUxITJg1JZu+hgblTes2OH1rZVOYEc0eF6RV6M6mu1E0UjegEjjIH8WWlbRMFzdxz1MD+/1DOZKc2X+0imGI5dm+g8REigzqPK2bFQ27ymsU332zAZHeycYzNJZHNdp4UR/78MkHalkV8QT8ArFIuR8WyWGAcupKZKTKZDQDkHR68+dbi95JnS5K2TO0ztqaqbDaf+2QVKSQJPXXVst31OaRxADe5QDF+gWz6G2CGvrh9brNfZvLSIZIq0RDVcRDDWS9wykYAHrdn7oaVfa7Ocv3ZDY7SQC/MrrrmS7+EAwIxzdtdsmo69WDKjrhL7ao98J9L0HeZ35yJn4tmTjEgevmu0Pd++DbtOec2XvEvqoiObWXn1Ez0VgwNU0wYDLKlVz7bBTb3mS9dHgjyfaienlH7CJVn1dLF4TzwJbL1D0bmQWRhgjGJNwgPEO9iqaXZyUEDXTP6gVXMMdxaDz0GZsdz300XMv5zqF+qo557ZSiJ0QxsOcSxuNw/WvzP2stoPcFXwc0saeVFmka2V3RXgBKax4pG6q0+/KW6rpO8xAQ8EsXo8FdGHsW/FygMpuPqtz7/TFsXjrm9eJTLeTjS+bxhFsupTQd9HMcfTpXgiOk5Z4hPDwhwwe5/h7U5W/swzbB8EgT5oF/i14xZVWes6eqE3Jy3EZgj3vnUJyYO8OG7N4DNlBHxIYTfcCyegMVe5Q5+ZuX6J3X1CbMzwmWcu3T6JxSiezjpbS9gOOZ1l4i9903qMP1opGRzv8ngX55HNkAwpD3G7mshzVBGRG9BlUlq4GPpHwNHMVzXY1m12hDrSsAv9FQUOLqlKkgwsPXJYdp4oGejAaw/C0MZuVGZl8CKozUoaXUCLf3ejkN55fpY5hwHQIQEp/7otAd68JvUDbawCY8SJwht0NDxWww"
|
||||
`endif
|
||||
+263
@@ -0,0 +1,263 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Packets to Bytes Component
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_packets_to_bytes
|
||||
//if ENCODING ==0, CHANNEL_WIDTH must be 8
|
||||
//else CHANNEL_WIDTH can be from 0 to 127
|
||||
#( parameter CHANNEL_WIDTH = 8,
|
||||
parameter ENCODING = 0)
|
||||
(
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in with packets
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
input [CHANNEL_WIDTH-1: 0] in_channel,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
localparam CHN_COUNT = (CHANNEL_WIDTH-1)/7;
|
||||
localparam CHN_EFFECTIVE = CHANNEL_WIDTH-1;
|
||||
reg sent_esc, sent_sop, sent_eop;
|
||||
reg sent_channel_char, channel_escaped, sent_channel;
|
||||
reg [CHANNEL_WIDTH-1:0] stored_channel;
|
||||
reg [4:0] channel_count;
|
||||
reg [((CHN_EFFECTIVE/7+1)*7)-1:0] stored_varchannel;
|
||||
reg channel_needs_esc;
|
||||
|
||||
|
||||
|
||||
wire need_sop, need_eop, need_esc, need_channel;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// SYNTHESIS ONLY
|
||||
// synthesis read_comments_as_HDL on
|
||||
// assign need_esc = (in_data == 8'h7a | in_data == 8'h7b | in_data == 8'h7c | in_data == 8'h7d );
|
||||
// synthesis read_comments_as_HDL off
|
||||
|
||||
// SIMULATION ONYLU
|
||||
// synthesis translate_off
|
||||
assign need_esc = (in_data === 8'h7a | in_data === 8'h7b | in_data === 8'h7c | in_data === 8'h7d );
|
||||
// synthesis translate_on
|
||||
|
||||
|
||||
assign need_eop = (in_endofpacket);
|
||||
assign need_sop = (in_startofpacket);
|
||||
|
||||
|
||||
generate
|
||||
if( CHANNEL_WIDTH > 0) begin
|
||||
wire channel_changed;
|
||||
assign channel_changed = (in_channel != stored_channel);
|
||||
assign need_channel = (need_sop | channel_changed);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
sent_channel <= 0;
|
||||
channel_escaped <= 0;
|
||||
sent_channel_char <= 0;
|
||||
out_data <= 0;
|
||||
out_valid <= 0;
|
||||
channel_count <= 0;
|
||||
channel_needs_esc <= 0;
|
||||
end else begin
|
||||
|
||||
if (out_ready )
|
||||
out_valid <= 0;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid )
|
||||
out_valid <= 1;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
if (need_channel & ~sent_channel) begin
|
||||
if (~sent_channel_char) begin
|
||||
sent_channel_char <= 1;
|
||||
out_data <= 8'h7c;
|
||||
channel_count <= CHN_COUNT[4:0];
|
||||
stored_varchannel <= in_channel;
|
||||
if ((ENCODING == 0) | (CHANNEL_WIDTH == 7)) begin
|
||||
channel_needs_esc <= (in_channel == 8'h7a |
|
||||
in_channel == 8'h7b |
|
||||
in_channel == 8'h7c |
|
||||
in_channel == 8'h7d );
|
||||
end
|
||||
end else if (channel_needs_esc & ~channel_escaped) begin
|
||||
out_data <= 8'h7d;
|
||||
channel_escaped <= 1;
|
||||
end else if (~sent_channel) begin
|
||||
if (ENCODING) begin
|
||||
// Sending out MSB=1, while not last 7 bits of Channel
|
||||
if (channel_count > 0) begin
|
||||
if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
|
||||
else out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
|
||||
stored_varchannel <= stored_varchannel<<7;
|
||||
|
||||
channel_count <= channel_count - 1'b1;
|
||||
// check whether the last 7 bits need escape or not
|
||||
if (channel_count ==1 & CHANNEL_WIDTH > 7) begin
|
||||
channel_needs_esc <=
|
||||
((stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7a)|
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7b) |
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7c) |
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7d) );
|
||||
end
|
||||
end else begin
|
||||
// Sending out MSB=0, last 7 bits of Channel
|
||||
if (channel_needs_esc) begin
|
||||
channel_needs_esc <= 0;
|
||||
out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
|
||||
end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end else begin
|
||||
if (channel_needs_esc) begin
|
||||
channel_needs_esc <= 0;
|
||||
out_data <= in_channel ^ 8'h20;
|
||||
end else out_data <= in_channel;
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end
|
||||
end else if (need_sop & ~sent_sop) begin
|
||||
sent_sop <= 1;
|
||||
out_data <= 8'h7a;
|
||||
|
||||
end else if (need_eop & ~sent_eop) begin
|
||||
sent_eop <= 1;
|
||||
out_data <= 8'h7b;
|
||||
|
||||
end else if (need_esc & ~sent_esc) begin
|
||||
sent_esc <= 1;
|
||||
out_data <= 8'h7d;
|
||||
end else begin
|
||||
if (sent_esc) out_data <= in_data ^ 8'h20;
|
||||
else out_data <= in_data;
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
sent_channel <= 0;
|
||||
channel_escaped <= 0;
|
||||
sent_channel_char <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//channel related signals
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
//extra bit in stored_channel to force reset
|
||||
stored_channel <= {CHANNEL_WIDTH{1'b1}};
|
||||
end else begin
|
||||
//update stored_channel only when it is sent out
|
||||
if (sent_channel) stored_channel <= in_channel;
|
||||
end
|
||||
end
|
||||
always @* begin
|
||||
|
||||
// in_ready. Low when:
|
||||
// back pressured, or when
|
||||
// we are outputting a control character, which means that one of
|
||||
// {escape_char, start of packet, end of packet, channel}
|
||||
// needs to be, but has not yet, been handled.
|
||||
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
|
||||
& (~need_sop | sent_sop)
|
||||
& (~need_eop | sent_eop)
|
||||
& (~need_channel | sent_channel);
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
assign need_channel = (need_sop);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
out_data <= 0;
|
||||
out_valid <= 0;
|
||||
sent_channel <= 0;
|
||||
sent_channel_char <= 0;
|
||||
end else begin
|
||||
|
||||
if (out_ready )
|
||||
out_valid <= 0;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid )
|
||||
out_valid <= 1;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
if (need_channel & ~sent_channel) begin
|
||||
if (~sent_channel_char) begin //Added sent channel 0 before the 1st SOP
|
||||
sent_channel_char <= 1;
|
||||
out_data <= 8'h7c;
|
||||
end else if (~sent_channel) begin
|
||||
out_data <= 'h0;
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end else if (need_sop & ~sent_sop) begin
|
||||
sent_sop <= 1;
|
||||
out_data <= 8'h7a;
|
||||
end else if (need_eop & ~sent_eop) begin
|
||||
sent_eop <= 1;
|
||||
out_data <= 8'h7b;
|
||||
end else if (need_esc & ~sent_esc) begin
|
||||
sent_esc <= 1;
|
||||
out_data <= 8'h7d;
|
||||
end else begin
|
||||
if (sent_esc) out_data <= in_data ^ 8'h20;
|
||||
else out_data <= in_data;
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
|
||||
& (~need_sop | sent_sop)
|
||||
& (~need_eop | sent_eop)
|
||||
& (~need_channel | sent_channel);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3ToCi97F+O4Jtd7lyb3HX6P4erEvg2ALdvMtyo/GHuQ/3I7pLrfwffqBLzWXXFs+6LextEIKaErTIQtRI5NPblwu4T4zWVtUAvzj5xOcu8gxOUxITJg1JZu+hgblTes2OH1rZVOYEc0eF6RV6M6mu1E0UjegEjjIH8WWlbRMFzdxz1MD+/1DOZKc2X+0imGI5dm+g8REigzqPK2bFQ27ymsU332zAZHeycYzNJZHNdp8+XrK3SsFR2TXk3FLIOUmw91xaAQa2pPF9I9+12OyjVG2j7UrmRpn+ju33pFdR5i8HjvX3QFyiR/4QzYCnXKXFTf/EbuhPYhm91NKEuGilm6Z9iXts0KIJ1aq4ua4i774oqTXgAIjXANyhyzGk5Ur3+smdc59bQ0Sc3RmPJ3T25tAVZoj11NQ3ZainP3Z5Y7iEIyrhuW0ZfcLAL4zUAr80q4aOvWun1iGrpTpWG9lw8gUoOsMcubxZPKnljcOAvngP0/HEe2NJuMfCuN1VXnnFVqM/f8miDEnsYbHQr1dAtF6nPFLnmjCz9PJlSLsknIn9XSlODFJZj523804/PT2LNZCWUVTP1SxC+eHsFXSKDwlX+6sBFC+fE9G29UYt6reIAw3Gd26uNnR/wmEv+CdXJSAaGORAYgT0/oqeojJaI5DdLsh769bfFLdhvKBf1UiMjagREV6OZHZU9j63BYPdZbrTBe8koPrfUD5PzFH26uU7fDSOD/wUOL4lZ1OM8aD6TDbCkDSEypvgByUHouVg4XkHfQD5BPepTp1QaQGEuLa83qx00cT62xUbb/sqh4Pbs5usdNejVBdKC9pIReQ8WCsSCpDLIkDTdeo9Cln0v2Kp0uYmoBqyK2hTP0gmjbSD6mm9c6Q2VCWOQ46h6HRSfc/aEoTLDDY0nDHlXssgeOKyKD4syMekhKo9f8bituh8dSnrpsvwSb4febBzcsonH3RHwGzym2vmfGfZm1kqG58y7aICrVpZOxfzI2/VYABROWLAtk2Jlthow6OtITe"
|
||||
`endif
|
||||
+263
@@ -0,0 +1,263 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Packets to Bytes Component
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_packets_to_bytes
|
||||
//if ENCODING ==0, CHANNEL_WIDTH must be 8
|
||||
//else CHANNEL_WIDTH can be from 0 to 127
|
||||
#( parameter CHANNEL_WIDTH = 8,
|
||||
parameter ENCODING = 0)
|
||||
(
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in with packets
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
input [CHANNEL_WIDTH-1: 0] in_channel,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
localparam CHN_COUNT = (CHANNEL_WIDTH-1)/7;
|
||||
localparam CHN_EFFECTIVE = CHANNEL_WIDTH-1;
|
||||
reg sent_esc, sent_sop, sent_eop;
|
||||
reg sent_channel_char, channel_escaped, sent_channel;
|
||||
reg [CHANNEL_WIDTH-1:0] stored_channel;
|
||||
reg [4:0] channel_count;
|
||||
reg [((CHN_EFFECTIVE/7+1)*7)-1:0] stored_varchannel;
|
||||
reg channel_needs_esc;
|
||||
|
||||
|
||||
|
||||
wire need_sop, need_eop, need_esc, need_channel;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// SYNTHESIS ONLY
|
||||
// synthesis read_comments_as_HDL on
|
||||
// assign need_esc = (in_data == 8'h7a | in_data == 8'h7b | in_data == 8'h7c | in_data == 8'h7d );
|
||||
// synthesis read_comments_as_HDL off
|
||||
|
||||
// SIMULATION ONYLU
|
||||
// synthesis translate_off
|
||||
assign need_esc = (in_data === 8'h7a | in_data === 8'h7b | in_data === 8'h7c | in_data === 8'h7d );
|
||||
// synthesis translate_on
|
||||
|
||||
|
||||
assign need_eop = (in_endofpacket);
|
||||
assign need_sop = (in_startofpacket);
|
||||
|
||||
|
||||
generate
|
||||
if( CHANNEL_WIDTH > 0) begin
|
||||
wire channel_changed;
|
||||
assign channel_changed = (in_channel != stored_channel);
|
||||
assign need_channel = (need_sop | channel_changed);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
sent_channel <= 0;
|
||||
channel_escaped <= 0;
|
||||
sent_channel_char <= 0;
|
||||
out_data <= 0;
|
||||
out_valid <= 0;
|
||||
channel_count <= 0;
|
||||
channel_needs_esc <= 0;
|
||||
end else begin
|
||||
|
||||
if (out_ready )
|
||||
out_valid <= 0;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid )
|
||||
out_valid <= 1;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
if (need_channel & ~sent_channel) begin
|
||||
if (~sent_channel_char) begin
|
||||
sent_channel_char <= 1;
|
||||
out_data <= 8'h7c;
|
||||
channel_count <= CHN_COUNT[4:0];
|
||||
stored_varchannel <= in_channel;
|
||||
if ((ENCODING == 0) | (CHANNEL_WIDTH == 7)) begin
|
||||
channel_needs_esc <= (in_channel == 8'h7a |
|
||||
in_channel == 8'h7b |
|
||||
in_channel == 8'h7c |
|
||||
in_channel == 8'h7d );
|
||||
end
|
||||
end else if (channel_needs_esc & ~channel_escaped) begin
|
||||
out_data <= 8'h7d;
|
||||
channel_escaped <= 1;
|
||||
end else if (~sent_channel) begin
|
||||
if (ENCODING) begin
|
||||
// Sending out MSB=1, while not last 7 bits of Channel
|
||||
if (channel_count > 0) begin
|
||||
if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
|
||||
else out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
|
||||
stored_varchannel <= stored_varchannel<<7;
|
||||
|
||||
channel_count <= channel_count - 1'b1;
|
||||
// check whether the last 7 bits need escape or not
|
||||
if (channel_count ==1 & CHANNEL_WIDTH > 7) begin
|
||||
channel_needs_esc <=
|
||||
((stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7a)|
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7b) |
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7c) |
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7d) );
|
||||
end
|
||||
end else begin
|
||||
// Sending out MSB=0, last 7 bits of Channel
|
||||
if (channel_needs_esc) begin
|
||||
channel_needs_esc <= 0;
|
||||
out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
|
||||
end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end else begin
|
||||
if (channel_needs_esc) begin
|
||||
channel_needs_esc <= 0;
|
||||
out_data <= in_channel ^ 8'h20;
|
||||
end else out_data <= in_channel;
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end
|
||||
end else if (need_sop & ~sent_sop) begin
|
||||
sent_sop <= 1;
|
||||
out_data <= 8'h7a;
|
||||
|
||||
end else if (need_eop & ~sent_eop) begin
|
||||
sent_eop <= 1;
|
||||
out_data <= 8'h7b;
|
||||
|
||||
end else if (need_esc & ~sent_esc) begin
|
||||
sent_esc <= 1;
|
||||
out_data <= 8'h7d;
|
||||
end else begin
|
||||
if (sent_esc) out_data <= in_data ^ 8'h20;
|
||||
else out_data <= in_data;
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
sent_channel <= 0;
|
||||
channel_escaped <= 0;
|
||||
sent_channel_char <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//channel related signals
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
//extra bit in stored_channel to force reset
|
||||
stored_channel <= {CHANNEL_WIDTH{1'b1}};
|
||||
end else begin
|
||||
//update stored_channel only when it is sent out
|
||||
if (sent_channel) stored_channel <= in_channel;
|
||||
end
|
||||
end
|
||||
always @* begin
|
||||
|
||||
// in_ready. Low when:
|
||||
// back pressured, or when
|
||||
// we are outputting a control character, which means that one of
|
||||
// {escape_char, start of packet, end of packet, channel}
|
||||
// needs to be, but has not yet, been handled.
|
||||
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
|
||||
& (~need_sop | sent_sop)
|
||||
& (~need_eop | sent_eop)
|
||||
& (~need_channel | sent_channel);
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
assign need_channel = (need_sop);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
out_data <= 0;
|
||||
out_valid <= 0;
|
||||
sent_channel <= 0;
|
||||
sent_channel_char <= 0;
|
||||
end else begin
|
||||
|
||||
if (out_ready )
|
||||
out_valid <= 0;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid )
|
||||
out_valid <= 1;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
if (need_channel & ~sent_channel) begin
|
||||
if (~sent_channel_char) begin //Added sent channel 0 before the 1st SOP
|
||||
sent_channel_char <= 1;
|
||||
out_data <= 8'h7c;
|
||||
end else if (~sent_channel) begin
|
||||
out_data <= 'h0;
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end else if (need_sop & ~sent_sop) begin
|
||||
sent_sop <= 1;
|
||||
out_data <= 8'h7a;
|
||||
end else if (need_eop & ~sent_eop) begin
|
||||
sent_eop <= 1;
|
||||
out_data <= 8'h7b;
|
||||
end else if (need_esc & ~sent_esc) begin
|
||||
sent_esc <= 1;
|
||||
out_data <= 8'h7d;
|
||||
end else begin
|
||||
if (sent_esc) out_data <= in_data ^ 8'h20;
|
||||
else out_data <= in_data;
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
|
||||
& (~need_sop | sent_sop)
|
||||
& (~need_eop | sent_eop)
|
||||
& (~need_channel | sent_channel);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3ToCi97F+O4Jtd7lyb3HX6P4erEvg2ALdvMtyo/GHuQ/3I7pLrfwffqBLzWXXFs+6LextEIKaErTIQtRI5NPblwu4T4zWVtUAvzj5xOcu8gxOUxITJg1JZu+hgblTes2OH1rZVOYEc0eF6RV6M6mu1E0UjegEjjIH8WWlbRMFzdxz1MD+/1DOZKc2X+0imGI5dm+g8REigzqPK2bFQ27ymsU332zAZHeycYzNJZHNdp8+XrK3SsFR2TXk3FLIOUmw91xaAQa2pPF9I9+12OyjVG2j7UrmRpn+ju33pFdR5i8HjvX3QFyiR/4QzYCnXKXFTf/EbuhPYhm91NKEuGilm6Z9iXts0KIJ1aq4ua4i774oqTXgAIjXANyhyzGk5Ur3+smdc59bQ0Sc3RmPJ3T25tAVZoj11NQ3ZainP3Z5Y7iEIyrhuW0ZfcLAL4zUAr80q4aOvWun1iGrpTpWG9lw8gUoOsMcubxZPKnljcOAvngP0/HEe2NJuMfCuN1VXnnFVqM/f8miDEnsYbHQr1dAtF6nPFLnmjCz9PJlSLsknIn9XSlODFJZj523804/PT2LNZCWUVTP1SxC+eHsFXSKDwlX+6sBFC+fE9G29UYt6reIAw3Gd26uNnR/wmEv+CdXJSAaGORAYgT0/oqeojJaI5DdLsh769bfFLdhvKBf1UiMjagREV6OZHZU9j63BYPdZbrTBe8koPrfUD5PzFH26uU7fDSOD/wUOL4lZ1OM8aD6TDbCkDSEypvgByUHouVg4XkHfQD5BPepTp1QaQGEuLa83qx00cT62xUbb/sqh4Pbs5usdNejVBdKC9pIReQ8WCsSCpDLIkDTdeo9Cln0v2Kp0uYmoBqyK2hTP0gmjbSD6mm9c6Q2VCWOQ46h6HRSfc/aEoTLDDY0nDHlXssgeOKyKD4syMekhKo9f8bituh8dSnrpsvwSb4febBzcsonH3RHwGzym2vmfGfZm1kqG58y7aICrVpZOxfzI2/VYABROWLAtk2Jlthow6OtITe"
|
||||
`endif
|
||||
+190
@@ -0,0 +1,190 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/26.1/ip/iconnect/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_clock_crosser(
|
||||
in_clk,
|
||||
in_reset,
|
||||
in_ready,
|
||||
in_valid,
|
||||
in_data,
|
||||
out_clk,
|
||||
out_reset,
|
||||
out_ready,
|
||||
out_valid,
|
||||
out_data
|
||||
);
|
||||
|
||||
parameter SYMBOLS_PER_BEAT = 1;
|
||||
parameter BITS_PER_SYMBOL = 8;
|
||||
parameter FORWARD_SYNC_DEPTH = 2;
|
||||
parameter BACKWARD_SYNC_DEPTH = 2;
|
||||
parameter USE_OUTPUT_PIPELINE = 1;
|
||||
|
||||
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
|
||||
|
||||
input in_clk;
|
||||
input in_reset;
|
||||
output in_ready;
|
||||
input in_valid;
|
||||
input [DATA_WIDTH-1:0] in_data;
|
||||
|
||||
input out_clk;
|
||||
input out_reset;
|
||||
input out_ready;
|
||||
output out_valid;
|
||||
output [DATA_WIDTH-1:0] out_data;
|
||||
|
||||
// Data is guaranteed valid by control signal clock crossing. Cut data
|
||||
// buffer false path.
|
||||
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
|
||||
(* altera_attribute = {"-name DESIGN_ASSISTANT_EXCLUDE \"CDC-50001,CDC-50006\""} *) reg [DATA_WIDTH-1:0] out_data_buffer;
|
||||
|
||||
reg in_data_toggle;
|
||||
wire in_data_toggle_returned;
|
||||
wire out_data_toggle;
|
||||
reg out_data_toggle_flopped, out_data_toggle_1, out_data_toggle_flopped_n;
|
||||
|
||||
wire take_in_data;
|
||||
wire out_data_taken;
|
||||
|
||||
wire out_valid_internal;
|
||||
wire out_ready_internal;
|
||||
wire reset_merged;
|
||||
wire out_reset_merged;
|
||||
wire in_reset_merged;
|
||||
|
||||
assign in_ready = (in_data_toggle_returned ^ in_data_toggle);
|
||||
assign take_in_data = in_valid & in_ready;
|
||||
assign out_valid_internal = out_data_toggle_1 ^ out_data_toggle_flopped;
|
||||
assign out_data_taken = out_ready_internal & out_valid_internal;
|
||||
|
||||
assign reset_merged = in_reset | out_reset;
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (2),
|
||||
.ASYNC_RESET(1'b1)
|
||||
)
|
||||
alt_rst_req_sync_in_rst
|
||||
(
|
||||
.clk (in_clk),
|
||||
.reset_in (reset_merged),
|
||||
.reset_out (in_reset_merged)
|
||||
);
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (2),
|
||||
.ASYNC_RESET(1'b1)
|
||||
)
|
||||
alt_rst_req_sync_out_rst
|
||||
(
|
||||
.clk (out_clk),
|
||||
.reset_in (reset_merged),
|
||||
.reset_out (out_reset_merged)
|
||||
);
|
||||
|
||||
always @(posedge in_clk or posedge in_reset_merged) begin
|
||||
if (in_reset_merged) begin
|
||||
in_data_buffer <= {DATA_WIDTH{1'b0}};
|
||||
in_data_toggle <= 1'b0;
|
||||
end else begin
|
||||
if (take_in_data) begin
|
||||
in_data_toggle <= ~in_data_toggle;
|
||||
in_data_buffer <= in_data;
|
||||
end
|
||||
end //in_reset
|
||||
end //in_clk always block
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_1 <= 1'b0;
|
||||
end else begin
|
||||
out_data_toggle_1 <= out_data_toggle;
|
||||
end //end if
|
||||
end //out_clk always block
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_flopped <= 1'b0;
|
||||
out_data_buffer <= {DATA_WIDTH{1'b0}};
|
||||
end else begin
|
||||
out_data_buffer <= in_data_buffer;
|
||||
if (out_data_taken) begin
|
||||
out_data_toggle_flopped <= out_data_toggle_1;
|
||||
end
|
||||
end //end if
|
||||
end //out_clk always block
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_flopped_n <= 1'b0;
|
||||
end else begin
|
||||
out_data_toggle_flopped_n <= ~out_data_toggle_flopped;
|
||||
end //end if
|
||||
end //out_clk always block
|
||||
|
||||
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
|
||||
.clk(out_clk),
|
||||
.reset_n(~out_reset_merged),
|
||||
.din(in_data_toggle),
|
||||
.dout(out_data_toggle)
|
||||
);
|
||||
|
||||
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
|
||||
.clk(in_clk),
|
||||
.reset_n(~in_reset_merged),
|
||||
.din(out_data_toggle_flopped_n),
|
||||
.dout(in_data_toggle_returned)
|
||||
);
|
||||
|
||||
|
||||
generate if (USE_OUTPUT_PIPELINE == 1) begin
|
||||
|
||||
altera_avalon_st_pipeline_base
|
||||
#(
|
||||
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
|
||||
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
|
||||
) output_stage (
|
||||
.clk(out_clk),
|
||||
.reset(out_reset_merged),
|
||||
.in_ready(out_ready_internal),
|
||||
.in_valid(out_valid_internal),
|
||||
.in_data(out_data_buffer),
|
||||
.out_ready(out_ready),
|
||||
.out_valid(out_valid),
|
||||
.out_data(out_data)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign out_valid = out_valid_internal;
|
||||
assign out_ready_internal = out_ready;
|
||||
assign out_data = out_data_buffer;
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43kLaZ1eFbVnzLHFC3Iy8C952zU9KJLT86rKkmt6MuQRY9VO2r7wzhfXVuNaV6/LGJ22nFWPP1Zlp8tX/FsFICDuTFBgn16uT/eLZl7yEPcOC57c1nPIQtrXm/twebJnc+420/b7beqdRjmppQV89jcr4IutIRg0q/UzyCC4/2fY5Vuv4y2RLPqG3uLPwFsqCGQQ6W2iLHjEudISQfpD6UFZwQM3AK0EzVxzO2mWaSdjScZLEwdTYkTvzmmmqgK+TppgH8xTxu9R5AwAToenaFVO1UaJ0UesZAYuLz4Ahtj/NeR6JnsD937RDOcuA62eNx+kNN/DMnDdPeLnBRdu8+7skTxOsOQNemerCiMmE6Ih9psV6MIJNze8KR3H/TkE0Z6Xx7ZWYwao+kgAd36vATAbQYoEbfBUQZ5WpWtOgrk+SqJeNG7vIyc6DZf0HiT9CijPfhXQ/uP1Zcm8+Fy4zQgMFFXQJ+0z1dZpHdx0uQGWb2MVH1ip8rfstVLmnIExXhwxtGnMINCGOCHKHQhSmJFCCcp781UT0l2SFb2k8JnGfjBeV3qEc+YdyQlCecvpIvwm7kFOZVcuAPEMLCj9iNGZ6zF3eAtE3BwutrR3T8syz+uo4KETCahmI3C0VORjpH/ycGC9BPN4dzvSLQbbmWPa5EFqOk3o8zmzsxSS46ez0RkoPKBnL5RjvwZS9Nj4uWl10xn0GfUSYfryakKZSUfz2FSwg5R7XHIhLtozCCbV18uqxJnYE6U/YTd6OOvjDpm2J2r0y2aXKWgm6UfBCO4D"
|
||||
`endif
|
||||
+75
@@ -0,0 +1,75 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Idle Inserter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_idle_inserter (
|
||||
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc;
|
||||
wire escape_char, idle_char;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign idle_char = (in_data == 8'h4a);
|
||||
assign escape_char = (in_data == 8'h4d);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
end else begin
|
||||
if (in_valid & out_ready) begin
|
||||
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
|
||||
received_esc <= 1;
|
||||
end else begin
|
||||
received_esc <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
//we are always valid
|
||||
out_valid = 1'b1;
|
||||
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
|
||||
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
|
||||
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
|
||||
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
|
||||
in_data; //send data
|
||||
end
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43kCRpW4r+SV5JNpaTWRJVwAk9Te9/4uDK/9P0jpNRt3FOTzSu+eCkD8vGTJ5ECpem121uVEsoaBkVw0tq6Pggh2yrt9+q2ZO2tCEdipsY9N2PU9Z9Nj4iWsLLcDXmWgIAHWGO4T2+T7mbqEU5LjSrAMcn2L1vYwRzCNJd0M7ZpmDzHaTrNjl85ThSXMoHSH7N+H07hgkxMC1B30BuOwJxbhVqM0O1bF1Lif3HQMwjuUEiZfWNAJCRVdGevNN+uFzb/N6ZI4U3aK1Pp5wbm6kdhIKTAGgK0GtE8hPWxh5G7DsFE2cHNdngQfX5OYn0LIFo9VE+RF0ce1Kk6/FBWv5zyZObFFLudpM+Dx4HKmNA0hqznPjcEK5HUx/CqIoy+T+89G2VSZc51jSHy763msXNjBNbnLPa0o0GL9GKYUn7eTjFkX0ic3rdZ/cy05luCYKmHyzGod00WDMbQb1yGwwwQ/ZnrEo9c2tl5FZE5pGnOxz7U0HTSL+F3xVmryBy3IzK7Wba5uEE/TNJcXcpdFNyidBoE5DdhffwjzH5ST+9v6dGBiQNWybRauhLu3glW4Y8SP5cbqGqNzDfH3p9Iuo1CS35rXY/zqTXCIYOMxMe/k4eBk5L31Xly023r2RGrhiNrbTK3oG3b458LgR4pkEiQOZI6XT5DbVqmDmF0vbLkOM3U8RLsM2vNiZaHGSgb9yLIl/jIiic1pGCTXXGy7dUH11hlrEfbCYR9WrhCbMQhdb09X6g0/OwAKyeKVpvZXKkoZj8g6iRj6JvK9gbgLl0Ot"
|
||||
`endif
|
||||
+73
@@ -0,0 +1,73 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Idle Remover
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_idle_remover (
|
||||
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc;
|
||||
wire escape_char, idle_char;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign idle_char = (in_data == 8'h4a);
|
||||
assign escape_char = (in_data == 8'h4d);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
end else begin
|
||||
if (in_valid & in_ready) begin
|
||||
if (escape_char & ~received_esc) begin
|
||||
received_esc <= 1;
|
||||
end else if (out_valid) begin
|
||||
received_esc <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
//out valid when in_valid. Except when we get idle or escape
|
||||
//however, if we have received an escape character, then we are valid
|
||||
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
|
||||
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
|
||||
end
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43m+IIK1ixAbxPYTwnlCpKSDGmf9frfeCOy1EuDdRMaMJDEncztGlmHshJHRvfDGi/EEg4qjealxu0yL1imOpUKwuC6jLHx+dcdMKTloQvSNAU4Ymo3vSmsF7htT5b7B+pQMk3eJ63Nlxzofxy0nRoc2DSa78oKwkrWsu24+0oPKMoSmiMZAgW09tP9QVzEx7lZXQxm+3D73Xk7A5PXrOZPeu7qTH+pV8ogw4chnFtGP8J3P7FSAaef2V+PkFrJZed+TxKjcfG1zWgD52v1YNr4EwgTXtsfI2IkNCcmUeiJzw0MmKBg0cFqgYY/KXk+ILqaO39elRp0WwiXa0ZgcZ01GZeKMErd/mirZg1w1BoqX+E7VvvuuBkzGRjDflArMJwOmqHDZXKvCmRaegV32DmVtkNv5em3f/A4hvUp6y11KPZoYd/lg3Dv7S2OZT8UtmT62CJPubbNCZr8O+odRCIgO+Msq0LW6sevM+v8eEJzcn8OCYmDyUHyW1XO9jmtBrFFtAYl97lb7cgg6nkgaN3+CafnTFJb+x8piB+Xk/S7gS9ZnKC8xMd1469RwAP9ohUVJHNA60UUFfc6uixYibBz9o86aCTZ0+ICG91msNAwFSGv7UmYnYK8TxTPc7V3eA8puX8bO4h6tt0EAs8Zb794I5mcDCYafM79/RkgRkWtxlMkqSYyASjn/anZHE8GW1Re7jrUJgxWBPIBOMY61EztDDdY/TKPhbH1O4tF7cI4lSVM5OQwfY5RgFqX52cCydrhFFqEIX1NmMX/N/4bLUcyX"
|
||||
`endif
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
# (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and other
|
||||
# software and tools, and its AMPP partner logic functions, and any output
|
||||
# files from any of the foregoing (including device programming or simulation
|
||||
# files), and any associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License Subscription
|
||||
# Agreement, Altera IP License Agreement, or other applicable
|
||||
# license agreement, including, without limitation, that your use is for the
|
||||
# sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
|
||||
set_false_path -from [get_registers *altera_jtag_src_crosser:*|sink_data_buffer*] -to [get_registers *altera_jtag_src_crosser:*|src_data*]
|
||||
+229
@@ -0,0 +1,229 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// This top level module chooses between the original Altera-ST JTAG Interface
|
||||
// component in ACDS version 8.1 and before, and the new one with the PLI
|
||||
// Simulation mode turned on, which adds a wrapper over the original component.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
// altera message_off 16735
|
||||
|
||||
module altera_avalon_st_jtag_interface #(
|
||||
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
|
||||
// for JTAG Phy, 1 for Packets to Master
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = 0,
|
||||
parameter EXPORT_JTAG = 0,
|
||||
parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
|
||||
parameter PLI_PORT = 50000 // PLI Simulation Port
|
||||
) (
|
||||
input wire jtag_tck,
|
||||
input wire jtag_tms,
|
||||
input wire jtag_tdi,
|
||||
output wire jtag_tdo,
|
||||
input wire jtag_ena,
|
||||
input wire jtag_usr1,
|
||||
input wire jtag_clr,
|
||||
input wire jtag_clrn,
|
||||
input wire jtag_state_tlr,
|
||||
input wire jtag_state_rti,
|
||||
input wire jtag_state_sdrs,
|
||||
input wire jtag_state_cdr,
|
||||
input wire jtag_state_sdr,
|
||||
input wire jtag_state_e1dr,
|
||||
input wire jtag_state_pdr,
|
||||
input wire jtag_state_e2dr,
|
||||
input wire jtag_state_udr,
|
||||
input wire jtag_state_sirs,
|
||||
input wire jtag_state_cir,
|
||||
input wire jtag_state_sir,
|
||||
input wire jtag_state_e1ir,
|
||||
input wire jtag_state_pir,
|
||||
input wire jtag_state_e2ir,
|
||||
input wire jtag_state_uir,
|
||||
input wire [2:0] jtag_ir_in,
|
||||
output wire jtag_irq,
|
||||
output wire [2:0] jtag_ir_out,
|
||||
input wire clk,
|
||||
input wire reset_n,
|
||||
input wire source_ready,
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
output wire resetrequest,
|
||||
output wire debug_reset,
|
||||
output wire mgmt_valid,
|
||||
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output wire mgmt_data
|
||||
);
|
||||
|
||||
// Signals in the JTAG clock domain
|
||||
wire tck;
|
||||
wire tdi;
|
||||
wire tdo;
|
||||
wire [2:0] ir_in;
|
||||
wire virtual_state_cdr;
|
||||
wire virtual_state_sdr;
|
||||
wire virtual_state_udr;
|
||||
|
||||
assign jtag_irq = 1'b0;
|
||||
assign jtag_ir_out = 3'b000;
|
||||
|
||||
generate
|
||||
if (EXPORT_JTAG == 0) begin
|
||||
// SLD node instantiation
|
||||
altera_jtag_sld_node node (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_out (3'b0),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr (virtual_state_cdr),
|
||||
.virtual_state_cir (),
|
||||
.virtual_state_e1dr (),
|
||||
.virtual_state_e2dr (),
|
||||
.virtual_state_pdr (),
|
||||
.virtual_state_sdr (virtual_state_sdr),
|
||||
.virtual_state_udr (virtual_state_udr),
|
||||
.virtual_state_uir ()
|
||||
);
|
||||
|
||||
assign jtag_tdo = 1'b0;
|
||||
end else begin
|
||||
assign tck = jtag_tck;
|
||||
assign tdi = jtag_tdi;
|
||||
assign jtag_tdo = tdo;
|
||||
assign ir_in = jtag_ir_in;
|
||||
assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
|
||||
assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
|
||||
assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (USE_PLI == 0)
|
||||
begin : normal
|
||||
altera_jtag_dc_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_dc_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.source_data(source_data),
|
||||
.source_valid(source_valid),
|
||||
.sink_data(sink_data),
|
||||
.sink_valid(sink_valid),
|
||||
.sink_ready(sink_ready),
|
||||
.resetrequest(resetrequest),
|
||||
.debug_reset(debug_reset),
|
||||
.mgmt_valid(mgmt_valid),
|
||||
.mgmt_channel(mgmt_channel),
|
||||
.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
end
|
||||
else
|
||||
begin : pli_mode
|
||||
|
||||
//synthesis translate_off
|
||||
reg pli_out_valid;
|
||||
reg pli_in_ready;
|
||||
reg [7 : 0] pli_out_data;
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
pli_out_valid <= 0;
|
||||
pli_out_data <= 'b0;
|
||||
pli_in_ready <= 0;
|
||||
end
|
||||
else begin
|
||||
`ifdef MODEL_TECH
|
||||
$do_transaction(
|
||||
PLI_PORT,
|
||||
pli_out_valid,
|
||||
source_ready,
|
||||
pli_out_data,
|
||||
sink_valid,
|
||||
pli_in_ready,
|
||||
sink_data
|
||||
);
|
||||
`endif
|
||||
end
|
||||
end
|
||||
|
||||
//synthesis translate_on
|
||||
wire [7:0] jtag_source_data;
|
||||
wire jtag_source_valid;
|
||||
wire jtag_sink_ready;
|
||||
wire jtag_resetrequest;
|
||||
|
||||
altera_jtag_dc_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_dc_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.source_data(jtag_source_data),
|
||||
.source_valid(jtag_source_valid),
|
||||
.sink_data(sink_data),
|
||||
.sink_valid(sink_valid),
|
||||
.sink_ready(jtag_sink_ready),
|
||||
.resetrequest(jtag_resetrequest)//,
|
||||
//.debug_reset(debug_reset),
|
||||
//.mgmt_valid(mgmt_valid),
|
||||
//.mgmt_channel(mgmt_channel),
|
||||
//.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
// synthesis read_comments_as_HDL on
|
||||
// assign source_valid = jtag_source_valid;
|
||||
// assign source_data = jtag_source_data;
|
||||
// assign sink_ready = jtag_sink_ready;
|
||||
// assign resetrequest = jtag_resetrequest;
|
||||
// synthesis read_comments_as_HDL off
|
||||
|
||||
//synthesis translate_off
|
||||
assign source_valid = pli_out_valid;
|
||||
assign source_data = pli_out_data;
|
||||
assign sink_ready = pli_in_ready;
|
||||
assign resetrequest = 1'b0;
|
||||
//synthesis translate_on
|
||||
assign jtag_tdo = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43kE5SETwJy1XH1XEICOs+R/qa00jHEPMso8nVR5QBxKZ3zmrNoJGALGfV84dFJY7TP7iACdYKKx96iRdKyFJaGqH/GObmGJBmKepuqsSvBxbvatkRUGFK/JteQ8Ui7UML33rpNB0DC9tzM4sjZGGDRROsVvNyeM/JoBEukWM0gp2LrwdU+q8fGVQlxl0Nx7Z+rcS00DCy6lJWwnJ7We9WtGffZfDH2xCBmmC0BI4zytrYMCswtE1vXzQEWmbJ6Hyj0yR9hYVQB3qbgw9w/KCzwPBB/KfwvNIuKJU00I89ABvezTidY9Yq7ybSF83M2CNNSpoF/mGcfnX34Ts8njIrUr/tnmjnUp3Vj3Ykrgr6Bpww5JTPI58bYlZkc9RKqFms1hz+T76tQgMjY2Puh+UVXjT5GNjZa0aeiooqibu2yukQK+h09B029L8BfIqleXx4v3RTJ8Fumdz4qrJWNwHUVcYoInUx+J4SPmD6MlAuIdM/FF/ASfYCTQ0svDaRUgKHAWI4TnxFd9T9Pguxt3p29Umz6BZwrQTmn73OPFtmgFjzqSIpubc6sK20vi8SZxjemX5z4na7wsgUYULmNw2OIDdNsaSiFkJlONz3crAxONGlyQ7/4xMJLOlk03I6UfRoHOO23yZ4vZUqcWl31MmDVkHybED5u1f3shr/pCIZ+nK+gfsvykwJ5psOap3kwbGh37URGjln5a6qQBF18+Ugzf44YSZ/sDI35oa9Tt5DXjk6nxH1oU2wXYC2MZ7JLYefvIxpwR07B8VkgIq2ejHbr4"
|
||||
`endif
|
||||
+222
@@ -0,0 +1,222 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2018 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/26.1/ip/iconnect/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_pipeline_base (
|
||||
clk,
|
||||
reset,
|
||||
in_ready,
|
||||
in_valid,
|
||||
in_data,
|
||||
out_ready,
|
||||
out_valid,
|
||||
out_data
|
||||
);
|
||||
|
||||
parameter SYMBOLS_PER_BEAT = 1;
|
||||
parameter BITS_PER_SYMBOL = 8;
|
||||
parameter PIPELINE_READY = 1;
|
||||
parameter SYNC_RESET = 0;
|
||||
parameter BACKPRESSURE_DURING_RESET = 0;
|
||||
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
|
||||
|
||||
input clk;
|
||||
input reset;
|
||||
|
||||
output in_ready;
|
||||
input in_valid;
|
||||
input [DATA_WIDTH-1:0] in_data;
|
||||
|
||||
input out_ready;
|
||||
output out_valid;
|
||||
output [DATA_WIDTH-1:0] out_data;
|
||||
|
||||
reg full0;
|
||||
reg full1;
|
||||
reg [DATA_WIDTH-1:0] data0;
|
||||
reg [DATA_WIDTH-1:0] data1;
|
||||
|
||||
assign out_valid = full1;
|
||||
assign out_data = data1;
|
||||
|
||||
// Generation of internal reset synchronization
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (PIPELINE_READY == 1)
|
||||
begin : REGISTERED_READY_PLINE
|
||||
|
||||
assign in_ready = !full0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
// ----------------------------
|
||||
// always load the second slot if we can
|
||||
// ----------------------------
|
||||
if (~full0)
|
||||
data0 <= in_data;
|
||||
// ----------------------------
|
||||
// first slot is loaded either from the second,
|
||||
// or with new data
|
||||
// ----------------------------
|
||||
if (~full1 || (out_ready && out_valid)) begin
|
||||
if (full0)
|
||||
data1 <= data0;
|
||||
else
|
||||
data1 <= in_data;
|
||||
end
|
||||
end
|
||||
|
||||
if (SYNC_RESET == 0) begin : async_rst0
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
full1 <= 1'b0;
|
||||
end else begin
|
||||
// out of reset.
|
||||
if(~full1 & full0)begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
|
||||
// no data in pipeline
|
||||
if (~full0 & ~full1) begin
|
||||
if (in_valid) begin
|
||||
full1 <= 1'b1;
|
||||
end
|
||||
end // ~f1 & ~f0
|
||||
|
||||
// one datum in pipeline
|
||||
if (full1 & ~full0) begin
|
||||
if (in_valid & ~out_ready) begin
|
||||
full0 <= 1'b1;
|
||||
end
|
||||
// back to empty
|
||||
if (~in_valid & out_ready) begin
|
||||
full1 <= 1'b0;
|
||||
end
|
||||
end // f1 & ~f0
|
||||
|
||||
// two data in pipeline
|
||||
if (full1 & full0) begin
|
||||
// go back to one datum state
|
||||
if (out_ready) begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
end // end go back to one datum stage
|
||||
end
|
||||
end
|
||||
end // async_rst0
|
||||
else begin // sync_rst0
|
||||
always @(posedge clk ) begin
|
||||
if (internal_sclr) begin
|
||||
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
full1 <= 1'b0;
|
||||
end else begin
|
||||
// out of reset.
|
||||
if(~full1 & full0)begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
|
||||
// no data in pipeline
|
||||
if (~full0 & ~full1) begin
|
||||
if (in_valid) begin
|
||||
full1 <= 1'b1;
|
||||
end
|
||||
end // ~f1 & ~f0
|
||||
|
||||
// one datum in pipeline
|
||||
if (full1 & ~full0) begin
|
||||
if (in_valid & ~out_ready) begin
|
||||
full0 <= 1'b1;
|
||||
end
|
||||
// back to empty
|
||||
if (~in_valid & out_ready) begin
|
||||
full1 <= 1'b0;
|
||||
end
|
||||
end // f1 & ~f0
|
||||
|
||||
// two data in pipeline
|
||||
if (full1 & full0) begin
|
||||
// go back to one datum state
|
||||
if (out_ready) begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
end // end go back to one datum stage
|
||||
end
|
||||
end
|
||||
end // sync_rst0
|
||||
end
|
||||
else
|
||||
begin : UNREGISTERED_READY_PLINE
|
||||
|
||||
// in_ready will be a pass through of the out_ready signal as it is not registered
|
||||
assign in_ready = (~full1) | out_ready;
|
||||
|
||||
if (SYNC_RESET == 0) begin : async_rst1
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
data1 <= 'b0;
|
||||
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (in_ready) begin
|
||||
data1 <= in_data;
|
||||
full1 <= in_valid;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // async_rst1
|
||||
else begin // sync_rst1
|
||||
always @(posedge clk ) begin
|
||||
if (internal_sclr) begin
|
||||
data1 <= 'b0;
|
||||
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (in_ready) begin
|
||||
data1 <= in_data;
|
||||
full1 <= in_valid;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // sync_rst1
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43m+2WbbziRXNHGvxsiU9BKfbzYIwxqkjbRY646Jry08YTxgl+u6Mpx3BaAnY8zD8arB0qHAHWeHxZk4Hc5CUUMkBqNpBDW51MKpXcPm9ytMiKASxRBYyGC1DUc1qjCFcJ5eP5kqviLbdBDKpFyc4xAZtJR3LjcT2rHr0r0dcOSAei50r8+hZH5ImpM5IZVnLbFjvfn4gTm34ATDBGaBb/k1ixtHUMFRwKcfLhVwgd8+qp2ZJ42U9B2sa83JRKaJOUtJVMRsuQ4zH1pDaBVKz7tvcbQ9KL6BBsCE6Sn4uDBb1m/T5jxvgV5CgkGSt3amLUBTupfKUvmukO0wGF8cOyjjsWhBq1qj9uHJBIsE6jwGoavEMRH7KppIs+N4blyw3mkk8JbsyZPTmQwkEUKc2Eu8+YcGa/yBIOJeGapk3JOOMjZMuI9zGnVgMljFU0MZZpzbVzMsGSddTz1Cd1namRpB7EOF2NFXOu8hoePaL/YYTrXZAfM5iEuTRjAzVa9LsjKI3vp/WpNZ6Kq6djMwZ7YilOOcNsiCALgQe+1s0QGFBQ7zYwJE7udtUdsEw9GhzuG98Vo/3mB6Z4cGzvj86WrHyy1X9WuRyTDVSGGvAxMWPBEHomZd8TS4+FkOF5oH9QDGhrzKgYpLsfkbAhYvDH4ZjsA2q1aJCrEUFoXGZC8fwYEgx9xhV5T9Hre3WKR3wWPXLu3J/SQ4ecRTdkpcZY0DRzrXao825TRnfAqfECespkaam8sE849QMiWHBh/p0vH+n54ztMPrCthmLaeUe5/O"
|
||||
`endif
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/26.1/ip/iconnect/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage.sv $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_pipeline_stage #(
|
||||
parameter
|
||||
USE_FIFO_IP = 0, // unsued at moment
|
||||
SYMBOLS_PER_BEAT = 1,
|
||||
BITS_PER_SYMBOL = 8,
|
||||
USE_PACKETS = 0,
|
||||
USE_EMPTY = 0,
|
||||
PIPELINE_READY = 1,
|
||||
SYNC_RESET = 0,
|
||||
// Optional ST signal widths. Value "0" means no such port.
|
||||
CHANNEL_WIDTH = 0,
|
||||
ERROR_WIDTH = 0,
|
||||
|
||||
// Derived parameters
|
||||
DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
|
||||
PACKET_WIDTH = 0,
|
||||
EMPTY_WIDTH = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
output in_ready,
|
||||
input in_valid,
|
||||
input [DATA_WIDTH - 1 : 0] in_data,
|
||||
input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
|
||||
input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
|
||||
|
||||
input out_ready,
|
||||
output out_valid,
|
||||
output [DATA_WIDTH - 1 : 0] out_data,
|
||||
output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
|
||||
output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
|
||||
output out_startofpacket,
|
||||
output out_endofpacket,
|
||||
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
|
||||
);
|
||||
localparam
|
||||
PAYLOAD_WIDTH =
|
||||
DATA_WIDTH +
|
||||
PACKET_WIDTH +
|
||||
CHANNEL_WIDTH +
|
||||
EMPTY_WIDTH +
|
||||
ERROR_WIDTH;
|
||||
|
||||
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
|
||||
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
|
||||
|
||||
// Assign in_data and other optional in_* interface signals to in_payload.
|
||||
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
|
||||
generate
|
||||
// optional packet inputs
|
||||
if (PACKET_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH - 1 :
|
||||
DATA_WIDTH
|
||||
] = {in_startofpacket, in_endofpacket};
|
||||
end
|
||||
// optional channel input
|
||||
if (CHANNEL_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH
|
||||
] = in_channel;
|
||||
end
|
||||
// optional empty input
|
||||
if (EMPTY_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
|
||||
] = in_empty;
|
||||
end
|
||||
// optional error input
|
||||
if (ERROR_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
|
||||
] = in_error;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
localparam NUM_128BIT_SLOTS = (PAYLOAD_WIDTH / 128) + (((PAYLOAD_WIDTH % 128) == 0) ? 0 : 1);
|
||||
localparam LAST_PAYLOAD_W = ((PAYLOAD_WIDTH % 128) == 0) ? 128 : (PAYLOAD_WIDTH % 128);
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < NUM_128BIT_SLOTS; i = i + 1) begin : gen_inst
|
||||
if (i == NUM_128BIT_SLOTS - 1) begin
|
||||
altera_avalon_st_pipeline_base #(
|
||||
.SYMBOLS_PER_BEAT (LAST_PAYLOAD_W),
|
||||
.BITS_PER_SYMBOL (1),
|
||||
.PIPELINE_READY (PIPELINE_READY),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) core (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (in_ready),
|
||||
.in_valid (in_valid),
|
||||
.in_data (in_payload[(i*128)+LAST_PAYLOAD_W-1:i*128]),
|
||||
.out_ready (out_ready),
|
||||
.out_valid (out_valid),
|
||||
.out_data (out_payload[(i*128)+LAST_PAYLOAD_W-1:i*128])
|
||||
);
|
||||
end
|
||||
else begin
|
||||
altera_avalon_st_pipeline_base #(
|
||||
.SYMBOLS_PER_BEAT (128),
|
||||
.BITS_PER_SYMBOL (1),
|
||||
.PIPELINE_READY (PIPELINE_READY),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) core (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (),
|
||||
.in_valid (in_valid),
|
||||
.in_data (in_payload[(i+1)*128-1:i*128]),
|
||||
.out_ready (out_ready),
|
||||
.out_valid (),
|
||||
.out_data (out_payload[(i+1)*128-1:i*128])
|
||||
);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Assign out_data and other optional out_* interface signals from out_payload.
|
||||
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
|
||||
generate
|
||||
// optional packet outputs
|
||||
if (PACKET_WIDTH) begin
|
||||
assign {out_startofpacket, out_endofpacket} =
|
||||
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign {out_startofpacket, out_endofpacket} = 2'b0;
|
||||
end
|
||||
|
||||
// optional channel output
|
||||
if (CHANNEL_WIDTH) begin
|
||||
assign out_channel = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_channel = 1'b0;
|
||||
end
|
||||
// optional empty output
|
||||
if (EMPTY_WIDTH) begin
|
||||
assign out_empty = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_empty = 1'b0;
|
||||
end
|
||||
// optional error output
|
||||
if (ERROR_WIDTH) begin
|
||||
assign out_error = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_error = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43lzNdzic8kf095rgT/UkF24bAsY8NGL39W2vnb6QHycbl1peRxuMswSGmotl+qU7rTPIN3gVwEy7e13KVfLqnUSbl5Aj/njXXTCqo0XReaJeMqVFNLoUFEke22KyVtbOBwxIqkfp66fh+LWjI8lLUheUnX8eq4FgV+krso2vFPZ546y52KsJs5qTfDpbX85DJ0+l6Sg4mvb0n9nLB+1SBwdQxY+r1X93owARyzVOcF5CIBN3i1YywJdDG2I6/wxZvAVIxD4KPrlWY8xxukciAYJpr7+Oxf07u7Bv9H7LS8ql7c3ZPPL6Kpk7gEXCnrndNnqENjDVEtnvbjA6q+vmxDW9LgWTd6FRrTHU5Um7j2HfYjJbl2DU/X/VTzmGL3KXLvc1D5ep6LYnHgBoyJbdio3ArirlItOV5zcEnJGUvohgbi/xykdpALrQjbFkskaqu+K/ngGgtZ4YyA1F1U3MJQ9F/wkhC/NqgVc4K5CDIi+J8c2KoINY8OXRB0RtZB0MHeyCpS3WwAzlWQKEYI7Lxkb+2RKzqymsSdH5CltjfEgf4SFk/bXwnv33gBS8bg6OZwu+StypSNvj5Z9C+2aokZD39boscHt24WZchtkJsQtgNM7leRuB9n60dKI+nHwPtiYa5FghnJBzSyeQ49QcgDovq9MQlu/FGFMeXM/mYvcN4Fo2janBMoGBSGEidqiL0nZZxZV6q0inrtQVERT2AkPmL/m7JtCU2FMDauZoOIZ6p2O1DWpE0OzBGyHYRE+yhwMyzOAlT6Yq8VeAt7hHIgA"
|
||||
`endif
|
||||
+264
@@ -0,0 +1,264 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// This module is a simple clock crosser for control signals. It will take
|
||||
// the asynchronous control signal and synchronize it to the clk domain
|
||||
// attached to the clk input. It does so by passing the control signal
|
||||
// through a pair of registers and then sensing the level transition from
|
||||
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
|
||||
// that the control signal will always transition every time is asserted.
|
||||
// i.e.:
|
||||
// ____ ___________________
|
||||
// -> ___| |___ and ___| |_____
|
||||
//
|
||||
// on the control signal will be seen as only one assertion of the control
|
||||
// signal. In short, if your control could be asserted back-to-back, then
|
||||
// don't use this module. You'll be losing data.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_jtag_control_signal_crosser (
|
||||
clk,
|
||||
reset_n,
|
||||
async_control_signal,
|
||||
sense_pos_edge,
|
||||
sync_control_signal
|
||||
);
|
||||
input clk;
|
||||
input reset_n;
|
||||
input async_control_signal;
|
||||
input sense_pos_edge;
|
||||
output sync_control_signal;
|
||||
|
||||
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
|
||||
|
||||
reg sync_control_signal;
|
||||
|
||||
wire synchronized_raw_signal;
|
||||
reg edge_detector_register;
|
||||
|
||||
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.din(async_control_signal),
|
||||
.dout(synchronized_raw_signal)
|
||||
);
|
||||
|
||||
always @ (posedge clk or negedge reset_n)
|
||||
if (~reset_n)
|
||||
edge_detector_register <= 1'b0;
|
||||
else
|
||||
edge_detector_register <= synchronized_raw_signal;
|
||||
|
||||
always @* begin
|
||||
if (sense_pos_edge)
|
||||
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
|
||||
else
|
||||
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
|
||||
end
|
||||
endmodule
|
||||
|
||||
// This module crosses the clock domain for a given source
|
||||
module altera_jtag_src_crosser (
|
||||
sink_clk,
|
||||
sink_reset_n,
|
||||
sink_valid,
|
||||
sink_data,
|
||||
src_clk,
|
||||
src_reset_n,
|
||||
src_valid,
|
||||
src_data
|
||||
);
|
||||
parameter WIDTH = 8;
|
||||
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
|
||||
|
||||
input sink_clk;
|
||||
input sink_reset_n;
|
||||
input sink_valid;
|
||||
input [WIDTH-1:0] sink_data;
|
||||
input src_clk;
|
||||
input src_reset_n;
|
||||
output src_valid;
|
||||
output [WIDTH-1:0] src_data;
|
||||
|
||||
reg sink_valid_buffer;
|
||||
reg [WIDTH-1:0] sink_data_buffer;
|
||||
|
||||
reg src_valid;
|
||||
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
|
||||
|
||||
wire synchronized_valid;
|
||||
|
||||
altera_jtag_control_signal_crosser #(
|
||||
.SYNC_DEPTH(SYNC_DEPTH)
|
||||
) crosser (
|
||||
.clk(src_clk),
|
||||
.reset_n(src_reset_n),
|
||||
.async_control_signal(sink_valid_buffer),
|
||||
.sense_pos_edge(1'b1),
|
||||
.sync_control_signal(synchronized_valid)
|
||||
);
|
||||
always @ (posedge sink_clk or negedge sink_reset_n) begin
|
||||
if (~sink_reset_n) begin
|
||||
sink_valid_buffer <= 1'b0;
|
||||
sink_data_buffer <= 'b0;
|
||||
end else begin
|
||||
sink_valid_buffer <= sink_valid;
|
||||
if (sink_valid) begin
|
||||
sink_data_buffer <= sink_data;
|
||||
end
|
||||
end //end if
|
||||
end //always sink_clk
|
||||
|
||||
always @ (posedge src_clk or negedge src_reset_n) begin
|
||||
if (~src_reset_n) begin
|
||||
src_valid <= 1'b0;
|
||||
src_data <= {WIDTH{1'b0}};
|
||||
end else begin
|
||||
src_valid <= synchronized_valid;
|
||||
src_data <= synchronized_valid ? sink_data_buffer : src_data;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module altera_jtag_dc_streaming #(
|
||||
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
|
||||
// for JTAG Phy, 1 for Packets to Master
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = 0
|
||||
) (
|
||||
// Signals in the JTAG clock domain
|
||||
input wire tck,
|
||||
input wire tdi,
|
||||
output wire tdo,
|
||||
input wire [2:0] ir_in,
|
||||
input wire virtual_state_cdr,
|
||||
input wire virtual_state_sdr,
|
||||
input wire virtual_state_udr,
|
||||
|
||||
input wire clk,
|
||||
input wire reset_n,
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
output wire resetrequest,
|
||||
output wire debug_reset,
|
||||
output wire mgmt_valid,
|
||||
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output wire mgmt_data
|
||||
);
|
||||
|
||||
// the tck to sysclk sync depth is fixed at 8
|
||||
// 8 is the worst case scenario from our metastability analysis, and since
|
||||
// using TCK serially is so slow we should have plenty of clock cycles.
|
||||
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
|
||||
// The clk to tck path is fixed at 3 deep for Synchronizer depth.
|
||||
// Since the tck clock is so slow, no parameter is exposed.
|
||||
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
|
||||
|
||||
wire jtag_clock_reset_n; // system reset is synchronized with tck
|
||||
wire [7:0] jtag_source_data;
|
||||
wire jtag_source_valid;
|
||||
wire [7:0] jtag_sink_data;
|
||||
wire jtag_sink_valid;
|
||||
wire jtag_sink_ready;
|
||||
|
||||
/* Reset Synchronizer module.
|
||||
*
|
||||
* The SLD Node does not provide a reset for the TCK clock domain.
|
||||
* Due to the handshaking nature of the Avalon-ST Clock Crosser,
|
||||
* internal states need to be reset to 0 in order to guarantee proper
|
||||
* functionality throughout resets.
|
||||
*
|
||||
* This reset block will asynchronously assert reset, and synchronously
|
||||
* deassert reset for the tck clock domain.
|
||||
*/
|
||||
altera_std_synchronizer #(
|
||||
.depth(SYSCLK_TO_TCK_SYNC_DEPTH)
|
||||
) synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(reset_n),
|
||||
.din(1'b1),
|
||||
.dout(jtag_clock_reset_n)
|
||||
);
|
||||
|
||||
altera_jtag_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
|
||||
.reset_n(jtag_clock_reset_n),
|
||||
.source_data(jtag_source_data),
|
||||
.source_valid(jtag_source_valid),
|
||||
.sink_data(jtag_sink_data),
|
||||
.sink_valid(jtag_sink_valid),
|
||||
.sink_ready(jtag_sink_ready),
|
||||
.clock_to_sample(clk),
|
||||
.reset_to_sample(reset_n),
|
||||
.resetrequest(resetrequest),
|
||||
.debug_reset(debug_reset),
|
||||
.mgmt_valid(mgmt_valid),
|
||||
.mgmt_channel(mgmt_channel),
|
||||
.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
// synchronization in both clock domain crossings takes place in the "clk" system clock domain!
|
||||
|
||||
altera_avalon_st_clock_crosser #(
|
||||
.SYMBOLS_PER_BEAT(1),
|
||||
.BITS_PER_SYMBOL(8),
|
||||
.FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH),
|
||||
.BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
|
||||
) sink_crosser (
|
||||
.in_clk(clk),
|
||||
.in_reset(~reset_n),
|
||||
.in_data(sink_data),
|
||||
.in_ready(sink_ready),
|
||||
.in_valid(sink_valid),
|
||||
.out_clk(tck),
|
||||
.out_reset(~jtag_clock_reset_n),
|
||||
.out_data(jtag_sink_data),
|
||||
.out_ready(jtag_sink_ready),
|
||||
.out_valid(jtag_sink_valid)
|
||||
);
|
||||
|
||||
altera_jtag_src_crosser #(
|
||||
.SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
|
||||
) source_crosser (
|
||||
.sink_clk(tck),
|
||||
.sink_reset_n(jtag_clock_reset_n),
|
||||
.sink_valid(jtag_source_valid),
|
||||
.sink_data(jtag_source_data),
|
||||
.src_clk(clk),
|
||||
.src_reset_n(reset_n),
|
||||
.src_valid(source_valid),
|
||||
.src_data(source_data)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43mf05yrKMA+uPdz5tOrx7e5HExSwPsvBYo6nuRS+JViKkGWUOniDW3NDMxPpUiEChz1wDtyqt0bYSnK0cPHA0neGHMbl9mxVDoyOW9dlDnU0P+Ym6p1vzyQYq52H54kJy0/c2GKCikQaqX+YZG1pBZ8V1YlMDOepq+7WF8JX+GAmDLFbl4L26qzoGrlN8LdW+Qr9k9ZxE8W1J5okyjtyTvqLTXCbxxGD0ZwAKjQeQl4U35Fdi4PNa2IdJc+h4nOoJ0WJEa6i65rhFGLDxHYlwWBBFZt4MoFrk7Bw7MzQXNHkV0UHlnK6oqS6Rka3xOujIzwzOqgDXjaSoXt7Ts4VRjY08temLjq2rgczO+5ED6hks3Qh9Yx1GnZnEnLTpc/zmAYd3jStXvd8MmeLvriTIAGcm4vNW1viqjaQaBnIobM3TOc+Z8P8oKk6P3JO/7t89bGi5/A7HojpJw0daAZkSDHyh7xQfDDc+GJeRg5k5tPVf65FmVbpco36fRM5fQwhnmXisNZkoEgYO044IoBceUE4HD6jbh2umBVPDrb66IvDZyr/64QmjHMNT6uzPUsph1jBD0BhzoPwllykfeQhEnHrIrXQ/s+QKBImnLRlix4+rMt0cWaqJ+tZ7i1V2tqTA1hSR5HjXN+NtuCoDTtnMV+fMrPTa2VARCrY6Bh2DM63R0fNSjnq+5pB8SbDlmb6EDxYKzZDSJTB2pXfiHco8gHytfgMSvg4m1LKS9xUVDV2VjnxoKbWPBfr8fCCcfSm1Qb54affjg0pAgS6lz2zkGD"
|
||||
`endif
|
||||
+264
@@ -0,0 +1,264 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ns / 1 ns
|
||||
// synopsys translate_on
|
||||
module altera_jtag_sld_node (
|
||||
ir_out,
|
||||
tdo,
|
||||
ir_in,
|
||||
tck,
|
||||
tdi,
|
||||
virtual_state_cdr,
|
||||
virtual_state_cir,
|
||||
virtual_state_e1dr,
|
||||
virtual_state_e2dr,
|
||||
virtual_state_pdr,
|
||||
virtual_state_sdr,
|
||||
virtual_state_udr,
|
||||
virtual_state_uir
|
||||
);
|
||||
|
||||
parameter TCK_FREQ_MHZ = 20;
|
||||
localparam TCK_HALF_PERIOD_US = (1000/TCK_FREQ_MHZ)/2;
|
||||
localparam IRWIDTH = 3;
|
||||
|
||||
input [IRWIDTH - 1:0] ir_out;
|
||||
input tdo;
|
||||
output reg [IRWIDTH - 1:0] ir_in;
|
||||
output tck;
|
||||
output reg tdi = 1'b0;
|
||||
output virtual_state_cdr;
|
||||
output virtual_state_cir;
|
||||
output virtual_state_e1dr;
|
||||
output virtual_state_e2dr;
|
||||
output virtual_state_pdr;
|
||||
output virtual_state_sdr;
|
||||
output virtual_state_udr;
|
||||
output virtual_state_uir;
|
||||
|
||||
// PHY Simulation signals
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
reg simulation_clock;
|
||||
reg sdrs;
|
||||
reg cdr;
|
||||
reg sdr;
|
||||
reg e1dr;
|
||||
reg udr;
|
||||
reg [7:0] bit_index;
|
||||
`endif
|
||||
|
||||
|
||||
// PHY Instantiation
|
||||
`ifdef ALTERA_RESERVED_QIS
|
||||
wire tdi_port;
|
||||
wire [IRWIDTH - 1:0] ir_in_port;
|
||||
always @(tdi_port)
|
||||
tdi = tdi_port;
|
||||
always @(ir_in_port)
|
||||
ir_in = ir_in_port;
|
||||
sld_virtual_jtag_basic sld_virtual_jtag_component (
|
||||
.ir_out (ir_out),
|
||||
.tdo (tdo),
|
||||
.tdi (tdi_port),
|
||||
.tck (tck),
|
||||
.ir_in (ir_in_port),
|
||||
.virtual_state_cir (virtual_state_cir),
|
||||
.virtual_state_pdr (virtual_state_pdr),
|
||||
.virtual_state_uir (virtual_state_uir),
|
||||
.virtual_state_sdr (virtual_state_sdr),
|
||||
.virtual_state_cdr (virtual_state_cdr),
|
||||
.virtual_state_udr (virtual_state_udr),
|
||||
.virtual_state_e1dr (virtual_state_e1dr),
|
||||
.virtual_state_e2dr (virtual_state_e2dr)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.jtag_state_cdr (),
|
||||
.jtag_state_cir (),
|
||||
.jtag_state_e1dr (),
|
||||
.jtag_state_e1ir (),
|
||||
.jtag_state_e2dr (),
|
||||
.jtag_state_e2ir (),
|
||||
.jtag_state_pdr (),
|
||||
.jtag_state_pir (),
|
||||
.jtag_state_rti (),
|
||||
.jtag_state_sdr (),
|
||||
.jtag_state_sdrs (),
|
||||
.jtag_state_sir (),
|
||||
.jtag_state_sirs (),
|
||||
.jtag_state_tlr (),
|
||||
.jtag_state_udr (),
|
||||
.jtag_state_uir (),
|
||||
.tms ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
sld_virtual_jtag_component.sld_mfg_id = 110,
|
||||
sld_virtual_jtag_component.sld_type_id = 132,
|
||||
sld_virtual_jtag_component.sld_version = 1,
|
||||
sld_virtual_jtag_component.sld_auto_instance_index = "YES",
|
||||
sld_virtual_jtag_component.sld_instance_index = 0,
|
||||
sld_virtual_jtag_component.sld_ir_width = IRWIDTH,
|
||||
sld_virtual_jtag_component.sld_sim_action = "",
|
||||
sld_virtual_jtag_component.sld_sim_n_scan = 0,
|
||||
sld_virtual_jtag_component.sld_sim_total_length = 0;
|
||||
`endif
|
||||
|
||||
// PHY Simulation
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
|
||||
localparam DATA = 0;
|
||||
localparam LOOPBACK = 1;
|
||||
localparam DEBUG = 2;
|
||||
localparam INFO = 3;
|
||||
localparam CONTROL = 4;
|
||||
localparam MGMT = 5;
|
||||
|
||||
always
|
||||
//#TCK_HALF_PERIOD_US simulation_clock = $random;
|
||||
#TCK_HALF_PERIOD_US simulation_clock = ~simulation_clock;
|
||||
|
||||
assign tck = simulation_clock;
|
||||
assign virtual_state_cdr = cdr;
|
||||
assign virtual_state_sdr = sdr;
|
||||
assign virtual_state_e1dr = e1dr;
|
||||
assign virtual_state_udr = udr;
|
||||
|
||||
task reset_jtag_state;
|
||||
begin
|
||||
simulation_clock = 0;
|
||||
enter_data_mode;
|
||||
clear_states_async;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_data_mode;
|
||||
begin
|
||||
ir_in = DATA;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_loopback_mode;
|
||||
begin
|
||||
ir_in = LOOPBACK;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_debug_mode;
|
||||
begin
|
||||
ir_in = DEBUG;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_info_mode;
|
||||
begin
|
||||
ir_in = INFO;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_control_mode;
|
||||
begin
|
||||
ir_in = CONTROL;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_mgmt_mode;
|
||||
begin
|
||||
ir_in = MGMT;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_sdrs_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b10000;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_cdr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b01000;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_e1dr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b00010;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_udr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b00001;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task clear_states;
|
||||
begin
|
||||
clear_states_async;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task clear_states_async;
|
||||
begin
|
||||
{cdr, sdr, e1dr, udr} = 4'b0000;
|
||||
end
|
||||
endtask
|
||||
|
||||
task shift_one_bit;
|
||||
input bit_to_send;
|
||||
output reg bit_received;
|
||||
begin
|
||||
{cdr, sdr, e1dr, udr} = 4'b0100;
|
||||
tdi = bit_to_send;
|
||||
@(posedge tck);
|
||||
bit_received = tdo;
|
||||
end
|
||||
endtask
|
||||
|
||||
task shift_one_byte;
|
||||
input [7:0] byte_to_send;
|
||||
output reg [7:0] byte_received;
|
||||
integer i;
|
||||
reg bit_received;
|
||||
begin
|
||||
for (i=0; i<8; i=i+1)
|
||||
begin
|
||||
bit_index = i;
|
||||
shift_one_bit(byte_to_send[i], bit_received);
|
||||
byte_received[i] = bit_received;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43lBZX0Ql68xHccZnfqaRGQKXb+suw0+G/pVTEtXeJpzBq/7bnHCezbavBscZWMlhms2Wz2URmxx5AQLfZNrIwyosndTDl7mhnY6ckOE2QmsqzCPHFVfq4mRCzHjlTEGBvU3Pi38puWVFCyHUhgA9k5vRLZLgICA671LQ7mWobio/jqN82rZy/80hkczOwRBCHIoEVojMe7Kee0pbosxgMF1hkjKr5sjgpJOuqnyk4mT2P6InXKbojsvp3j8x0NMlhZOLjYgGBtL4CeflmEzC2f1K6TWppWrqIv/d8t6sEGsAcEGhf/yaUUSe52KNjrmgKMp4cGL2M9LaQ++/BgomIZGsd5X3dgDh1XBHnCeY3AWP5sbZTrUGvsMJQBDYG/U9hdKB3l+nEMztYgo/WSROuURMSAuR14Qo+CHE6+OhjGLoOK1H+5Au7Alv7ZPDO39BRzf5JTH9LBHOCmhvRB7L5PsG9GP1+JpBpvCRQTt5Hv+fyOo521Uk2R1SU2tiXA2S3GgwsxTJjt9PLhSg2EgIkvixp5B4uO24Xy4vepP5zBOrHa/viz3qjUzdfJsOUOm/0q9mtykoOCHfBQ/mraGzh6nemQdKQ5vLYUn+G6AseV+rRLINc0S8qKakNetEG0zXEKBXfXIism4w+uKFnlomoQ1+TS+kj2fXKzUZW2eiWHL9azON0cDdGmTDQS8hu0p7Lf2x6iOlJUT9Po56UXAOLwOpCXHhiz8kfDU6ZBQDuZx0B/acIgjJ0p57A0qd2sFzN8oX7UcAIq/FF4EUfKiHNDk"
|
||||
`endif
|
||||
+650
@@ -0,0 +1,650 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ns / 1 ns
|
||||
// synopsys translate_on
|
||||
|
||||
module altera_jtag_streaming #(
|
||||
parameter PURPOSE = 0,
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = 0
|
||||
) (
|
||||
// JTAG Signals
|
||||
input wire tck,
|
||||
input wire tdi,
|
||||
output reg tdo,
|
||||
input wire [2:0] ir_in,
|
||||
input wire virtual_state_cdr,
|
||||
input wire virtual_state_sdr,
|
||||
input wire virtual_state_udr,
|
||||
|
||||
input wire reset_n,
|
||||
// Source Signals
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
// Sink Signals
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
// Clock Debug Signals
|
||||
input wire clock_to_sample,
|
||||
input wire reset_to_sample,
|
||||
// Resetrequest signal
|
||||
output reg resetrequest,
|
||||
// Debug reset and management channel
|
||||
output wire debug_reset,
|
||||
output reg mgmt_valid,
|
||||
output reg [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output reg mgmt_data
|
||||
);
|
||||
|
||||
// function to calculate log2, floored.
|
||||
function integer flog2;
|
||||
input [31:0] Depth;
|
||||
integer i;
|
||||
begin
|
||||
i = Depth;
|
||||
if ( i <= 0 ) flog2 = 0;
|
||||
else begin
|
||||
for(flog2 = -1; i > 0; flog2 = flog2 + 1)
|
||||
i = i >> 1;
|
||||
end
|
||||
end
|
||||
endfunction // flog2
|
||||
|
||||
localparam UPSTREAM_ENCODED_SIZE = flog2(UPSTREAM_FIFO_SIZE);
|
||||
localparam DOWNSTREAM_ENCODED_SIZE = flog2(DOWNSTREAM_FIFO_SIZE);
|
||||
|
||||
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
|
||||
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
|
||||
localparam TCK_TO_SYSCLK_SYNC_DEPTH_PLUS_ONE = 9;
|
||||
|
||||
// IR values determine the operating modes
|
||||
localparam DATA = 0;
|
||||
localparam LOOPBACK = 1;
|
||||
localparam DEBUG = 2;
|
||||
localparam INFO = 3;
|
||||
localparam CONTROL = 4;
|
||||
localparam MGMT = 5;
|
||||
|
||||
// Operating Modes:
|
||||
// Data - To send data which its size and valid position are encoded in the header bytes of the data stream
|
||||
// Loopback - To become a JTAG loopback with a bypass register
|
||||
// Debug - To read the values of the clock sensing, clock sampling and reset sampling
|
||||
// Info - To read the parameterized values that describe the components connected to JTAG Phy which is of great interest to the driver
|
||||
// Control - To set the offset of bit-padding and to do a reset request
|
||||
// Mgmt - Send management commands (resets mostly) to agents
|
||||
|
||||
localparam IRWIDTH = 3;
|
||||
|
||||
// State machine encoding for write_state
|
||||
localparam ST_BYPASS = 'h0;
|
||||
localparam ST_HEADER_1 = 'h1;
|
||||
localparam ST_HEADER_2 = 'h2;
|
||||
localparam ST_WRITE_DATA = 'h3;
|
||||
|
||||
// State machine encoding for read_state
|
||||
localparam ST_HEADER = 'h0;
|
||||
localparam ST_PADDED = 'h1;
|
||||
localparam ST_READ_DATA = 'h2;
|
||||
|
||||
reg [1:0] write_state = ST_BYPASS;
|
||||
reg [1:0] read_state = ST_HEADER;
|
||||
|
||||
reg [ 7:0] dr_data_in = 'b0;
|
||||
reg [ 7:0] dr_data_out = 'b0;
|
||||
reg dr_loopback = 'b0;
|
||||
reg [ 2:0] dr_debug = 'b0;
|
||||
reg [10:0] dr_info = 'b0;
|
||||
reg [ 8:0] dr_control = 'b0;
|
||||
reg [MGMT_CHANNEL_WIDTH+2:0] dr_mgmt = 'b0;
|
||||
|
||||
reg [ 8:0] padded_bit_counter = 'b0;
|
||||
reg [ 7:0] bypass_bit_counter = 'b0;
|
||||
reg [ 2:0] write_data_bit_counter = 'b0;
|
||||
reg [ 2:0] read_data_bit_counter = 'b0;
|
||||
reg [ 3:0] header_in_bit_counter = 'b0;
|
||||
reg [ 3:0] header_out_bit_counter = 'b0;
|
||||
reg [18:0] scan_length_byte_counter = 'b0;
|
||||
reg [18:0] valid_write_data_length_byte_counter = 'b0;
|
||||
|
||||
reg write_data_valid = 'b0;
|
||||
reg read_data_valid = 'b0;
|
||||
reg read_data_all_valid = 'b0;
|
||||
|
||||
reg decode_header_1 = 'b0;
|
||||
reg decode_header_2 = 'b0;
|
||||
|
||||
wire write_data_byte_aligned;
|
||||
wire read_data_byte_aligned;
|
||||
wire padded_bit_byte_aligned;
|
||||
wire bytestream_end;
|
||||
|
||||
assign write_data_byte_aligned = (write_data_bit_counter == 1);
|
||||
assign read_data_byte_aligned = (read_data_bit_counter == 1);
|
||||
assign padded_bit_byte_aligned = (padded_bit_counter[2:0] == 'b0);
|
||||
assign bytestream_end = (scan_length_byte_counter == 'b0);
|
||||
|
||||
reg [ 7:0] offset = 'b0;
|
||||
reg [15:0] header_in = 'b0;
|
||||
|
||||
reg [9:0] scan_length = 'b0;
|
||||
reg [2:0] read_data_length = 'b0;
|
||||
reg [2:0] write_data_length = 'b0;
|
||||
|
||||
wire [7:0] idle_inserter_sink_data;
|
||||
wire idle_inserter_sink_valid;
|
||||
wire idle_inserter_sink_ready;
|
||||
wire [7:0] idle_inserter_source_data;
|
||||
reg idle_inserter_source_ready = 'b0;
|
||||
reg [7:0] idle_remover_sink_data = 'b0;
|
||||
reg idle_remover_sink_valid = 'b0;
|
||||
wire [7:0] idle_remover_source_data;
|
||||
wire idle_remover_source_valid;
|
||||
|
||||
assign source_data = idle_remover_source_data;
|
||||
assign source_valid = idle_remover_source_valid;
|
||||
assign sink_ready = idle_inserter_sink_ready;
|
||||
assign idle_inserter_sink_data = sink_data;
|
||||
assign idle_inserter_sink_valid = sink_valid;
|
||||
|
||||
reg clock_sensor = 'b0;
|
||||
reg clock_to_sample_div2 = 'b0;
|
||||
(* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) reg clock_sense_reset_n = 'b1;
|
||||
|
||||
wire data_available;
|
||||
|
||||
assign data_available = sink_valid;
|
||||
|
||||
wire [18:0] decoded_scan_length;
|
||||
wire [18:0] decoded_write_data_length;
|
||||
wire [18:0] decoded_read_data_length;
|
||||
|
||||
assign decoded_scan_length = { scan_length, {8{1'b1}} };
|
||||
// +-------------------+----------------+---------------------+
|
||||
// | scan_length | Length (bytes) | decoded_scan_length |
|
||||
// +-------------------+----------------+---------------------+
|
||||
// | 0x0 | 256 | 0x0ff (255) |
|
||||
// | 0x1 | 512 | 0x1ff (511) |
|
||||
// | 0x2 | 768 | 0x2ff (767) |
|
||||
// | . | . | . |
|
||||
// | 0x3ff | 256k | 0x3ff (256k-1) |
|
||||
// +-------------------+----------------+---------------------+
|
||||
|
||||
// TODO: use look up table to save LEs?
|
||||
// Decoded value is correct except for 0x7
|
||||
assign decoded_write_data_length = (write_data_length == 0) ? 19'h0 : (19'h00080 << write_data_length);
|
||||
assign decoded_read_data_length = (read_data_length == 0) ? 19'h0 : (19'h00080 << read_data_length);
|
||||
// +-------------------+---------------+---------------------------+
|
||||
// | read_data_length | Length | decoded_read_data_length |
|
||||
// | write_data_length | (bytes) | decoded_write_data_length |
|
||||
// +-------------------+---------------+---------------------------+
|
||||
// | 0x0 | 0 | 0x0000 (0) |
|
||||
// | 0x1 | 256 | 0x0100 (256) |
|
||||
// | 0x2 | 512 | 0x0200 (512) |
|
||||
// | 0x3 | 1k | 0x0400 (1024) |
|
||||
// | 0x4 | 2k | 0x0800 (2048) |
|
||||
// | 0x5 | 4k | 0x1000 (4096) |
|
||||
// | 0x6 | 8k | 0x2000 (8192) |
|
||||
// | 0x7 | scan_length | invalid |
|
||||
// +-------------------+---------------+---------------------------+
|
||||
|
||||
wire clock_sensor_sync;
|
||||
wire reset_to_sample_sync;
|
||||
wire clock_to_sample_div2_sync;
|
||||
wire clock_sense_reset_n_sync;
|
||||
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_sensor_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(clock_sensor),
|
||||
.dout(clock_sensor_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) reset_to_sample_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(reset_to_sample),
|
||||
.dout(reset_to_sample_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_to_sample_div2_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(clock_to_sample_div2),
|
||||
.dout(clock_to_sample_div2_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) clock_sense_reset_n_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(clock_sense_reset_n),
|
||||
.din(1'b1),
|
||||
.dout(clock_sense_reset_n_sync));
|
||||
|
||||
|
||||
|
||||
always @ (posedge clock_to_sample or negedge clock_sense_reset_n_sync) begin
|
||||
if (~clock_sense_reset_n_sync) begin
|
||||
clock_sensor <= 1'b0;
|
||||
end else begin
|
||||
clock_sensor <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge clock_to_sample) begin
|
||||
clock_to_sample_div2 <= ~clock_to_sample_div2;
|
||||
end
|
||||
|
||||
always @ (posedge tck) begin
|
||||
|
||||
idle_remover_sink_valid <= 1'b0;
|
||||
idle_inserter_source_ready <= 1'b0;
|
||||
|
||||
// Data mode sourcing (write)
|
||||
|
||||
// offset(rounded 8) m-i i 16 offset
|
||||
// +------------+-----------+------------------+--------+------------+
|
||||
// tdi -> | padded_bit | undefined | valid_write_data | header | bypass_bit |
|
||||
// +------------+-----------+------------------+--------+------------+
|
||||
// Data mode DR data stream write format (as seen by hardware)
|
||||
//
|
||||
if (ir_in == DATA) begin
|
||||
|
||||
|
||||
if (virtual_state_cdr) begin
|
||||
if (offset == 'b0) begin
|
||||
write_state <= ST_HEADER_1;
|
||||
end else begin
|
||||
write_state <= ST_BYPASS;
|
||||
end
|
||||
// 8-bit bypass_bit_counter
|
||||
bypass_bit_counter <= offset;
|
||||
// 4-bit header_in_bit_counter
|
||||
header_in_bit_counter <= 15;
|
||||
// 3-bit write_data_bit_counter
|
||||
write_data_bit_counter <= 0;
|
||||
// Reset the registers
|
||||
// TODO: not necessarily all, reduce LE
|
||||
decode_header_1 <= 1'b0;
|
||||
decode_header_2 <= 1'b0;
|
||||
read_data_all_valid <= 1'b0;
|
||||
valid_write_data_length_byte_counter <= 0;
|
||||
end
|
||||
|
||||
if (virtual_state_sdr) begin
|
||||
// Discard bypass bits, then decode the 16-bit header
|
||||
// 3 3 10
|
||||
// +-------------------+------------------+-------------+
|
||||
// | write_data_length | read_data_length | scan_length |
|
||||
// +-------------------+------------------+-------------+
|
||||
// Header format
|
||||
|
||||
case (write_state)
|
||||
ST_BYPASS: begin
|
||||
// Discard the bypass bit
|
||||
bypass_bit_counter <= bypass_bit_counter - 1'b1;
|
||||
if (bypass_bit_counter == 1) begin
|
||||
write_state <= ST_HEADER_1;
|
||||
end
|
||||
end
|
||||
// Shift the scan_length and read_data_length
|
||||
ST_HEADER_1: begin
|
||||
// TODO: header_in can be shorter
|
||||
// Shift into header_in
|
||||
header_in <= {tdi, header_in[15:1]};
|
||||
header_in_bit_counter <= header_in_bit_counter - 1'b1;
|
||||
if (header_in_bit_counter == 3) begin
|
||||
read_data_length <= {tdi, header_in[15:14]};
|
||||
scan_length <= header_in[13:4];
|
||||
write_state <= ST_HEADER_2;
|
||||
decode_header_1 <= 1'b1;
|
||||
end
|
||||
end
|
||||
// Shift the write_data_length
|
||||
ST_HEADER_2: begin
|
||||
// Shift into header_in
|
||||
header_in <= {tdi, header_in[15:1]};
|
||||
header_in_bit_counter <= header_in_bit_counter - 1'b1;
|
||||
// Decode read_data_length and scan_length
|
||||
if (decode_header_1) begin
|
||||
decode_header_1 <= 1'b0;
|
||||
// Set read_data_all_valid
|
||||
if (read_data_length == 3'b111) begin
|
||||
read_data_all_valid <= 1'b1;
|
||||
end
|
||||
// Load scan_length_byte_counter
|
||||
scan_length_byte_counter <= decoded_scan_length;
|
||||
end
|
||||
if (header_in_bit_counter == 0) begin
|
||||
write_data_length <= {tdi, header_in[15:14]};
|
||||
write_state <= ST_WRITE_DATA;
|
||||
decode_header_2 <= 1'b1;
|
||||
end
|
||||
end
|
||||
// Shift the valid_write_data
|
||||
ST_WRITE_DATA: begin
|
||||
// Shift into dr_data_in
|
||||
dr_data_in <= {tdi, dr_data_in[7:1]};
|
||||
// Decode write_data_length
|
||||
if (decode_header_2) begin
|
||||
decode_header_2 <= 1'b0;
|
||||
// Load valid_write_data_length_byte_counter
|
||||
case (write_data_length)
|
||||
3'b111: valid_write_data_length_byte_counter <= decoded_scan_length + 1'b1;
|
||||
3'b000: valid_write_data_length_byte_counter <= 'b0;
|
||||
default: valid_write_data_length_byte_counter <= decoded_write_data_length;
|
||||
endcase
|
||||
end
|
||||
write_data_bit_counter <= write_data_bit_counter - 1'b1;
|
||||
write_data_valid <= (valid_write_data_length_byte_counter != 0);
|
||||
// Feed the data to the idle remover
|
||||
if (write_data_byte_aligned && write_data_valid) begin
|
||||
valid_write_data_length_byte_counter <= valid_write_data_length_byte_counter - 1'b1;
|
||||
idle_remover_sink_valid <= 1'b1;
|
||||
idle_remover_sink_data <= {tdi, dr_data_in[7:1]};
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// Data mode sinking (read)
|
||||
|
||||
// i m-i offset(rounded 8) 16
|
||||
// +-----------------+-----------+------------+--------+
|
||||
// | valid_read_data | undefined | padded_bit | header | -> tdo
|
||||
// +-----------------+-----------+------------+--------+
|
||||
// Data mode DR data stream read format (as seen by hardware)
|
||||
//
|
||||
if (ir_in == DATA) begin
|
||||
|
||||
if (virtual_state_cdr) begin
|
||||
|
||||
read_state <= ST_HEADER;
|
||||
// Offset is rounded to nearest ceiling x8 to byte-align padded bits
|
||||
// 9-bit padded_bit_counter
|
||||
if (|offset[2:0]) begin
|
||||
padded_bit_counter[8:3] <= offset[7:3] + 1'b1;
|
||||
padded_bit_counter[2:0] <= 3'b0;
|
||||
end else begin
|
||||
padded_bit_counter <= {1'b0, offset};
|
||||
end
|
||||
// 4-bit header_out_bit_counter
|
||||
header_out_bit_counter <= 0;
|
||||
// 3-bit read_data_bit_counter
|
||||
read_data_bit_counter <= 0;
|
||||
// Load the data_available bit into header
|
||||
dr_data_out <= {{7{1'b0}}, data_available};
|
||||
read_data_valid <= 0;
|
||||
|
||||
end
|
||||
|
||||
if (virtual_state_sdr) begin
|
||||
// 10 1
|
||||
// +-----------------------------------+----------------+
|
||||
// | reserved | data_available |
|
||||
// +-----------------------------------+----------------+
|
||||
// Header format
|
||||
|
||||
dr_data_out <= {1'b0, dr_data_out[7:1]};
|
||||
case (read_state)
|
||||
// Shift the scan_length and read_data_length
|
||||
ST_HEADER: begin
|
||||
header_out_bit_counter <= header_out_bit_counter - 1'b1;
|
||||
// Retrieve data from idle inserter for the next shift if no paddded bits
|
||||
if (header_out_bit_counter == 2) begin
|
||||
if (padded_bit_counter == 0) begin
|
||||
idle_inserter_source_ready <= read_data_all_valid;
|
||||
end
|
||||
end
|
||||
if (header_out_bit_counter == 1) begin
|
||||
if (padded_bit_counter == 0) begin
|
||||
read_state <= ST_READ_DATA;
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
|
||||
end else begin
|
||||
read_state <= ST_PADDED;
|
||||
padded_bit_counter <= padded_bit_counter - 1'b1;
|
||||
idle_inserter_source_ready <= 1'b0;
|
||||
dr_data_out <= 8'h4a;
|
||||
end
|
||||
end
|
||||
end
|
||||
ST_PADDED: begin
|
||||
padded_bit_counter <= padded_bit_counter - 1'b1;
|
||||
if (padded_bit_byte_aligned) begin
|
||||
// Load idle character into data register
|
||||
dr_data_out <= 8'h4a;
|
||||
end
|
||||
// Retrieve data from idle inserter for the next shift when padded bits finish
|
||||
if (padded_bit_counter == 1) begin
|
||||
idle_inserter_source_ready <= read_data_all_valid;
|
||||
end
|
||||
if (padded_bit_counter == 0) begin // TODO: might make use of (padded_bit_counter[8:3]&padded_bit_byte_aligned)
|
||||
read_state <= ST_READ_DATA;
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
|
||||
end
|
||||
end
|
||||
ST_READ_DATA: begin
|
||||
read_data_bit_counter <= read_data_bit_counter - 1'b1;
|
||||
// Retrieve data from idle inserter just before read_data_byte_aligned
|
||||
if (read_data_bit_counter == 2) begin
|
||||
// Assert ready to retrieve data from idle inserter only when the bytestream has not ended,
|
||||
// data is valid (idle_inserter is always valid) and data is needed (read_data_valid)
|
||||
idle_inserter_source_ready <= bytestream_end ? 1'b0 : read_data_valid;
|
||||
end
|
||||
if (read_data_byte_aligned) begin
|
||||
// Note that bytestream_end is driven by scan_length_byte_counter
|
||||
if (~bytestream_end) begin
|
||||
scan_length_byte_counter <= scan_length_byte_counter - 1'b1;
|
||||
end
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
// Load idle character if bytestream has ended, else get data from the idle inserter
|
||||
dr_data_out <= (read_data_valid & ~bytestream_end) ? idle_inserter_source_data : 8'h4a;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// Loopback mode
|
||||
if (ir_in == LOOPBACK) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_loopback <= 1'b0; // capture 0
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_loopback
|
||||
dr_loopback <= tdi;
|
||||
end
|
||||
end
|
||||
|
||||
// Debug mode
|
||||
if (ir_in == DEBUG) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_debug <= {clock_sensor_sync, clock_to_sample_div2_sync, reset_to_sample_sync};
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_debug
|
||||
dr_debug <= {1'b0, dr_debug[2:1]}; // tdi is ignored
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
clock_sense_reset_n <= 1'b0;
|
||||
end else begin
|
||||
clock_sense_reset_n <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Info mode
|
||||
if (ir_in == INFO) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_info <= {PURPOSE[2:0], UPSTREAM_ENCODED_SIZE[3:0], DOWNSTREAM_ENCODED_SIZE[3:0]};
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_info
|
||||
dr_info <= {1'b0, dr_info[10:1]}; // tdi is ignored
|
||||
end
|
||||
end
|
||||
|
||||
// Control mode
|
||||
if (ir_in == CONTROL) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_control <= 'b0; // capture 0
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_control
|
||||
dr_control <= {tdi, dr_control[8:1]};
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
// Update resetrequest and offset
|
||||
{resetrequest, offset} <= dr_control;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @ * begin
|
||||
if (virtual_state_sdr) begin
|
||||
case (ir_in)
|
||||
DATA: tdo <= dr_data_out[0];
|
||||
LOOPBACK: tdo <= dr_loopback;
|
||||
DEBUG: tdo <= dr_debug[0];
|
||||
INFO: tdo <= dr_info[0];
|
||||
CONTROL: tdo <= dr_control[0];
|
||||
MGMT: tdo <= dr_mgmt[0];
|
||||
default: tdo <= 1'b0;
|
||||
endcase
|
||||
end else begin
|
||||
tdo <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Idle Remover
|
||||
altera_avalon_st_idle_remover idle_remover (
|
||||
// Interface: clk
|
||||
.clk (tck),
|
||||
.reset_n (reset_n),
|
||||
|
||||
// Interface: ST in
|
||||
.in_ready (), // left disconnected
|
||||
.in_valid (idle_remover_sink_valid),
|
||||
.in_data (idle_remover_sink_data),
|
||||
|
||||
// Interface: ST out
|
||||
.out_ready (1'b1), // downstream is expected to be always ready
|
||||
.out_valid (idle_remover_source_valid),
|
||||
.out_data (idle_remover_source_data)
|
||||
);
|
||||
|
||||
// Idle Inserter
|
||||
altera_avalon_st_idle_inserter idle_inserter (
|
||||
// Interface: clk
|
||||
.clk (tck),
|
||||
.reset_n (reset_n),
|
||||
|
||||
// Interface: ST in
|
||||
.in_ready (idle_inserter_sink_ready),
|
||||
.in_valid (idle_inserter_sink_valid),
|
||||
.in_data (idle_inserter_sink_data),
|
||||
|
||||
// Interface: ST out
|
||||
.out_ready (idle_inserter_source_ready),
|
||||
.out_valid (),
|
||||
.out_data (idle_inserter_source_data)
|
||||
);
|
||||
|
||||
generate
|
||||
if (MGMT_CHANNEL_WIDTH > 0)
|
||||
begin : has_mgmt
|
||||
reg [MGMT_CHANNEL_WIDTH+2:0] mgmt_out = 'b0;
|
||||
reg mgmt_toggle = 1'b0;
|
||||
wire mgmt_toggle_sync;
|
||||
reg mgmt_toggle_prev;
|
||||
wire mgmt_out_sync_ctl;
|
||||
|
||||
always @ (posedge tck) begin
|
||||
// Debug mode
|
||||
if (ir_in == MGMT) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_mgmt <= 'b0;
|
||||
dr_mgmt[MGMT_CHANNEL_WIDTH+2] <= 1'b1;
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_debug
|
||||
dr_mgmt <= {tdi, dr_mgmt[MGMT_CHANNEL_WIDTH+2:1]};
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
mgmt_out <= dr_mgmt;
|
||||
mgmt_toggle <= mgmt_out[MGMT_CHANNEL_WIDTH+2] ? 1'b0 : ~mgmt_toggle;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) debug_reset_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(1'b1),
|
||||
.din(mgmt_out[MGMT_CHANNEL_WIDTH+2]),
|
||||
.dout(debug_reset));
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH_PLUS_ONE)) mgmt_toggle_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(1'b1),
|
||||
.din(mgmt_toggle),
|
||||
.dout(mgmt_toggle_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) mgmt_out_synchornizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(1'b1),
|
||||
.din(mgmt_out[MGMT_CHANNEL_WIDTH+1]),
|
||||
.dout(mgmt_out_sync_ctl));
|
||||
|
||||
|
||||
|
||||
always @ (posedge clock_to_sample or posedge debug_reset) begin
|
||||
if (debug_reset) begin
|
||||
mgmt_valid <= 1'b0;
|
||||
mgmt_toggle_prev <= 1'b0;
|
||||
end else begin
|
||||
if ((mgmt_toggle_sync ^ mgmt_toggle_prev) && mgmt_out_sync_ctl) begin
|
||||
mgmt_valid <= 1'b1;
|
||||
mgmt_channel <= mgmt_out[MGMT_CHANNEL_WIDTH:1];
|
||||
mgmt_data <= mgmt_out[0];
|
||||
end else begin
|
||||
mgmt_valid <= 1'b0;
|
||||
end
|
||||
mgmt_toggle_prev <= mgmt_toggle_sync;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
else
|
||||
begin : no_mgmt
|
||||
always @ (posedge tck) begin
|
||||
dr_mgmt[0] <= 1'b0;
|
||||
end
|
||||
assign debug_reset = 1'b0;
|
||||
always @ (posedge clock_to_sample) begin
|
||||
mgmt_valid <= 1'b0;
|
||||
mgmt_data <= 'b0;
|
||||
mgmt_channel <= 'b0;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43nch1THUj1J8wIocquwt/bKC/6wb5IrPaKQhLL4d9X7qOL25fim0OQ3w1e0kI9Su7SxOq7ZeSyLHj+thEW81l9l8AIIwYAnL8RErrsKah5+K4cM0jnu4Q57T7g5np938yAiAJHtcHjIGKM7kBQ8LOc/GvAIFGNaoWSAU+fzOm9T0zKuxhwPOFnvX/y2bCxbSGVw0YUtrKWi6k3DtxMHvxpI1B0A/PRseX5R/ZU0YsatatbrJ9bBer2Cgm95xnVbEsjyotNgilqeYUu/UgEby87pNGmOZd+Q8kTdNo6dBoHXXd3SQgzQZmNfyzZ0rudNzqJIG1q1YDtm3mMyQLIPhgneAjvB3l4HHHEdZaQW7QqQekZIxvqWjb6uCAKdfleuj/5tSASLRRKfjbS3tgmSR/vENA8bCbwBIQyPjO6a8sP/cVJJ1SY1UpSWi8lFdOA/YU8Y93mbIp3zqbCGvJX2uFvY9isn0VI71r0cYtq0LiKIv1+cEhjBsjHkjTHOSIfB45TxCawv4zFyTFlXFMeu1eSw+gKDrO3f944d/+fO5hb9awxgONZ1Qc8sdjDvw+JSnNwIvj+CZHWhF7k8EnUrGrA3id6ahcy5ss0wiZSNia7RwLg/y+hBdhnmCSMTdDFwXQ8UCndkIJi6mfsx3C+/NbHL7Mq1WOF/8+t0eBVEWrBrbtoiet15r/GMbZycW2wzHUUd5lW5CrMBdqVcOXKkS4nid4gZdeUdB5gifM6uvnL0hMwlftSdr1VbxBNE8EnzL5+Sbe7tRYnJrpPaI9v467AP"
|
||||
`endif
|
||||
+89
@@ -0,0 +1,89 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// -----------------------------------------------
|
||||
// Reset Synchronizer
|
||||
// -----------------------------------------------
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_synchronizer
|
||||
#(
|
||||
parameter ASYNC_RESET = 1,
|
||||
parameter DEPTH = 2
|
||||
)
|
||||
(
|
||||
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
|
||||
|
||||
input clk,
|
||||
output reset_out
|
||||
);
|
||||
|
||||
// -----------------------------------------------
|
||||
// Synchronizer register chain. We cannot reuse the
|
||||
// standard synchronizer in this implementation
|
||||
// because our timing constraints are different.
|
||||
//
|
||||
// Instead of cutting the timing path to the d-input
|
||||
// on the first flop we need to cut the aclr input.
|
||||
//
|
||||
// We omit the "preserve" attribute on the final
|
||||
// output register, so that the synthesis tool can
|
||||
// duplicate it where needed.
|
||||
// -----------------------------------------------
|
||||
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
|
||||
reg altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
generate if (ASYNC_RESET) begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert asynchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk or posedge reset_in) begin
|
||||
if (reset_in) begin
|
||||
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
|
||||
altera_reset_synchronizer_int_chain_out <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end else begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert synchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk) begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43m3wnlehhyl/tvDkBTp1EtPpbSB7YBxMa/I8ZSI1dsWR/qcwyHhk27aoKzAbN2oGgXxnkwGf/9jPkx/jeL/VKbKIEY/78RjwxdNSCxTIRDJqQC4btrU936foYfcH4GIkOj1Pb8nFcEnnGY2UJoXMYcN51IJ1jy971+TxnUYP9B6ARYUmle9XtPoHHUKAYDS/tpju+pAaSva2iqW+gYvhSLYW1152f8xap7C5X60qVk8Bs11aIz0KJPZdF+f8bl9mwoAU39/rZQ6WcxvYEj1WnTK9f+aUGqcmmR+vUNBXXNN0C54sq0s5+6Nl8rpoXhs5VLdHpQr7Hat1GKzvMbNFmVBKP7BMC8ZPrGL63Oy6brcicq+7H7Ba23PxPyxRFJRiTAzutT9yIp3fNKDF8Mxfa18JediNCf2ZaBWrSnyppAn3tdQhF/5EzJyKO4hnV97MohBYYq5jOYf9FAlLGWdPlUgTCu3eUDmAhDMLjL1gJ3Ra4I6eUQfUcGeV3naPYko4wBX4pUYdx5CfIVAObW/RPsXGvLBU/6Ua16JjWk9+HRLtyu1oF+tSyHwHSe6GTbtVimKfBv+Z9iq9fw3/pchuMmvOQ0erCRAWsGe1gVpq3THnpq2rsWByBDOpaxfSLEyW/s5dLZy5F77rEz3L5gN6hPD1Ip/9hRQqCswu8HpGj2nu8SfFiMcD7SGKBiuaXTY5Cjib0cZWywM7PTWyZf2PACVBwRn7evdMFX0LLrqaC0VbIgjapuMBfJ9UfmsFIdeEDpIFZUwIkWqsKmeF1BIPe1C"
|
||||
`endif
|
||||
+267
@@ -0,0 +1,267 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
|
||||
// $Revision: #8 $
|
||||
// $Date: 2009/02/18 $
|
||||
// $Author: pscheidt $
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// File: altera_std_synchronizer_nocut.v
|
||||
//
|
||||
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
|
||||
// as altera_std_synchronizer.v, except that the embedded false
|
||||
// path constraint is removed in this module. If you use this
|
||||
// module, you will have to apply the appropriate timing
|
||||
// constraints.
|
||||
//
|
||||
// We expect to make this a standard Quartus atom eventually.
|
||||
//
|
||||
// Composed of two or more flip flops connected in series.
|
||||
// Random metastable condition is simulated when the
|
||||
// __ALTERA_STD__METASTABLE_SIM macro is defined.
|
||||
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
|
||||
// on the Verilog simulator compiler command line to
|
||||
// enable this mode. In addition, define the macro
|
||||
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
|
||||
// with every metastable event generated in the synchronizer.
|
||||
//
|
||||
// Copyright (C) Altera Corporation 2009, All Rights Reserved
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_std_synchronizer_nocut (
|
||||
clk,
|
||||
reset_n,
|
||||
din,
|
||||
dout
|
||||
);
|
||||
|
||||
parameter depth = 3; // This value must be >= 2 !
|
||||
parameter rst_value = 0;
|
||||
|
||||
//when enabled, this will allow retiming for the sync depth >3.
|
||||
parameter retiming_reg_en = 0;
|
||||
|
||||
input clk;
|
||||
input reset_n;
|
||||
input din;
|
||||
output dout;
|
||||
|
||||
// QuartusII synthesis directives:
|
||||
// 1. Preserve all registers ie. do not touch them.
|
||||
// 2. Do not merge other flip-flops with synchronizer flip-flops.
|
||||
// QuartusII TimeQuest directives:
|
||||
// 1. Identify all flip-flops in this module as members of the synchronizer
|
||||
// to enable automatic metastability MTBF analysis.
|
||||
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
|
||||
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
|
||||
|
||||
//synthesis translate_off
|
||||
`ifndef QUARTUS_CDC
|
||||
initial begin
|
||||
if (retiming_reg_en == 0 ) begin
|
||||
if (depth <2) begin
|
||||
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (depth <4) begin
|
||||
$display("%m: Error: synchronizer length: %0d less than 4 with retiming enabled.", depth);
|
||||
end
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
// the first synchronizer register is either a simple D flop for synthesis
|
||||
// and non-metastable simulation or a D flop with a method to inject random
|
||||
// metastable events resulting in random delay of [0,1] cycles
|
||||
|
||||
`ifdef __ALTERA_STD__METASTABLE_SIM
|
||||
|
||||
reg[31:0] RANDOM_SEED = 123456;
|
||||
wire next_din_s1;
|
||||
wire dout;
|
||||
reg din_last;
|
||||
reg random;
|
||||
event metastable_event; // hook for debug monitoring
|
||||
|
||||
initial begin
|
||||
$display("%m: Info: Metastable event injection simulation mode enabled");
|
||||
random = $random;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset_n == 0)
|
||||
random <= $random(RANDOM_SEED);
|
||||
else
|
||||
random <= $random;
|
||||
end
|
||||
|
||||
assign next_din_s1 = (din_last ^ din) ? random : din;
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_last <= (rst_value == 0)? 1'b0 : 1'b1;
|
||||
else
|
||||
din_last <= din;
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
|
||||
else
|
||||
din_s1 <= next_din_s1;
|
||||
end
|
||||
|
||||
`else
|
||||
|
||||
//synthesis translate_on
|
||||
generate if (rst_value == 0)
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= 1'b0;
|
||||
else
|
||||
din_s1 <= din;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (rst_value == 1)
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= 1'b1;
|
||||
else
|
||||
din_s1 <= din;
|
||||
end
|
||||
endgenerate
|
||||
//synthesis translate_off
|
||||
|
||||
`endif
|
||||
|
||||
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
|
||||
always @(*) begin
|
||||
if (reset_n && (din_last != din) && (random != din)) begin
|
||||
$display("%m: Verbose Info: metastable event @ time %t", $time);
|
||||
->metastable_event;
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
//synthesis translate_on
|
||||
|
||||
// the remaining synchronizer registers form a simple shift register
|
||||
// of length depth-1
|
||||
generate if (rst_value == 0) begin
|
||||
if (retiming_reg_en == 0) begin
|
||||
if (depth < 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg <= din_s1;
|
||||
end
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg <= {dreg[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
|
||||
assign dout = dreg[depth-2];
|
||||
end
|
||||
|
||||
else begin //This part is enabled when we set retiming_reg_en =1
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [1:0] dreg1;
|
||||
reg [depth-4:0] dreg2;
|
||||
wire [depth-2:0] dreg3;
|
||||
|
||||
assign dreg3 = {dreg2,dreg1};
|
||||
|
||||
if (depth <= 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg1 <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg1 <= din_s1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
{dreg2,dreg1} <= {depth-1{1'b0}};
|
||||
else
|
||||
{dreg2,dreg1} <= {dreg3[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg3[depth-2];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
else begin
|
||||
if (retiming_reg_en == 0) begin
|
||||
if (depth < 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg <= din_s1;
|
||||
end
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg <= {dreg[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg[depth-2];
|
||||
end
|
||||
|
||||
else begin
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [1:0] dreg1;
|
||||
reg [depth-4:0] dreg2;
|
||||
wire [depth-2:0] dreg3;
|
||||
|
||||
assign dreg3 = {dreg2,dreg1};
|
||||
|
||||
if (depth <= 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg1 <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg1 <= din_s1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
{dreg2,dreg1} <= {depth-1{1'b1}};
|
||||
else
|
||||
{dreg2,dreg1} <= {dreg3[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg3[depth-2];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43mCNPgtQr4hyUU4j86E903EvNfn1Ii/WXb12AEo64XSzinw4H9M64X3VrqZhPbCO8xw9VuZTidKsxxCiGMDNJFPc5y1BTrLcKFthIozfH+O4KS+/oVUEBy9vO4GOsJxaSxhKvtTgjz5HZCGqEVWWYErC33V9PybEQtP4jtcp/BoprsnJd8iwiVAgsTIGcopMmGgf84pOj3nOuhzeU8d7uS3dusa48HLsimnu0BhQMaLC4weSp1Kt/Up8x/ernjcbOKU1hpYaJ4Ujin7FtRELzaVB/EYUhMmzNw94lF0CD9pLiLXhAhE2Keh19nNOqWY1WDhkTvMYyVp7CBh3Dryo3df78teIPhp52/W2iSie+4uUmcM5fMbH8OxEAonWNr09vofAiynIGfHVpzGGj6ut3v2SLN2gEtbakpZAaFooskDYgGwsJRa9S2uVGkTs5Gsa8vKFHOs96TdG59fw54QNai04RRZs6VlOcKk4dVTr9WYthRGlandQHiCDG85hyUn9M6QRI5hA5vsf3xqBsiP7RrHqFZzoVWopikMJzkNCQxbcIqmp+Pp85b9szMI7qPO9knJD2ujGcuLRYMBaFNQtoGTzU+PhfLRHQEdH7lI63TRJpwDx41BBVljDGLpc4lBF4PBIEZ5LeeFzjMIY+Oy2asXd7c93WPJbmwZDcwvoO3ZH9CJefKH3y0z83QRTPgYlTp1Cpe6jtY3L0HNttlWFhj4b7rwi+SRJgWVdxPcc+WoE/0/gN4BxAYeAs4HJ2gfBLX/cP75eNMU/eXC/UlLFneB"
|
||||
`endif
|
||||
+190
@@ -0,0 +1,190 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/26.1/ip/iconnect/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_clock_crosser(
|
||||
in_clk,
|
||||
in_reset,
|
||||
in_ready,
|
||||
in_valid,
|
||||
in_data,
|
||||
out_clk,
|
||||
out_reset,
|
||||
out_ready,
|
||||
out_valid,
|
||||
out_data
|
||||
);
|
||||
|
||||
parameter SYMBOLS_PER_BEAT = 1;
|
||||
parameter BITS_PER_SYMBOL = 8;
|
||||
parameter FORWARD_SYNC_DEPTH = 2;
|
||||
parameter BACKWARD_SYNC_DEPTH = 2;
|
||||
parameter USE_OUTPUT_PIPELINE = 1;
|
||||
|
||||
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
|
||||
|
||||
input in_clk;
|
||||
input in_reset;
|
||||
output in_ready;
|
||||
input in_valid;
|
||||
input [DATA_WIDTH-1:0] in_data;
|
||||
|
||||
input out_clk;
|
||||
input out_reset;
|
||||
input out_ready;
|
||||
output out_valid;
|
||||
output [DATA_WIDTH-1:0] out_data;
|
||||
|
||||
// Data is guaranteed valid by control signal clock crossing. Cut data
|
||||
// buffer false path.
|
||||
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
|
||||
(* altera_attribute = {"-name DESIGN_ASSISTANT_EXCLUDE \"CDC-50001,CDC-50006\""} *) reg [DATA_WIDTH-1:0] out_data_buffer;
|
||||
|
||||
reg in_data_toggle;
|
||||
wire in_data_toggle_returned;
|
||||
wire out_data_toggle;
|
||||
reg out_data_toggle_flopped, out_data_toggle_1, out_data_toggle_flopped_n;
|
||||
|
||||
wire take_in_data;
|
||||
wire out_data_taken;
|
||||
|
||||
wire out_valid_internal;
|
||||
wire out_ready_internal;
|
||||
wire reset_merged;
|
||||
wire out_reset_merged;
|
||||
wire in_reset_merged;
|
||||
|
||||
assign in_ready = (in_data_toggle_returned ^ in_data_toggle);
|
||||
assign take_in_data = in_valid & in_ready;
|
||||
assign out_valid_internal = out_data_toggle_1 ^ out_data_toggle_flopped;
|
||||
assign out_data_taken = out_ready_internal & out_valid_internal;
|
||||
|
||||
assign reset_merged = in_reset | out_reset;
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (2),
|
||||
.ASYNC_RESET(1'b1)
|
||||
)
|
||||
alt_rst_req_sync_in_rst
|
||||
(
|
||||
.clk (in_clk),
|
||||
.reset_in (reset_merged),
|
||||
.reset_out (in_reset_merged)
|
||||
);
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (2),
|
||||
.ASYNC_RESET(1'b1)
|
||||
)
|
||||
alt_rst_req_sync_out_rst
|
||||
(
|
||||
.clk (out_clk),
|
||||
.reset_in (reset_merged),
|
||||
.reset_out (out_reset_merged)
|
||||
);
|
||||
|
||||
always @(posedge in_clk or posedge in_reset_merged) begin
|
||||
if (in_reset_merged) begin
|
||||
in_data_buffer <= {DATA_WIDTH{1'b0}};
|
||||
in_data_toggle <= 1'b0;
|
||||
end else begin
|
||||
if (take_in_data) begin
|
||||
in_data_toggle <= ~in_data_toggle;
|
||||
in_data_buffer <= in_data;
|
||||
end
|
||||
end //in_reset
|
||||
end //in_clk always block
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_1 <= 1'b0;
|
||||
end else begin
|
||||
out_data_toggle_1 <= out_data_toggle;
|
||||
end //end if
|
||||
end //out_clk always block
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_flopped <= 1'b0;
|
||||
out_data_buffer <= {DATA_WIDTH{1'b0}};
|
||||
end else begin
|
||||
out_data_buffer <= in_data_buffer;
|
||||
if (out_data_taken) begin
|
||||
out_data_toggle_flopped <= out_data_toggle_1;
|
||||
end
|
||||
end //end if
|
||||
end //out_clk always block
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_flopped_n <= 1'b0;
|
||||
end else begin
|
||||
out_data_toggle_flopped_n <= ~out_data_toggle_flopped;
|
||||
end //end if
|
||||
end //out_clk always block
|
||||
|
||||
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
|
||||
.clk(out_clk),
|
||||
.reset_n(~out_reset_merged),
|
||||
.din(in_data_toggle),
|
||||
.dout(out_data_toggle)
|
||||
);
|
||||
|
||||
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
|
||||
.clk(in_clk),
|
||||
.reset_n(~in_reset_merged),
|
||||
.din(out_data_toggle_flopped_n),
|
||||
.dout(in_data_toggle_returned)
|
||||
);
|
||||
|
||||
|
||||
generate if (USE_OUTPUT_PIPELINE == 1) begin
|
||||
|
||||
altera_avalon_st_pipeline_base
|
||||
#(
|
||||
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
|
||||
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
|
||||
) output_stage (
|
||||
.clk(out_clk),
|
||||
.reset(out_reset_merged),
|
||||
.in_ready(out_ready_internal),
|
||||
.in_valid(out_valid_internal),
|
||||
.in_data(out_data_buffer),
|
||||
.out_ready(out_ready),
|
||||
.out_valid(out_valid),
|
||||
.out_data(out_data)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign out_valid = out_valid_internal;
|
||||
assign out_ready_internal = out_ready;
|
||||
assign out_data = out_data_buffer;
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43kLaZ1eFbVnzLHFC3Iy8C952zU9KJLT86rKkmt6MuQRY9VO2r7wzhfXVuNaV6/LGJ22nFWPP1Zlp8tX/FsFICDuTFBgn16uT/eLZl7yEPcOC57c1nPIQtrXm/twebJnc+420/b7beqdRjmppQV89jcr4IutIRg0q/UzyCC4/2fY5Vuv4y2RLPqG3uLPwFsqCGQQ6W2iLHjEudISQfpD6UFZwQM3AK0EzVxzO2mWaSdjScZLEwdTYkTvzmmmqgK+TppgH8xTxu9R5AwAToenaFVO1UaJ0UesZAYuLz4Ahtj/NeR6JnsD937RDOcuA62eNx+kNN/DMnDdPeLnBRdu8+7skTxOsOQNemerCiMmE6Ih9psV6MIJNze8KR3H/TkE0Z6Xx7ZWYwao+kgAd36vATAbQYoEbfBUQZ5WpWtOgrk+SqJeNG7vIyc6DZf0HiT9CijPfhXQ/uP1Zcm8+Fy4zQgMFFXQJ+0z1dZpHdx0uQGWb2MVH1ip8rfstVLmnIExXhwxtGnMINCGOCHKHQhSmJFCCcp781UT0l2SFb2k8JnGfjBeV3qEc+YdyQlCecvpIvwm7kFOZVcuAPEMLCj9iNGZ6zF3eAtE3BwutrR3T8syz+uo4KETCahmI3C0VORjpH/ycGC9BPN4dzvSLQbbmWPa5EFqOk3o8zmzsxSS46ez0RkoPKBnL5RjvwZS9Nj4uWl10xn0GfUSYfryakKZSUfz2FSwg5R7XHIhLtozCCbV18uqxJnYE6U/YTd6OOvjDpm2J2r0y2aXKWgm6UfBCO4D"
|
||||
`endif
|
||||
+75
@@ -0,0 +1,75 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Idle Inserter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_idle_inserter (
|
||||
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc;
|
||||
wire escape_char, idle_char;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign idle_char = (in_data == 8'h4a);
|
||||
assign escape_char = (in_data == 8'h4d);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
end else begin
|
||||
if (in_valid & out_ready) begin
|
||||
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
|
||||
received_esc <= 1;
|
||||
end else begin
|
||||
received_esc <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
//we are always valid
|
||||
out_valid = 1'b1;
|
||||
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
|
||||
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
|
||||
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
|
||||
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
|
||||
in_data; //send data
|
||||
end
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43kCRpW4r+SV5JNpaTWRJVwAk9Te9/4uDK/9P0jpNRt3FOTzSu+eCkD8vGTJ5ECpem121uVEsoaBkVw0tq6Pggh2yrt9+q2ZO2tCEdipsY9N2PU9Z9Nj4iWsLLcDXmWgIAHWGO4T2+T7mbqEU5LjSrAMcn2L1vYwRzCNJd0M7ZpmDzHaTrNjl85ThSXMoHSH7N+H07hgkxMC1B30BuOwJxbhVqM0O1bF1Lif3HQMwjuUEiZfWNAJCRVdGevNN+uFzb/N6ZI4U3aK1Pp5wbm6kdhIKTAGgK0GtE8hPWxh5G7DsFE2cHNdngQfX5OYn0LIFo9VE+RF0ce1Kk6/FBWv5zyZObFFLudpM+Dx4HKmNA0hqznPjcEK5HUx/CqIoy+T+89G2VSZc51jSHy763msXNjBNbnLPa0o0GL9GKYUn7eTjFkX0ic3rdZ/cy05luCYKmHyzGod00WDMbQb1yGwwwQ/ZnrEo9c2tl5FZE5pGnOxz7U0HTSL+F3xVmryBy3IzK7Wba5uEE/TNJcXcpdFNyidBoE5DdhffwjzH5ST+9v6dGBiQNWybRauhLu3glW4Y8SP5cbqGqNzDfH3p9Iuo1CS35rXY/zqTXCIYOMxMe/k4eBk5L31Xly023r2RGrhiNrbTK3oG3b458LgR4pkEiQOZI6XT5DbVqmDmF0vbLkOM3U8RLsM2vNiZaHGSgb9yLIl/jIiic1pGCTXXGy7dUH11hlrEfbCYR9WrhCbMQhdb09X6g0/OwAKyeKVpvZXKkoZj8g6iRj6JvK9gbgLl0Ot"
|
||||
`endif
|
||||
+73
@@ -0,0 +1,73 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Idle Remover
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_idle_remover (
|
||||
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc;
|
||||
wire escape_char, idle_char;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign idle_char = (in_data == 8'h4a);
|
||||
assign escape_char = (in_data == 8'h4d);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
end else begin
|
||||
if (in_valid & in_ready) begin
|
||||
if (escape_char & ~received_esc) begin
|
||||
received_esc <= 1;
|
||||
end else if (out_valid) begin
|
||||
received_esc <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
//out valid when in_valid. Except when we get idle or escape
|
||||
//however, if we have received an escape character, then we are valid
|
||||
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
|
||||
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
|
||||
end
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43m+IIK1ixAbxPYTwnlCpKSDGmf9frfeCOy1EuDdRMaMJDEncztGlmHshJHRvfDGi/EEg4qjealxu0yL1imOpUKwuC6jLHx+dcdMKTloQvSNAU4Ymo3vSmsF7htT5b7B+pQMk3eJ63Nlxzofxy0nRoc2DSa78oKwkrWsu24+0oPKMoSmiMZAgW09tP9QVzEx7lZXQxm+3D73Xk7A5PXrOZPeu7qTH+pV8ogw4chnFtGP8J3P7FSAaef2V+PkFrJZed+TxKjcfG1zWgD52v1YNr4EwgTXtsfI2IkNCcmUeiJzw0MmKBg0cFqgYY/KXk+ILqaO39elRp0WwiXa0ZgcZ01GZeKMErd/mirZg1w1BoqX+E7VvvuuBkzGRjDflArMJwOmqHDZXKvCmRaegV32DmVtkNv5em3f/A4hvUp6y11KPZoYd/lg3Dv7S2OZT8UtmT62CJPubbNCZr8O+odRCIgO+Msq0LW6sevM+v8eEJzcn8OCYmDyUHyW1XO9jmtBrFFtAYl97lb7cgg6nkgaN3+CafnTFJb+x8piB+Xk/S7gS9ZnKC8xMd1469RwAP9ohUVJHNA60UUFfc6uixYibBz9o86aCTZ0+ICG91msNAwFSGv7UmYnYK8TxTPc7V3eA8puX8bO4h6tt0EAs8Zb794I5mcDCYafM79/RkgRkWtxlMkqSYyASjn/anZHE8GW1Re7jrUJgxWBPIBOMY61EztDDdY/TKPhbH1O4tF7cI4lSVM5OQwfY5RgFqX52cCydrhFFqEIX1NmMX/N/4bLUcyX"
|
||||
`endif
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
# (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and other
|
||||
# software and tools, and its AMPP partner logic functions, and any output
|
||||
# files from any of the foregoing (including device programming or simulation
|
||||
# files), and any associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License Subscription
|
||||
# Agreement, Altera IP License Agreement, or other applicable
|
||||
# license agreement, including, without limitation, that your use is for the
|
||||
# sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
|
||||
set_false_path -from [get_registers *altera_jtag_src_crosser:*|sink_data_buffer*] -to [get_registers *altera_jtag_src_crosser:*|src_data*]
|
||||
+229
@@ -0,0 +1,229 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// This top level module chooses between the original Altera-ST JTAG Interface
|
||||
// component in ACDS version 8.1 and before, and the new one with the PLI
|
||||
// Simulation mode turned on, which adds a wrapper over the original component.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
// altera message_off 16735
|
||||
|
||||
module altera_avalon_st_jtag_interface #(
|
||||
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
|
||||
// for JTAG Phy, 1 for Packets to Master
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = 0,
|
||||
parameter EXPORT_JTAG = 0,
|
||||
parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
|
||||
parameter PLI_PORT = 50000 // PLI Simulation Port
|
||||
) (
|
||||
input wire jtag_tck,
|
||||
input wire jtag_tms,
|
||||
input wire jtag_tdi,
|
||||
output wire jtag_tdo,
|
||||
input wire jtag_ena,
|
||||
input wire jtag_usr1,
|
||||
input wire jtag_clr,
|
||||
input wire jtag_clrn,
|
||||
input wire jtag_state_tlr,
|
||||
input wire jtag_state_rti,
|
||||
input wire jtag_state_sdrs,
|
||||
input wire jtag_state_cdr,
|
||||
input wire jtag_state_sdr,
|
||||
input wire jtag_state_e1dr,
|
||||
input wire jtag_state_pdr,
|
||||
input wire jtag_state_e2dr,
|
||||
input wire jtag_state_udr,
|
||||
input wire jtag_state_sirs,
|
||||
input wire jtag_state_cir,
|
||||
input wire jtag_state_sir,
|
||||
input wire jtag_state_e1ir,
|
||||
input wire jtag_state_pir,
|
||||
input wire jtag_state_e2ir,
|
||||
input wire jtag_state_uir,
|
||||
input wire [2:0] jtag_ir_in,
|
||||
output wire jtag_irq,
|
||||
output wire [2:0] jtag_ir_out,
|
||||
input wire clk,
|
||||
input wire reset_n,
|
||||
input wire source_ready,
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
output wire resetrequest,
|
||||
output wire debug_reset,
|
||||
output wire mgmt_valid,
|
||||
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output wire mgmt_data
|
||||
);
|
||||
|
||||
// Signals in the JTAG clock domain
|
||||
wire tck;
|
||||
wire tdi;
|
||||
wire tdo;
|
||||
wire [2:0] ir_in;
|
||||
wire virtual_state_cdr;
|
||||
wire virtual_state_sdr;
|
||||
wire virtual_state_udr;
|
||||
|
||||
assign jtag_irq = 1'b0;
|
||||
assign jtag_ir_out = 3'b000;
|
||||
|
||||
generate
|
||||
if (EXPORT_JTAG == 0) begin
|
||||
// SLD node instantiation
|
||||
altera_jtag_sld_node node (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_out (3'b0),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr (virtual_state_cdr),
|
||||
.virtual_state_cir (),
|
||||
.virtual_state_e1dr (),
|
||||
.virtual_state_e2dr (),
|
||||
.virtual_state_pdr (),
|
||||
.virtual_state_sdr (virtual_state_sdr),
|
||||
.virtual_state_udr (virtual_state_udr),
|
||||
.virtual_state_uir ()
|
||||
);
|
||||
|
||||
assign jtag_tdo = 1'b0;
|
||||
end else begin
|
||||
assign tck = jtag_tck;
|
||||
assign tdi = jtag_tdi;
|
||||
assign jtag_tdo = tdo;
|
||||
assign ir_in = jtag_ir_in;
|
||||
assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
|
||||
assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
|
||||
assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (USE_PLI == 0)
|
||||
begin : normal
|
||||
altera_jtag_dc_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_dc_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.source_data(source_data),
|
||||
.source_valid(source_valid),
|
||||
.sink_data(sink_data),
|
||||
.sink_valid(sink_valid),
|
||||
.sink_ready(sink_ready),
|
||||
.resetrequest(resetrequest),
|
||||
.debug_reset(debug_reset),
|
||||
.mgmt_valid(mgmt_valid),
|
||||
.mgmt_channel(mgmt_channel),
|
||||
.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
end
|
||||
else
|
||||
begin : pli_mode
|
||||
|
||||
//synthesis translate_off
|
||||
reg pli_out_valid;
|
||||
reg pli_in_ready;
|
||||
reg [7 : 0] pli_out_data;
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
pli_out_valid <= 0;
|
||||
pli_out_data <= 'b0;
|
||||
pli_in_ready <= 0;
|
||||
end
|
||||
else begin
|
||||
`ifdef MODEL_TECH
|
||||
$do_transaction(
|
||||
PLI_PORT,
|
||||
pli_out_valid,
|
||||
source_ready,
|
||||
pli_out_data,
|
||||
sink_valid,
|
||||
pli_in_ready,
|
||||
sink_data
|
||||
);
|
||||
`endif
|
||||
end
|
||||
end
|
||||
|
||||
//synthesis translate_on
|
||||
wire [7:0] jtag_source_data;
|
||||
wire jtag_source_valid;
|
||||
wire jtag_sink_ready;
|
||||
wire jtag_resetrequest;
|
||||
|
||||
altera_jtag_dc_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_dc_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.source_data(jtag_source_data),
|
||||
.source_valid(jtag_source_valid),
|
||||
.sink_data(sink_data),
|
||||
.sink_valid(sink_valid),
|
||||
.sink_ready(jtag_sink_ready),
|
||||
.resetrequest(jtag_resetrequest)//,
|
||||
//.debug_reset(debug_reset),
|
||||
//.mgmt_valid(mgmt_valid),
|
||||
//.mgmt_channel(mgmt_channel),
|
||||
//.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
// synthesis read_comments_as_HDL on
|
||||
// assign source_valid = jtag_source_valid;
|
||||
// assign source_data = jtag_source_data;
|
||||
// assign sink_ready = jtag_sink_ready;
|
||||
// assign resetrequest = jtag_resetrequest;
|
||||
// synthesis read_comments_as_HDL off
|
||||
|
||||
//synthesis translate_off
|
||||
assign source_valid = pli_out_valid;
|
||||
assign source_data = pli_out_data;
|
||||
assign sink_ready = pli_in_ready;
|
||||
assign resetrequest = 1'b0;
|
||||
//synthesis translate_on
|
||||
assign jtag_tdo = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43kE5SETwJy1XH1XEICOs+R/qa00jHEPMso8nVR5QBxKZ3zmrNoJGALGfV84dFJY7TP7iACdYKKx96iRdKyFJaGqH/GObmGJBmKepuqsSvBxbvatkRUGFK/JteQ8Ui7UML33rpNB0DC9tzM4sjZGGDRROsVvNyeM/JoBEukWM0gp2LrwdU+q8fGVQlxl0Nx7Z+rcS00DCy6lJWwnJ7We9WtGffZfDH2xCBmmC0BI4zytrYMCswtE1vXzQEWmbJ6Hyj0yR9hYVQB3qbgw9w/KCzwPBB/KfwvNIuKJU00I89ABvezTidY9Yq7ybSF83M2CNNSpoF/mGcfnX34Ts8njIrUr/tnmjnUp3Vj3Ykrgr6Bpww5JTPI58bYlZkc9RKqFms1hz+T76tQgMjY2Puh+UVXjT5GNjZa0aeiooqibu2yukQK+h09B029L8BfIqleXx4v3RTJ8Fumdz4qrJWNwHUVcYoInUx+J4SPmD6MlAuIdM/FF/ASfYCTQ0svDaRUgKHAWI4TnxFd9T9Pguxt3p29Umz6BZwrQTmn73OPFtmgFjzqSIpubc6sK20vi8SZxjemX5z4na7wsgUYULmNw2OIDdNsaSiFkJlONz3crAxONGlyQ7/4xMJLOlk03I6UfRoHOO23yZ4vZUqcWl31MmDVkHybED5u1f3shr/pCIZ+nK+gfsvykwJ5psOap3kwbGh37URGjln5a6qQBF18+Ugzf44YSZ/sDI35oa9Tt5DXjk6nxH1oU2wXYC2MZ7JLYefvIxpwR07B8VkgIq2ejHbr4"
|
||||
`endif
|
||||
+222
@@ -0,0 +1,222 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2018 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/26.1/ip/iconnect/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_pipeline_base (
|
||||
clk,
|
||||
reset,
|
||||
in_ready,
|
||||
in_valid,
|
||||
in_data,
|
||||
out_ready,
|
||||
out_valid,
|
||||
out_data
|
||||
);
|
||||
|
||||
parameter SYMBOLS_PER_BEAT = 1;
|
||||
parameter BITS_PER_SYMBOL = 8;
|
||||
parameter PIPELINE_READY = 1;
|
||||
parameter SYNC_RESET = 0;
|
||||
parameter BACKPRESSURE_DURING_RESET = 0;
|
||||
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
|
||||
|
||||
input clk;
|
||||
input reset;
|
||||
|
||||
output in_ready;
|
||||
input in_valid;
|
||||
input [DATA_WIDTH-1:0] in_data;
|
||||
|
||||
input out_ready;
|
||||
output out_valid;
|
||||
output [DATA_WIDTH-1:0] out_data;
|
||||
|
||||
reg full0;
|
||||
reg full1;
|
||||
reg [DATA_WIDTH-1:0] data0;
|
||||
reg [DATA_WIDTH-1:0] data1;
|
||||
|
||||
assign out_valid = full1;
|
||||
assign out_data = data1;
|
||||
|
||||
// Generation of internal reset synchronization
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (PIPELINE_READY == 1)
|
||||
begin : REGISTERED_READY_PLINE
|
||||
|
||||
assign in_ready = !full0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
// ----------------------------
|
||||
// always load the second slot if we can
|
||||
// ----------------------------
|
||||
if (~full0)
|
||||
data0 <= in_data;
|
||||
// ----------------------------
|
||||
// first slot is loaded either from the second,
|
||||
// or with new data
|
||||
// ----------------------------
|
||||
if (~full1 || (out_ready && out_valid)) begin
|
||||
if (full0)
|
||||
data1 <= data0;
|
||||
else
|
||||
data1 <= in_data;
|
||||
end
|
||||
end
|
||||
|
||||
if (SYNC_RESET == 0) begin : async_rst0
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
full1 <= 1'b0;
|
||||
end else begin
|
||||
// out of reset.
|
||||
if(~full1 & full0)begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
|
||||
// no data in pipeline
|
||||
if (~full0 & ~full1) begin
|
||||
if (in_valid) begin
|
||||
full1 <= 1'b1;
|
||||
end
|
||||
end // ~f1 & ~f0
|
||||
|
||||
// one datum in pipeline
|
||||
if (full1 & ~full0) begin
|
||||
if (in_valid & ~out_ready) begin
|
||||
full0 <= 1'b1;
|
||||
end
|
||||
// back to empty
|
||||
if (~in_valid & out_ready) begin
|
||||
full1 <= 1'b0;
|
||||
end
|
||||
end // f1 & ~f0
|
||||
|
||||
// two data in pipeline
|
||||
if (full1 & full0) begin
|
||||
// go back to one datum state
|
||||
if (out_ready) begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
end // end go back to one datum stage
|
||||
end
|
||||
end
|
||||
end // async_rst0
|
||||
else begin // sync_rst0
|
||||
always @(posedge clk ) begin
|
||||
if (internal_sclr) begin
|
||||
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
full1 <= 1'b0;
|
||||
end else begin
|
||||
// out of reset.
|
||||
if(~full1 & full0)begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
|
||||
// no data in pipeline
|
||||
if (~full0 & ~full1) begin
|
||||
if (in_valid) begin
|
||||
full1 <= 1'b1;
|
||||
end
|
||||
end // ~f1 & ~f0
|
||||
|
||||
// one datum in pipeline
|
||||
if (full1 & ~full0) begin
|
||||
if (in_valid & ~out_ready) begin
|
||||
full0 <= 1'b1;
|
||||
end
|
||||
// back to empty
|
||||
if (~in_valid & out_ready) begin
|
||||
full1 <= 1'b0;
|
||||
end
|
||||
end // f1 & ~f0
|
||||
|
||||
// two data in pipeline
|
||||
if (full1 & full0) begin
|
||||
// go back to one datum state
|
||||
if (out_ready) begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
end // end go back to one datum stage
|
||||
end
|
||||
end
|
||||
end // sync_rst0
|
||||
end
|
||||
else
|
||||
begin : UNREGISTERED_READY_PLINE
|
||||
|
||||
// in_ready will be a pass through of the out_ready signal as it is not registered
|
||||
assign in_ready = (~full1) | out_ready;
|
||||
|
||||
if (SYNC_RESET == 0) begin : async_rst1
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
data1 <= 'b0;
|
||||
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (in_ready) begin
|
||||
data1 <= in_data;
|
||||
full1 <= in_valid;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // async_rst1
|
||||
else begin // sync_rst1
|
||||
always @(posedge clk ) begin
|
||||
if (internal_sclr) begin
|
||||
data1 <= 'b0;
|
||||
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (in_ready) begin
|
||||
data1 <= in_data;
|
||||
full1 <= in_valid;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // sync_rst1
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43m+2WbbziRXNHGvxsiU9BKfbzYIwxqkjbRY646Jry08YTxgl+u6Mpx3BaAnY8zD8arB0qHAHWeHxZk4Hc5CUUMkBqNpBDW51MKpXcPm9ytMiKASxRBYyGC1DUc1qjCFcJ5eP5kqviLbdBDKpFyc4xAZtJR3LjcT2rHr0r0dcOSAei50r8+hZH5ImpM5IZVnLbFjvfn4gTm34ATDBGaBb/k1ixtHUMFRwKcfLhVwgd8+qp2ZJ42U9B2sa83JRKaJOUtJVMRsuQ4zH1pDaBVKz7tvcbQ9KL6BBsCE6Sn4uDBb1m/T5jxvgV5CgkGSt3amLUBTupfKUvmukO0wGF8cOyjjsWhBq1qj9uHJBIsE6jwGoavEMRH7KppIs+N4blyw3mkk8JbsyZPTmQwkEUKc2Eu8+YcGa/yBIOJeGapk3JOOMjZMuI9zGnVgMljFU0MZZpzbVzMsGSddTz1Cd1namRpB7EOF2NFXOu8hoePaL/YYTrXZAfM5iEuTRjAzVa9LsjKI3vp/WpNZ6Kq6djMwZ7YilOOcNsiCALgQe+1s0QGFBQ7zYwJE7udtUdsEw9GhzuG98Vo/3mB6Z4cGzvj86WrHyy1X9WuRyTDVSGGvAxMWPBEHomZd8TS4+FkOF5oH9QDGhrzKgYpLsfkbAhYvDH4ZjsA2q1aJCrEUFoXGZC8fwYEgx9xhV5T9Hre3WKR3wWPXLu3J/SQ4ecRTdkpcZY0DRzrXao825TRnfAqfECespkaam8sE849QMiWHBh/p0vH+n54ztMPrCthmLaeUe5/O"
|
||||
`endif
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/26.1/ip/iconnect/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage.sv $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_pipeline_stage #(
|
||||
parameter
|
||||
USE_FIFO_IP = 0, // unsued at moment
|
||||
SYMBOLS_PER_BEAT = 1,
|
||||
BITS_PER_SYMBOL = 8,
|
||||
USE_PACKETS = 0,
|
||||
USE_EMPTY = 0,
|
||||
PIPELINE_READY = 1,
|
||||
SYNC_RESET = 0,
|
||||
// Optional ST signal widths. Value "0" means no such port.
|
||||
CHANNEL_WIDTH = 0,
|
||||
ERROR_WIDTH = 0,
|
||||
|
||||
// Derived parameters
|
||||
DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
|
||||
PACKET_WIDTH = 0,
|
||||
EMPTY_WIDTH = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
output in_ready,
|
||||
input in_valid,
|
||||
input [DATA_WIDTH - 1 : 0] in_data,
|
||||
input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
|
||||
input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
|
||||
|
||||
input out_ready,
|
||||
output out_valid,
|
||||
output [DATA_WIDTH - 1 : 0] out_data,
|
||||
output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
|
||||
output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
|
||||
output out_startofpacket,
|
||||
output out_endofpacket,
|
||||
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
|
||||
);
|
||||
localparam
|
||||
PAYLOAD_WIDTH =
|
||||
DATA_WIDTH +
|
||||
PACKET_WIDTH +
|
||||
CHANNEL_WIDTH +
|
||||
EMPTY_WIDTH +
|
||||
ERROR_WIDTH;
|
||||
|
||||
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
|
||||
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
|
||||
|
||||
// Assign in_data and other optional in_* interface signals to in_payload.
|
||||
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
|
||||
generate
|
||||
// optional packet inputs
|
||||
if (PACKET_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH - 1 :
|
||||
DATA_WIDTH
|
||||
] = {in_startofpacket, in_endofpacket};
|
||||
end
|
||||
// optional channel input
|
||||
if (CHANNEL_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH
|
||||
] = in_channel;
|
||||
end
|
||||
// optional empty input
|
||||
if (EMPTY_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
|
||||
] = in_empty;
|
||||
end
|
||||
// optional error input
|
||||
if (ERROR_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
|
||||
] = in_error;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
localparam NUM_128BIT_SLOTS = (PAYLOAD_WIDTH / 128) + (((PAYLOAD_WIDTH % 128) == 0) ? 0 : 1);
|
||||
localparam LAST_PAYLOAD_W = ((PAYLOAD_WIDTH % 128) == 0) ? 128 : (PAYLOAD_WIDTH % 128);
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < NUM_128BIT_SLOTS; i = i + 1) begin : gen_inst
|
||||
if (i == NUM_128BIT_SLOTS - 1) begin
|
||||
altera_avalon_st_pipeline_base #(
|
||||
.SYMBOLS_PER_BEAT (LAST_PAYLOAD_W),
|
||||
.BITS_PER_SYMBOL (1),
|
||||
.PIPELINE_READY (PIPELINE_READY),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) core (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (in_ready),
|
||||
.in_valid (in_valid),
|
||||
.in_data (in_payload[(i*128)+LAST_PAYLOAD_W-1:i*128]),
|
||||
.out_ready (out_ready),
|
||||
.out_valid (out_valid),
|
||||
.out_data (out_payload[(i*128)+LAST_PAYLOAD_W-1:i*128])
|
||||
);
|
||||
end
|
||||
else begin
|
||||
altera_avalon_st_pipeline_base #(
|
||||
.SYMBOLS_PER_BEAT (128),
|
||||
.BITS_PER_SYMBOL (1),
|
||||
.PIPELINE_READY (PIPELINE_READY),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) core (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (),
|
||||
.in_valid (in_valid),
|
||||
.in_data (in_payload[(i+1)*128-1:i*128]),
|
||||
.out_ready (out_ready),
|
||||
.out_valid (),
|
||||
.out_data (out_payload[(i+1)*128-1:i*128])
|
||||
);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Assign out_data and other optional out_* interface signals from out_payload.
|
||||
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
|
||||
generate
|
||||
// optional packet outputs
|
||||
if (PACKET_WIDTH) begin
|
||||
assign {out_startofpacket, out_endofpacket} =
|
||||
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign {out_startofpacket, out_endofpacket} = 2'b0;
|
||||
end
|
||||
|
||||
// optional channel output
|
||||
if (CHANNEL_WIDTH) begin
|
||||
assign out_channel = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_channel = 1'b0;
|
||||
end
|
||||
// optional empty output
|
||||
if (EMPTY_WIDTH) begin
|
||||
assign out_empty = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_empty = 1'b0;
|
||||
end
|
||||
// optional error output
|
||||
if (ERROR_WIDTH) begin
|
||||
assign out_error = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_error = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43lzNdzic8kf095rgT/UkF24bAsY8NGL39W2vnb6QHycbl1peRxuMswSGmotl+qU7rTPIN3gVwEy7e13KVfLqnUSbl5Aj/njXXTCqo0XReaJeMqVFNLoUFEke22KyVtbOBwxIqkfp66fh+LWjI8lLUheUnX8eq4FgV+krso2vFPZ546y52KsJs5qTfDpbX85DJ0+l6Sg4mvb0n9nLB+1SBwdQxY+r1X93owARyzVOcF5CIBN3i1YywJdDG2I6/wxZvAVIxD4KPrlWY8xxukciAYJpr7+Oxf07u7Bv9H7LS8ql7c3ZPPL6Kpk7gEXCnrndNnqENjDVEtnvbjA6q+vmxDW9LgWTd6FRrTHU5Um7j2HfYjJbl2DU/X/VTzmGL3KXLvc1D5ep6LYnHgBoyJbdio3ArirlItOV5zcEnJGUvohgbi/xykdpALrQjbFkskaqu+K/ngGgtZ4YyA1F1U3MJQ9F/wkhC/NqgVc4K5CDIi+J8c2KoINY8OXRB0RtZB0MHeyCpS3WwAzlWQKEYI7Lxkb+2RKzqymsSdH5CltjfEgf4SFk/bXwnv33gBS8bg6OZwu+StypSNvj5Z9C+2aokZD39boscHt24WZchtkJsQtgNM7leRuB9n60dKI+nHwPtiYa5FghnJBzSyeQ49QcgDovq9MQlu/FGFMeXM/mYvcN4Fo2janBMoGBSGEidqiL0nZZxZV6q0inrtQVERT2AkPmL/m7JtCU2FMDauZoOIZ6p2O1DWpE0OzBGyHYRE+yhwMyzOAlT6Yq8VeAt7hHIgA"
|
||||
`endif
|
||||
+264
@@ -0,0 +1,264 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// This module is a simple clock crosser for control signals. It will take
|
||||
// the asynchronous control signal and synchronize it to the clk domain
|
||||
// attached to the clk input. It does so by passing the control signal
|
||||
// through a pair of registers and then sensing the level transition from
|
||||
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
|
||||
// that the control signal will always transition every time is asserted.
|
||||
// i.e.:
|
||||
// ____ ___________________
|
||||
// -> ___| |___ and ___| |_____
|
||||
//
|
||||
// on the control signal will be seen as only one assertion of the control
|
||||
// signal. In short, if your control could be asserted back-to-back, then
|
||||
// don't use this module. You'll be losing data.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_jtag_control_signal_crosser (
|
||||
clk,
|
||||
reset_n,
|
||||
async_control_signal,
|
||||
sense_pos_edge,
|
||||
sync_control_signal
|
||||
);
|
||||
input clk;
|
||||
input reset_n;
|
||||
input async_control_signal;
|
||||
input sense_pos_edge;
|
||||
output sync_control_signal;
|
||||
|
||||
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
|
||||
|
||||
reg sync_control_signal;
|
||||
|
||||
wire synchronized_raw_signal;
|
||||
reg edge_detector_register;
|
||||
|
||||
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.din(async_control_signal),
|
||||
.dout(synchronized_raw_signal)
|
||||
);
|
||||
|
||||
always @ (posedge clk or negedge reset_n)
|
||||
if (~reset_n)
|
||||
edge_detector_register <= 1'b0;
|
||||
else
|
||||
edge_detector_register <= synchronized_raw_signal;
|
||||
|
||||
always @* begin
|
||||
if (sense_pos_edge)
|
||||
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
|
||||
else
|
||||
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
|
||||
end
|
||||
endmodule
|
||||
|
||||
// This module crosses the clock domain for a given source
|
||||
module altera_jtag_src_crosser (
|
||||
sink_clk,
|
||||
sink_reset_n,
|
||||
sink_valid,
|
||||
sink_data,
|
||||
src_clk,
|
||||
src_reset_n,
|
||||
src_valid,
|
||||
src_data
|
||||
);
|
||||
parameter WIDTH = 8;
|
||||
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
|
||||
|
||||
input sink_clk;
|
||||
input sink_reset_n;
|
||||
input sink_valid;
|
||||
input [WIDTH-1:0] sink_data;
|
||||
input src_clk;
|
||||
input src_reset_n;
|
||||
output src_valid;
|
||||
output [WIDTH-1:0] src_data;
|
||||
|
||||
reg sink_valid_buffer;
|
||||
reg [WIDTH-1:0] sink_data_buffer;
|
||||
|
||||
reg src_valid;
|
||||
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
|
||||
|
||||
wire synchronized_valid;
|
||||
|
||||
altera_jtag_control_signal_crosser #(
|
||||
.SYNC_DEPTH(SYNC_DEPTH)
|
||||
) crosser (
|
||||
.clk(src_clk),
|
||||
.reset_n(src_reset_n),
|
||||
.async_control_signal(sink_valid_buffer),
|
||||
.sense_pos_edge(1'b1),
|
||||
.sync_control_signal(synchronized_valid)
|
||||
);
|
||||
always @ (posedge sink_clk or negedge sink_reset_n) begin
|
||||
if (~sink_reset_n) begin
|
||||
sink_valid_buffer <= 1'b0;
|
||||
sink_data_buffer <= 'b0;
|
||||
end else begin
|
||||
sink_valid_buffer <= sink_valid;
|
||||
if (sink_valid) begin
|
||||
sink_data_buffer <= sink_data;
|
||||
end
|
||||
end //end if
|
||||
end //always sink_clk
|
||||
|
||||
always @ (posedge src_clk or negedge src_reset_n) begin
|
||||
if (~src_reset_n) begin
|
||||
src_valid <= 1'b0;
|
||||
src_data <= {WIDTH{1'b0}};
|
||||
end else begin
|
||||
src_valid <= synchronized_valid;
|
||||
src_data <= synchronized_valid ? sink_data_buffer : src_data;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module altera_jtag_dc_streaming #(
|
||||
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
|
||||
// for JTAG Phy, 1 for Packets to Master
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = 0
|
||||
) (
|
||||
// Signals in the JTAG clock domain
|
||||
input wire tck,
|
||||
input wire tdi,
|
||||
output wire tdo,
|
||||
input wire [2:0] ir_in,
|
||||
input wire virtual_state_cdr,
|
||||
input wire virtual_state_sdr,
|
||||
input wire virtual_state_udr,
|
||||
|
||||
input wire clk,
|
||||
input wire reset_n,
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
output wire resetrequest,
|
||||
output wire debug_reset,
|
||||
output wire mgmt_valid,
|
||||
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output wire mgmt_data
|
||||
);
|
||||
|
||||
// the tck to sysclk sync depth is fixed at 8
|
||||
// 8 is the worst case scenario from our metastability analysis, and since
|
||||
// using TCK serially is so slow we should have plenty of clock cycles.
|
||||
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
|
||||
// The clk to tck path is fixed at 3 deep for Synchronizer depth.
|
||||
// Since the tck clock is so slow, no parameter is exposed.
|
||||
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
|
||||
|
||||
wire jtag_clock_reset_n; // system reset is synchronized with tck
|
||||
wire [7:0] jtag_source_data;
|
||||
wire jtag_source_valid;
|
||||
wire [7:0] jtag_sink_data;
|
||||
wire jtag_sink_valid;
|
||||
wire jtag_sink_ready;
|
||||
|
||||
/* Reset Synchronizer module.
|
||||
*
|
||||
* The SLD Node does not provide a reset for the TCK clock domain.
|
||||
* Due to the handshaking nature of the Avalon-ST Clock Crosser,
|
||||
* internal states need to be reset to 0 in order to guarantee proper
|
||||
* functionality throughout resets.
|
||||
*
|
||||
* This reset block will asynchronously assert reset, and synchronously
|
||||
* deassert reset for the tck clock domain.
|
||||
*/
|
||||
altera_std_synchronizer #(
|
||||
.depth(SYSCLK_TO_TCK_SYNC_DEPTH)
|
||||
) synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(reset_n),
|
||||
.din(1'b1),
|
||||
.dout(jtag_clock_reset_n)
|
||||
);
|
||||
|
||||
altera_jtag_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
|
||||
.reset_n(jtag_clock_reset_n),
|
||||
.source_data(jtag_source_data),
|
||||
.source_valid(jtag_source_valid),
|
||||
.sink_data(jtag_sink_data),
|
||||
.sink_valid(jtag_sink_valid),
|
||||
.sink_ready(jtag_sink_ready),
|
||||
.clock_to_sample(clk),
|
||||
.reset_to_sample(reset_n),
|
||||
.resetrequest(resetrequest),
|
||||
.debug_reset(debug_reset),
|
||||
.mgmt_valid(mgmt_valid),
|
||||
.mgmt_channel(mgmt_channel),
|
||||
.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
// synchronization in both clock domain crossings takes place in the "clk" system clock domain!
|
||||
|
||||
altera_avalon_st_clock_crosser #(
|
||||
.SYMBOLS_PER_BEAT(1),
|
||||
.BITS_PER_SYMBOL(8),
|
||||
.FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH),
|
||||
.BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
|
||||
) sink_crosser (
|
||||
.in_clk(clk),
|
||||
.in_reset(~reset_n),
|
||||
.in_data(sink_data),
|
||||
.in_ready(sink_ready),
|
||||
.in_valid(sink_valid),
|
||||
.out_clk(tck),
|
||||
.out_reset(~jtag_clock_reset_n),
|
||||
.out_data(jtag_sink_data),
|
||||
.out_ready(jtag_sink_ready),
|
||||
.out_valid(jtag_sink_valid)
|
||||
);
|
||||
|
||||
altera_jtag_src_crosser #(
|
||||
.SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
|
||||
) source_crosser (
|
||||
.sink_clk(tck),
|
||||
.sink_reset_n(jtag_clock_reset_n),
|
||||
.sink_valid(jtag_source_valid),
|
||||
.sink_data(jtag_source_data),
|
||||
.src_clk(clk),
|
||||
.src_reset_n(reset_n),
|
||||
.src_valid(source_valid),
|
||||
.src_data(source_data)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43mf05yrKMA+uPdz5tOrx7e5HExSwPsvBYo6nuRS+JViKkGWUOniDW3NDMxPpUiEChz1wDtyqt0bYSnK0cPHA0neGHMbl9mxVDoyOW9dlDnU0P+Ym6p1vzyQYq52H54kJy0/c2GKCikQaqX+YZG1pBZ8V1YlMDOepq+7WF8JX+GAmDLFbl4L26qzoGrlN8LdW+Qr9k9ZxE8W1J5okyjtyTvqLTXCbxxGD0ZwAKjQeQl4U35Fdi4PNa2IdJc+h4nOoJ0WJEa6i65rhFGLDxHYlwWBBFZt4MoFrk7Bw7MzQXNHkV0UHlnK6oqS6Rka3xOujIzwzOqgDXjaSoXt7Ts4VRjY08temLjq2rgczO+5ED6hks3Qh9Yx1GnZnEnLTpc/zmAYd3jStXvd8MmeLvriTIAGcm4vNW1viqjaQaBnIobM3TOc+Z8P8oKk6P3JO/7t89bGi5/A7HojpJw0daAZkSDHyh7xQfDDc+GJeRg5k5tPVf65FmVbpco36fRM5fQwhnmXisNZkoEgYO044IoBceUE4HD6jbh2umBVPDrb66IvDZyr/64QmjHMNT6uzPUsph1jBD0BhzoPwllykfeQhEnHrIrXQ/s+QKBImnLRlix4+rMt0cWaqJ+tZ7i1V2tqTA1hSR5HjXN+NtuCoDTtnMV+fMrPTa2VARCrY6Bh2DM63R0fNSjnq+5pB8SbDlmb6EDxYKzZDSJTB2pXfiHco8gHytfgMSvg4m1LKS9xUVDV2VjnxoKbWPBfr8fCCcfSm1Qb54affjg0pAgS6lz2zkGD"
|
||||
`endif
|
||||
+264
@@ -0,0 +1,264 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ns / 1 ns
|
||||
// synopsys translate_on
|
||||
module altera_jtag_sld_node (
|
||||
ir_out,
|
||||
tdo,
|
||||
ir_in,
|
||||
tck,
|
||||
tdi,
|
||||
virtual_state_cdr,
|
||||
virtual_state_cir,
|
||||
virtual_state_e1dr,
|
||||
virtual_state_e2dr,
|
||||
virtual_state_pdr,
|
||||
virtual_state_sdr,
|
||||
virtual_state_udr,
|
||||
virtual_state_uir
|
||||
);
|
||||
|
||||
parameter TCK_FREQ_MHZ = 20;
|
||||
localparam TCK_HALF_PERIOD_US = (1000/TCK_FREQ_MHZ)/2;
|
||||
localparam IRWIDTH = 3;
|
||||
|
||||
input [IRWIDTH - 1:0] ir_out;
|
||||
input tdo;
|
||||
output reg [IRWIDTH - 1:0] ir_in;
|
||||
output tck;
|
||||
output reg tdi = 1'b0;
|
||||
output virtual_state_cdr;
|
||||
output virtual_state_cir;
|
||||
output virtual_state_e1dr;
|
||||
output virtual_state_e2dr;
|
||||
output virtual_state_pdr;
|
||||
output virtual_state_sdr;
|
||||
output virtual_state_udr;
|
||||
output virtual_state_uir;
|
||||
|
||||
// PHY Simulation signals
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
reg simulation_clock;
|
||||
reg sdrs;
|
||||
reg cdr;
|
||||
reg sdr;
|
||||
reg e1dr;
|
||||
reg udr;
|
||||
reg [7:0] bit_index;
|
||||
`endif
|
||||
|
||||
|
||||
// PHY Instantiation
|
||||
`ifdef ALTERA_RESERVED_QIS
|
||||
wire tdi_port;
|
||||
wire [IRWIDTH - 1:0] ir_in_port;
|
||||
always @(tdi_port)
|
||||
tdi = tdi_port;
|
||||
always @(ir_in_port)
|
||||
ir_in = ir_in_port;
|
||||
sld_virtual_jtag_basic sld_virtual_jtag_component (
|
||||
.ir_out (ir_out),
|
||||
.tdo (tdo),
|
||||
.tdi (tdi_port),
|
||||
.tck (tck),
|
||||
.ir_in (ir_in_port),
|
||||
.virtual_state_cir (virtual_state_cir),
|
||||
.virtual_state_pdr (virtual_state_pdr),
|
||||
.virtual_state_uir (virtual_state_uir),
|
||||
.virtual_state_sdr (virtual_state_sdr),
|
||||
.virtual_state_cdr (virtual_state_cdr),
|
||||
.virtual_state_udr (virtual_state_udr),
|
||||
.virtual_state_e1dr (virtual_state_e1dr),
|
||||
.virtual_state_e2dr (virtual_state_e2dr)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.jtag_state_cdr (),
|
||||
.jtag_state_cir (),
|
||||
.jtag_state_e1dr (),
|
||||
.jtag_state_e1ir (),
|
||||
.jtag_state_e2dr (),
|
||||
.jtag_state_e2ir (),
|
||||
.jtag_state_pdr (),
|
||||
.jtag_state_pir (),
|
||||
.jtag_state_rti (),
|
||||
.jtag_state_sdr (),
|
||||
.jtag_state_sdrs (),
|
||||
.jtag_state_sir (),
|
||||
.jtag_state_sirs (),
|
||||
.jtag_state_tlr (),
|
||||
.jtag_state_udr (),
|
||||
.jtag_state_uir (),
|
||||
.tms ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
sld_virtual_jtag_component.sld_mfg_id = 110,
|
||||
sld_virtual_jtag_component.sld_type_id = 132,
|
||||
sld_virtual_jtag_component.sld_version = 1,
|
||||
sld_virtual_jtag_component.sld_auto_instance_index = "YES",
|
||||
sld_virtual_jtag_component.sld_instance_index = 0,
|
||||
sld_virtual_jtag_component.sld_ir_width = IRWIDTH,
|
||||
sld_virtual_jtag_component.sld_sim_action = "",
|
||||
sld_virtual_jtag_component.sld_sim_n_scan = 0,
|
||||
sld_virtual_jtag_component.sld_sim_total_length = 0;
|
||||
`endif
|
||||
|
||||
// PHY Simulation
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
|
||||
localparam DATA = 0;
|
||||
localparam LOOPBACK = 1;
|
||||
localparam DEBUG = 2;
|
||||
localparam INFO = 3;
|
||||
localparam CONTROL = 4;
|
||||
localparam MGMT = 5;
|
||||
|
||||
always
|
||||
//#TCK_HALF_PERIOD_US simulation_clock = $random;
|
||||
#TCK_HALF_PERIOD_US simulation_clock = ~simulation_clock;
|
||||
|
||||
assign tck = simulation_clock;
|
||||
assign virtual_state_cdr = cdr;
|
||||
assign virtual_state_sdr = sdr;
|
||||
assign virtual_state_e1dr = e1dr;
|
||||
assign virtual_state_udr = udr;
|
||||
|
||||
task reset_jtag_state;
|
||||
begin
|
||||
simulation_clock = 0;
|
||||
enter_data_mode;
|
||||
clear_states_async;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_data_mode;
|
||||
begin
|
||||
ir_in = DATA;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_loopback_mode;
|
||||
begin
|
||||
ir_in = LOOPBACK;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_debug_mode;
|
||||
begin
|
||||
ir_in = DEBUG;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_info_mode;
|
||||
begin
|
||||
ir_in = INFO;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_control_mode;
|
||||
begin
|
||||
ir_in = CONTROL;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_mgmt_mode;
|
||||
begin
|
||||
ir_in = MGMT;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_sdrs_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b10000;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_cdr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b01000;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_e1dr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b00010;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_udr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b00001;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task clear_states;
|
||||
begin
|
||||
clear_states_async;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task clear_states_async;
|
||||
begin
|
||||
{cdr, sdr, e1dr, udr} = 4'b0000;
|
||||
end
|
||||
endtask
|
||||
|
||||
task shift_one_bit;
|
||||
input bit_to_send;
|
||||
output reg bit_received;
|
||||
begin
|
||||
{cdr, sdr, e1dr, udr} = 4'b0100;
|
||||
tdi = bit_to_send;
|
||||
@(posedge tck);
|
||||
bit_received = tdo;
|
||||
end
|
||||
endtask
|
||||
|
||||
task shift_one_byte;
|
||||
input [7:0] byte_to_send;
|
||||
output reg [7:0] byte_received;
|
||||
integer i;
|
||||
reg bit_received;
|
||||
begin
|
||||
for (i=0; i<8; i=i+1)
|
||||
begin
|
||||
bit_index = i;
|
||||
shift_one_bit(byte_to_send[i], bit_received);
|
||||
byte_received[i] = bit_received;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43lBZX0Ql68xHccZnfqaRGQKXb+suw0+G/pVTEtXeJpzBq/7bnHCezbavBscZWMlhms2Wz2URmxx5AQLfZNrIwyosndTDl7mhnY6ckOE2QmsqzCPHFVfq4mRCzHjlTEGBvU3Pi38puWVFCyHUhgA9k5vRLZLgICA671LQ7mWobio/jqN82rZy/80hkczOwRBCHIoEVojMe7Kee0pbosxgMF1hkjKr5sjgpJOuqnyk4mT2P6InXKbojsvp3j8x0NMlhZOLjYgGBtL4CeflmEzC2f1K6TWppWrqIv/d8t6sEGsAcEGhf/yaUUSe52KNjrmgKMp4cGL2M9LaQ++/BgomIZGsd5X3dgDh1XBHnCeY3AWP5sbZTrUGvsMJQBDYG/U9hdKB3l+nEMztYgo/WSROuURMSAuR14Qo+CHE6+OhjGLoOK1H+5Au7Alv7ZPDO39BRzf5JTH9LBHOCmhvRB7L5PsG9GP1+JpBpvCRQTt5Hv+fyOo521Uk2R1SU2tiXA2S3GgwsxTJjt9PLhSg2EgIkvixp5B4uO24Xy4vepP5zBOrHa/viz3qjUzdfJsOUOm/0q9mtykoOCHfBQ/mraGzh6nemQdKQ5vLYUn+G6AseV+rRLINc0S8qKakNetEG0zXEKBXfXIism4w+uKFnlomoQ1+TS+kj2fXKzUZW2eiWHL9azON0cDdGmTDQS8hu0p7Lf2x6iOlJUT9Po56UXAOLwOpCXHhiz8kfDU6ZBQDuZx0B/acIgjJ0p57A0qd2sFzN8oX7UcAIq/FF4EUfKiHNDk"
|
||||
`endif
|
||||
+650
@@ -0,0 +1,650 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ns / 1 ns
|
||||
// synopsys translate_on
|
||||
|
||||
module altera_jtag_streaming #(
|
||||
parameter PURPOSE = 0,
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = 0
|
||||
) (
|
||||
// JTAG Signals
|
||||
input wire tck,
|
||||
input wire tdi,
|
||||
output reg tdo,
|
||||
input wire [2:0] ir_in,
|
||||
input wire virtual_state_cdr,
|
||||
input wire virtual_state_sdr,
|
||||
input wire virtual_state_udr,
|
||||
|
||||
input wire reset_n,
|
||||
// Source Signals
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
// Sink Signals
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
// Clock Debug Signals
|
||||
input wire clock_to_sample,
|
||||
input wire reset_to_sample,
|
||||
// Resetrequest signal
|
||||
output reg resetrequest,
|
||||
// Debug reset and management channel
|
||||
output wire debug_reset,
|
||||
output reg mgmt_valid,
|
||||
output reg [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output reg mgmt_data
|
||||
);
|
||||
|
||||
// function to calculate log2, floored.
|
||||
function integer flog2;
|
||||
input [31:0] Depth;
|
||||
integer i;
|
||||
begin
|
||||
i = Depth;
|
||||
if ( i <= 0 ) flog2 = 0;
|
||||
else begin
|
||||
for(flog2 = -1; i > 0; flog2 = flog2 + 1)
|
||||
i = i >> 1;
|
||||
end
|
||||
end
|
||||
endfunction // flog2
|
||||
|
||||
localparam UPSTREAM_ENCODED_SIZE = flog2(UPSTREAM_FIFO_SIZE);
|
||||
localparam DOWNSTREAM_ENCODED_SIZE = flog2(DOWNSTREAM_FIFO_SIZE);
|
||||
|
||||
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
|
||||
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
|
||||
localparam TCK_TO_SYSCLK_SYNC_DEPTH_PLUS_ONE = 9;
|
||||
|
||||
// IR values determine the operating modes
|
||||
localparam DATA = 0;
|
||||
localparam LOOPBACK = 1;
|
||||
localparam DEBUG = 2;
|
||||
localparam INFO = 3;
|
||||
localparam CONTROL = 4;
|
||||
localparam MGMT = 5;
|
||||
|
||||
// Operating Modes:
|
||||
// Data - To send data which its size and valid position are encoded in the header bytes of the data stream
|
||||
// Loopback - To become a JTAG loopback with a bypass register
|
||||
// Debug - To read the values of the clock sensing, clock sampling and reset sampling
|
||||
// Info - To read the parameterized values that describe the components connected to JTAG Phy which is of great interest to the driver
|
||||
// Control - To set the offset of bit-padding and to do a reset request
|
||||
// Mgmt - Send management commands (resets mostly) to agents
|
||||
|
||||
localparam IRWIDTH = 3;
|
||||
|
||||
// State machine encoding for write_state
|
||||
localparam ST_BYPASS = 'h0;
|
||||
localparam ST_HEADER_1 = 'h1;
|
||||
localparam ST_HEADER_2 = 'h2;
|
||||
localparam ST_WRITE_DATA = 'h3;
|
||||
|
||||
// State machine encoding for read_state
|
||||
localparam ST_HEADER = 'h0;
|
||||
localparam ST_PADDED = 'h1;
|
||||
localparam ST_READ_DATA = 'h2;
|
||||
|
||||
reg [1:0] write_state = ST_BYPASS;
|
||||
reg [1:0] read_state = ST_HEADER;
|
||||
|
||||
reg [ 7:0] dr_data_in = 'b0;
|
||||
reg [ 7:0] dr_data_out = 'b0;
|
||||
reg dr_loopback = 'b0;
|
||||
reg [ 2:0] dr_debug = 'b0;
|
||||
reg [10:0] dr_info = 'b0;
|
||||
reg [ 8:0] dr_control = 'b0;
|
||||
reg [MGMT_CHANNEL_WIDTH+2:0] dr_mgmt = 'b0;
|
||||
|
||||
reg [ 8:0] padded_bit_counter = 'b0;
|
||||
reg [ 7:0] bypass_bit_counter = 'b0;
|
||||
reg [ 2:0] write_data_bit_counter = 'b0;
|
||||
reg [ 2:0] read_data_bit_counter = 'b0;
|
||||
reg [ 3:0] header_in_bit_counter = 'b0;
|
||||
reg [ 3:0] header_out_bit_counter = 'b0;
|
||||
reg [18:0] scan_length_byte_counter = 'b0;
|
||||
reg [18:0] valid_write_data_length_byte_counter = 'b0;
|
||||
|
||||
reg write_data_valid = 'b0;
|
||||
reg read_data_valid = 'b0;
|
||||
reg read_data_all_valid = 'b0;
|
||||
|
||||
reg decode_header_1 = 'b0;
|
||||
reg decode_header_2 = 'b0;
|
||||
|
||||
wire write_data_byte_aligned;
|
||||
wire read_data_byte_aligned;
|
||||
wire padded_bit_byte_aligned;
|
||||
wire bytestream_end;
|
||||
|
||||
assign write_data_byte_aligned = (write_data_bit_counter == 1);
|
||||
assign read_data_byte_aligned = (read_data_bit_counter == 1);
|
||||
assign padded_bit_byte_aligned = (padded_bit_counter[2:0] == 'b0);
|
||||
assign bytestream_end = (scan_length_byte_counter == 'b0);
|
||||
|
||||
reg [ 7:0] offset = 'b0;
|
||||
reg [15:0] header_in = 'b0;
|
||||
|
||||
reg [9:0] scan_length = 'b0;
|
||||
reg [2:0] read_data_length = 'b0;
|
||||
reg [2:0] write_data_length = 'b0;
|
||||
|
||||
wire [7:0] idle_inserter_sink_data;
|
||||
wire idle_inserter_sink_valid;
|
||||
wire idle_inserter_sink_ready;
|
||||
wire [7:0] idle_inserter_source_data;
|
||||
reg idle_inserter_source_ready = 'b0;
|
||||
reg [7:0] idle_remover_sink_data = 'b0;
|
||||
reg idle_remover_sink_valid = 'b0;
|
||||
wire [7:0] idle_remover_source_data;
|
||||
wire idle_remover_source_valid;
|
||||
|
||||
assign source_data = idle_remover_source_data;
|
||||
assign source_valid = idle_remover_source_valid;
|
||||
assign sink_ready = idle_inserter_sink_ready;
|
||||
assign idle_inserter_sink_data = sink_data;
|
||||
assign idle_inserter_sink_valid = sink_valid;
|
||||
|
||||
reg clock_sensor = 'b0;
|
||||
reg clock_to_sample_div2 = 'b0;
|
||||
(* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) reg clock_sense_reset_n = 'b1;
|
||||
|
||||
wire data_available;
|
||||
|
||||
assign data_available = sink_valid;
|
||||
|
||||
wire [18:0] decoded_scan_length;
|
||||
wire [18:0] decoded_write_data_length;
|
||||
wire [18:0] decoded_read_data_length;
|
||||
|
||||
assign decoded_scan_length = { scan_length, {8{1'b1}} };
|
||||
// +-------------------+----------------+---------------------+
|
||||
// | scan_length | Length (bytes) | decoded_scan_length |
|
||||
// +-------------------+----------------+---------------------+
|
||||
// | 0x0 | 256 | 0x0ff (255) |
|
||||
// | 0x1 | 512 | 0x1ff (511) |
|
||||
// | 0x2 | 768 | 0x2ff (767) |
|
||||
// | . | . | . |
|
||||
// | 0x3ff | 256k | 0x3ff (256k-1) |
|
||||
// +-------------------+----------------+---------------------+
|
||||
|
||||
// TODO: use look up table to save LEs?
|
||||
// Decoded value is correct except for 0x7
|
||||
assign decoded_write_data_length = (write_data_length == 0) ? 19'h0 : (19'h00080 << write_data_length);
|
||||
assign decoded_read_data_length = (read_data_length == 0) ? 19'h0 : (19'h00080 << read_data_length);
|
||||
// +-------------------+---------------+---------------------------+
|
||||
// | read_data_length | Length | decoded_read_data_length |
|
||||
// | write_data_length | (bytes) | decoded_write_data_length |
|
||||
// +-------------------+---------------+---------------------------+
|
||||
// | 0x0 | 0 | 0x0000 (0) |
|
||||
// | 0x1 | 256 | 0x0100 (256) |
|
||||
// | 0x2 | 512 | 0x0200 (512) |
|
||||
// | 0x3 | 1k | 0x0400 (1024) |
|
||||
// | 0x4 | 2k | 0x0800 (2048) |
|
||||
// | 0x5 | 4k | 0x1000 (4096) |
|
||||
// | 0x6 | 8k | 0x2000 (8192) |
|
||||
// | 0x7 | scan_length | invalid |
|
||||
// +-------------------+---------------+---------------------------+
|
||||
|
||||
wire clock_sensor_sync;
|
||||
wire reset_to_sample_sync;
|
||||
wire clock_to_sample_div2_sync;
|
||||
wire clock_sense_reset_n_sync;
|
||||
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_sensor_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(clock_sensor),
|
||||
.dout(clock_sensor_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) reset_to_sample_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(reset_to_sample),
|
||||
.dout(reset_to_sample_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_to_sample_div2_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(clock_to_sample_div2),
|
||||
.dout(clock_to_sample_div2_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) clock_sense_reset_n_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(clock_sense_reset_n),
|
||||
.din(1'b1),
|
||||
.dout(clock_sense_reset_n_sync));
|
||||
|
||||
|
||||
|
||||
always @ (posedge clock_to_sample or negedge clock_sense_reset_n_sync) begin
|
||||
if (~clock_sense_reset_n_sync) begin
|
||||
clock_sensor <= 1'b0;
|
||||
end else begin
|
||||
clock_sensor <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge clock_to_sample) begin
|
||||
clock_to_sample_div2 <= ~clock_to_sample_div2;
|
||||
end
|
||||
|
||||
always @ (posedge tck) begin
|
||||
|
||||
idle_remover_sink_valid <= 1'b0;
|
||||
idle_inserter_source_ready <= 1'b0;
|
||||
|
||||
// Data mode sourcing (write)
|
||||
|
||||
// offset(rounded 8) m-i i 16 offset
|
||||
// +------------+-----------+------------------+--------+------------+
|
||||
// tdi -> | padded_bit | undefined | valid_write_data | header | bypass_bit |
|
||||
// +------------+-----------+------------------+--------+------------+
|
||||
// Data mode DR data stream write format (as seen by hardware)
|
||||
//
|
||||
if (ir_in == DATA) begin
|
||||
|
||||
|
||||
if (virtual_state_cdr) begin
|
||||
if (offset == 'b0) begin
|
||||
write_state <= ST_HEADER_1;
|
||||
end else begin
|
||||
write_state <= ST_BYPASS;
|
||||
end
|
||||
// 8-bit bypass_bit_counter
|
||||
bypass_bit_counter <= offset;
|
||||
// 4-bit header_in_bit_counter
|
||||
header_in_bit_counter <= 15;
|
||||
// 3-bit write_data_bit_counter
|
||||
write_data_bit_counter <= 0;
|
||||
// Reset the registers
|
||||
// TODO: not necessarily all, reduce LE
|
||||
decode_header_1 <= 1'b0;
|
||||
decode_header_2 <= 1'b0;
|
||||
read_data_all_valid <= 1'b0;
|
||||
valid_write_data_length_byte_counter <= 0;
|
||||
end
|
||||
|
||||
if (virtual_state_sdr) begin
|
||||
// Discard bypass bits, then decode the 16-bit header
|
||||
// 3 3 10
|
||||
// +-------------------+------------------+-------------+
|
||||
// | write_data_length | read_data_length | scan_length |
|
||||
// +-------------------+------------------+-------------+
|
||||
// Header format
|
||||
|
||||
case (write_state)
|
||||
ST_BYPASS: begin
|
||||
// Discard the bypass bit
|
||||
bypass_bit_counter <= bypass_bit_counter - 1'b1;
|
||||
if (bypass_bit_counter == 1) begin
|
||||
write_state <= ST_HEADER_1;
|
||||
end
|
||||
end
|
||||
// Shift the scan_length and read_data_length
|
||||
ST_HEADER_1: begin
|
||||
// TODO: header_in can be shorter
|
||||
// Shift into header_in
|
||||
header_in <= {tdi, header_in[15:1]};
|
||||
header_in_bit_counter <= header_in_bit_counter - 1'b1;
|
||||
if (header_in_bit_counter == 3) begin
|
||||
read_data_length <= {tdi, header_in[15:14]};
|
||||
scan_length <= header_in[13:4];
|
||||
write_state <= ST_HEADER_2;
|
||||
decode_header_1 <= 1'b1;
|
||||
end
|
||||
end
|
||||
// Shift the write_data_length
|
||||
ST_HEADER_2: begin
|
||||
// Shift into header_in
|
||||
header_in <= {tdi, header_in[15:1]};
|
||||
header_in_bit_counter <= header_in_bit_counter - 1'b1;
|
||||
// Decode read_data_length and scan_length
|
||||
if (decode_header_1) begin
|
||||
decode_header_1 <= 1'b0;
|
||||
// Set read_data_all_valid
|
||||
if (read_data_length == 3'b111) begin
|
||||
read_data_all_valid <= 1'b1;
|
||||
end
|
||||
// Load scan_length_byte_counter
|
||||
scan_length_byte_counter <= decoded_scan_length;
|
||||
end
|
||||
if (header_in_bit_counter == 0) begin
|
||||
write_data_length <= {tdi, header_in[15:14]};
|
||||
write_state <= ST_WRITE_DATA;
|
||||
decode_header_2 <= 1'b1;
|
||||
end
|
||||
end
|
||||
// Shift the valid_write_data
|
||||
ST_WRITE_DATA: begin
|
||||
// Shift into dr_data_in
|
||||
dr_data_in <= {tdi, dr_data_in[7:1]};
|
||||
// Decode write_data_length
|
||||
if (decode_header_2) begin
|
||||
decode_header_2 <= 1'b0;
|
||||
// Load valid_write_data_length_byte_counter
|
||||
case (write_data_length)
|
||||
3'b111: valid_write_data_length_byte_counter <= decoded_scan_length + 1'b1;
|
||||
3'b000: valid_write_data_length_byte_counter <= 'b0;
|
||||
default: valid_write_data_length_byte_counter <= decoded_write_data_length;
|
||||
endcase
|
||||
end
|
||||
write_data_bit_counter <= write_data_bit_counter - 1'b1;
|
||||
write_data_valid <= (valid_write_data_length_byte_counter != 0);
|
||||
// Feed the data to the idle remover
|
||||
if (write_data_byte_aligned && write_data_valid) begin
|
||||
valid_write_data_length_byte_counter <= valid_write_data_length_byte_counter - 1'b1;
|
||||
idle_remover_sink_valid <= 1'b1;
|
||||
idle_remover_sink_data <= {tdi, dr_data_in[7:1]};
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// Data mode sinking (read)
|
||||
|
||||
// i m-i offset(rounded 8) 16
|
||||
// +-----------------+-----------+------------+--------+
|
||||
// | valid_read_data | undefined | padded_bit | header | -> tdo
|
||||
// +-----------------+-----------+------------+--------+
|
||||
// Data mode DR data stream read format (as seen by hardware)
|
||||
//
|
||||
if (ir_in == DATA) begin
|
||||
|
||||
if (virtual_state_cdr) begin
|
||||
|
||||
read_state <= ST_HEADER;
|
||||
// Offset is rounded to nearest ceiling x8 to byte-align padded bits
|
||||
// 9-bit padded_bit_counter
|
||||
if (|offset[2:0]) begin
|
||||
padded_bit_counter[8:3] <= offset[7:3] + 1'b1;
|
||||
padded_bit_counter[2:0] <= 3'b0;
|
||||
end else begin
|
||||
padded_bit_counter <= {1'b0, offset};
|
||||
end
|
||||
// 4-bit header_out_bit_counter
|
||||
header_out_bit_counter <= 0;
|
||||
// 3-bit read_data_bit_counter
|
||||
read_data_bit_counter <= 0;
|
||||
// Load the data_available bit into header
|
||||
dr_data_out <= {{7{1'b0}}, data_available};
|
||||
read_data_valid <= 0;
|
||||
|
||||
end
|
||||
|
||||
if (virtual_state_sdr) begin
|
||||
// 10 1
|
||||
// +-----------------------------------+----------------+
|
||||
// | reserved | data_available |
|
||||
// +-----------------------------------+----------------+
|
||||
// Header format
|
||||
|
||||
dr_data_out <= {1'b0, dr_data_out[7:1]};
|
||||
case (read_state)
|
||||
// Shift the scan_length and read_data_length
|
||||
ST_HEADER: begin
|
||||
header_out_bit_counter <= header_out_bit_counter - 1'b1;
|
||||
// Retrieve data from idle inserter for the next shift if no paddded bits
|
||||
if (header_out_bit_counter == 2) begin
|
||||
if (padded_bit_counter == 0) begin
|
||||
idle_inserter_source_ready <= read_data_all_valid;
|
||||
end
|
||||
end
|
||||
if (header_out_bit_counter == 1) begin
|
||||
if (padded_bit_counter == 0) begin
|
||||
read_state <= ST_READ_DATA;
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
|
||||
end else begin
|
||||
read_state <= ST_PADDED;
|
||||
padded_bit_counter <= padded_bit_counter - 1'b1;
|
||||
idle_inserter_source_ready <= 1'b0;
|
||||
dr_data_out <= 8'h4a;
|
||||
end
|
||||
end
|
||||
end
|
||||
ST_PADDED: begin
|
||||
padded_bit_counter <= padded_bit_counter - 1'b1;
|
||||
if (padded_bit_byte_aligned) begin
|
||||
// Load idle character into data register
|
||||
dr_data_out <= 8'h4a;
|
||||
end
|
||||
// Retrieve data from idle inserter for the next shift when padded bits finish
|
||||
if (padded_bit_counter == 1) begin
|
||||
idle_inserter_source_ready <= read_data_all_valid;
|
||||
end
|
||||
if (padded_bit_counter == 0) begin // TODO: might make use of (padded_bit_counter[8:3]&padded_bit_byte_aligned)
|
||||
read_state <= ST_READ_DATA;
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
|
||||
end
|
||||
end
|
||||
ST_READ_DATA: begin
|
||||
read_data_bit_counter <= read_data_bit_counter - 1'b1;
|
||||
// Retrieve data from idle inserter just before read_data_byte_aligned
|
||||
if (read_data_bit_counter == 2) begin
|
||||
// Assert ready to retrieve data from idle inserter only when the bytestream has not ended,
|
||||
// data is valid (idle_inserter is always valid) and data is needed (read_data_valid)
|
||||
idle_inserter_source_ready <= bytestream_end ? 1'b0 : read_data_valid;
|
||||
end
|
||||
if (read_data_byte_aligned) begin
|
||||
// Note that bytestream_end is driven by scan_length_byte_counter
|
||||
if (~bytestream_end) begin
|
||||
scan_length_byte_counter <= scan_length_byte_counter - 1'b1;
|
||||
end
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
// Load idle character if bytestream has ended, else get data from the idle inserter
|
||||
dr_data_out <= (read_data_valid & ~bytestream_end) ? idle_inserter_source_data : 8'h4a;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// Loopback mode
|
||||
if (ir_in == LOOPBACK) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_loopback <= 1'b0; // capture 0
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_loopback
|
||||
dr_loopback <= tdi;
|
||||
end
|
||||
end
|
||||
|
||||
// Debug mode
|
||||
if (ir_in == DEBUG) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_debug <= {clock_sensor_sync, clock_to_sample_div2_sync, reset_to_sample_sync};
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_debug
|
||||
dr_debug <= {1'b0, dr_debug[2:1]}; // tdi is ignored
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
clock_sense_reset_n <= 1'b0;
|
||||
end else begin
|
||||
clock_sense_reset_n <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Info mode
|
||||
if (ir_in == INFO) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_info <= {PURPOSE[2:0], UPSTREAM_ENCODED_SIZE[3:0], DOWNSTREAM_ENCODED_SIZE[3:0]};
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_info
|
||||
dr_info <= {1'b0, dr_info[10:1]}; // tdi is ignored
|
||||
end
|
||||
end
|
||||
|
||||
// Control mode
|
||||
if (ir_in == CONTROL) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_control <= 'b0; // capture 0
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_control
|
||||
dr_control <= {tdi, dr_control[8:1]};
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
// Update resetrequest and offset
|
||||
{resetrequest, offset} <= dr_control;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @ * begin
|
||||
if (virtual_state_sdr) begin
|
||||
case (ir_in)
|
||||
DATA: tdo <= dr_data_out[0];
|
||||
LOOPBACK: tdo <= dr_loopback;
|
||||
DEBUG: tdo <= dr_debug[0];
|
||||
INFO: tdo <= dr_info[0];
|
||||
CONTROL: tdo <= dr_control[0];
|
||||
MGMT: tdo <= dr_mgmt[0];
|
||||
default: tdo <= 1'b0;
|
||||
endcase
|
||||
end else begin
|
||||
tdo <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Idle Remover
|
||||
altera_avalon_st_idle_remover idle_remover (
|
||||
// Interface: clk
|
||||
.clk (tck),
|
||||
.reset_n (reset_n),
|
||||
|
||||
// Interface: ST in
|
||||
.in_ready (), // left disconnected
|
||||
.in_valid (idle_remover_sink_valid),
|
||||
.in_data (idle_remover_sink_data),
|
||||
|
||||
// Interface: ST out
|
||||
.out_ready (1'b1), // downstream is expected to be always ready
|
||||
.out_valid (idle_remover_source_valid),
|
||||
.out_data (idle_remover_source_data)
|
||||
);
|
||||
|
||||
// Idle Inserter
|
||||
altera_avalon_st_idle_inserter idle_inserter (
|
||||
// Interface: clk
|
||||
.clk (tck),
|
||||
.reset_n (reset_n),
|
||||
|
||||
// Interface: ST in
|
||||
.in_ready (idle_inserter_sink_ready),
|
||||
.in_valid (idle_inserter_sink_valid),
|
||||
.in_data (idle_inserter_sink_data),
|
||||
|
||||
// Interface: ST out
|
||||
.out_ready (idle_inserter_source_ready),
|
||||
.out_valid (),
|
||||
.out_data (idle_inserter_source_data)
|
||||
);
|
||||
|
||||
generate
|
||||
if (MGMT_CHANNEL_WIDTH > 0)
|
||||
begin : has_mgmt
|
||||
reg [MGMT_CHANNEL_WIDTH+2:0] mgmt_out = 'b0;
|
||||
reg mgmt_toggle = 1'b0;
|
||||
wire mgmt_toggle_sync;
|
||||
reg mgmt_toggle_prev;
|
||||
wire mgmt_out_sync_ctl;
|
||||
|
||||
always @ (posedge tck) begin
|
||||
// Debug mode
|
||||
if (ir_in == MGMT) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_mgmt <= 'b0;
|
||||
dr_mgmt[MGMT_CHANNEL_WIDTH+2] <= 1'b1;
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_debug
|
||||
dr_mgmt <= {tdi, dr_mgmt[MGMT_CHANNEL_WIDTH+2:1]};
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
mgmt_out <= dr_mgmt;
|
||||
mgmt_toggle <= mgmt_out[MGMT_CHANNEL_WIDTH+2] ? 1'b0 : ~mgmt_toggle;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) debug_reset_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(1'b1),
|
||||
.din(mgmt_out[MGMT_CHANNEL_WIDTH+2]),
|
||||
.dout(debug_reset));
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH_PLUS_ONE)) mgmt_toggle_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(1'b1),
|
||||
.din(mgmt_toggle),
|
||||
.dout(mgmt_toggle_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) mgmt_out_synchornizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(1'b1),
|
||||
.din(mgmt_out[MGMT_CHANNEL_WIDTH+1]),
|
||||
.dout(mgmt_out_sync_ctl));
|
||||
|
||||
|
||||
|
||||
always @ (posedge clock_to_sample or posedge debug_reset) begin
|
||||
if (debug_reset) begin
|
||||
mgmt_valid <= 1'b0;
|
||||
mgmt_toggle_prev <= 1'b0;
|
||||
end else begin
|
||||
if ((mgmt_toggle_sync ^ mgmt_toggle_prev) && mgmt_out_sync_ctl) begin
|
||||
mgmt_valid <= 1'b1;
|
||||
mgmt_channel <= mgmt_out[MGMT_CHANNEL_WIDTH:1];
|
||||
mgmt_data <= mgmt_out[0];
|
||||
end else begin
|
||||
mgmt_valid <= 1'b0;
|
||||
end
|
||||
mgmt_toggle_prev <= mgmt_toggle_sync;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
else
|
||||
begin : no_mgmt
|
||||
always @ (posedge tck) begin
|
||||
dr_mgmt[0] <= 1'b0;
|
||||
end
|
||||
assign debug_reset = 1'b0;
|
||||
always @ (posedge clock_to_sample) begin
|
||||
mgmt_valid <= 1'b0;
|
||||
mgmt_data <= 'b0;
|
||||
mgmt_channel <= 'b0;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43nch1THUj1J8wIocquwt/bKC/6wb5IrPaKQhLL4d9X7qOL25fim0OQ3w1e0kI9Su7SxOq7ZeSyLHj+thEW81l9l8AIIwYAnL8RErrsKah5+K4cM0jnu4Q57T7g5np938yAiAJHtcHjIGKM7kBQ8LOc/GvAIFGNaoWSAU+fzOm9T0zKuxhwPOFnvX/y2bCxbSGVw0YUtrKWi6k3DtxMHvxpI1B0A/PRseX5R/ZU0YsatatbrJ9bBer2Cgm95xnVbEsjyotNgilqeYUu/UgEby87pNGmOZd+Q8kTdNo6dBoHXXd3SQgzQZmNfyzZ0rudNzqJIG1q1YDtm3mMyQLIPhgneAjvB3l4HHHEdZaQW7QqQekZIxvqWjb6uCAKdfleuj/5tSASLRRKfjbS3tgmSR/vENA8bCbwBIQyPjO6a8sP/cVJJ1SY1UpSWi8lFdOA/YU8Y93mbIp3zqbCGvJX2uFvY9isn0VI71r0cYtq0LiKIv1+cEhjBsjHkjTHOSIfB45TxCawv4zFyTFlXFMeu1eSw+gKDrO3f944d/+fO5hb9awxgONZ1Qc8sdjDvw+JSnNwIvj+CZHWhF7k8EnUrGrA3id6ahcy5ss0wiZSNia7RwLg/y+hBdhnmCSMTdDFwXQ8UCndkIJi6mfsx3C+/NbHL7Mq1WOF/8+t0eBVEWrBrbtoiet15r/GMbZycW2wzHUUd5lW5CrMBdqVcOXKkS4nid4gZdeUdB5gifM6uvnL0hMwlftSdr1VbxBNE8EnzL5+Sbe7tRYnJrpPaI9v467AP"
|
||||
`endif
|
||||
+89
@@ -0,0 +1,89 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// -----------------------------------------------
|
||||
// Reset Synchronizer
|
||||
// -----------------------------------------------
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_synchronizer
|
||||
#(
|
||||
parameter ASYNC_RESET = 1,
|
||||
parameter DEPTH = 2
|
||||
)
|
||||
(
|
||||
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
|
||||
|
||||
input clk,
|
||||
output reset_out
|
||||
);
|
||||
|
||||
// -----------------------------------------------
|
||||
// Synchronizer register chain. We cannot reuse the
|
||||
// standard synchronizer in this implementation
|
||||
// because our timing constraints are different.
|
||||
//
|
||||
// Instead of cutting the timing path to the d-input
|
||||
// on the first flop we need to cut the aclr input.
|
||||
//
|
||||
// We omit the "preserve" attribute on the final
|
||||
// output register, so that the synthesis tool can
|
||||
// duplicate it where needed.
|
||||
// -----------------------------------------------
|
||||
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
|
||||
reg altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
generate if (ASYNC_RESET) begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert asynchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk or posedge reset_in) begin
|
||||
if (reset_in) begin
|
||||
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
|
||||
altera_reset_synchronizer_int_chain_out <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end else begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert synchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk) begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43m3wnlehhyl/tvDkBTp1EtPpbSB7YBxMa/I8ZSI1dsWR/qcwyHhk27aoKzAbN2oGgXxnkwGf/9jPkx/jeL/VKbKIEY/78RjwxdNSCxTIRDJqQC4btrU936foYfcH4GIkOj1Pb8nFcEnnGY2UJoXMYcN51IJ1jy971+TxnUYP9B6ARYUmle9XtPoHHUKAYDS/tpju+pAaSva2iqW+gYvhSLYW1152f8xap7C5X60qVk8Bs11aIz0KJPZdF+f8bl9mwoAU39/rZQ6WcxvYEj1WnTK9f+aUGqcmmR+vUNBXXNN0C54sq0s5+6Nl8rpoXhs5VLdHpQr7Hat1GKzvMbNFmVBKP7BMC8ZPrGL63Oy6brcicq+7H7Ba23PxPyxRFJRiTAzutT9yIp3fNKDF8Mxfa18JediNCf2ZaBWrSnyppAn3tdQhF/5EzJyKO4hnV97MohBYYq5jOYf9FAlLGWdPlUgTCu3eUDmAhDMLjL1gJ3Ra4I6eUQfUcGeV3naPYko4wBX4pUYdx5CfIVAObW/RPsXGvLBU/6Ua16JjWk9+HRLtyu1oF+tSyHwHSe6GTbtVimKfBv+Z9iq9fw3/pchuMmvOQ0erCRAWsGe1gVpq3THnpq2rsWByBDOpaxfSLEyW/s5dLZy5F77rEz3L5gN6hPD1Ip/9hRQqCswu8HpGj2nu8SfFiMcD7SGKBiuaXTY5Cjib0cZWywM7PTWyZf2PACVBwRn7evdMFX0LLrqaC0VbIgjapuMBfJ9UfmsFIdeEDpIFZUwIkWqsKmeF1BIPe1C"
|
||||
`endif
|
||||
+267
@@ -0,0 +1,267 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
|
||||
// $Revision: #8 $
|
||||
// $Date: 2009/02/18 $
|
||||
// $Author: pscheidt $
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// File: altera_std_synchronizer_nocut.v
|
||||
//
|
||||
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
|
||||
// as altera_std_synchronizer.v, except that the embedded false
|
||||
// path constraint is removed in this module. If you use this
|
||||
// module, you will have to apply the appropriate timing
|
||||
// constraints.
|
||||
//
|
||||
// We expect to make this a standard Quartus atom eventually.
|
||||
//
|
||||
// Composed of two or more flip flops connected in series.
|
||||
// Random metastable condition is simulated when the
|
||||
// __ALTERA_STD__METASTABLE_SIM macro is defined.
|
||||
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
|
||||
// on the Verilog simulator compiler command line to
|
||||
// enable this mode. In addition, define the macro
|
||||
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
|
||||
// with every metastable event generated in the synchronizer.
|
||||
//
|
||||
// Copyright (C) Altera Corporation 2009, All Rights Reserved
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_std_synchronizer_nocut (
|
||||
clk,
|
||||
reset_n,
|
||||
din,
|
||||
dout
|
||||
);
|
||||
|
||||
parameter depth = 3; // This value must be >= 2 !
|
||||
parameter rst_value = 0;
|
||||
|
||||
//when enabled, this will allow retiming for the sync depth >3.
|
||||
parameter retiming_reg_en = 0;
|
||||
|
||||
input clk;
|
||||
input reset_n;
|
||||
input din;
|
||||
output dout;
|
||||
|
||||
// QuartusII synthesis directives:
|
||||
// 1. Preserve all registers ie. do not touch them.
|
||||
// 2. Do not merge other flip-flops with synchronizer flip-flops.
|
||||
// QuartusII TimeQuest directives:
|
||||
// 1. Identify all flip-flops in this module as members of the synchronizer
|
||||
// to enable automatic metastability MTBF analysis.
|
||||
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
|
||||
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
|
||||
|
||||
//synthesis translate_off
|
||||
`ifndef QUARTUS_CDC
|
||||
initial begin
|
||||
if (retiming_reg_en == 0 ) begin
|
||||
if (depth <2) begin
|
||||
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (depth <4) begin
|
||||
$display("%m: Error: synchronizer length: %0d less than 4 with retiming enabled.", depth);
|
||||
end
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
// the first synchronizer register is either a simple D flop for synthesis
|
||||
// and non-metastable simulation or a D flop with a method to inject random
|
||||
// metastable events resulting in random delay of [0,1] cycles
|
||||
|
||||
`ifdef __ALTERA_STD__METASTABLE_SIM
|
||||
|
||||
reg[31:0] RANDOM_SEED = 123456;
|
||||
wire next_din_s1;
|
||||
wire dout;
|
||||
reg din_last;
|
||||
reg random;
|
||||
event metastable_event; // hook for debug monitoring
|
||||
|
||||
initial begin
|
||||
$display("%m: Info: Metastable event injection simulation mode enabled");
|
||||
random = $random;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset_n == 0)
|
||||
random <= $random(RANDOM_SEED);
|
||||
else
|
||||
random <= $random;
|
||||
end
|
||||
|
||||
assign next_din_s1 = (din_last ^ din) ? random : din;
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_last <= (rst_value == 0)? 1'b0 : 1'b1;
|
||||
else
|
||||
din_last <= din;
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
|
||||
else
|
||||
din_s1 <= next_din_s1;
|
||||
end
|
||||
|
||||
`else
|
||||
|
||||
//synthesis translate_on
|
||||
generate if (rst_value == 0)
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= 1'b0;
|
||||
else
|
||||
din_s1 <= din;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (rst_value == 1)
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= 1'b1;
|
||||
else
|
||||
din_s1 <= din;
|
||||
end
|
||||
endgenerate
|
||||
//synthesis translate_off
|
||||
|
||||
`endif
|
||||
|
||||
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
|
||||
always @(*) begin
|
||||
if (reset_n && (din_last != din) && (random != din)) begin
|
||||
$display("%m: Verbose Info: metastable event @ time %t", $time);
|
||||
->metastable_event;
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
//synthesis translate_on
|
||||
|
||||
// the remaining synchronizer registers form a simple shift register
|
||||
// of length depth-1
|
||||
generate if (rst_value == 0) begin
|
||||
if (retiming_reg_en == 0) begin
|
||||
if (depth < 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg <= din_s1;
|
||||
end
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg <= {dreg[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
|
||||
assign dout = dreg[depth-2];
|
||||
end
|
||||
|
||||
else begin //This part is enabled when we set retiming_reg_en =1
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [1:0] dreg1;
|
||||
reg [depth-4:0] dreg2;
|
||||
wire [depth-2:0] dreg3;
|
||||
|
||||
assign dreg3 = {dreg2,dreg1};
|
||||
|
||||
if (depth <= 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg1 <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg1 <= din_s1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
{dreg2,dreg1} <= {depth-1{1'b0}};
|
||||
else
|
||||
{dreg2,dreg1} <= {dreg3[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg3[depth-2];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
else begin
|
||||
if (retiming_reg_en == 0) begin
|
||||
if (depth < 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg <= din_s1;
|
||||
end
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg <= {dreg[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg[depth-2];
|
||||
end
|
||||
|
||||
else begin
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [1:0] dreg1;
|
||||
reg [depth-4:0] dreg2;
|
||||
wire [depth-2:0] dreg3;
|
||||
|
||||
assign dreg3 = {dreg2,dreg1};
|
||||
|
||||
if (depth <= 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg1 <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg1 <= din_s1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
{dreg2,dreg1} <= {depth-1{1'b1}};
|
||||
else
|
||||
{dreg2,dreg1} <= {dreg3[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg3[depth-2];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43mCNPgtQr4hyUU4j86E903EvNfn1Ii/WXb12AEo64XSzinw4H9M64X3VrqZhPbCO8xw9VuZTidKsxxCiGMDNJFPc5y1BTrLcKFthIozfH+O4KS+/oVUEBy9vO4GOsJxaSxhKvtTgjz5HZCGqEVWWYErC33V9PybEQtP4jtcp/BoprsnJd8iwiVAgsTIGcopMmGgf84pOj3nOuhzeU8d7uS3dusa48HLsimnu0BhQMaLC4weSp1Kt/Up8x/ernjcbOKU1hpYaJ4Ujin7FtRELzaVB/EYUhMmzNw94lF0CD9pLiLXhAhE2Keh19nNOqWY1WDhkTvMYyVp7CBh3Dryo3df78teIPhp52/W2iSie+4uUmcM5fMbH8OxEAonWNr09vofAiynIGfHVpzGGj6ut3v2SLN2gEtbakpZAaFooskDYgGwsJRa9S2uVGkTs5Gsa8vKFHOs96TdG59fw54QNai04RRZs6VlOcKk4dVTr9WYthRGlandQHiCDG85hyUn9M6QRI5hA5vsf3xqBsiP7RrHqFZzoVWopikMJzkNCQxbcIqmp+Pp85b9szMI7qPO9knJD2ujGcuLRYMBaFNQtoGTzU+PhfLRHQEdH7lI63TRJpwDx41BBVljDGLpc4lBF4PBIEZ5LeeFzjMIY+Oy2asXd7c93WPJbmwZDcwvoO3ZH9CJefKH3y0z83QRTPgYlTp1Cpe6jtY3L0HNttlWFhj4b7rwi+SRJgWVdxPcc+WoE/0/gN4BxAYeAs4HJ2gfBLX/cP75eNMU/eXC/UlLFneB"
|
||||
`endif
|
||||
+44
@@ -0,0 +1,44 @@
|
||||
# (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and other
|
||||
# software and tools, and its AMPP partner logic functions, and any output
|
||||
# files from any of the foregoing (including device programming or simulation
|
||||
# files), and any associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License Subscription
|
||||
# Agreement, Altera IP License Agreement, or other applicable
|
||||
# license agreement, including, without limitation, that your use is for the
|
||||
# sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
|
||||
# +---------------------------------------------------
|
||||
# | Cut the async clear paths
|
||||
# +---------------------------------------------------
|
||||
set aclr_counter 0
|
||||
set clrn_counter 0
|
||||
if { [expr ![info exists show_hpath_of_all_reset_controller_inst]] } {
|
||||
set show_hpath_of_all_reset_controller_inst 0
|
||||
}
|
||||
if {[get_current_instance] == ""} {set hpath ""} else {set hpath "[get_current_instance]|*"}
|
||||
if {$show_hpath_of_all_reset_controller_inst == 1} {
|
||||
post_message -type info "Following instance found in the design - $hpath"
|
||||
}
|
||||
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
set num_sync_stage [get_registers -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[*]]
|
||||
set num_sync_count [get_collection_size $num_sync_stage]
|
||||
set aclr_counter [get_collection_size $aclr_collection]
|
||||
set clrn_counter [get_collection_size $clrn_collection]
|
||||
|
||||
if {$aclr_counter == 0 && $clrn_counter == 0 && $num_sync_count > 0} {
|
||||
set_max_delay -to [get_registers ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[[expr $num_sync_count-1]]] 100
|
||||
set_min_delay -to [get_registers ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[[expr $num_sync_count-1]]] -100
|
||||
}
|
||||
|
||||
if {$aclr_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
}
|
||||
|
||||
if {$clrn_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
}
|
||||
+367
@@ -0,0 +1,367 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_controller.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// --------------------------------------
|
||||
// Reset controller
|
||||
//
|
||||
// Combines all the input resets and synchronizes
|
||||
// the result to the clk.
|
||||
// ACDS13.1 - Added reset request as part of reset sequencing
|
||||
// --------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_controller
|
||||
#(
|
||||
parameter NUM_RESET_INPUTS = 6,
|
||||
parameter USE_RESET_REQUEST_IN0 = 0,
|
||||
parameter USE_RESET_REQUEST_IN1 = 0,
|
||||
parameter USE_RESET_REQUEST_IN2 = 0,
|
||||
parameter USE_RESET_REQUEST_IN3 = 0,
|
||||
parameter USE_RESET_REQUEST_IN4 = 0,
|
||||
parameter USE_RESET_REQUEST_IN5 = 0,
|
||||
parameter USE_RESET_REQUEST_IN6 = 0,
|
||||
parameter USE_RESET_REQUEST_IN7 = 0,
|
||||
parameter USE_RESET_REQUEST_IN8 = 0,
|
||||
parameter USE_RESET_REQUEST_IN9 = 0,
|
||||
parameter USE_RESET_REQUEST_IN10 = 0,
|
||||
parameter USE_RESET_REQUEST_IN11 = 0,
|
||||
parameter USE_RESET_REQUEST_IN12 = 0,
|
||||
parameter USE_RESET_REQUEST_IN13 = 0,
|
||||
parameter USE_RESET_REQUEST_IN14 = 0,
|
||||
parameter USE_RESET_REQUEST_IN15 = 0,
|
||||
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
|
||||
parameter SYNC_DEPTH = 2,
|
||||
parameter RESET_REQUEST_PRESENT = 0,
|
||||
parameter RESET_REQ_WAIT_TIME = 3,
|
||||
parameter MIN_RST_ASSERTION_TIME = 11,
|
||||
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
|
||||
parameter ADAPT_RESET_REQUEST = 0
|
||||
)
|
||||
(
|
||||
// --------------------------------------
|
||||
// We support up to 16 reset inputs, for now
|
||||
// --------------------------------------
|
||||
input reset_in0,
|
||||
input reset_in1,
|
||||
input reset_in2,
|
||||
input reset_in3,
|
||||
input reset_in4,
|
||||
input reset_in5,
|
||||
input reset_in6,
|
||||
input reset_in7,
|
||||
input reset_in8,
|
||||
input reset_in9,
|
||||
input reset_in10,
|
||||
input reset_in11,
|
||||
input reset_in12,
|
||||
input reset_in13,
|
||||
input reset_in14,
|
||||
input reset_in15,
|
||||
input reset_req_in0,
|
||||
input reset_req_in1,
|
||||
input reset_req_in2,
|
||||
input reset_req_in3,
|
||||
input reset_req_in4,
|
||||
input reset_req_in5,
|
||||
input reset_req_in6,
|
||||
input reset_req_in7,
|
||||
input reset_req_in8,
|
||||
input reset_req_in9,
|
||||
input reset_req_in10,
|
||||
input reset_req_in11,
|
||||
input reset_req_in12,
|
||||
input reset_req_in13,
|
||||
input reset_req_in14,
|
||||
input reset_req_in15,
|
||||
|
||||
|
||||
input clk,
|
||||
output reg reset_out,
|
||||
output reg reset_req
|
||||
);
|
||||
|
||||
// Always use async reset synchronizer if reset_req is used
|
||||
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
|
||||
|
||||
// --------------------------------------
|
||||
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
|
||||
// --------------------------------------
|
||||
localparam MIN_METASTABLE = 3;
|
||||
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
|
||||
|
||||
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
|
||||
|
||||
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
|
||||
MIN_RST_ASSERTION_TIME + 1 :
|
||||
(
|
||||
(MIN_RST_ASSERTION_TIME > LARGER)?
|
||||
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
|
||||
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
|
||||
);
|
||||
|
||||
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
|
||||
// --------------------------------------
|
||||
|
||||
wire merged_reset;
|
||||
wire merged_reset_req_in;
|
||||
wire reset_out_pre;
|
||||
reg reset_out_pre_reg;
|
||||
wire reset_req_pre;
|
||||
|
||||
// Registers and Interconnect
|
||||
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
|
||||
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
|
||||
reg r_sync_rst;
|
||||
reg r_early_rst;
|
||||
|
||||
// --------------------------------------
|
||||
// "Or" all the input resets together
|
||||
// --------------------------------------
|
||||
assign merged_reset = (
|
||||
reset_in0 |
|
||||
reset_in1 |
|
||||
reset_in2 |
|
||||
reset_in3 |
|
||||
reset_in4 |
|
||||
reset_in5 |
|
||||
reset_in6 |
|
||||
reset_in7 |
|
||||
reset_in8 |
|
||||
reset_in9 |
|
||||
reset_in10 |
|
||||
reset_in11 |
|
||||
reset_in12 |
|
||||
reset_in13 |
|
||||
reset_in14 |
|
||||
reset_in15
|
||||
);
|
||||
|
||||
assign merged_reset_req_in = (
|
||||
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
|
||||
);
|
||||
|
||||
|
||||
// --------------------------------------
|
||||
// And if required, synchronize it to the required clock domain,
|
||||
// with the correct synchronization type
|
||||
// --------------------------------------
|
||||
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
|
||||
|
||||
assign reset_out_pre = merged_reset;
|
||||
assign reset_req_pre = merged_reset_req_in;
|
||||
|
||||
end else begin
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
|
||||
)
|
||||
alt_rst_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset),
|
||||
.reset_out (reset_out_pre)
|
||||
);
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_req_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset_req_in),
|
||||
.reset_out (reset_req_pre)
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
|
||||
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
|
||||
always @* begin
|
||||
reset_out = reset_out_pre;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
|
||||
|
||||
wire reset_out_pre2;
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH+1),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_sync_uq2
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (reset_out_pre),
|
||||
.reset_out (reset_out_pre2)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
reset_out = reset_out_pre2;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
|
||||
end
|
||||
else begin
|
||||
|
||||
// 3-FF Metastability Synchronizer
|
||||
//synthesis translate_off
|
||||
initial
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
|
||||
end
|
||||
|
||||
// Synchronous reset pipe
|
||||
initial
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
//synthesis translate_on
|
||||
|
||||
always @(posedge clk or posedge reset_out_pre)
|
||||
begin
|
||||
if (reset_out_pre)
|
||||
reset_out_pre_reg <= 1'h1;
|
||||
else
|
||||
reset_out_pre_reg <= reset_out_pre;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
|
||||
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre_reg};
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
else
|
||||
begin
|
||||
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
|
||||
end
|
||||
end
|
||||
|
||||
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
|
||||
// matches the early input.
|
||||
if (OUTPUT_RESET_SYNC_EDGES != "deassert" ) begin
|
||||
always @(posedge clk)
|
||||
begin
|
||||
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
|
||||
3'b000: r_sync_rst <= 1'b0; // Not reset
|
||||
3'b001: r_sync_rst <= 1'b0;
|
||||
3'b010: r_sync_rst <= 1'b0;
|
||||
3'b011: r_sync_rst <= 1'b1;
|
||||
3'b100: r_sync_rst <= 1'b1;
|
||||
3'b101: r_sync_rst <= 1'b1;
|
||||
3'b110: r_sync_rst <= 1'b1;
|
||||
3'b111: r_sync_rst <= 1'b1; // In Reset
|
||||
default: r_sync_rst <= 1'b1;
|
||||
endcase
|
||||
|
||||
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
|
||||
2'b00: r_early_rst <= 1'b0; // Not reset
|
||||
2'b01: r_early_rst <= 1'b1; // Coming out of reset
|
||||
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
|
||||
2'b11: r_early_rst <= 1'b1; // Held in reset
|
||||
default: r_early_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk)
|
||||
begin
|
||||
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
|
||||
3'b000: r_sync_rst <= 1'b0; // Not reset
|
||||
3'b001: r_sync_rst <= 1'b0;
|
||||
3'b010: r_sync_rst <= 1'b0;
|
||||
3'b011: r_sync_rst <= 1'b1;
|
||||
3'b100: r_sync_rst <= 1'b1;
|
||||
3'b101: r_sync_rst <= 1'b1;
|
||||
3'b110: r_sync_rst <= 1'b1;
|
||||
3'b111: r_sync_rst <= 1'b1; // In Reset
|
||||
default: r_sync_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge reset_out_pre )
|
||||
begin
|
||||
if(reset_out_pre) begin
|
||||
r_early_rst <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
|
||||
2'b00: r_early_rst <= 1'b0; // Not reset
|
||||
2'b01: r_early_rst <= 1'b1; // Coming out of reset
|
||||
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
|
||||
2'b11: r_early_rst <= 1'b1; // Held in reset
|
||||
default: r_early_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @* begin
|
||||
reset_out = r_sync_rst;
|
||||
reset_req = r_early_rst;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZnnPJQ9GW+KzJV34fwWUvQ3dkA3L6G1Y5K7Msyidrmy1+Wu1L3OcWjX9FvtOw9qp2N3MEsh8d37Y/XaDWgwPKNC8qRv7AvhMJ8gFYwiLYTkPi1JGF8rlDOciOlSe0OOKsr8Qz81WHxnR038xpX6fIqkZWCweSvngUTKyauUaG3pcY+PLaI1oAcJ9eRym8kGs7+NwWcvmELdBMCucyRm52xLUprKDGjl1P42hAILSXrJXQndIyOW9vmm5Nz2evvj2gB7JvvzIfzZNuCdhnar89ChldW1j3A+Y5m6PjMM9pOU+Kdh26eGwj9fZZaPPrvl+VD5Hayq5zw3hzxXM33wd7ilCEvwS6rEk8Y9ZOslAUf74KejNArjekIHMmeFTx8aBtKMMm9wuP0WfEDxS4D7dDYDACm+FLX34qfxBjV7W/HokgwigFzSriqhaJqGkXLfN5+hTHkfsgDXx2KmN06gp1nCxVedTw83W3GZ0BDKFGGS0SrJDzge4q0Uk/lHtpo0n3W2FLL7TnG2r0QOY3YYnu0XSzCwIGa7WV4lIgGQ2UA+tiJkkVFL8zBqM6qqSx9ti08BQh/ob6g2E6CgPAuslJthgrG6/r1FvrY6mpyjO0c0vIAKswPchm+wB2Dx4+tBsnmX0peJXGJsrHXXjvrk52pzvpmXakJa2qerImbpknUXUBPR32Ek97/2wIEZ2iBp/jGeJDFttVPGoIXLHd4UgEdCmpFbUpZryi8bTJExus/YhIhp284WmXYOU22OgxwRtIPZ4CLG3lWeyiuxybU+R6eL"
|
||||
`endif
|
||||
+89
@@ -0,0 +1,89 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// -----------------------------------------------
|
||||
// Reset Synchronizer
|
||||
// -----------------------------------------------
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_synchronizer
|
||||
#(
|
||||
parameter ASYNC_RESET = 1,
|
||||
parameter DEPTH = 2
|
||||
)
|
||||
(
|
||||
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
|
||||
|
||||
input clk,
|
||||
output reset_out
|
||||
);
|
||||
|
||||
// -----------------------------------------------
|
||||
// Synchronizer register chain. We cannot reuse the
|
||||
// standard synchronizer in this implementation
|
||||
// because our timing constraints are different.
|
||||
//
|
||||
// Instead of cutting the timing path to the d-input
|
||||
// on the first flop we need to cut the aclr input.
|
||||
//
|
||||
// We omit the "preserve" attribute on the final
|
||||
// output register, so that the synthesis tool can
|
||||
// duplicate it where needed.
|
||||
// -----------------------------------------------
|
||||
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
|
||||
reg altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
generate if (ASYNC_RESET) begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert asynchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk or posedge reset_in) begin
|
||||
if (reset_in) begin
|
||||
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
|
||||
altera_reset_synchronizer_int_chain_out <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end else begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert synchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk) begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZm98qIL7ekOBsgi3Jk6JINlBn1MPss/MY/onstD48jcwiif8Gs4IWdQ2N3ArmvPwztGaa9pFUdrqFC/ySuZse43QXHTSLktppbb5RWP6kUriuoicmo6krAD1dbg/gJD2CPBniH3lvaXSbq4NXuXvaIi5JFjsHvqYH5AYGEBbEYIvX50OtmvM7MmdXWz8yMt/2x5MXTWbyba6bfKDJO6u5VlcHp85j3oXhLyoSx6ddNAgFJy9rjF3Z+u9E7PhkTCkebQtUzC8lIU9rG1+dwJE98atxbf1BPMRyiFcpFny635Ygt4p5jSQaXJnjSr6IUlFMLGpbYxPn1FcSkyMGPl2hZ7QtQENnQ3zejAwBl3Ze7ED8vOSzEBB93wGiKKZGd9hNwx5qeE0sgSNJa00qx6RLsg5tdDdzTo2bNXHlCtfYMIt2/YE75hzYCE//Zmb1mMx8nElfiU7/CpeYigjPvinVN5SqMGjIfMFWJasqdSm9Kw1UAN9s0LK8S6K3T1TGkHThOkJWDfpad7wvhxSkVJ99h9FdBLMlmkBYEwI/u/MKtNrzgKPsLz1FZ5EHB/JZti7aWbfhXQS1FoZYSLodk3NCTCmYgyghebDnmxCjIcHta/kmoyhMwLpM8ogUx6J3QA9oOxI+AvWy9A+id8Pj2XJjjQZxXzlg9JOVaXvn88zi6LVC88csY6kT+ANYw3OMfSjw9C2F6wme2VCibcI+DhqZCNXC41h1m9pqNYMUyyrBy5GMRZpEvb5yXb0+fS85rTPw4BgZkbkOxcmoA92mjOky5L"
|
||||
`endif
|
||||
+44
@@ -0,0 +1,44 @@
|
||||
# (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and other
|
||||
# software and tools, and its AMPP partner logic functions, and any output
|
||||
# files from any of the foregoing (including device programming or simulation
|
||||
# files), and any associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License Subscription
|
||||
# Agreement, Altera IP License Agreement, or other applicable
|
||||
# license agreement, including, without limitation, that your use is for the
|
||||
# sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
|
||||
# +---------------------------------------------------
|
||||
# | Cut the async clear paths
|
||||
# +---------------------------------------------------
|
||||
set aclr_counter 0
|
||||
set clrn_counter 0
|
||||
if { [expr ![info exists show_hpath_of_all_reset_controller_inst]] } {
|
||||
set show_hpath_of_all_reset_controller_inst 0
|
||||
}
|
||||
if {[get_current_instance] == ""} {set hpath ""} else {set hpath "[get_current_instance]|*"}
|
||||
if {$show_hpath_of_all_reset_controller_inst == 1} {
|
||||
post_message -type info "Following instance found in the design - $hpath"
|
||||
}
|
||||
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
set num_sync_stage [get_registers -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[*]]
|
||||
set num_sync_count [get_collection_size $num_sync_stage]
|
||||
set aclr_counter [get_collection_size $aclr_collection]
|
||||
set clrn_counter [get_collection_size $clrn_collection]
|
||||
|
||||
if {$aclr_counter == 0 && $clrn_counter == 0 && $num_sync_count > 0} {
|
||||
set_max_delay -to [get_registers ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[[expr $num_sync_count-1]]] 100
|
||||
set_min_delay -to [get_registers ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[[expr $num_sync_count-1]]] -100
|
||||
}
|
||||
|
||||
if {$aclr_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
}
|
||||
|
||||
if {$clrn_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
}
|
||||
+367
@@ -0,0 +1,367 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_controller.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// --------------------------------------
|
||||
// Reset controller
|
||||
//
|
||||
// Combines all the input resets and synchronizes
|
||||
// the result to the clk.
|
||||
// ACDS13.1 - Added reset request as part of reset sequencing
|
||||
// --------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_controller
|
||||
#(
|
||||
parameter NUM_RESET_INPUTS = 6,
|
||||
parameter USE_RESET_REQUEST_IN0 = 0,
|
||||
parameter USE_RESET_REQUEST_IN1 = 0,
|
||||
parameter USE_RESET_REQUEST_IN2 = 0,
|
||||
parameter USE_RESET_REQUEST_IN3 = 0,
|
||||
parameter USE_RESET_REQUEST_IN4 = 0,
|
||||
parameter USE_RESET_REQUEST_IN5 = 0,
|
||||
parameter USE_RESET_REQUEST_IN6 = 0,
|
||||
parameter USE_RESET_REQUEST_IN7 = 0,
|
||||
parameter USE_RESET_REQUEST_IN8 = 0,
|
||||
parameter USE_RESET_REQUEST_IN9 = 0,
|
||||
parameter USE_RESET_REQUEST_IN10 = 0,
|
||||
parameter USE_RESET_REQUEST_IN11 = 0,
|
||||
parameter USE_RESET_REQUEST_IN12 = 0,
|
||||
parameter USE_RESET_REQUEST_IN13 = 0,
|
||||
parameter USE_RESET_REQUEST_IN14 = 0,
|
||||
parameter USE_RESET_REQUEST_IN15 = 0,
|
||||
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
|
||||
parameter SYNC_DEPTH = 2,
|
||||
parameter RESET_REQUEST_PRESENT = 0,
|
||||
parameter RESET_REQ_WAIT_TIME = 3,
|
||||
parameter MIN_RST_ASSERTION_TIME = 11,
|
||||
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
|
||||
parameter ADAPT_RESET_REQUEST = 0
|
||||
)
|
||||
(
|
||||
// --------------------------------------
|
||||
// We support up to 16 reset inputs, for now
|
||||
// --------------------------------------
|
||||
input reset_in0,
|
||||
input reset_in1,
|
||||
input reset_in2,
|
||||
input reset_in3,
|
||||
input reset_in4,
|
||||
input reset_in5,
|
||||
input reset_in6,
|
||||
input reset_in7,
|
||||
input reset_in8,
|
||||
input reset_in9,
|
||||
input reset_in10,
|
||||
input reset_in11,
|
||||
input reset_in12,
|
||||
input reset_in13,
|
||||
input reset_in14,
|
||||
input reset_in15,
|
||||
input reset_req_in0,
|
||||
input reset_req_in1,
|
||||
input reset_req_in2,
|
||||
input reset_req_in3,
|
||||
input reset_req_in4,
|
||||
input reset_req_in5,
|
||||
input reset_req_in6,
|
||||
input reset_req_in7,
|
||||
input reset_req_in8,
|
||||
input reset_req_in9,
|
||||
input reset_req_in10,
|
||||
input reset_req_in11,
|
||||
input reset_req_in12,
|
||||
input reset_req_in13,
|
||||
input reset_req_in14,
|
||||
input reset_req_in15,
|
||||
|
||||
|
||||
input clk,
|
||||
output reg reset_out,
|
||||
output reg reset_req
|
||||
);
|
||||
|
||||
// Always use async reset synchronizer if reset_req is used
|
||||
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
|
||||
|
||||
// --------------------------------------
|
||||
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
|
||||
// --------------------------------------
|
||||
localparam MIN_METASTABLE = 3;
|
||||
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
|
||||
|
||||
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
|
||||
|
||||
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
|
||||
MIN_RST_ASSERTION_TIME + 1 :
|
||||
(
|
||||
(MIN_RST_ASSERTION_TIME > LARGER)?
|
||||
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
|
||||
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
|
||||
);
|
||||
|
||||
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
|
||||
// --------------------------------------
|
||||
|
||||
wire merged_reset;
|
||||
wire merged_reset_req_in;
|
||||
wire reset_out_pre;
|
||||
reg reset_out_pre_reg;
|
||||
wire reset_req_pre;
|
||||
|
||||
// Registers and Interconnect
|
||||
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
|
||||
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
|
||||
reg r_sync_rst;
|
||||
reg r_early_rst;
|
||||
|
||||
// --------------------------------------
|
||||
// "Or" all the input resets together
|
||||
// --------------------------------------
|
||||
assign merged_reset = (
|
||||
reset_in0 |
|
||||
reset_in1 |
|
||||
reset_in2 |
|
||||
reset_in3 |
|
||||
reset_in4 |
|
||||
reset_in5 |
|
||||
reset_in6 |
|
||||
reset_in7 |
|
||||
reset_in8 |
|
||||
reset_in9 |
|
||||
reset_in10 |
|
||||
reset_in11 |
|
||||
reset_in12 |
|
||||
reset_in13 |
|
||||
reset_in14 |
|
||||
reset_in15
|
||||
);
|
||||
|
||||
assign merged_reset_req_in = (
|
||||
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
|
||||
);
|
||||
|
||||
|
||||
// --------------------------------------
|
||||
// And if required, synchronize it to the required clock domain,
|
||||
// with the correct synchronization type
|
||||
// --------------------------------------
|
||||
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
|
||||
|
||||
assign reset_out_pre = merged_reset;
|
||||
assign reset_req_pre = merged_reset_req_in;
|
||||
|
||||
end else begin
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
|
||||
)
|
||||
alt_rst_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset),
|
||||
.reset_out (reset_out_pre)
|
||||
);
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_req_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset_req_in),
|
||||
.reset_out (reset_req_pre)
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
|
||||
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
|
||||
always @* begin
|
||||
reset_out = reset_out_pre;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
|
||||
|
||||
wire reset_out_pre2;
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH+1),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_sync_uq2
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (reset_out_pre),
|
||||
.reset_out (reset_out_pre2)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
reset_out = reset_out_pre2;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
|
||||
end
|
||||
else begin
|
||||
|
||||
// 3-FF Metastability Synchronizer
|
||||
//synthesis translate_off
|
||||
initial
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
|
||||
end
|
||||
|
||||
// Synchronous reset pipe
|
||||
initial
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
//synthesis translate_on
|
||||
|
||||
always @(posedge clk or posedge reset_out_pre)
|
||||
begin
|
||||
if (reset_out_pre)
|
||||
reset_out_pre_reg <= 1'h1;
|
||||
else
|
||||
reset_out_pre_reg <= reset_out_pre;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
|
||||
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre_reg};
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
else
|
||||
begin
|
||||
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
|
||||
end
|
||||
end
|
||||
|
||||
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
|
||||
// matches the early input.
|
||||
if (OUTPUT_RESET_SYNC_EDGES != "deassert" ) begin
|
||||
always @(posedge clk)
|
||||
begin
|
||||
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
|
||||
3'b000: r_sync_rst <= 1'b0; // Not reset
|
||||
3'b001: r_sync_rst <= 1'b0;
|
||||
3'b010: r_sync_rst <= 1'b0;
|
||||
3'b011: r_sync_rst <= 1'b1;
|
||||
3'b100: r_sync_rst <= 1'b1;
|
||||
3'b101: r_sync_rst <= 1'b1;
|
||||
3'b110: r_sync_rst <= 1'b1;
|
||||
3'b111: r_sync_rst <= 1'b1; // In Reset
|
||||
default: r_sync_rst <= 1'b1;
|
||||
endcase
|
||||
|
||||
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
|
||||
2'b00: r_early_rst <= 1'b0; // Not reset
|
||||
2'b01: r_early_rst <= 1'b1; // Coming out of reset
|
||||
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
|
||||
2'b11: r_early_rst <= 1'b1; // Held in reset
|
||||
default: r_early_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk)
|
||||
begin
|
||||
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
|
||||
3'b000: r_sync_rst <= 1'b0; // Not reset
|
||||
3'b001: r_sync_rst <= 1'b0;
|
||||
3'b010: r_sync_rst <= 1'b0;
|
||||
3'b011: r_sync_rst <= 1'b1;
|
||||
3'b100: r_sync_rst <= 1'b1;
|
||||
3'b101: r_sync_rst <= 1'b1;
|
||||
3'b110: r_sync_rst <= 1'b1;
|
||||
3'b111: r_sync_rst <= 1'b1; // In Reset
|
||||
default: r_sync_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge reset_out_pre )
|
||||
begin
|
||||
if(reset_out_pre) begin
|
||||
r_early_rst <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
|
||||
2'b00: r_early_rst <= 1'b0; // Not reset
|
||||
2'b01: r_early_rst <= 1'b1; // Coming out of reset
|
||||
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
|
||||
2'b11: r_early_rst <= 1'b1; // Held in reset
|
||||
default: r_early_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @* begin
|
||||
reset_out = r_sync_rst;
|
||||
reset_req = r_early_rst;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZnnPJQ9GW+KzJV34fwWUvQ3dkA3L6G1Y5K7Msyidrmy1+Wu1L3OcWjX9FvtOw9qp2N3MEsh8d37Y/XaDWgwPKNC8qRv7AvhMJ8gFYwiLYTkPi1JGF8rlDOciOlSe0OOKsr8Qz81WHxnR038xpX6fIqkZWCweSvngUTKyauUaG3pcY+PLaI1oAcJ9eRym8kGs7+NwWcvmELdBMCucyRm52xLUprKDGjl1P42hAILSXrJXQndIyOW9vmm5Nz2evvj2gB7JvvzIfzZNuCdhnar89ChldW1j3A+Y5m6PjMM9pOU+Kdh26eGwj9fZZaPPrvl+VD5Hayq5zw3hzxXM33wd7ilCEvwS6rEk8Y9ZOslAUf74KejNArjekIHMmeFTx8aBtKMMm9wuP0WfEDxS4D7dDYDACm+FLX34qfxBjV7W/HokgwigFzSriqhaJqGkXLfN5+hTHkfsgDXx2KmN06gp1nCxVedTw83W3GZ0BDKFGGS0SrJDzge4q0Uk/lHtpo0n3W2FLL7TnG2r0QOY3YYnu0XSzCwIGa7WV4lIgGQ2UA+tiJkkVFL8zBqM6qqSx9ti08BQh/ob6g2E6CgPAuslJthgrG6/r1FvrY6mpyjO0c0vIAKswPchm+wB2Dx4+tBsnmX0peJXGJsrHXXjvrk52pzvpmXakJa2qerImbpknUXUBPR32Ek97/2wIEZ2iBp/jGeJDFttVPGoIXLHd4UgEdCmpFbUpZryi8bTJExus/YhIhp284WmXYOU22OgxwRtIPZ4CLG3lWeyiuxybU+R6eL"
|
||||
`endif
|
||||
+89
@@ -0,0 +1,89 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// -----------------------------------------------
|
||||
// Reset Synchronizer
|
||||
// -----------------------------------------------
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_synchronizer
|
||||
#(
|
||||
parameter ASYNC_RESET = 1,
|
||||
parameter DEPTH = 2
|
||||
)
|
||||
(
|
||||
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
|
||||
|
||||
input clk,
|
||||
output reset_out
|
||||
);
|
||||
|
||||
// -----------------------------------------------
|
||||
// Synchronizer register chain. We cannot reuse the
|
||||
// standard synchronizer in this implementation
|
||||
// because our timing constraints are different.
|
||||
//
|
||||
// Instead of cutting the timing path to the d-input
|
||||
// on the first flop we need to cut the aclr input.
|
||||
//
|
||||
// We omit the "preserve" attribute on the final
|
||||
// output register, so that the synthesis tool can
|
||||
// duplicate it where needed.
|
||||
// -----------------------------------------------
|
||||
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
|
||||
reg altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
generate if (ASYNC_RESET) begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert asynchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk or posedge reset_in) begin
|
||||
if (reset_in) begin
|
||||
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
|
||||
altera_reset_synchronizer_int_chain_out <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end else begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert synchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk) begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZm98qIL7ekOBsgi3Jk6JINlBn1MPss/MY/onstD48jcwiif8Gs4IWdQ2N3ArmvPwztGaa9pFUdrqFC/ySuZse43QXHTSLktppbb5RWP6kUriuoicmo6krAD1dbg/gJD2CPBniH3lvaXSbq4NXuXvaIi5JFjsHvqYH5AYGEBbEYIvX50OtmvM7MmdXWz8yMt/2x5MXTWbyba6bfKDJO6u5VlcHp85j3oXhLyoSx6ddNAgFJy9rjF3Z+u9E7PhkTCkebQtUzC8lIU9rG1+dwJE98atxbf1BPMRyiFcpFny635Ygt4p5jSQaXJnjSr6IUlFMLGpbYxPn1FcSkyMGPl2hZ7QtQENnQ3zejAwBl3Ze7ED8vOSzEBB93wGiKKZGd9hNwx5qeE0sgSNJa00qx6RLsg5tdDdzTo2bNXHlCtfYMIt2/YE75hzYCE//Zmb1mMx8nElfiU7/CpeYigjPvinVN5SqMGjIfMFWJasqdSm9Kw1UAN9s0LK8S6K3T1TGkHThOkJWDfpad7wvhxSkVJ99h9FdBLMlmkBYEwI/u/MKtNrzgKPsLz1FZ5EHB/JZti7aWbfhXQS1FoZYSLodk3NCTCmYgyghebDnmxCjIcHta/kmoyhMwLpM8ogUx6J3QA9oOxI+AvWy9A+id8Pj2XJjjQZxXzlg9JOVaXvn88zi6LVC88csY6kT+ANYw3OMfSjw9C2F6wme2VCibcI+DhqZCNXC41h1m9pqNYMUyyrBy5GMRZpEvb5yXb0+fS85rTPw4BgZkbkOxcmoA92mjOky5L"
|
||||
`endif
|
||||
+98
@@ -0,0 +1,98 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2013/09/09 $
|
||||
// $Author: dmunday $
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon Streaming Channel Adapter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a
|
||||
// in_channel_width: 0
|
||||
// in_max_channel: 0
|
||||
// out_channel_width: 8
|
||||
// out_max_channel: 255
|
||||
// data_width: 8
|
||||
// error_width: 0
|
||||
// use_ready: true
|
||||
// use_packets: true
|
||||
// use_empty: 0
|
||||
// empty_width: 0
|
||||
|
||||
// ------------------------------------------
|
||||
|
||||
// altera message_off 13469
|
||||
|
||||
module EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a
|
||||
(
|
||||
// Interface: in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [8-1: 0] in_data,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
// Interface: out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [8-1: 0] out_data,
|
||||
output reg [8-1: 0] out_channel,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
// Interface: clk
|
||||
input clk,
|
||||
// Interface: reset
|
||||
input reset_n
|
||||
|
||||
|
||||
);
|
||||
|
||||
wire in_channel;
|
||||
assign in_channel =0 ;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Payload Mapping
|
||||
// ---------------------------------------------------------------------
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = in_valid;
|
||||
out_data = in_data;
|
||||
out_startofpacket = in_startofpacket;
|
||||
out_endofpacket = in_endofpacket;
|
||||
|
||||
out_channel = 0;
|
||||
out_channel = in_channel;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
+101
@@ -0,0 +1,101 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2013/09/09 $
|
||||
// $Author: dmunday $
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon Streaming Channel Adapter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy
|
||||
// in_channel_width: 8
|
||||
// in_max_channel: 255
|
||||
// out_channel_width: 0
|
||||
// out_max_channel: 0
|
||||
// data_width: 8
|
||||
// error_width: 0
|
||||
// use_ready: true
|
||||
// use_packets: true
|
||||
// use_empty: 0
|
||||
// empty_width: 0
|
||||
|
||||
// ------------------------------------------
|
||||
|
||||
// altera message_off 13469
|
||||
|
||||
module EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy
|
||||
(
|
||||
// Interface: in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [8-1: 0] in_data,
|
||||
input [8-1: 0] in_channel,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
// Interface: out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [8-1: 0] out_data,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
// Interface: clk
|
||||
input clk,
|
||||
// Interface: reset
|
||||
input reset_n
|
||||
|
||||
|
||||
);
|
||||
|
||||
reg out_channel;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Payload Mapping
|
||||
// ---------------------------------------------------------------------
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = in_valid;
|
||||
out_data = in_data;
|
||||
out_startofpacket = in_startofpacket;
|
||||
out_endofpacket = in_endofpacket;
|
||||
|
||||
out_channel = in_channel; //TODO delete this to avoid Quartus warnings
|
||||
|
||||
// Suppress channels that are higher than the destination's max_channel.
|
||||
if (in_channel > 0) begin
|
||||
out_valid = 0;
|
||||
// Simulation Message goes here.
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
+98
@@ -0,0 +1,98 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2013/09/09 $
|
||||
// $Author: dmunday $
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon Streaming Channel Adapter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a
|
||||
// in_channel_width: 0
|
||||
// in_max_channel: 0
|
||||
// out_channel_width: 8
|
||||
// out_max_channel: 255
|
||||
// data_width: 8
|
||||
// error_width: 0
|
||||
// use_ready: true
|
||||
// use_packets: true
|
||||
// use_empty: 0
|
||||
// empty_width: 0
|
||||
|
||||
// ------------------------------------------
|
||||
|
||||
// altera message_off 13469
|
||||
|
||||
module EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a
|
||||
(
|
||||
// Interface: in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [8-1: 0] in_data,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
// Interface: out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [8-1: 0] out_data,
|
||||
output reg [8-1: 0] out_channel,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
// Interface: clk
|
||||
input clk,
|
||||
// Interface: reset
|
||||
input reset_n
|
||||
|
||||
|
||||
);
|
||||
|
||||
wire in_channel;
|
||||
assign in_channel =0 ;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Payload Mapping
|
||||
// ---------------------------------------------------------------------
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = in_valid;
|
||||
out_data = in_data;
|
||||
out_startofpacket = in_startofpacket;
|
||||
out_endofpacket = in_endofpacket;
|
||||
|
||||
out_channel = 0;
|
||||
out_channel = in_channel;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
+101
@@ -0,0 +1,101 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2013/09/09 $
|
||||
// $Author: dmunday $
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon Streaming Channel Adapter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy
|
||||
// in_channel_width: 8
|
||||
// in_max_channel: 255
|
||||
// out_channel_width: 0
|
||||
// out_max_channel: 0
|
||||
// data_width: 8
|
||||
// error_width: 0
|
||||
// use_ready: true
|
||||
// use_packets: true
|
||||
// use_empty: 0
|
||||
// empty_width: 0
|
||||
|
||||
// ------------------------------------------
|
||||
|
||||
// altera message_off 13469
|
||||
|
||||
module EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy
|
||||
(
|
||||
// Interface: in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [8-1: 0] in_data,
|
||||
input [8-1: 0] in_channel,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
// Interface: out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [8-1: 0] out_data,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
// Interface: clk
|
||||
input clk,
|
||||
// Interface: reset
|
||||
input reset_n
|
||||
|
||||
|
||||
);
|
||||
|
||||
reg out_channel;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Payload Mapping
|
||||
// ---------------------------------------------------------------------
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = in_valid;
|
||||
out_data = in_data;
|
||||
out_startofpacket = in_startofpacket;
|
||||
out_endofpacket = in_endofpacket;
|
||||
|
||||
out_channel = in_channel; //TODO delete this to avoid Quartus warnings
|
||||
|
||||
// Suppress channels that are higher than the destination's max_channel.
|
||||
if (in_channel > 0) begin
|
||||
out_valid = 0;
|
||||
// Simulation Message goes here.
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
+536
File diff suppressed because one or more lines are too long
+369
@@ -0,0 +1,369 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
// altera message_off 24541 13469
|
||||
module io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_arbitrator #(
|
||||
AMM_TO_AXIL_INTERCONNECT_ONLY = ""
|
||||
) (
|
||||
|
||||
input s0_axi4lite_clk,
|
||||
input s0_axi4lite_rst_n,
|
||||
|
||||
input [26:0] s0_axi4lite_awaddr,
|
||||
input [2:0] s0_axi4lite_awprot,
|
||||
input s0_axi4lite_awvalid,
|
||||
output s0_axi4lite_awready,
|
||||
input [31:0] s0_axi4lite_wdata,
|
||||
input [3:0] s0_axi4lite_wstrb,
|
||||
input s0_axi4lite_wvalid,
|
||||
output s0_axi4lite_wready,
|
||||
output [1:0] s0_axi4lite_bresp,
|
||||
output s0_axi4lite_bvalid,
|
||||
input s0_axi4lite_bready,
|
||||
input [26:0] s0_axi4lite_araddr,
|
||||
input [2:0] s0_axi4lite_arprot,
|
||||
input s0_axi4lite_arvalid,
|
||||
output s0_axi4lite_arready,
|
||||
output [31:0] s0_axi4lite_rdata,
|
||||
output [1:0] s0_axi4lite_rresp,
|
||||
output s0_axi4lite_rvalid,
|
||||
input s0_axi4lite_rready,
|
||||
|
||||
input [31:0] jamb_master_address,
|
||||
output [31:0] jamb_master_readdata,
|
||||
input jamb_master_read,
|
||||
input jamb_master_write,
|
||||
input [31:0] jamb_master_writedata,
|
||||
output jamb_master_waitrequest,
|
||||
output jamb_master_readdatavalid,
|
||||
input [3:0] jamb_master_byteenable,
|
||||
|
||||
output [26:0] cal_arch_0_s0_axi4lite_axi4_lite_awaddr,
|
||||
output [2:0] cal_arch_0_s0_axi4lite_axi4_lite_awprot,
|
||||
output cal_arch_0_s0_axi4lite_axi4_lite_awvalid,
|
||||
input cal_arch_0_s0_axi4lite_axi4_lite_awready,
|
||||
output [31:0] cal_arch_0_s0_axi4lite_axi4_lite_wdata,
|
||||
output [3:0] cal_arch_0_s0_axi4lite_axi4_lite_wstrb,
|
||||
output cal_arch_0_s0_axi4lite_axi4_lite_wvalid,
|
||||
input cal_arch_0_s0_axi4lite_axi4_lite_wready,
|
||||
input [1:0] cal_arch_0_s0_axi4lite_axi4_lite_bresp,
|
||||
input cal_arch_0_s0_axi4lite_axi4_lite_bvalid,
|
||||
output cal_arch_0_s0_axi4lite_axi4_lite_bready,
|
||||
output [26:0] cal_arch_0_s0_axi4lite_axi4_lite_araddr,
|
||||
output [2:0] cal_arch_0_s0_axi4lite_axi4_lite_arprot,
|
||||
output cal_arch_0_s0_axi4lite_axi4_lite_arvalid,
|
||||
input cal_arch_0_s0_axi4lite_axi4_lite_arready,
|
||||
input [31:0] cal_arch_0_s0_axi4lite_axi4_lite_rdata,
|
||||
input [1:0] cal_arch_0_s0_axi4lite_axi4_lite_rresp,
|
||||
input cal_arch_0_s0_axi4lite_axi4_lite_rvalid,
|
||||
output cal_arch_0_s0_axi4lite_axi4_lite_rready
|
||||
|
||||
);
|
||||
|
||||
|
||||
wire [31:0] mm_interconnect_0_arbit_s0_axi4lite_awaddr;
|
||||
wire [1:0] mm_interconnect_0_arbit_s0_axi4lite_bresp;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_arready;
|
||||
wire [31:0] mm_interconnect_0_arbit_s0_axi4lite_rdata;
|
||||
wire [3:0] mm_interconnect_0_arbit_s0_axi4lite_wstrb;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_wready;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_awready;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_rready;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_bready;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_wvalid;
|
||||
wire [31:0] mm_interconnect_0_arbit_s0_axi4lite_araddr;
|
||||
wire [2:0] mm_interconnect_0_arbit_s0_axi4lite_arprot;
|
||||
wire [1:0] mm_interconnect_0_arbit_s0_axi4lite_rresp;
|
||||
wire [2:0] mm_interconnect_0_arbit_s0_axi4lite_awprot;
|
||||
wire [31:0] mm_interconnect_0_arbit_s0_axi4lite_wdata;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_arvalid;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_bvalid;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_awvalid;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_rvalid;
|
||||
wire [31:0] arbit_m_axi4_ruser;
|
||||
wire [31:0] arbit_m_axi4_wuser;
|
||||
wire [1:0] arbit_m_axi4_awburst;
|
||||
wire [7:0] arbit_m_axi4_arlen;
|
||||
wire [3:0] arbit_m_axi4_arqos;
|
||||
wire [10:0] arbit_m_axi4_awuser;
|
||||
wire [31:0] arbit_m_axi4_wstrb;
|
||||
wire arbit_m_axi4_wready;
|
||||
wire [6:0] arbit_m_axi4_rid;
|
||||
wire arbit_m_axi4_rready;
|
||||
wire [7:0] arbit_m_axi4_awlen;
|
||||
wire [3:0] arbit_m_axi4_awqos;
|
||||
wire [31:0] arbit_m_axi4_araddr;
|
||||
wire arbit_m_axi4_wvalid;
|
||||
wire [2:0] arbit_m_axi4_arprot;
|
||||
wire arbit_m_axi4_arvalid;
|
||||
wire [2:0] arbit_m_axi4_awprot;
|
||||
wire [255:0] arbit_m_axi4_wdata;
|
||||
wire [6:0] arbit_m_axi4_arid;
|
||||
wire arbit_m_axi4_arlock;
|
||||
wire arbit_m_axi4_awlock;
|
||||
wire [31:0] arbit_m_axi4_awaddr;
|
||||
wire arbit_m_axi4_arready;
|
||||
wire [1:0] arbit_m_axi4_bresp;
|
||||
wire [255:0] arbit_m_axi4_rdata;
|
||||
wire [1:0] arbit_m_axi4_arburst;
|
||||
wire arbit_m_axi4_awready;
|
||||
wire [2:0] arbit_m_axi4_arsize;
|
||||
wire arbit_m_axi4_rlast;
|
||||
wire arbit_m_axi4_bready;
|
||||
wire arbit_m_axi4_wlast;
|
||||
wire [1:0] arbit_m_axi4_rresp;
|
||||
wire [6:0] arbit_m_axi4_awid;
|
||||
wire [6:0] arbit_m_axi4_bid;
|
||||
wire arbit_m_axi4_bvalid;
|
||||
wire [10:0] arbit_m_axi4_aruser;
|
||||
wire arbit_m_axi4_rvalid;
|
||||
wire [2:0] arbit_m_axi4_awsize;
|
||||
wire arbit_m_axi4_awvalid;
|
||||
|
||||
altera_reset_synchronizer #(
|
||||
.DEPTH (2),
|
||||
.ASYNC_RESET(0)
|
||||
) reset_sync (
|
||||
.clk (s0_axi4lite_clk),
|
||||
.reset_in (~s0_axi4lite_rst_n),
|
||||
.reset_out (s0_axi4lite_rst_sync)
|
||||
);
|
||||
|
||||
ed_synth_dut_altera_mm_interconnect_1920_jmzr6ly mm_interconnect_0 (
|
||||
.jamb_master_address (jamb_master_address),
|
||||
.jamb_master_waitrequest (jamb_master_waitrequest),
|
||||
.jamb_master_byteenable (jamb_master_byteenable),
|
||||
.jamb_master_read (jamb_master_read),
|
||||
.jamb_master_readdata (jamb_master_readdata),
|
||||
.jamb_master_readdatavalid (jamb_master_readdatavalid),
|
||||
.jamb_master_write (jamb_master_write),
|
||||
.jamb_master_writedata (jamb_master_writedata),
|
||||
.arbit_s0_axi4lite_awaddr (mm_interconnect_0_arbit_s0_axi4lite_awaddr),
|
||||
.arbit_s0_axi4lite_awprot (mm_interconnect_0_arbit_s0_axi4lite_awprot),
|
||||
.arbit_s0_axi4lite_awvalid (mm_interconnect_0_arbit_s0_axi4lite_awvalid),
|
||||
.arbit_s0_axi4lite_awready (mm_interconnect_0_arbit_s0_axi4lite_awready),
|
||||
.arbit_s0_axi4lite_wdata (mm_interconnect_0_arbit_s0_axi4lite_wdata),
|
||||
.arbit_s0_axi4lite_wstrb (mm_interconnect_0_arbit_s0_axi4lite_wstrb),
|
||||
.arbit_s0_axi4lite_wvalid (mm_interconnect_0_arbit_s0_axi4lite_wvalid),
|
||||
.arbit_s0_axi4lite_wready (mm_interconnect_0_arbit_s0_axi4lite_wready),
|
||||
.arbit_s0_axi4lite_bresp (mm_interconnect_0_arbit_s0_axi4lite_bresp),
|
||||
.arbit_s0_axi4lite_bvalid (mm_interconnect_0_arbit_s0_axi4lite_bvalid),
|
||||
.arbit_s0_axi4lite_bready (mm_interconnect_0_arbit_s0_axi4lite_bready),
|
||||
.arbit_s0_axi4lite_araddr (mm_interconnect_0_arbit_s0_axi4lite_araddr),
|
||||
.arbit_s0_axi4lite_arprot (mm_interconnect_0_arbit_s0_axi4lite_arprot),
|
||||
.arbit_s0_axi4lite_arvalid (mm_interconnect_0_arbit_s0_axi4lite_arvalid),
|
||||
.arbit_s0_axi4lite_arready (mm_interconnect_0_arbit_s0_axi4lite_arready),
|
||||
.arbit_s0_axi4lite_rdata (mm_interconnect_0_arbit_s0_axi4lite_rdata),
|
||||
.arbit_s0_axi4lite_rresp (mm_interconnect_0_arbit_s0_axi4lite_rresp),
|
||||
.arbit_s0_axi4lite_rvalid (mm_interconnect_0_arbit_s0_axi4lite_rvalid),
|
||||
.arbit_s0_axi4lite_rready (mm_interconnect_0_arbit_s0_axi4lite_rready),
|
||||
.arbit_s0_axi4lite_aresetn_reset_bridge_in_reset_reset (s0_axi4lite_rst_sync),
|
||||
.jamb_master_translator_reset_reset_bridge_in_reset_reset (s0_axi4lite_rst_sync),
|
||||
.clk_bridge_out_clk_clk (s0_axi4lite_clk),
|
||||
.clk_bridge_out_clk_3_clk (s0_axi4lite_clk)
|
||||
);
|
||||
|
||||
|
||||
|
||||
generate
|
||||
if (!AMM_TO_AXIL_INTERCONNECT_ONLY) begin: gen_arbit
|
||||
ed_synth_dut_intel_axi4lite_injector_100_2yowc3a #(
|
||||
.NUM_ACTIVE_AXI4LITE_S_INTERFACES (2),
|
||||
.AXI4LITE_QOS (0),
|
||||
.NUM_ACTIVE_AXI4_S_INTERFACES (0),
|
||||
.BUFFER_AXI4_S_READ_RESPONSES (0),
|
||||
.AXI4_S_TRANSFER_MULTIPLE (9),
|
||||
.INIU_AXI4_ADDR_WIDTH (32)
|
||||
) arbit (
|
||||
.m_axi4_aclk (s0_axi4lite_clk),
|
||||
.m_axi4_aresetn (~s0_axi4lite_rst_sync),
|
||||
.m_axi4_arid (arbit_m_axi4_arid),
|
||||
.m_axi4_araddr (arbit_m_axi4_araddr),
|
||||
.m_axi4_arlen (arbit_m_axi4_arlen),
|
||||
.m_axi4_arsize (arbit_m_axi4_arsize),
|
||||
.m_axi4_arburst (arbit_m_axi4_arburst),
|
||||
.m_axi4_arlock (arbit_m_axi4_arlock),
|
||||
.m_axi4_arprot (arbit_m_axi4_arprot),
|
||||
.m_axi4_arqos (arbit_m_axi4_arqos),
|
||||
.m_axi4_aruser (arbit_m_axi4_aruser),
|
||||
.m_axi4_arvalid (arbit_m_axi4_arvalid),
|
||||
.m_axi4_arready (arbit_m_axi4_arready),
|
||||
.m_axi4_rid (arbit_m_axi4_rid),
|
||||
.m_axi4_rdata (arbit_m_axi4_rdata),
|
||||
.m_axi4_rresp (arbit_m_axi4_rresp),
|
||||
.m_axi4_rlast (arbit_m_axi4_rlast),
|
||||
.m_axi4_ruser (arbit_m_axi4_ruser),
|
||||
.m_axi4_rvalid (arbit_m_axi4_rvalid),
|
||||
.m_axi4_rready (arbit_m_axi4_rready),
|
||||
.m_axi4_awid (arbit_m_axi4_awid),
|
||||
.m_axi4_awaddr (arbit_m_axi4_awaddr),
|
||||
.m_axi4_awlen (arbit_m_axi4_awlen),
|
||||
.m_axi4_awsize (arbit_m_axi4_awsize),
|
||||
.m_axi4_awburst (arbit_m_axi4_awburst),
|
||||
.m_axi4_awlock (arbit_m_axi4_awlock),
|
||||
.m_axi4_awprot (arbit_m_axi4_awprot),
|
||||
.m_axi4_awqos (arbit_m_axi4_awqos),
|
||||
.m_axi4_awuser (arbit_m_axi4_awuser),
|
||||
.m_axi4_awvalid (arbit_m_axi4_awvalid),
|
||||
.m_axi4_awready (arbit_m_axi4_awready),
|
||||
.m_axi4_wdata (arbit_m_axi4_wdata),
|
||||
.m_axi4_wstrb (arbit_m_axi4_wstrb),
|
||||
.m_axi4_wlast (arbit_m_axi4_wlast),
|
||||
.m_axi4_wuser (arbit_m_axi4_wuser),
|
||||
.m_axi4_wvalid (arbit_m_axi4_wvalid),
|
||||
.m_axi4_wready (arbit_m_axi4_wready),
|
||||
.m_axi4_bid (arbit_m_axi4_bid),
|
||||
.m_axi4_bresp (arbit_m_axi4_bresp),
|
||||
.m_axi4_bvalid (arbit_m_axi4_bvalid),
|
||||
.m_axi4_bready (arbit_m_axi4_bready),
|
||||
.s0_axi4lite_aclk (s0_axi4lite_clk),
|
||||
.s0_axi4lite_aresetn (~s0_axi4lite_rst_sync),
|
||||
.s0_axi4lite_awaddr (mm_interconnect_0_arbit_s0_axi4lite_awaddr),
|
||||
.s0_axi4lite_awvalid (mm_interconnect_0_arbit_s0_axi4lite_awvalid),
|
||||
.s0_axi4lite_awready (mm_interconnect_0_arbit_s0_axi4lite_awready),
|
||||
.s0_axi4lite_wdata (mm_interconnect_0_arbit_s0_axi4lite_wdata),
|
||||
.s0_axi4lite_wstrb (mm_interconnect_0_arbit_s0_axi4lite_wstrb),
|
||||
.s0_axi4lite_wvalid (mm_interconnect_0_arbit_s0_axi4lite_wvalid),
|
||||
.s0_axi4lite_wready (mm_interconnect_0_arbit_s0_axi4lite_wready),
|
||||
.s0_axi4lite_bresp (mm_interconnect_0_arbit_s0_axi4lite_bresp),
|
||||
.s0_axi4lite_bvalid (mm_interconnect_0_arbit_s0_axi4lite_bvalid),
|
||||
.s0_axi4lite_bready (mm_interconnect_0_arbit_s0_axi4lite_bready),
|
||||
.s0_axi4lite_araddr (mm_interconnect_0_arbit_s0_axi4lite_araddr),
|
||||
.s0_axi4lite_arvalid (mm_interconnect_0_arbit_s0_axi4lite_arvalid),
|
||||
.s0_axi4lite_arready (mm_interconnect_0_arbit_s0_axi4lite_arready),
|
||||
.s0_axi4lite_rdata (mm_interconnect_0_arbit_s0_axi4lite_rdata),
|
||||
.s0_axi4lite_rresp (mm_interconnect_0_arbit_s0_axi4lite_rresp),
|
||||
.s0_axi4lite_rvalid (mm_interconnect_0_arbit_s0_axi4lite_rvalid),
|
||||
.s0_axi4lite_rready (mm_interconnect_0_arbit_s0_axi4lite_rready),
|
||||
.s0_axi4lite_awprot (mm_interconnect_0_arbit_s0_axi4lite_awprot),
|
||||
.s0_axi4lite_arprot (mm_interconnect_0_arbit_s0_axi4lite_arprot),
|
||||
.s1_axi4lite_aclk (s0_axi4lite_clk),
|
||||
.s1_axi4lite_aresetn (~s0_axi4lite_rst_sync),
|
||||
.s1_axi4lite_awaddr (s0_axi4lite_awaddr),
|
||||
.s1_axi4lite_awvalid (s0_axi4lite_awvalid),
|
||||
.s1_axi4lite_awready (s0_axi4lite_awready),
|
||||
.s1_axi4lite_wdata (s0_axi4lite_wdata),
|
||||
.s1_axi4lite_wstrb (s0_axi4lite_wstrb),
|
||||
.s1_axi4lite_wvalid (s0_axi4lite_wvalid),
|
||||
.s1_axi4lite_wready (s0_axi4lite_wready),
|
||||
.s1_axi4lite_bresp (s0_axi4lite_bresp),
|
||||
.s1_axi4lite_bvalid (s0_axi4lite_bvalid),
|
||||
.s1_axi4lite_bready (s0_axi4lite_bready),
|
||||
.s1_axi4lite_araddr (s0_axi4lite_araddr),
|
||||
.s1_axi4lite_arvalid (s0_axi4lite_arvalid),
|
||||
.s1_axi4lite_arready (s0_axi4lite_arready),
|
||||
.s1_axi4lite_rdata (s0_axi4lite_rdata),
|
||||
.s1_axi4lite_rresp (s0_axi4lite_rresp),
|
||||
.s1_axi4lite_rvalid (s0_axi4lite_rvalid),
|
||||
.s1_axi4lite_rready (s0_axi4lite_rready),
|
||||
.s1_axi4lite_awprot (s0_axi4lite_awprot),
|
||||
.s1_axi4lite_arprot (s0_axi4lite_arprot)
|
||||
);
|
||||
|
||||
ed_synth_dut_altera_mm_interconnect_1920_5sovoyi mm_interconnect_1 (
|
||||
.arbit_m_axi4_awid (arbit_m_axi4_awid),
|
||||
.arbit_m_axi4_awaddr (arbit_m_axi4_awaddr),
|
||||
.arbit_m_axi4_awlen (arbit_m_axi4_awlen),
|
||||
.arbit_m_axi4_awsize (arbit_m_axi4_awsize),
|
||||
.arbit_m_axi4_awburst (arbit_m_axi4_awburst),
|
||||
.arbit_m_axi4_awlock (arbit_m_axi4_awlock),
|
||||
.arbit_m_axi4_awprot (arbit_m_axi4_awprot),
|
||||
.arbit_m_axi4_awuser (arbit_m_axi4_awuser),
|
||||
.arbit_m_axi4_awqos (arbit_m_axi4_awqos),
|
||||
.arbit_m_axi4_awvalid (arbit_m_axi4_awvalid),
|
||||
.arbit_m_axi4_awready (arbit_m_axi4_awready),
|
||||
.arbit_m_axi4_wdata (arbit_m_axi4_wdata),
|
||||
.arbit_m_axi4_wstrb (arbit_m_axi4_wstrb),
|
||||
.arbit_m_axi4_wlast (arbit_m_axi4_wlast),
|
||||
.arbit_m_axi4_wvalid (arbit_m_axi4_wvalid),
|
||||
.arbit_m_axi4_wuser (arbit_m_axi4_wuser),
|
||||
.arbit_m_axi4_wready (arbit_m_axi4_wready),
|
||||
.arbit_m_axi4_bid (arbit_m_axi4_bid),
|
||||
.arbit_m_axi4_bresp (arbit_m_axi4_bresp),
|
||||
.arbit_m_axi4_bvalid (arbit_m_axi4_bvalid),
|
||||
.arbit_m_axi4_bready (arbit_m_axi4_bready),
|
||||
.arbit_m_axi4_arid (arbit_m_axi4_arid),
|
||||
.arbit_m_axi4_araddr (arbit_m_axi4_araddr),
|
||||
.arbit_m_axi4_arlen (arbit_m_axi4_arlen),
|
||||
.arbit_m_axi4_arsize (arbit_m_axi4_arsize),
|
||||
.arbit_m_axi4_arburst (arbit_m_axi4_arburst),
|
||||
.arbit_m_axi4_arlock (arbit_m_axi4_arlock),
|
||||
.arbit_m_axi4_arprot (arbit_m_axi4_arprot),
|
||||
.arbit_m_axi4_aruser (arbit_m_axi4_aruser),
|
||||
.arbit_m_axi4_arqos (arbit_m_axi4_arqos),
|
||||
.arbit_m_axi4_arvalid (arbit_m_axi4_arvalid),
|
||||
.arbit_m_axi4_arready (arbit_m_axi4_arready),
|
||||
.arbit_m_axi4_rid (arbit_m_axi4_rid),
|
||||
.arbit_m_axi4_rdata (arbit_m_axi4_rdata),
|
||||
.arbit_m_axi4_rresp (arbit_m_axi4_rresp),
|
||||
.arbit_m_axi4_rlast (arbit_m_axi4_rlast),
|
||||
.arbit_m_axi4_rvalid (arbit_m_axi4_rvalid),
|
||||
.arbit_m_axi4_rready (arbit_m_axi4_rready),
|
||||
.arbit_m_axi4_ruser (arbit_m_axi4_ruser),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_awaddr (cal_arch_0_s0_axi4lite_axi4_lite_awaddr),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_awprot (cal_arch_0_s0_axi4lite_axi4_lite_awprot),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_awvalid (cal_arch_0_s0_axi4lite_axi4_lite_awvalid),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_awready (cal_arch_0_s0_axi4lite_axi4_lite_awready),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_wdata (cal_arch_0_s0_axi4lite_axi4_lite_wdata),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_wstrb (cal_arch_0_s0_axi4lite_axi4_lite_wstrb),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_wvalid (cal_arch_0_s0_axi4lite_axi4_lite_wvalid),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_wready (cal_arch_0_s0_axi4lite_axi4_lite_wready),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_bresp (cal_arch_0_s0_axi4lite_axi4_lite_bresp),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_bvalid (cal_arch_0_s0_axi4lite_axi4_lite_bvalid),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_bready (cal_arch_0_s0_axi4lite_axi4_lite_bready),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_araddr (cal_arch_0_s0_axi4lite_axi4_lite_araddr),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_arprot (cal_arch_0_s0_axi4lite_axi4_lite_arprot),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_arvalid (cal_arch_0_s0_axi4lite_axi4_lite_arvalid),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_arready (cal_arch_0_s0_axi4lite_axi4_lite_arready),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_rdata (cal_arch_0_s0_axi4lite_axi4_lite_rdata),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_rresp (cal_arch_0_s0_axi4lite_axi4_lite_rresp),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_rvalid (cal_arch_0_s0_axi4lite_axi4_lite_rvalid),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_rready (cal_arch_0_s0_axi4lite_axi4_lite_rready),
|
||||
.arbit_m_axi4_aresetn_reset_bridge_in_reset_reset (s0_axi4lite_rst_sync),
|
||||
.cal_arch_0_s0_axi4lite_rst_n_reset_bridge_in_reset_reset (s0_axi4lite_rst_sync),
|
||||
.clk_bridge_out_clk_2_clk (s0_axi4lite_clk),
|
||||
.clk_bridge_out_clk_1_clk (s0_axi4lite_clk)
|
||||
);
|
||||
|
||||
end else begin: gen_connect_axil_output_intf
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_awaddr = mm_interconnect_0_arbit_s0_axi4lite_awaddr;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_awprot = mm_interconnect_0_arbit_s0_axi4lite_awprot;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_awvalid = mm_interconnect_0_arbit_s0_axi4lite_awvalid;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_awready = cal_arch_0_s0_axi4lite_axi4_lite_awready;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_wdata = mm_interconnect_0_arbit_s0_axi4lite_wdata;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_wstrb = mm_interconnect_0_arbit_s0_axi4lite_wstrb;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_wvalid = mm_interconnect_0_arbit_s0_axi4lite_wvalid;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_wready = cal_arch_0_s0_axi4lite_axi4_lite_wready;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_bresp = cal_arch_0_s0_axi4lite_axi4_lite_bresp;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_bvalid = cal_arch_0_s0_axi4lite_axi4_lite_bvalid;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_bready = mm_interconnect_0_arbit_s0_axi4lite_bready;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_araddr = mm_interconnect_0_arbit_s0_axi4lite_araddr;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_arprot = mm_interconnect_0_arbit_s0_axi4lite_arprot;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_arvalid = mm_interconnect_0_arbit_s0_axi4lite_arvalid;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_arready = cal_arch_0_s0_axi4lite_axi4_lite_arready;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_rdata = cal_arch_0_s0_axi4lite_axi4_lite_rdata;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_rresp = cal_arch_0_s0_axi4lite_axi4_lite_rresp;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_rvalid = cal_arch_0_s0_axi4lite_axi4_lite_rvalid;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_rready = mm_interconnect_0_arbit_s0_axi4lite_rready;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
module cal_arch_fp_atom_inst_comp #(
|
||||
parameter IS_USED = 0,
|
||||
|
||||
parameter BASE_ADDRESS = 0,
|
||||
|
||||
localparam PORT_I_AVM_ADDRESS_WIDTH = 22,
|
||||
localparam PORT_I_AVM_WRITEDATA_WIDTH = 32,
|
||||
localparam PORT_O_AVM_READDATA_COMP_WIDTH = 32
|
||||
) (
|
||||
);
|
||||
timeunit 1ns;
|
||||
timeprecision 1ps;
|
||||
|
||||
logic avm_clk;
|
||||
logic avm_rst_n;
|
||||
logic [PORT_I_AVM_ADDRESS_WIDTH-1:0] i_avm_address;
|
||||
logic i_avm_read;
|
||||
logic i_avm_write;
|
||||
logic [PORT_I_AVM_WRITEDATA_WIDTH-1:0] i_avm_writedata;
|
||||
logic [PORT_O_AVM_READDATA_COMP_WIDTH-1:0] o_avm_readdata_comp;
|
||||
|
||||
tennm_compensation_block # (
|
||||
.base_address (BASE_ADDRESS)
|
||||
) comp (
|
||||
.avm_clk (avm_clk),
|
||||
.avm_rst_n (avm_rst_n),
|
||||
.i_avm_address (i_avm_address),
|
||||
.i_avm_read (i_avm_read),
|
||||
.i_avm_write (i_avm_write),
|
||||
.i_avm_writedata (i_avm_writedata),
|
||||
.o_avm_readdata_comp (o_avm_readdata_comp)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc9h3nWj04w/zCV+gxx1kFjPwr42c+wh9viQCcXe8AdUB+HG9kFmXLWB4teTAazeuYuyNN3cihTIPcdr6lIWE/4KmE4wPDHe1eUH8M1N4QnHBz1/623ugjhsPacmVcSgQCPcfXVtRrkty7jsn7mPRzqlvVuwhm/DBR+rATS3FHAql0W79WgG+4ojlEuu8R4oxRnMIwCs8wqdQMkxqU2gAo4z9UCTK3rRHjhZpykFv1h1DcwSCfV6L8niZh0au+/9WClx5hwgB9usGkdmNOOy4bfIQd6xkLnhzQV0CWpRFqyEW4+z59T3U8x0yETuXqBgXiCQAcpSvymtFtmhcYT1B3kbnhgmuw80H0sa4d4bCgQm3XuAQMnalCzAIu7g5sVV1Idf+za3/k8/MHu+fd0nDmd6cKAw4qTAdVQRIia2Ck4t395Ogknb+wUZ4C+7f+6kkwbTg/062nCIm6mivxfsP2NARo0ZjAMJFREWqoagsfovx33ejk+gM54L5eFupLAwFJlCzISw8+vrrlk0Uy/+oQKzE9RnHu+Afr4H8WeHoX4qyC3wopUliQxeN9/TeS10EJl7lEdY8yY5xfxthnF77iLdyE51Y3MxGmtM0Gi/wZKiM5CfoJO6+V4tGToSAXiVQYPr8C/sXuhA0loNp/B1bTYUExmP0H8tM+f4S4sshkb6AvdE/FEQiYKdo0V5tP3dTFsP7bHGTpGXOnaJaASn2CuzvVqoh44/+OxtyPmncQlMNwBNR+ot6UuXkqaGhS4146I6Rc1QmlxqiUm9Npy8Dj9+"
|
||||
`endif
|
||||
+61
@@ -0,0 +1,61 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
module stdfn_inst_fa_c2p_ssm #(
|
||||
parameter IS_USED = 0,
|
||||
|
||||
parameter SSM_C2P_DATA_MODE = "SSM_C2P_DATA_MODE_BYPASS",
|
||||
parameter FA_CORE_PERIPH_CLK_SEL_DATA_MODE = "FA_CORE_PERIPH_CLK_SEL_DATA_MODE_UNUSED",
|
||||
parameter SSM_P2C_DATA_MODE = "SSM_P2C_DATA_MODE_BYPASS",
|
||||
localparam PORT_I_SSM_C2P_WIDTH = 40,
|
||||
localparam PORT_O_SSM_C2P_WIDTH = 40,
|
||||
localparam PORT_I_SSM_P2C_WIDTH = 20,
|
||||
localparam PORT_O_SSM_P2C_WIDTH = 20
|
||||
) (
|
||||
input i_core_clk,
|
||||
input [PORT_I_SSM_C2P_WIDTH-1:0] i_ssm_c2p,
|
||||
output [PORT_O_SSM_C2P_WIDTH-1:0] o_ssm_c2p,
|
||||
input i_phy_clk_fr,
|
||||
input i_phy_clk_sync,
|
||||
input [PORT_I_SSM_P2C_WIDTH-1:0] i_ssm_p2c,
|
||||
output [PORT_O_SSM_P2C_WIDTH-1:0] o_ssm_p2c
|
||||
);
|
||||
timeunit 1ns;
|
||||
timeprecision 1ps;
|
||||
|
||||
tennm_ssm_c2p_fabric_adaptor # (
|
||||
.ssm_c2p_data_mode (SSM_C2P_DATA_MODE),
|
||||
.fa_core_periph_clk_sel_data_mode (FA_CORE_PERIPH_CLK_SEL_DATA_MODE)
|
||||
) fa_c2p_ssm (
|
||||
.i_core_clk (i_core_clk),
|
||||
.i_phy_clk_fr (i_phy_clk_fr),
|
||||
.i_phy_clk_sync (i_phy_clk_sync),
|
||||
.i_ssm_c2p (i_ssm_c2p),
|
||||
.o_ssm_c2p (o_ssm_c2p)
|
||||
);
|
||||
tennm_ssm_p2c_fabric_adaptor # (
|
||||
.ssm_p2c_data_mode (SSM_P2C_DATA_MODE),
|
||||
.fa_core_periph_clk_sel_data_mode (FA_CORE_PERIPH_CLK_SEL_DATA_MODE)
|
||||
) fa_p2c_ssm (
|
||||
.i_core_clk (i_core_clk),
|
||||
.i_phy_clk_fr (i_phy_clk_fr),
|
||||
.i_phy_clk_sync (i_phy_clk_sync),
|
||||
.i_ssm_p2c (i_ssm_p2c),
|
||||
.o_ssm_p2c (o_ssm_p2c)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc+96bwJRyKwPdrMtYSy7m+X0yzYshDLSxe/WLUb3qsczNZaIWpknYTeedvLKw/e1EnLil9SSlUaAB9RYBjO5BB6xCFjoi9OwEQ0Q52WST0YiB57jUOsXiyNw/1ZUY8o0YzYGzlvDXM1ty7Hn3WnJYLW1WfdBDwhyLWR1/cYX+VG7FQYJxHGlb6SN+stmztbJjnrLUj8iBoLZL+F0l5Ote0peaY0j2vY6Xv/RY2IqJsmpi1/LjrikCDY9fQjkplfr2oCqChH+5qZ+O/Ejg/hKXGxp8quekqCzbplbwa7ZY/oG3h5WhybqEhOz6R0f4UOfGoKHxTFyzuAS6htuJ9YLiBE/ZqaGWbe4S+UmGSEizMJHAmT3ZbwuyWUKqp1AvHI6WqE/hXRI6LI/3+4MaoMTern7Fy27oP8lexuJUK45PT6Mtoy/sD+ZFFP2fG2S72m7Gi9U+4EmXdAYvwVbpoesy+GrvcCBuMN6XlN2PH3XwI5kLMSLbLydOfpe1KRIMeDxktajCoUk3HKgQDT+2L/MWk9/2Pb90MRKAhGT2Ek8QmTo1w/XNHV/Z5mDb2mxm1G0YrQSyUApISqnrANcd6OC/VxLYDUhXU2Sl9KGrF+maS05FaWKomFRC8NiWqZEOYZMi/LpLbEJQLd+Jh+h+CHSTMdntEuCr2hlAJJFq9pYzFMsAOkPRW+5BpBjHCmyVxtDLpdyMXF2tnfV5qPSoO+QEbtX1HgCGMofqg38PyKPy/nsFfpcY59ZK2uphMWteiELe5CwrAxqoOFPyhYhEXkZoAz"
|
||||
`endif
|
||||
+301
@@ -0,0 +1,301 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
module io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_stdfn_inst_iossm #(
|
||||
|
||||
localparam PORT_AXIL_ARADDR_WIDTH = 27,
|
||||
localparam PORT_AXIL_AWADDR_WIDTH = 27,
|
||||
localparam PORT_AXIL_BRESP_WIDTH = 2,
|
||||
localparam PORT_AXIL_RDATA_WIDTH = 32,
|
||||
localparam PORT_AXIL_RRESP_WIDTH = 2,
|
||||
localparam PORT_AXIL_WDATA_WIDTH = 32,
|
||||
localparam PORT_AXIL_WSTRB_WIDTH = 4,
|
||||
localparam PORT_CALBUS0_ADDR_WIDTH = 22,
|
||||
localparam PORT_CALBUS0_READDATA_WIDTH = 32,
|
||||
localparam PORT_CALBUS0_WRITEDATA_WIDTH = 32,
|
||||
localparam PORT_HADDR_WIDTH = 16,
|
||||
localparam PORT_HBURST_WIDTH = 3,
|
||||
localparam PORT_HSIZE_WIDTH = 3,
|
||||
localparam PORT_HTRANS_WIDTH = 2,
|
||||
localparam PORT_HWDATA_WIDTH = 32,
|
||||
localparam PORT_IOFBRADAPT_SSM_C2P_WIDTH = 31,
|
||||
localparam PORT_IOFBRADAPT_SSM_P2C_WIDTH = 8,
|
||||
localparam PORT_I_SIM_PARAM_TABLE_WIDTH = 16384,
|
||||
localparam PORT_MC_HRDATA_WIDTH = 32,
|
||||
localparam PORT_MC_HRESP_WIDTH = 2
|
||||
|
||||
) (
|
||||
input [PORT_AXIL_ARADDR_WIDTH-1:0] axil_araddr,
|
||||
output axil_arready,
|
||||
input axil_arvalid,
|
||||
input [PORT_AXIL_AWADDR_WIDTH-1:0] axil_awaddr,
|
||||
output axil_awready,
|
||||
input axil_awvalid,
|
||||
input axil_bready,
|
||||
output [PORT_AXIL_BRESP_WIDTH-1:0] axil_bresp,
|
||||
output axil_bvalid,
|
||||
output axil_clk,
|
||||
output [PORT_AXIL_RDATA_WIDTH-1:0] axil_rdata,
|
||||
input axil_rready,
|
||||
output [PORT_AXIL_RRESP_WIDTH-1:0] axil_rresp,
|
||||
output axil_rvalid,
|
||||
input [PORT_AXIL_WDATA_WIDTH-1:0] axil_wdata,
|
||||
output axil_wready,
|
||||
input [PORT_AXIL_WSTRB_WIDTH-1:0] axil_wstrb,
|
||||
input axil_wvalid,
|
||||
|
||||
input c2p_clk,
|
||||
|
||||
output [PORT_CALBUS0_ADDR_WIDTH-1:0] calbus0_addr,
|
||||
output calbus0_clock,
|
||||
output calbus0_read,
|
||||
input [PORT_CALBUS0_READDATA_WIDTH-1:0] calbus0_readdata,
|
||||
output calbus0_rst_n,
|
||||
output calbus0_write,
|
||||
output [PORT_CALBUS0_WRITEDATA_WIDTH-1:0] calbus0_writedata,
|
||||
|
||||
output clk_en_in,
|
||||
|
||||
output [PORT_HADDR_WIDTH-1:0] haddr,
|
||||
output [PORT_HBURST_WIDTH-1:0] hburst,
|
||||
output hclk,
|
||||
output hready,
|
||||
output hresetn,
|
||||
output hsel,
|
||||
output [PORT_HSIZE_WIDTH-1:0] hsize,
|
||||
output [PORT_HTRANS_WIDTH-1:0] htrans,
|
||||
output [PORT_HWDATA_WIDTH-1:0] hwdata,
|
||||
output hwrite,
|
||||
input [PORT_MC_HRDATA_WIDTH-1:0] mc0_hrdata,
|
||||
input mc0_hreadyout,
|
||||
input [PORT_MC_HRESP_WIDTH-1:0] mc0_hresp,
|
||||
input [PORT_MC_HRDATA_WIDTH-1:0] mc1_hrdata,
|
||||
input mc1_hreadyout,
|
||||
input [PORT_MC_HRESP_WIDTH-1:0] mc1_hresp,
|
||||
|
||||
input [PORT_I_SIM_PARAM_TABLE_WIDTH-1:0] i_sim_param_table_0,
|
||||
input [PORT_I_SIM_PARAM_TABLE_WIDTH-1:0] i_sim_param_table_1,
|
||||
input mc0_irq,
|
||||
input mc1_irq,
|
||||
output mc0_rst_n,
|
||||
output mc1_rst_n,
|
||||
|
||||
output i3c_scl,
|
||||
output i3c_sda_dr_en_n,
|
||||
output i3c_sda_pp,
|
||||
input i3c_sda_rx,
|
||||
output i3c_sda_tx,
|
||||
|
||||
input [PORT_IOFBRADAPT_SSM_C2P_WIDTH-1:0] iofbradapt_ssm_c2p,
|
||||
output [PORT_IOFBRADAPT_SSM_P2C_WIDTH-1:0] iofbradapt_ssm_p2c
|
||||
);
|
||||
timeunit 1ns;
|
||||
timeprecision 1ps;
|
||||
import io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_iossm::*;
|
||||
|
||||
tennm_ph2_iossm # (
|
||||
.iossm_mem_init_onekb_hexfile (IOSSM_MEM_INIT_ONEKB_HEXFILE),
|
||||
.iossm_mem_init_onekb (IOSSM_MEM_INIT_ONEKB),
|
||||
.iossm_mem_init_hexfile (IOSSM_MEM_INIT_HEXFILE),
|
||||
.iossm_mem_init_99 (IOSSM_MEM_INIT_UPPER[99-64]),
|
||||
.iossm_mem_init_98 (IOSSM_MEM_INIT_UPPER[98-64]),
|
||||
.iossm_mem_init_97 (IOSSM_MEM_INIT_UPPER[97-64]),
|
||||
.iossm_mem_init_96 (IOSSM_MEM_INIT_UPPER[96-64]),
|
||||
.iossm_mem_init_95 (IOSSM_MEM_INIT_UPPER[95-64]),
|
||||
.iossm_mem_init_94 (IOSSM_MEM_INIT_UPPER[94-64]),
|
||||
.iossm_mem_init_93 (IOSSM_MEM_INIT_UPPER[93-64]),
|
||||
.iossm_mem_init_92 (IOSSM_MEM_INIT_UPPER[92-64]),
|
||||
.iossm_mem_init_91 (IOSSM_MEM_INIT_UPPER[91-64]),
|
||||
.iossm_mem_init_90 (IOSSM_MEM_INIT_UPPER[90-64]),
|
||||
.iossm_mem_init_9 (IOSSM_MEM_INIT_LOWER[9]),
|
||||
.iossm_mem_init_89 (IOSSM_MEM_INIT_UPPER[89-64]),
|
||||
.iossm_mem_init_88 (IOSSM_MEM_INIT_UPPER[88-64]),
|
||||
.iossm_mem_init_87 (IOSSM_MEM_INIT_UPPER[87-64]),
|
||||
.iossm_mem_init_86 (IOSSM_MEM_INIT_UPPER[86-64]),
|
||||
.iossm_mem_init_85 (IOSSM_MEM_INIT_UPPER[85-64]),
|
||||
.iossm_mem_init_84 (IOSSM_MEM_INIT_UPPER[84-64]),
|
||||
.iossm_mem_init_83 (IOSSM_MEM_INIT_UPPER[83-64]),
|
||||
.iossm_mem_init_82 (IOSSM_MEM_INIT_UPPER[82-64]),
|
||||
.iossm_mem_init_81 (IOSSM_MEM_INIT_UPPER[81-64]),
|
||||
.iossm_mem_init_80 (IOSSM_MEM_INIT_UPPER[80-64]),
|
||||
.iossm_mem_init_8 (IOSSM_MEM_INIT_LOWER[8]),
|
||||
.iossm_mem_init_79 (IOSSM_MEM_INIT_UPPER[79-64]),
|
||||
.iossm_mem_init_78 (IOSSM_MEM_INIT_UPPER[78-64]),
|
||||
.iossm_mem_init_77 (IOSSM_MEM_INIT_UPPER[77-64]),
|
||||
.iossm_mem_init_76 (IOSSM_MEM_INIT_UPPER[76-64]),
|
||||
.iossm_mem_init_75 (IOSSM_MEM_INIT_UPPER[75-64]),
|
||||
.iossm_mem_init_74 (IOSSM_MEM_INIT_UPPER[74-64]),
|
||||
.iossm_mem_init_73 (IOSSM_MEM_INIT_UPPER[73-64]),
|
||||
.iossm_mem_init_72 (IOSSM_MEM_INIT_UPPER[72-64]),
|
||||
.iossm_mem_init_71 (IOSSM_MEM_INIT_UPPER[71-64]),
|
||||
.iossm_mem_init_70 (IOSSM_MEM_INIT_UPPER[70-64]),
|
||||
.iossm_mem_init_7 (IOSSM_MEM_INIT_LOWER[7]),
|
||||
.iossm_mem_init_69 (IOSSM_MEM_INIT_UPPER[69-64]),
|
||||
.iossm_mem_init_68 (IOSSM_MEM_INIT_UPPER[68-64]),
|
||||
.iossm_mem_init_67 (IOSSM_MEM_INIT_UPPER[67-64]),
|
||||
.iossm_mem_init_66 (IOSSM_MEM_INIT_UPPER[66-64]),
|
||||
.iossm_mem_init_65 (IOSSM_MEM_INIT_UPPER[65-64]),
|
||||
.iossm_mem_init_64 (IOSSM_MEM_INIT_UPPER[64-64]),
|
||||
.iossm_mem_init_63 (IOSSM_MEM_INIT_LOWER[63]),
|
||||
.iossm_mem_init_62 (IOSSM_MEM_INIT_LOWER[62]),
|
||||
.iossm_mem_init_61 (IOSSM_MEM_INIT_LOWER[61]),
|
||||
.iossm_mem_init_60 (IOSSM_MEM_INIT_LOWER[60]),
|
||||
.iossm_mem_init_6 (IOSSM_MEM_INIT_LOWER[6]),
|
||||
.iossm_mem_init_59 (IOSSM_MEM_INIT_LOWER[59]),
|
||||
.iossm_mem_init_58 (IOSSM_MEM_INIT_LOWER[58]),
|
||||
.iossm_mem_init_57 (IOSSM_MEM_INIT_LOWER[57]),
|
||||
.iossm_mem_init_56 (IOSSM_MEM_INIT_LOWER[56]),
|
||||
.iossm_mem_init_55 (IOSSM_MEM_INIT_LOWER[55]),
|
||||
.iossm_mem_init_54 (IOSSM_MEM_INIT_LOWER[54]),
|
||||
.iossm_mem_init_53 (IOSSM_MEM_INIT_LOWER[53]),
|
||||
.iossm_mem_init_52 (IOSSM_MEM_INIT_LOWER[52]),
|
||||
.iossm_mem_init_51 (IOSSM_MEM_INIT_LOWER[51]),
|
||||
.iossm_mem_init_50 (IOSSM_MEM_INIT_LOWER[50]),
|
||||
.iossm_mem_init_5 (IOSSM_MEM_INIT_LOWER[5]),
|
||||
.iossm_mem_init_49 (IOSSM_MEM_INIT_LOWER[49]),
|
||||
.iossm_mem_init_48 (IOSSM_MEM_INIT_LOWER[48]),
|
||||
.iossm_mem_init_47 (IOSSM_MEM_INIT_LOWER[47]),
|
||||
.iossm_mem_init_46 (IOSSM_MEM_INIT_LOWER[46]),
|
||||
.iossm_mem_init_45 (IOSSM_MEM_INIT_LOWER[45]),
|
||||
.iossm_mem_init_44 (IOSSM_MEM_INIT_LOWER[44]),
|
||||
.iossm_mem_init_43 (IOSSM_MEM_INIT_LOWER[43]),
|
||||
.iossm_mem_init_42 (IOSSM_MEM_INIT_LOWER[42]),
|
||||
.iossm_mem_init_41 (IOSSM_MEM_INIT_LOWER[41]),
|
||||
.iossm_mem_init_40 (IOSSM_MEM_INIT_LOWER[40]),
|
||||
.iossm_mem_init_4 (IOSSM_MEM_INIT_LOWER[4]),
|
||||
.iossm_mem_init_39 (IOSSM_MEM_INIT_LOWER[39]),
|
||||
.iossm_mem_init_38 (IOSSM_MEM_INIT_LOWER[38]),
|
||||
.iossm_mem_init_37 (IOSSM_MEM_INIT_LOWER[37]),
|
||||
.iossm_mem_init_36 (IOSSM_MEM_INIT_LOWER[36]),
|
||||
.iossm_mem_init_35 (IOSSM_MEM_INIT_LOWER[35]),
|
||||
.iossm_mem_init_34 (IOSSM_MEM_INIT_LOWER[34]),
|
||||
.iossm_mem_init_33 (IOSSM_MEM_INIT_LOWER[33]),
|
||||
.iossm_mem_init_32 (IOSSM_MEM_INIT_LOWER[32]),
|
||||
.iossm_mem_init_31 (IOSSM_MEM_INIT_LOWER[31]),
|
||||
.iossm_mem_init_30 (IOSSM_MEM_INIT_LOWER[30]),
|
||||
.iossm_mem_init_3 (IOSSM_MEM_INIT_LOWER[3]),
|
||||
.iossm_mem_init_29 (IOSSM_MEM_INIT_LOWER[29]),
|
||||
.iossm_mem_init_28 (IOSSM_MEM_INIT_LOWER[28]),
|
||||
.iossm_mem_init_27 (IOSSM_MEM_INIT_LOWER[27]),
|
||||
.iossm_mem_init_26 (IOSSM_MEM_INIT_LOWER[26]),
|
||||
.iossm_mem_init_25 (IOSSM_MEM_INIT_LOWER[25]),
|
||||
.iossm_mem_init_24 (IOSSM_MEM_INIT_LOWER[24]),
|
||||
.iossm_mem_init_23 (IOSSM_MEM_INIT_LOWER[23]),
|
||||
.iossm_mem_init_22 (IOSSM_MEM_INIT_LOWER[22]),
|
||||
.iossm_mem_init_21 (IOSSM_MEM_INIT_LOWER[21]),
|
||||
.iossm_mem_init_20 (IOSSM_MEM_INIT_LOWER[20]),
|
||||
.iossm_mem_init_2 (IOSSM_MEM_INIT_LOWER[2]),
|
||||
.iossm_mem_init_19 (IOSSM_MEM_INIT_LOWER[19]),
|
||||
.iossm_mem_init_18 (IOSSM_MEM_INIT_LOWER[18]),
|
||||
.iossm_mem_init_17 (IOSSM_MEM_INIT_LOWER[17]),
|
||||
.iossm_mem_init_16 (IOSSM_MEM_INIT_LOWER[16]),
|
||||
.iossm_mem_init_15 (IOSSM_MEM_INIT_LOWER[15]),
|
||||
.iossm_mem_init_14 (IOSSM_MEM_INIT_LOWER[14]),
|
||||
.iossm_mem_init_13 (IOSSM_MEM_INIT_LOWER[13]),
|
||||
.iossm_mem_init_127 (IOSSM_MEM_INIT_UPPER[127-64]),
|
||||
.iossm_mem_init_126 (IOSSM_MEM_INIT_UPPER[126-64]),
|
||||
.iossm_mem_init_125 (IOSSM_MEM_INIT_UPPER[125-64]),
|
||||
.iossm_mem_init_124 (IOSSM_MEM_INIT_UPPER[124-64]),
|
||||
.iossm_mem_init_123 (IOSSM_MEM_INIT_UPPER[123-64]),
|
||||
.iossm_mem_init_122 (IOSSM_MEM_INIT_UPPER[122-64]),
|
||||
.iossm_mem_init_121 (IOSSM_MEM_INIT_UPPER[121-64]),
|
||||
.iossm_mem_init_120 (IOSSM_MEM_INIT_UPPER[120-64]),
|
||||
.iossm_mem_init_12 (IOSSM_MEM_INIT_LOWER[12]),
|
||||
.iossm_mem_init_119 (IOSSM_MEM_INIT_UPPER[119-64]),
|
||||
.iossm_mem_init_118 (IOSSM_MEM_INIT_UPPER[118-64]),
|
||||
.iossm_mem_init_117 (IOSSM_MEM_INIT_UPPER[117-64]),
|
||||
.iossm_mem_init_116 (IOSSM_MEM_INIT_UPPER[116-64]),
|
||||
.iossm_mem_init_115 (IOSSM_MEM_INIT_UPPER[115-64]),
|
||||
.iossm_mem_init_114 (IOSSM_MEM_INIT_UPPER[114-64]),
|
||||
.iossm_mem_init_113 (IOSSM_MEM_INIT_UPPER[113-64]),
|
||||
.iossm_mem_init_112 (IOSSM_MEM_INIT_UPPER[112-64]),
|
||||
.iossm_mem_init_111 (IOSSM_MEM_INIT_UPPER[111-64]),
|
||||
.iossm_mem_init_110 (IOSSM_MEM_INIT_UPPER[110-64]),
|
||||
.iossm_mem_init_11 (IOSSM_MEM_INIT_LOWER[11]),
|
||||
.iossm_mem_init_109 (IOSSM_MEM_INIT_UPPER[109-64]),
|
||||
.iossm_mem_init_108 (IOSSM_MEM_INIT_UPPER[108-64]),
|
||||
.iossm_mem_init_107 (IOSSM_MEM_INIT_UPPER[107-64]),
|
||||
.iossm_mem_init_106 (IOSSM_MEM_INIT_UPPER[106-64]),
|
||||
.iossm_mem_init_105 (IOSSM_MEM_INIT_UPPER[105-64]),
|
||||
.iossm_mem_init_104 (IOSSM_MEM_INIT_UPPER[104-64]),
|
||||
.iossm_mem_init_103 (IOSSM_MEM_INIT_UPPER[103-64]),
|
||||
.iossm_mem_init_102 (IOSSM_MEM_INIT_UPPER[102-64]),
|
||||
.iossm_mem_init_101 (IOSSM_MEM_INIT_UPPER[101-64]),
|
||||
.iossm_mem_init_100 (IOSSM_MEM_INIT_UPPER[100-64]),
|
||||
.iossm_mem_init_10 (IOSSM_MEM_INIT_LOWER[10]),
|
||||
.iossm_mem_init_1 (IOSSM_MEM_INIT_LOWER[1]),
|
||||
.iossm_mem_init_0 (IOSSM_MEM_INIT_LOWER[0]),
|
||||
.parameter_table_hexfile (PARAMETER_TABLE_HEXFILE)
|
||||
) iossm (
|
||||
.axil_araddr (axil_araddr),
|
||||
.axil_arready (axil_arready),
|
||||
.axil_arvalid (axil_arvalid),
|
||||
.axil_awaddr (axil_awaddr),
|
||||
.axil_awready (axil_awready),
|
||||
.axil_awvalid (axil_awvalid),
|
||||
.axil_bready (axil_bready),
|
||||
.axil_bresp (axil_bresp),
|
||||
.axil_bvalid (axil_bvalid),
|
||||
.axil_clk (axil_clk),
|
||||
.axil_rdata (axil_rdata),
|
||||
.axil_rready (axil_rready),
|
||||
.axil_rresp (axil_rresp),
|
||||
.axil_rvalid (axil_rvalid),
|
||||
.axil_wdata (axil_wdata),
|
||||
.axil_wready (axil_wready),
|
||||
.axil_wstrb (axil_wstrb),
|
||||
.axil_wvalid (axil_wvalid),
|
||||
.c2p_clk (c2p_clk),
|
||||
.calbus0_addr (calbus0_addr),
|
||||
.calbus0_clock (calbus0_clock),
|
||||
.calbus0_read (calbus0_read),
|
||||
.calbus0_readdata (calbus0_readdata),
|
||||
.calbus0_rst_n (calbus0_rst_n),
|
||||
.calbus0_write (calbus0_write),
|
||||
.calbus0_writedata (calbus0_writedata),
|
||||
.clk_en_in (clk_en_in),
|
||||
.haddr (haddr),
|
||||
.hburst (hburst),
|
||||
.hclk (hclk),
|
||||
.hready (hready),
|
||||
.hresetn (hresetn),
|
||||
.hsel (hsel),
|
||||
.hsize (hsize),
|
||||
.htrans (htrans),
|
||||
.hwdata (hwdata),
|
||||
.hwrite (hwrite),
|
||||
.i3c_scl (i3c_scl),
|
||||
.i3c_sda_dr_en_n (i3c_sda_dr_en_n),
|
||||
.i3c_sda_pp (i3c_sda_pp),
|
||||
.i3c_sda_rx (i3c_sda_rx),
|
||||
.i3c_sda_tx (i3c_sda_tx),
|
||||
.iofbradapt_ssm_c2p (iofbradapt_ssm_c2p),
|
||||
.iofbradapt_ssm_p2c (iofbradapt_ssm_p2c),
|
||||
.i_sim_param_table_0 (i_sim_param_table_0),
|
||||
.i_sim_param_table_1 (i_sim_param_table_1),
|
||||
.mc0_hrdata (mc0_hrdata),
|
||||
.mc0_hreadyout (mc0_hreadyout),
|
||||
.mc0_hresp (mc0_hresp),
|
||||
.mc0_irq (mc0_irq),
|
||||
.mc0_rst_n (mc0_rst_n),
|
||||
.mc1_hrdata (mc1_hrdata),
|
||||
.mc1_hreadyout (mc1_hreadyout),
|
||||
.mc1_hresp (mc1_hresp),
|
||||
.mc1_irq (mc1_irq),
|
||||
.mc1_rst_n (mc1_rst_n)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
+399
@@ -0,0 +1,399 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
module io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_stdfn_inst_seq #(
|
||||
localparam PORT_I_AVL_ADDRESS_WIDTH = 22,
|
||||
localparam PORT_I_AVL_READDATA_CKGEN_WIDTH = 32,
|
||||
localparam PORT_I_AVL_READDATA_COMP_WIDTH = 32,
|
||||
localparam PORT_I_AVL_READDATA_FBRPLL_WIDTH = 32,
|
||||
localparam PORT_I_AVL_READDATA_IOPLL_WIDTH = 32,
|
||||
localparam PORT_I_AVL_READDATA_LANE_WIDTH = 32,
|
||||
localparam PORT_I_AVL_WRITEDATA_WIDTH = 32,
|
||||
localparam PORT_I_RB_BASE_ADDRESS_PA_WIDTH = 11,
|
||||
localparam PORT_I_SEQ_RDDATA_WIDTH = 96,
|
||||
localparam PORT_I_SEQ_RDDATA_VALID_WIDTH = 4,
|
||||
localparam PORT_O_AVL_ADDRESS_CKGEN_WIDTH = 22,
|
||||
localparam PORT_O_AVL_ADDRESS_COMP_WIDTH = 22,
|
||||
localparam PORT_O_AVL_ADDRESS_LANE_WIDTH = 22,
|
||||
localparam PORT_O_AVL_ADDRESS_PLL_WIDTH = 22,
|
||||
localparam PORT_O_AVL_READDATA_WIDTH = 32,
|
||||
localparam PORT_O_AVL_WRITEDATA_CKGEN_WIDTH = 32,
|
||||
localparam PORT_O_AVL_WRITEDATA_COMP_WIDTH = 32,
|
||||
localparam PORT_O_AVL_WRITEDATA_LANE_WIDTH = 32,
|
||||
localparam PORT_O_AVL_WRITEDATA_PLL_WIDTH = 32,
|
||||
localparam PORT_O_SEQ_RDDATA_EN_WIDTH = 4,
|
||||
localparam PORT_O_SEQ_RD_RANK_WIDTH = 8,
|
||||
localparam PORT_O_SEQ_SUPPRESSION_WIDTH = 12,
|
||||
localparam PORT_O_SEQ_WRDATA_WIDTH = 96,
|
||||
localparam PORT_O_SEQ_WRDATA_EN_WIDTH = 4,
|
||||
localparam PORT_O_SEQ_WR_DQS_EN_WIDTH = 4,
|
||||
localparam PORT_O_SEQ_WR_RANK_WIDTH = 8
|
||||
) (
|
||||
|
||||
input [PORT_I_AVL_ADDRESS_WIDTH-1:0] i_avl_address,
|
||||
input i_avl_clk,
|
||||
input i_avl_read,
|
||||
input [PORT_I_AVL_READDATA_CKGEN_WIDTH-1:0] i_avl_readdata_ckgen0,
|
||||
input [PORT_I_AVL_READDATA_CKGEN_WIDTH-1:0] i_avl_readdata_ckgen1,
|
||||
input [PORT_I_AVL_READDATA_COMP_WIDTH-1:0] i_avl_readdata_comp,
|
||||
input [PORT_I_AVL_READDATA_FBRPLL_WIDTH-1:0] i_avl_readdata_fbrpll,
|
||||
input [PORT_I_AVL_READDATA_IOPLL_WIDTH-1:0] i_avl_readdata_iopll0,
|
||||
input [PORT_I_AVL_READDATA_IOPLL_WIDTH-1:0] i_avl_readdata_iopll1,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane0,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane1,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane2,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane3,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane4,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane5,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane6,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane7,
|
||||
input i_avl_rstn,
|
||||
input i_avl_write,
|
||||
input [PORT_I_AVL_WRITEDATA_WIDTH-1:0] i_avl_writedata,
|
||||
input i_phy_clka,
|
||||
input i_phy_clkb,
|
||||
input i_phy_clksync_a,
|
||||
input i_phy_clksync_b,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa0,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa1,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa2,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa3,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa4,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa5,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa6,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa7,
|
||||
input i_rb_ddr_lane_mode_pa0,
|
||||
input i_rb_ddr_lane_mode_pa1,
|
||||
input i_rb_ddr_lane_mode_pa2,
|
||||
input i_rb_ddr_lane_mode_pa3,
|
||||
input i_rb_ddr_lane_mode_pa4,
|
||||
input i_rb_ddr_lane_mode_pa5,
|
||||
input i_rb_ddr_lane_mode_pa6,
|
||||
input i_rb_ddr_lane_mode_pa7,
|
||||
input i_rb_if_sel_pa0,
|
||||
input i_rb_if_sel_pa1,
|
||||
input i_rb_if_sel_pa2,
|
||||
input i_rb_if_sel_pa3,
|
||||
input i_rb_if_sel_pa4,
|
||||
input i_rb_if_sel_pa5,
|
||||
input i_rb_if_sel_pa6,
|
||||
input i_rb_if_sel_pa7,
|
||||
input i_rb_phy_clk_en_pa0,
|
||||
input i_rb_phy_clk_en_pa1,
|
||||
input i_rb_phy_clk_en_pa2,
|
||||
input i_rb_phy_clk_en_pa3,
|
||||
input i_rb_phy_clk_en_pa4,
|
||||
input i_rb_phy_clk_en_pa5,
|
||||
input i_rb_phy_clk_en_pa6,
|
||||
input i_rb_phy_clk_en_pa7,
|
||||
input i_rb_rate_conv_en_pa0,
|
||||
input i_rb_rate_conv_en_pa1,
|
||||
input i_rb_rate_conv_en_pa2,
|
||||
input i_rb_rate_conv_en_pa3,
|
||||
input i_rb_rate_conv_en_pa4,
|
||||
input i_rb_rate_conv_en_pa5,
|
||||
input i_rb_rate_conv_en_pa6,
|
||||
input i_rb_rate_conv_en_pa7,
|
||||
input i_seq_cmd_sync,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_0,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_1,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_2,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_3,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_4,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_5,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_6,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_7,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_0,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_1,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_2,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_3,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_4,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_5,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_6,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_7,
|
||||
output [PORT_O_AVL_ADDRESS_CKGEN_WIDTH-1:0] o_avl_address_ckgen,
|
||||
output [PORT_O_AVL_ADDRESS_COMP_WIDTH-1:0] o_avl_address_comp,
|
||||
output [PORT_O_AVL_ADDRESS_LANE_WIDTH-1:0] o_avl_address_lane,
|
||||
output [PORT_O_AVL_ADDRESS_PLL_WIDTH-1:0] o_avl_address_pll,
|
||||
output o_avl_clk_ckgen,
|
||||
output o_avl_clk_comp,
|
||||
output o_avl_clk_lane,
|
||||
output o_avl_clk_pll,
|
||||
output [PORT_O_AVL_READDATA_WIDTH-1:0] o_avl_readdata,
|
||||
output o_avl_read_ckgen,
|
||||
output o_avl_read_comp,
|
||||
output o_avl_read_lane,
|
||||
output o_avl_read_pll,
|
||||
output o_avl_rstn_ckgen,
|
||||
output o_avl_rstn_comp,
|
||||
output o_avl_rstn_lane,
|
||||
output o_avl_rstn_pll,
|
||||
output [PORT_O_AVL_WRITEDATA_CKGEN_WIDTH-1:0] o_avl_writedata_ckgen,
|
||||
output [PORT_O_AVL_WRITEDATA_COMP_WIDTH-1:0] o_avl_writedata_comp,
|
||||
output [PORT_O_AVL_WRITEDATA_LANE_WIDTH-1:0] o_avl_writedata_lane,
|
||||
output [PORT_O_AVL_WRITEDATA_PLL_WIDTH-1:0] o_avl_writedata_pll,
|
||||
output o_avl_write_ckgen,
|
||||
output o_avl_write_comp,
|
||||
output o_avl_write_lane,
|
||||
output o_avl_write_pll,
|
||||
output o_seq_cmd_sync,
|
||||
output o_seq_en_0,
|
||||
output o_seq_en_1,
|
||||
output o_seq_en_2,
|
||||
output o_seq_en_3,
|
||||
output o_seq_en_4,
|
||||
output o_seq_en_5,
|
||||
output o_seq_en_6,
|
||||
output o_seq_en_7,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_0,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_1,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_2,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_3,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_4,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_5,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_6,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_7,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_0,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_1,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_2,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_3,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_4,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_5,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_6,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_7,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_0,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_1,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_2,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_3,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_4,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_5,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_6,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_7,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_0,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_1,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_2,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_3,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_4,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_5,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_6,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_7,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_0,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_1,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_2,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_3,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_4,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_5,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_6,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_7,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_0,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_1,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_2,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_3,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_4,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_5,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_6,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_7,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_0,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_1,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_2,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_3,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_4,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_5,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_6,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_7
|
||||
|
||||
);
|
||||
timeunit 1ns;
|
||||
timeprecision 1ps;
|
||||
import io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_seq::*;
|
||||
|
||||
tennm_seq # (
|
||||
.base_address_ctrl (BASE_ADDRESS_CTRL)
|
||||
) seq (
|
||||
.i_avl_address (i_avl_address),
|
||||
.i_avl_clk (i_avl_clk),
|
||||
.i_avl_read (i_avl_read),
|
||||
.i_avl_readdata_ckgen0 (i_avl_readdata_ckgen0),
|
||||
.i_avl_readdata_ckgen1 (i_avl_readdata_ckgen1),
|
||||
.i_avl_readdata_comp (i_avl_readdata_comp),
|
||||
.i_avl_readdata_fbrpll (i_avl_readdata_fbrpll),
|
||||
.i_avl_readdata_iopll0 (i_avl_readdata_iopll0),
|
||||
.i_avl_readdata_iopll1 (i_avl_readdata_iopll1),
|
||||
.i_avl_readdata_lane0 (i_avl_readdata_lane0),
|
||||
.i_avl_readdata_lane1 (i_avl_readdata_lane1),
|
||||
.i_avl_readdata_lane2 (i_avl_readdata_lane2),
|
||||
.i_avl_readdata_lane3 (i_avl_readdata_lane3),
|
||||
.i_avl_readdata_lane4 (i_avl_readdata_lane4),
|
||||
.i_avl_readdata_lane5 (i_avl_readdata_lane5),
|
||||
.i_avl_readdata_lane6 (i_avl_readdata_lane6),
|
||||
.i_avl_readdata_lane7 (i_avl_readdata_lane7),
|
||||
.i_avl_rstn (i_avl_rstn),
|
||||
.i_avl_write (i_avl_write),
|
||||
.i_avl_writedata (i_avl_writedata),
|
||||
.i_phy_clka (i_phy_clka),
|
||||
.i_phy_clkb (i_phy_clkb),
|
||||
.i_phy_clksync_a (i_phy_clksync_a),
|
||||
.i_phy_clksync_b (i_phy_clksync_b),
|
||||
.i_rb_base_address_pa0 (i_rb_base_address_pa0),
|
||||
.i_rb_base_address_pa1 (i_rb_base_address_pa1),
|
||||
.i_rb_base_address_pa2 (i_rb_base_address_pa2),
|
||||
.i_rb_base_address_pa3 (i_rb_base_address_pa3),
|
||||
.i_rb_base_address_pa4 (i_rb_base_address_pa4),
|
||||
.i_rb_base_address_pa5 (i_rb_base_address_pa5),
|
||||
.i_rb_base_address_pa6 (i_rb_base_address_pa6),
|
||||
.i_rb_base_address_pa7 (i_rb_base_address_pa7),
|
||||
.i_rb_ddr_lane_mode_pa0 (i_rb_ddr_lane_mode_pa0),
|
||||
.i_rb_ddr_lane_mode_pa1 (i_rb_ddr_lane_mode_pa1),
|
||||
.i_rb_ddr_lane_mode_pa2 (i_rb_ddr_lane_mode_pa2),
|
||||
.i_rb_ddr_lane_mode_pa3 (i_rb_ddr_lane_mode_pa3),
|
||||
.i_rb_ddr_lane_mode_pa4 (i_rb_ddr_lane_mode_pa4),
|
||||
.i_rb_ddr_lane_mode_pa5 (i_rb_ddr_lane_mode_pa5),
|
||||
.i_rb_ddr_lane_mode_pa6 (i_rb_ddr_lane_mode_pa6),
|
||||
.i_rb_ddr_lane_mode_pa7 (i_rb_ddr_lane_mode_pa7),
|
||||
.i_rb_if_sel_pa0 (i_rb_if_sel_pa0),
|
||||
.i_rb_if_sel_pa1 (i_rb_if_sel_pa1),
|
||||
.i_rb_if_sel_pa2 (i_rb_if_sel_pa2),
|
||||
.i_rb_if_sel_pa3 (i_rb_if_sel_pa3),
|
||||
.i_rb_if_sel_pa4 (i_rb_if_sel_pa4),
|
||||
.i_rb_if_sel_pa5 (i_rb_if_sel_pa5),
|
||||
.i_rb_if_sel_pa6 (i_rb_if_sel_pa6),
|
||||
.i_rb_if_sel_pa7 (i_rb_if_sel_pa7),
|
||||
.i_rb_phy_clk_en_pa0 (i_rb_phy_clk_en_pa0),
|
||||
.i_rb_phy_clk_en_pa1 (i_rb_phy_clk_en_pa1),
|
||||
.i_rb_phy_clk_en_pa2 (i_rb_phy_clk_en_pa2),
|
||||
.i_rb_phy_clk_en_pa3 (i_rb_phy_clk_en_pa3),
|
||||
.i_rb_phy_clk_en_pa4 (i_rb_phy_clk_en_pa4),
|
||||
.i_rb_phy_clk_en_pa5 (i_rb_phy_clk_en_pa5),
|
||||
.i_rb_phy_clk_en_pa6 (i_rb_phy_clk_en_pa6),
|
||||
.i_rb_phy_clk_en_pa7 (i_rb_phy_clk_en_pa7),
|
||||
.i_rb_rate_conv_en_pa0 (i_rb_rate_conv_en_pa0),
|
||||
.i_rb_rate_conv_en_pa1 (i_rb_rate_conv_en_pa1),
|
||||
.i_rb_rate_conv_en_pa2 (i_rb_rate_conv_en_pa2),
|
||||
.i_rb_rate_conv_en_pa3 (i_rb_rate_conv_en_pa3),
|
||||
.i_rb_rate_conv_en_pa4 (i_rb_rate_conv_en_pa4),
|
||||
.i_rb_rate_conv_en_pa5 (i_rb_rate_conv_en_pa5),
|
||||
.i_rb_rate_conv_en_pa6 (i_rb_rate_conv_en_pa6),
|
||||
.i_rb_rate_conv_en_pa7 (i_rb_rate_conv_en_pa7),
|
||||
.i_seq_cmd_sync (i_seq_cmd_sync),
|
||||
.i_seq_rddata_0 (i_seq_rddata_0),
|
||||
.i_seq_rddata_1 (i_seq_rddata_1),
|
||||
.i_seq_rddata_2 (i_seq_rddata_2),
|
||||
.i_seq_rddata_3 (i_seq_rddata_3),
|
||||
.i_seq_rddata_4 (i_seq_rddata_4),
|
||||
.i_seq_rddata_5 (i_seq_rddata_5),
|
||||
.i_seq_rddata_6 (i_seq_rddata_6),
|
||||
.i_seq_rddata_7 (i_seq_rddata_7),
|
||||
.i_seq_rddata_valid_0 (i_seq_rddata_valid_0),
|
||||
.i_seq_rddata_valid_1 (i_seq_rddata_valid_1),
|
||||
.i_seq_rddata_valid_2 (i_seq_rddata_valid_2),
|
||||
.i_seq_rddata_valid_3 (i_seq_rddata_valid_3),
|
||||
.i_seq_rddata_valid_4 (i_seq_rddata_valid_4),
|
||||
.i_seq_rddata_valid_5 (i_seq_rddata_valid_5),
|
||||
.i_seq_rddata_valid_6 (i_seq_rddata_valid_6),
|
||||
.i_seq_rddata_valid_7 (i_seq_rddata_valid_7),
|
||||
.o_avl_address_ckgen (o_avl_address_ckgen),
|
||||
.o_avl_address_comp (o_avl_address_comp),
|
||||
.o_avl_address_lane (o_avl_address_lane),
|
||||
.o_avl_address_pll (o_avl_address_pll),
|
||||
.o_avl_clk_ckgen (o_avl_clk_ckgen),
|
||||
.o_avl_clk_comp (o_avl_clk_comp),
|
||||
.o_avl_clk_lane (o_avl_clk_lane),
|
||||
.o_avl_clk_pll (o_avl_clk_pll),
|
||||
.o_avl_readdata (o_avl_readdata),
|
||||
.o_avl_read_ckgen (o_avl_read_ckgen),
|
||||
.o_avl_read_comp (o_avl_read_comp),
|
||||
.o_avl_read_lane (o_avl_read_lane),
|
||||
.o_avl_read_pll (o_avl_read_pll),
|
||||
.o_avl_rstn_ckgen (o_avl_rstn_ckgen),
|
||||
.o_avl_rstn_comp (o_avl_rstn_comp),
|
||||
.o_avl_rstn_lane (o_avl_rstn_lane),
|
||||
.o_avl_rstn_pll (o_avl_rstn_pll),
|
||||
.o_avl_writedata_ckgen (o_avl_writedata_ckgen),
|
||||
.o_avl_writedata_comp (o_avl_writedata_comp),
|
||||
.o_avl_writedata_lane (o_avl_writedata_lane),
|
||||
.o_avl_writedata_pll (o_avl_writedata_pll),
|
||||
.o_avl_write_ckgen (o_avl_write_ckgen),
|
||||
.o_avl_write_comp (o_avl_write_comp),
|
||||
.o_avl_write_lane (o_avl_write_lane),
|
||||
.o_avl_write_pll (o_avl_write_pll),
|
||||
.o_seq_cmd_sync (o_seq_cmd_sync),
|
||||
.o_seq_en_0 (o_seq_en_0),
|
||||
.o_seq_en_1 (o_seq_en_1),
|
||||
.o_seq_en_2 (o_seq_en_2),
|
||||
.o_seq_en_3 (o_seq_en_3),
|
||||
.o_seq_en_4 (o_seq_en_4),
|
||||
.o_seq_en_5 (o_seq_en_5),
|
||||
.o_seq_en_6 (o_seq_en_6),
|
||||
.o_seq_en_7 (o_seq_en_7),
|
||||
.o_seq_rddata_en_0 (o_seq_rddata_en_0),
|
||||
.o_seq_rddata_en_1 (o_seq_rddata_en_1),
|
||||
.o_seq_rddata_en_2 (o_seq_rddata_en_2),
|
||||
.o_seq_rddata_en_3 (o_seq_rddata_en_3),
|
||||
.o_seq_rddata_en_4 (o_seq_rddata_en_4),
|
||||
.o_seq_rddata_en_5 (o_seq_rddata_en_5),
|
||||
.o_seq_rddata_en_6 (o_seq_rddata_en_6),
|
||||
.o_seq_rddata_en_7 (o_seq_rddata_en_7),
|
||||
.o_seq_rd_rank_0 (o_seq_rd_rank_0),
|
||||
.o_seq_rd_rank_1 (o_seq_rd_rank_1),
|
||||
.o_seq_rd_rank_2 (o_seq_rd_rank_2),
|
||||
.o_seq_rd_rank_3 (o_seq_rd_rank_3),
|
||||
.o_seq_rd_rank_4 (o_seq_rd_rank_4),
|
||||
.o_seq_rd_rank_5 (o_seq_rd_rank_5),
|
||||
.o_seq_rd_rank_6 (o_seq_rd_rank_6),
|
||||
.o_seq_rd_rank_7 (o_seq_rd_rank_7),
|
||||
.o_seq_suppression_0 (o_seq_suppression_0),
|
||||
.o_seq_suppression_1 (o_seq_suppression_1),
|
||||
.o_seq_suppression_2 (o_seq_suppression_2),
|
||||
.o_seq_suppression_3 (o_seq_suppression_3),
|
||||
.o_seq_suppression_4 (o_seq_suppression_4),
|
||||
.o_seq_suppression_5 (o_seq_suppression_5),
|
||||
.o_seq_suppression_6 (o_seq_suppression_6),
|
||||
.o_seq_suppression_7 (o_seq_suppression_7),
|
||||
.o_seq_wrdata_0 (o_seq_wrdata_0),
|
||||
.o_seq_wrdata_1 (o_seq_wrdata_1),
|
||||
.o_seq_wrdata_2 (o_seq_wrdata_2),
|
||||
.o_seq_wrdata_3 (o_seq_wrdata_3),
|
||||
.o_seq_wrdata_4 (o_seq_wrdata_4),
|
||||
.o_seq_wrdata_5 (o_seq_wrdata_5),
|
||||
.o_seq_wrdata_6 (o_seq_wrdata_6),
|
||||
.o_seq_wrdata_7 (o_seq_wrdata_7),
|
||||
.o_seq_wrdata_en_0 (o_seq_wrdata_en_0),
|
||||
.o_seq_wrdata_en_1 (o_seq_wrdata_en_1),
|
||||
.o_seq_wrdata_en_2 (o_seq_wrdata_en_2),
|
||||
.o_seq_wrdata_en_3 (o_seq_wrdata_en_3),
|
||||
.o_seq_wrdata_en_4 (o_seq_wrdata_en_4),
|
||||
.o_seq_wrdata_en_5 (o_seq_wrdata_en_5),
|
||||
.o_seq_wrdata_en_6 (o_seq_wrdata_en_6),
|
||||
.o_seq_wrdata_en_7 (o_seq_wrdata_en_7),
|
||||
.o_seq_wr_dqs_en_0 (o_seq_wr_dqs_en_0),
|
||||
.o_seq_wr_dqs_en_1 (o_seq_wr_dqs_en_1),
|
||||
.o_seq_wr_dqs_en_2 (o_seq_wr_dqs_en_2),
|
||||
.o_seq_wr_dqs_en_3 (o_seq_wr_dqs_en_3),
|
||||
.o_seq_wr_dqs_en_4 (o_seq_wr_dqs_en_4),
|
||||
.o_seq_wr_dqs_en_5 (o_seq_wr_dqs_en_5),
|
||||
.o_seq_wr_dqs_en_6 (o_seq_wr_dqs_en_6),
|
||||
.o_seq_wr_dqs_en_7 (o_seq_wr_dqs_en_7),
|
||||
.o_seq_wr_rank_0 (o_seq_wr_rank_0),
|
||||
.o_seq_wr_rank_1 (o_seq_wr_rank_1),
|
||||
.o_seq_wr_rank_2 (o_seq_wr_rank_2),
|
||||
.o_seq_wr_rank_3 (o_seq_wr_rank_3),
|
||||
.o_seq_wr_rank_4 (o_seq_wr_rank_4),
|
||||
.o_seq_wr_rank_5 (o_seq_wr_rank_5),
|
||||
.o_seq_wr_rank_6 (o_seq_wr_rank_6),
|
||||
.o_seq_wr_rank_7 (o_seq_wr_rank_7)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user