Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
@@ -0,0 +1,475 @@
|
||||
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:52:56
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script rivierapro_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# qsys_top
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level script that compiles Intel simulation libraries and
|
||||
# the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "aldec.do", and modify the text as directed.
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# set QSYS_SIMDIR <script generation output directory>
|
||||
# #
|
||||
# # Source the generated IP simulation script.
|
||||
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
|
||||
# #
|
||||
# # Set any compilation options you require (this is unusual).
|
||||
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
|
||||
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
|
||||
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
|
||||
# #
|
||||
# # Call command to compile the Quartus EDA simulation library.
|
||||
# dev_com
|
||||
# #
|
||||
# # Call command to compile the Quartus-generated IP simulation files.
|
||||
# com
|
||||
# #
|
||||
# # Add commands to compile all design files and testbench files, including
|
||||
# # the top level. (These are all the files required for simulation other
|
||||
# # than the files compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# vlog -sv2k5 <your compilation options> <design and testbench files>
|
||||
# #
|
||||
# # Set the top-level simulation or testbench module/entity name, which is
|
||||
# # used by the elab command to elaborate the top level.
|
||||
# #
|
||||
# set TOP_LEVEL_NAME <simulation top>
|
||||
# #
|
||||
# # Set any elaboration options you require.
|
||||
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
|
||||
# #
|
||||
# # Call command to elaborate your design and testbench.
|
||||
# elab
|
||||
# #
|
||||
# # Run the simulation.
|
||||
# run
|
||||
# #
|
||||
# # Report success to the shell.
|
||||
# exit -code 0
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If qsys_top is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Intel IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Intel IP within the design.
|
||||
# ----------------------------------------
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize variables
|
||||
if ![info exists SYSTEM_INSTANCE_NAME] {
|
||||
set SYSTEM_INSTANCE_NAME ""
|
||||
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
|
||||
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
|
||||
}
|
||||
|
||||
if ![info exists TOP_LEVEL_NAME] {
|
||||
set TOP_LEVEL_NAME "qsys_top.qsys_top"
|
||||
}
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_INSTALL_DIR] {
|
||||
set QUARTUS_INSTALL_DIR "/opt/altera_pro/26.1/quartus/"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_SIM_LIB_DIR] {
|
||||
set QUARTUS_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/eda/sim_lib/"
|
||||
}
|
||||
|
||||
if ![info exists DEVICES_SIM_LIB_DIR] {
|
||||
set DEVICES_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
|
||||
set USER_DEFINED_ELAB_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists SILENCE] {
|
||||
set SILENCE "false"
|
||||
}
|
||||
|
||||
if ![info exists PRECOMP_DEVICE_LIB_FILE] {
|
||||
set PRECOMP_DEVICE_LIB_FILE ""
|
||||
}
|
||||
|
||||
|
||||
#-------------------------------------------
|
||||
# read .tcl file to override initialized variables
|
||||
if { [info exists ::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)] && [file exist $::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)] } {
|
||||
echo "Sourcing $::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)"
|
||||
source $::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)
|
||||
}
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Source Common Tcl File
|
||||
source $QSYS_SIMDIR/common/riviera_files.tcl
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize simulation properties - DO NOT MODIFY!
|
||||
set ELAB_OPTIONS ""
|
||||
set SIM_OPTIONS ""
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
if { ![ string match "*-64 vsim*" [ vsim -version ] ] } {
|
||||
set SIMULATOR_TOOL_BITNESS "bit_32"
|
||||
} else {
|
||||
set SIMULATOR_TOOL_BITNESS "bit_64"
|
||||
}
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [qsys_top::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
if {[dict size $LD_LIBRARY_PATH] !=0 } {
|
||||
set LD_LIBRARY_PATH [subst [join [dict keys $LD_LIBRARY_PATH] ":"]]
|
||||
setenv LD_LIBRARY_PATH "$LD_LIBRARY_PATH"
|
||||
}
|
||||
append ELAB_OPTIONS [subst [qsys_top::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append SIM_OPTIONS [subst [qsys_top::get_sim_options $SIMULATOR_TOOL_BITNESS]]
|
||||
|
||||
#-------------------------------------------
|
||||
# Check if $PRECOMP_DEVICE_LIB_FILE is set and points to correct file
|
||||
if { $PRECOMP_DEVICE_LIB_FILE ne "" } {
|
||||
set PRECOMP_DEVICE_LIB_FILE [string trim $PRECOMP_DEVICE_LIB_FILE]
|
||||
if { [file exists $PRECOMP_DEVICE_LIB_FILE] && [string match [file tail $PRECOMP_DEVICE_LIB_FILE] "library.cfg" ] } {
|
||||
echo "Using $PRECOMP_DEVICE_LIB_FILE for device library mapping"
|
||||
} else {
|
||||
echo "Unable to use $PRECOMP_DEVICE_LIB_FILE for device library mapping. Switching back to local library compilation"
|
||||
set PRECOMP_DEVICE_LIB_FILE ""
|
||||
}
|
||||
}
|
||||
|
||||
set Aldec "Riviera"
|
||||
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
|
||||
set Aldec "Active"
|
||||
}
|
||||
|
||||
if { [ string match "Active" $Aldec ] } {
|
||||
scripterconf -tcl
|
||||
createdesign "$TOP_LEVEL_NAME" "."
|
||||
opendesign "$TOP_LEVEL_NAME"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Copy ROM/RAM files to simulation directory
|
||||
alias file_copy {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] file_copy"
|
||||
}
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [qsys_top::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
foreach file $memory_files {
|
||||
set itercount 0
|
||||
while {$itercount < 10 && [file type $file] eq "link"} {
|
||||
set nf [file readlink $file]
|
||||
if {[string index $nf 0] ne "/"} {
|
||||
set nf [file dirname $file]/$nf
|
||||
}
|
||||
set file $nf
|
||||
}
|
||||
set dest_file [file join ./ [file tail $file]]
|
||||
set normalized_src [qsys_top::normalize_path "$file"]
|
||||
set normalized_dest [qsys_top::normalize_path "$dest_file"]
|
||||
if { $normalized_src ne $normalized_dest } {
|
||||
file copy -force $file ./
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Create compilation libraries
|
||||
|
||||
set logical_libraries [list "work" "work_lib" "lpm_ver" "sgate_ver" "altera_ver" "altera_mf_ver" "altera_lnsim_ver" "tennm_ver" "tennm_sm_hps_ver" "tennm_sm4_hssi_ver" "tennm_revb_hvio_ver" "tennm_revb_io96_ver" "lpm" "sgate" "altera" "altera_mf" "altera_lnsim" "tennm" "tennm_sm_hps" "tennm_sm4_hssi" "tennm_revb_hvio" "tennm_revb_io96"]
|
||||
|
||||
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
|
||||
|
||||
# ----------------------------------------
|
||||
# get DPI libraries
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [qsys_top::get_dpi_libraries "$QSYS_SIMDIR"]]
|
||||
set dpi_libraries [dict values $libraries]
|
||||
|
||||
# ----------------------------------------
|
||||
# setup shared libraries
|
||||
set DPI_LIBRARIES_ELAB ""
|
||||
if { [llength $dpi_libraries] != 0 } {
|
||||
echo "Using DPI Library settings"
|
||||
foreach library $dpi_libraries {
|
||||
append DPI_LIBRARIES_ELAB "-sv_lib $library "
|
||||
}
|
||||
}
|
||||
|
||||
ensure_lib ./libraries/
|
||||
ensure_lib ./libraries/work
|
||||
vmap work ./libraries/work
|
||||
if { $PRECOMP_DEVICE_LIB_FILE eq "" } {
|
||||
ensure_lib ./libraries/lpm_ver
|
||||
vmap lpm_ver ./libraries/lpm_ver
|
||||
ensure_lib ./libraries/sgate_ver
|
||||
vmap sgate_ver ./libraries/sgate_ver
|
||||
ensure_lib ./libraries/altera_ver
|
||||
vmap altera_ver ./libraries/altera_ver
|
||||
ensure_lib ./libraries/altera_mf_ver
|
||||
vmap altera_mf_ver ./libraries/altera_mf_ver
|
||||
ensure_lib ./libraries/altera_lnsim_ver
|
||||
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
|
||||
ensure_lib ./libraries/tennm_ver
|
||||
vmap tennm_ver ./libraries/tennm_ver
|
||||
ensure_lib ./libraries/tennm_sm_hps_ver
|
||||
vmap tennm_sm_hps_ver ./libraries/tennm_sm_hps_ver
|
||||
ensure_lib ./libraries/tennm_sm4_hssi_ver
|
||||
vmap tennm_sm4_hssi_ver ./libraries/tennm_sm4_hssi_ver
|
||||
ensure_lib ./libraries/tennm_revb_hvio_ver
|
||||
vmap tennm_revb_hvio_ver ./libraries/tennm_revb_hvio_ver
|
||||
ensure_lib ./libraries/tennm_revb_io96_ver
|
||||
vmap tennm_revb_io96_ver ./libraries/tennm_revb_io96_ver
|
||||
ensure_lib ./libraries/lpm
|
||||
vmap lpm ./libraries/lpm
|
||||
ensure_lib ./libraries/sgate
|
||||
vmap sgate ./libraries/sgate
|
||||
ensure_lib ./libraries/altera
|
||||
vmap altera ./libraries/altera
|
||||
ensure_lib ./libraries/altera_mf
|
||||
vmap altera_mf ./libraries/altera_mf
|
||||
ensure_lib ./libraries/altera_lnsim
|
||||
vmap altera_lnsim ./libraries/altera_lnsim
|
||||
ensure_lib ./libraries/tennm
|
||||
vmap tennm ./libraries/tennm
|
||||
ensure_lib ./libraries/tennm_sm_hps
|
||||
vmap tennm_sm_hps ./libraries/tennm_sm_hps
|
||||
ensure_lib ./libraries/tennm_sm4_hssi
|
||||
vmap tennm_sm4_hssi ./libraries/tennm_sm4_hssi
|
||||
ensure_lib ./libraries/tennm_revb_hvio
|
||||
vmap tennm_revb_hvio ./libraries/tennm_revb_hvio
|
||||
ensure_lib ./libraries/tennm_revb_io96
|
||||
vmap tennm_revb_io96 ./libraries/tennm_revb_io96
|
||||
} else {
|
||||
vmap -link $PRECOMP_DEVICE_LIB_FILE
|
||||
}
|
||||
set design_libraries [dict create]
|
||||
set design_libraries [dict merge $design_libraries [qsys_top::get_design_libraries]]
|
||||
set libraries [dict keys $design_libraries]
|
||||
foreach library $libraries {
|
||||
ensure_lib ./libraries/$library/
|
||||
vmap $library ./libraries/$library/
|
||||
lappend logical_libraries $library
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile device library files
|
||||
alias dev_com {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] dev_com"
|
||||
}
|
||||
if { $PRECOMP_DEVICE_LIB_FILE eq "" } {
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/aldec/tennm_atoms_ncrypt.sv" -work tennm_ver
|
||||
eval vlog -dpilib +define+fm7_fmica_SVA_OFF $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps_ver
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps_ver
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi_ver
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96_ver
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -work lpm
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.vhd" -work lpm
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -work sgate
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -work sgate
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -work altera_mf
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -work altera_mf
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -work altera_lnsim
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/aldec/tennm_atoms_ncrypt.sv" -work tennm
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -work tennm
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -work tennm
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96
|
||||
}
|
||||
ccomp -dpi -sc -o work "$QUARTUS_SIM_LIB_DIR/simsf_dpi.cpp"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# add device library elaboration and simulation properties
|
||||
append ELAB_OPTIONS " -sv_lib work"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile the design files in correct order
|
||||
alias com {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] com"
|
||||
}
|
||||
set design_files [dict create]
|
||||
set design_files [dict merge [qsys_top::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
|
||||
set common_design_files [dict values $design_files]
|
||||
foreach file $common_design_files {
|
||||
eval $file
|
||||
}
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [qsys_top::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
foreach file $design_files {
|
||||
eval $file
|
||||
}
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate top level design
|
||||
alias elab {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] elab"
|
||||
}
|
||||
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
|
||||
foreach library $logical_libraries { append elabcommand " -L $library" }
|
||||
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
|
||||
eval vsim +access +r $elabcommand
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate the top level design with -dbg -O2 option
|
||||
alias elab_debug {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] elab_debug"
|
||||
}
|
||||
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
|
||||
foreach library $logical_libraries { append elabcommand " -L $library" }
|
||||
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
|
||||
eval vsim -dbg -O2 +access +r $elabcommand
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design
|
||||
alias ld "
|
||||
dev_com
|
||||
com
|
||||
elab
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design with -dbg -O2
|
||||
alias ld_debug "
|
||||
dev_com
|
||||
com
|
||||
elab_debug
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Print out user commmand line aliases
|
||||
alias h {
|
||||
echo "List Of Command Line Aliases"
|
||||
echo
|
||||
echo "file_copy -- Copy ROM/RAM files to simulation directory"
|
||||
echo
|
||||
echo "dev_com -- Compile device library files"
|
||||
echo
|
||||
echo "com -- Compile the design files in correct order"
|
||||
echo
|
||||
echo "elab -- Elaborate top level design"
|
||||
echo
|
||||
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
|
||||
echo
|
||||
echo "ld -- Compile all the design files and elaborate the top level design"
|
||||
echo
|
||||
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
|
||||
echo
|
||||
echo
|
||||
echo
|
||||
echo "List Of Variables"
|
||||
echo
|
||||
echo "TOP_LEVEL_NAME -- Top level module name."
|
||||
echo " For most designs, this should be overridden"
|
||||
echo " to enable the elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
|
||||
echo
|
||||
echo "QSYS_SIMDIR -- Qsys base simulation directory."
|
||||
echo
|
||||
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
|
||||
echo
|
||||
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. "
|
||||
echo
|
||||
echo "PRECOMP_DEVICE_LIB_FILE -- Precompiled device library file."
|
||||
echo " Use this variable to provide library.cfg containing device library mapping and dev_com will be skipped"
|
||||
echo " If value is empty, device libraries will be compiled local"
|
||||
}
|
||||
file_copy
|
||||
h
|
||||
@@ -0,0 +1,34 @@
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:52:56
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script run_rivierapro_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to run the rivierapro_setup.tcl script for the following IP detected in
|
||||
# your Quartus project:
|
||||
# qsys_top
|
||||
#
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script to compile, elab and run the design without any customization.
|
||||
# For customization, please follow the steps mentioned in rivierapro_setup.tcl.
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
|
||||
ld
|
||||
run -all
|
||||
quit
|
||||
@@ -0,0 +1,168 @@
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/rst_in/sim/common/modelsim_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../hps_subsys/hps_subsys/sim/common/modelsim_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/clk_100/sim/common/modelsim_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/user_rst_clkgate_0/sim/common/modelsim_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../peripheral_subsys/peripheral_subsys/sim/common/modelsim_files.tcl]
|
||||
|
||||
namespace eval qsys_top {
|
||||
proc get_design_libraries {} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [rst_in::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [hps_subsys::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [clk_100::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [user_rst_clkgate_0::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [peripheral_subsys::get_design_libraries]]
|
||||
dict set libraries altera_merlin_axi_translator_1987 1
|
||||
dict set libraries altera_merlin_slave_translator_191 1
|
||||
dict set libraries altera_merlin_axi_master_ni_19117 1
|
||||
dict set libraries altera_merlin_slave_agent_1930 1
|
||||
dict set libraries altera_avalon_sc_fifo_1932 1
|
||||
dict set libraries altera_merlin_router_1921 1
|
||||
dict set libraries altera_avalon_st_pipeline_stage_1930 1
|
||||
dict set libraries altera_merlin_burst_adapter_1940 1
|
||||
dict set libraries altera_merlin_demultiplexer_1921 1
|
||||
dict set libraries altera_merlin_multiplexer_1922 1
|
||||
dict set libraries altera_mm_interconnect_1920 1
|
||||
dict set libraries altera_irq_mapper_2001 1
|
||||
dict set libraries altera_reset_controller_1924 1
|
||||
dict set libraries qsys_top 1
|
||||
return $libraries
|
||||
}
|
||||
|
||||
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [rst_in::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [hps_subsys::get_memory_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [clk_100::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [user_rst_clkgate_0::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [peripheral_subsys::get_memory_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
return $memory_files
|
||||
}
|
||||
|
||||
proc get_common_design_files {QSYS_SIMDIR} {
|
||||
set design_files [dict create]
|
||||
set design_files [dict merge $design_files [rst_in::get_common_design_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
|
||||
set design_files [dict merge $design_files [hps_subsys::get_common_design_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
|
||||
set design_files [dict merge $design_files [clk_100::get_common_design_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
|
||||
set design_files [dict merge $design_files [user_rst_clkgate_0::get_common_design_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
|
||||
set design_files [dict merge $design_files [peripheral_subsys::get_common_design_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_design_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [rst_in::get_design_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [hps_subsys::get_design_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [clk_100::get_design_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [user_rst_clkgate_0::get_design_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [peripheral_subsys::get_design_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
lappend design_files "-makelib altera_merlin_axi_translator_1987 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_slave_translator_191 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_axi_master_ni_19117 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_axi_master_ni_19117 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_slave_agent_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_slave_agent_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_avalon_sc_fifo_1932 \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_router_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_router_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_avalon_st_pipeline_stage_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_avalon_st_pipeline_stage_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_demultiplexer_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_demultiplexer_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_mm_interconnect_1920 \"[normalize_path "$QSYS_SIMDIR/../altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v"]\" -end"
|
||||
lappend design_files "-makelib altera_irq_mapper_2001 \"[normalize_path "$QSYS_SIMDIR/../altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_reset_controller_1924 \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_controller.v"]\" -end"
|
||||
lappend design_files "-makelib altera_reset_controller_1924 \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_synchronizer.v"]\" -end"
|
||||
lappend design_files "-makelib qsys_top \"[normalize_path "$QSYS_SIMDIR/qsys_top.v"]\" -end"
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
|
||||
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
|
||||
if {$IS_DUPLICATE == -1} {
|
||||
return $NEW_ELAB_OPTION
|
||||
} else {
|
||||
return ""
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [rst_in::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [hps_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [clk_100::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [user_rst_clkgate_0::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [peripheral_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ELAB_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [rst_in::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [hps_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [clk_100::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [user_rst_clkgate_0::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [peripheral_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $SIM_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
|
||||
set ENV_VARIABLES [dict create]
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [rst_in::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [hps_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [clk_100::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [user_rst_clkgate_0::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [peripheral_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ENV_VARIABLES
|
||||
}
|
||||
|
||||
|
||||
proc normalize_path {FILEPATH} {
|
||||
if {[catch { package require fileutil } err]} {
|
||||
return $FILEPATH
|
||||
}
|
||||
set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]
|
||||
if {[file pathtype $FILEPATH] eq "relative"} {
|
||||
set path [fileutil::relative [pwd] $path]
|
||||
}
|
||||
return $path
|
||||
}
|
||||
proc get_dpi_libraries {QSYS_SIMDIR} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [rst_in::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
|
||||
set libraries [dict merge $libraries [hps_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
|
||||
set libraries [dict merge $libraries [clk_100::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
|
||||
set libraries [dict merge $libraries [user_rst_clkgate_0::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
|
||||
set libraries [dict merge $libraries [peripheral_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
|
||||
|
||||
return $libraries
|
||||
}
|
||||
|
||||
}
|
||||
@@ -0,0 +1,168 @@
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/rst_in/sim/common/riviera_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../hps_subsys/hps_subsys/sim/common/riviera_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/clk_100/sim/common/riviera_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/user_rst_clkgate_0/sim/common/riviera_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../peripheral_subsys/peripheral_subsys/sim/common/riviera_files.tcl]
|
||||
|
||||
namespace eval qsys_top {
|
||||
proc get_design_libraries {} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [rst_in::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [hps_subsys::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [clk_100::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [user_rst_clkgate_0::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [peripheral_subsys::get_design_libraries]]
|
||||
dict set libraries altera_merlin_axi_translator_1987 1
|
||||
dict set libraries altera_merlin_slave_translator_191 1
|
||||
dict set libraries altera_merlin_axi_master_ni_19117 1
|
||||
dict set libraries altera_merlin_slave_agent_1930 1
|
||||
dict set libraries altera_avalon_sc_fifo_1932 1
|
||||
dict set libraries altera_merlin_router_1921 1
|
||||
dict set libraries altera_avalon_st_pipeline_stage_1930 1
|
||||
dict set libraries altera_merlin_burst_adapter_1940 1
|
||||
dict set libraries altera_merlin_demultiplexer_1921 1
|
||||
dict set libraries altera_merlin_multiplexer_1922 1
|
||||
dict set libraries altera_mm_interconnect_1920 1
|
||||
dict set libraries altera_irq_mapper_2001 1
|
||||
dict set libraries altera_reset_controller_1924 1
|
||||
dict set libraries qsys_top 1
|
||||
return $libraries
|
||||
}
|
||||
|
||||
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [rst_in::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [hps_subsys::get_memory_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [clk_100::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [user_rst_clkgate_0::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [peripheral_subsys::get_memory_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
return $memory_files
|
||||
}
|
||||
|
||||
proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
|
||||
set design_files [dict create]
|
||||
set design_files [dict merge $design_files [rst_in::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
|
||||
set design_files [dict merge $design_files [hps_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
|
||||
set design_files [dict merge $design_files [clk_100::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
|
||||
set design_files [dict merge $design_files [user_rst_clkgate_0::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
|
||||
set design_files [dict merge $design_files [peripheral_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [rst_in::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [hps_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [clk_100::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [user_rst_clkgate_0::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [peripheral_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv"]\" -work altera_merlin_axi_translator_1987"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv"]\" -work altera_merlin_slave_translator_191"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv"]\" -work altera_merlin_axi_master_ni_19117"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv"]\" -work altera_merlin_axi_master_ni_19117"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv"]\" -work altera_merlin_slave_agent_1930"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv"]\" -work altera_merlin_slave_agent_1930"
|
||||
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v"]\" -work altera_avalon_sc_fifo_1932"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv"]\" -work altera_merlin_router_1921"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv"]\" -work altera_merlin_router_1921"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv"]\" -work altera_avalon_st_pipeline_stage_1930"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v"]\" -work altera_avalon_st_pipeline_stage_1930"
|
||||
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v"]\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv"]\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv"]\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv"]\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv"]\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv"]\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv"]\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv"]\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv"]\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv"]\" -work altera_merlin_demultiplexer_1921"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv"]\" -work altera_merlin_multiplexer_1922"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\" -work altera_merlin_multiplexer_1922"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv"]\" -work altera_merlin_demultiplexer_1921"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv"]\" -work altera_merlin_multiplexer_1922"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\" -work altera_merlin_multiplexer_1922"
|
||||
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v"]\" -work altera_mm_interconnect_1920"
|
||||
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv"]\" -work altera_irq_mapper_2001"
|
||||
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_controller.v"]\" -work altera_reset_controller_1924"
|
||||
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_synchronizer.v"]\" -work altera_reset_controller_1924"
|
||||
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/qsys_top.v"]\" -work qsys_top"
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
|
||||
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
|
||||
if {$IS_DUPLICATE == -1} {
|
||||
return $NEW_ELAB_OPTION
|
||||
} else {
|
||||
return ""
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [rst_in::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [hps_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [clk_100::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [user_rst_clkgate_0::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [peripheral_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ELAB_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [rst_in::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [hps_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [clk_100::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [user_rst_clkgate_0::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [peripheral_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $SIM_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
|
||||
set ENV_VARIABLES [dict create]
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [rst_in::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [hps_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [clk_100::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [user_rst_clkgate_0::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [peripheral_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ENV_VARIABLES
|
||||
}
|
||||
|
||||
|
||||
proc normalize_path {FILEPATH} {
|
||||
if {[catch { package require fileutil } err]} {
|
||||
return $FILEPATH
|
||||
}
|
||||
set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]
|
||||
if {[file pathtype $FILEPATH] eq "relative"} {
|
||||
set path [fileutil::relative [pwd] $path]
|
||||
}
|
||||
return $path
|
||||
}
|
||||
proc get_dpi_libraries {QSYS_SIMDIR} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [rst_in::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
|
||||
set libraries [dict merge $libraries [hps_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
|
||||
set libraries [dict merge $libraries [clk_100::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
|
||||
set libraries [dict merge $libraries [user_rst_clkgate_0::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
|
||||
set libraries [dict merge $libraries [peripheral_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
|
||||
|
||||
return $libraries
|
||||
}
|
||||
|
||||
}
|
||||
@@ -0,0 +1,158 @@
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/rst_in/sim/common/vcsmx_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../hps_subsys/hps_subsys/sim/common/vcsmx_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/clk_100/sim/common/vcsmx_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/user_rst_clkgate_0/sim/common/vcsmx_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../peripheral_subsys/peripheral_subsys/sim/common/vcsmx_files.tcl]
|
||||
|
||||
namespace eval qsys_top {
|
||||
proc get_design_libraries {} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [rst_in::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [hps_subsys::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [clk_100::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [user_rst_clkgate_0::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [peripheral_subsys::get_design_libraries]]
|
||||
dict set libraries altera_merlin_axi_translator_1987 1
|
||||
dict set libraries altera_merlin_slave_translator_191 1
|
||||
dict set libraries altera_merlin_axi_master_ni_19117 1
|
||||
dict set libraries altera_merlin_slave_agent_1930 1
|
||||
dict set libraries altera_avalon_sc_fifo_1932 1
|
||||
dict set libraries altera_merlin_router_1921 1
|
||||
dict set libraries altera_avalon_st_pipeline_stage_1930 1
|
||||
dict set libraries altera_merlin_burst_adapter_1940 1
|
||||
dict set libraries altera_merlin_demultiplexer_1921 1
|
||||
dict set libraries altera_merlin_multiplexer_1922 1
|
||||
dict set libraries altera_mm_interconnect_1920 1
|
||||
dict set libraries altera_irq_mapper_2001 1
|
||||
dict set libraries altera_reset_controller_1924 1
|
||||
dict set libraries qsys_top 1
|
||||
return $libraries
|
||||
}
|
||||
|
||||
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [rst_in::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [hps_subsys::get_memory_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [clk_100::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [user_rst_clkgate_0::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [peripheral_subsys::get_memory_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
return $memory_files
|
||||
}
|
||||
|
||||
proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
|
||||
set design_files [dict create]
|
||||
set design_files [dict merge $design_files [rst_in::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
|
||||
set design_files [dict merge $design_files [hps_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
|
||||
set design_files [dict merge $design_files [clk_100::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
|
||||
set design_files [dict merge $design_files [user_rst_clkgate_0::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
|
||||
set design_files [dict merge $design_files [peripheral_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [rst_in::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [hps_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [clk_100::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [user_rst_clkgate_0::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [peripheral_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv\" -work altera_merlin_axi_translator_1987"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv\" -work altera_merlin_slave_translator_191"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv\" -work altera_merlin_axi_master_ni_19117"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv\" -work altera_merlin_axi_master_ni_19117"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv\" -work altera_merlin_slave_agent_1930"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv\" -work altera_merlin_slave_agent_1930"
|
||||
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v\" -work altera_avalon_sc_fifo_1932"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv\" -work altera_merlin_router_1921"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv\" -work altera_merlin_router_1921"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv\" -work altera_avalon_st_pipeline_stage_1930"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v\" -work altera_avalon_st_pipeline_stage_1930"
|
||||
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv\" -work altera_merlin_demultiplexer_1921"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv\" -work altera_merlin_multiplexer_1922"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv\" -work altera_merlin_multiplexer_1922"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv\" -work altera_merlin_demultiplexer_1921"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv\" -work altera_merlin_multiplexer_1922"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv\" -work altera_merlin_multiplexer_1922"
|
||||
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v\" -work altera_mm_interconnect_1920"
|
||||
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv\" -work altera_irq_mapper_2001"
|
||||
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_controller.v\" -work altera_reset_controller_1924"
|
||||
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_synchronizer.v\" -work altera_reset_controller_1924"
|
||||
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/qsys_top.v\" -work qsys_top"
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
|
||||
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
|
||||
if {$IS_DUPLICATE == -1} {
|
||||
return $NEW_ELAB_OPTION
|
||||
} else {
|
||||
return ""
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [rst_in::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [hps_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [clk_100::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [user_rst_clkgate_0::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [peripheral_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ELAB_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [rst_in::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [hps_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [clk_100::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [user_rst_clkgate_0::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [peripheral_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $SIM_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
|
||||
set ENV_VARIABLES [dict create]
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [rst_in::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [hps_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [clk_100::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [user_rst_clkgate_0::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [peripheral_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ENV_VARIABLES
|
||||
}
|
||||
|
||||
|
||||
proc get_dpi_libraries {QSYS_SIMDIR} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [rst_in::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
|
||||
set libraries [dict merge $libraries [hps_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
|
||||
set libraries [dict merge $libraries [clk_100::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
|
||||
set libraries [dict merge $libraries [user_rst_clkgate_0::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
|
||||
set libraries [dict merge $libraries [peripheral_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
|
||||
|
||||
return $libraries
|
||||
}
|
||||
|
||||
}
|
||||
@@ -0,0 +1,158 @@
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/rst_in/sim/common/xcelium_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../hps_subsys/hps_subsys/sim/common/xcelium_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/clk_100/sim/common/xcelium_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/user_rst_clkgate_0/sim/common/xcelium_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../peripheral_subsys/peripheral_subsys/sim/common/xcelium_files.tcl]
|
||||
|
||||
namespace eval qsys_top {
|
||||
proc get_design_libraries {} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [rst_in::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [hps_subsys::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [clk_100::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [user_rst_clkgate_0::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [peripheral_subsys::get_design_libraries]]
|
||||
dict set libraries altera_merlin_axi_translator_1987 1
|
||||
dict set libraries altera_merlin_slave_translator_191 1
|
||||
dict set libraries altera_merlin_axi_master_ni_19117 1
|
||||
dict set libraries altera_merlin_slave_agent_1930 1
|
||||
dict set libraries altera_avalon_sc_fifo_1932 1
|
||||
dict set libraries altera_merlin_router_1921 1
|
||||
dict set libraries altera_avalon_st_pipeline_stage_1930 1
|
||||
dict set libraries altera_merlin_burst_adapter_1940 1
|
||||
dict set libraries altera_merlin_demultiplexer_1921 1
|
||||
dict set libraries altera_merlin_multiplexer_1922 1
|
||||
dict set libraries altera_mm_interconnect_1920 1
|
||||
dict set libraries altera_irq_mapper_2001 1
|
||||
dict set libraries altera_reset_controller_1924 1
|
||||
dict set libraries qsys_top 1
|
||||
return $libraries
|
||||
}
|
||||
|
||||
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [rst_in::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [hps_subsys::get_memory_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [clk_100::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [user_rst_clkgate_0::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [peripheral_subsys::get_memory_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
return $memory_files
|
||||
}
|
||||
|
||||
proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
|
||||
set design_files [dict create]
|
||||
set design_files [dict merge $design_files [rst_in::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
|
||||
set design_files [dict merge $design_files [hps_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
|
||||
set design_files [dict merge $design_files [clk_100::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
|
||||
set design_files [dict merge $design_files [user_rst_clkgate_0::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
|
||||
set design_files [dict merge $design_files [peripheral_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [rst_in::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [hps_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [clk_100::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [user_rst_clkgate_0::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [peripheral_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv\" -work altera_merlin_axi_translator_1987 -cdslib ./cds_libs/altera_merlin_axi_translator_1987.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv\" -work altera_merlin_slave_translator_191 -cdslib ./cds_libs/altera_merlin_slave_translator_191.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv\" -work altera_merlin_axi_master_ni_19117 -cdslib ./cds_libs/altera_merlin_axi_master_ni_19117.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv\" -work altera_merlin_axi_master_ni_19117 -cdslib ./cds_libs/altera_merlin_axi_master_ni_19117.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv\" -work altera_merlin_slave_agent_1930 -cdslib ./cds_libs/altera_merlin_slave_agent_1930.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv\" -work altera_merlin_slave_agent_1930 -cdslib ./cds_libs/altera_merlin_slave_agent_1930.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v\" -work altera_avalon_sc_fifo_1932 -cdslib ./cds_libs/altera_avalon_sc_fifo_1932.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv\" -work altera_merlin_router_1921 -cdslib ./cds_libs/altera_merlin_router_1921.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv\" -work altera_merlin_router_1921 -cdslib ./cds_libs/altera_merlin_router_1921.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv\" -work altera_avalon_st_pipeline_stage_1930 -cdslib ./cds_libs/altera_avalon_st_pipeline_stage_1930.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v\" -work altera_avalon_st_pipeline_stage_1930 -cdslib ./cds_libs/altera_avalon_st_pipeline_stage_1930.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v\" -work altera_merlin_burst_adapter_1940"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv\" -work altera_merlin_demultiplexer_1921 -cdslib ./cds_libs/altera_merlin_demultiplexer_1921.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv\" -work altera_merlin_multiplexer_1922 -cdslib ./cds_libs/altera_merlin_multiplexer_1922.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv\" -work altera_merlin_multiplexer_1922 -cdslib ./cds_libs/altera_merlin_multiplexer_1922.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv\" -work altera_merlin_demultiplexer_1921 -cdslib ./cds_libs/altera_merlin_demultiplexer_1921.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv\" -work altera_merlin_multiplexer_1922 -cdslib ./cds_libs/altera_merlin_multiplexer_1922.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv\" -work altera_merlin_multiplexer_1922 -cdslib ./cds_libs/altera_merlin_multiplexer_1922.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v\" -work altera_mm_interconnect_1920"
|
||||
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv\" -work altera_irq_mapper_2001 -cdslib ./cds_libs/altera_irq_mapper_2001.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_controller.v\" -work altera_reset_controller_1924 -cdslib ./cds_libs/altera_reset_controller_1924.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_synchronizer.v\" -work altera_reset_controller_1924 -cdslib ./cds_libs/altera_reset_controller_1924.cds.lib"
|
||||
lappend design_files "xmvlog -zlib 1 -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/qsys_top.v\" -work qsys_top"
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
|
||||
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
|
||||
if {$IS_DUPLICATE == -1} {
|
||||
return $NEW_ELAB_OPTION
|
||||
} else {
|
||||
return ""
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [rst_in::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [hps_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [clk_100::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [user_rst_clkgate_0::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [peripheral_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ELAB_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [rst_in::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [hps_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [clk_100::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [user_rst_clkgate_0::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [peripheral_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $SIM_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
|
||||
set ENV_VARIABLES [dict create]
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [rst_in::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [hps_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [clk_100::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [user_rst_clkgate_0::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [peripheral_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ENV_VARIABLES
|
||||
}
|
||||
|
||||
|
||||
proc get_dpi_libraries {QSYS_SIMDIR} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [rst_in::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
|
||||
set libraries [dict merge $libraries [hps_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
|
||||
set libraries [dict merge $libraries [clk_100::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
|
||||
set libraries [dict merge $libraries [user_rst_clkgate_0::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
|
||||
set libraries [dict merge $libraries [peripheral_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
|
||||
|
||||
return $libraries
|
||||
}
|
||||
|
||||
}
|
||||
@@ -0,0 +1,505 @@
|
||||
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script msim_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# qsys_top
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level script that compiles Intel simulation libraries and
|
||||
# the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "mentor.do", and modify the text as directed.
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# set QSYS_SIMDIR <script generation output directory>
|
||||
# #
|
||||
# # Source the generated IP simulation script.
|
||||
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
|
||||
# #
|
||||
# # Set any compilation options you require (this is unusual).
|
||||
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
|
||||
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
|
||||
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
|
||||
# #
|
||||
# # Call command to compile the Quartus EDA simulation library.
|
||||
# dev_com
|
||||
# #
|
||||
# # Call command to compile the Quartus-generated IP simulation files.
|
||||
# com
|
||||
# #
|
||||
# # Add commands to compile all design files and testbench files, including
|
||||
# # the top level. (These are all the files required for simulation other
|
||||
# # than the files compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# vlog <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # Set the top-level simulation or testbench module/entity name, which is
|
||||
# # used by the elab command to elaborate the top level.
|
||||
# #
|
||||
# set TOP_LEVEL_NAME <simulation top>
|
||||
# #
|
||||
# # Set any elaboration options you require.
|
||||
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
|
||||
# #
|
||||
# # Call command to elaborate your design and testbench.
|
||||
# elab
|
||||
# #
|
||||
# # Run the simulation.
|
||||
# run -a
|
||||
# #
|
||||
# # Report success to the shell.
|
||||
# exit -code 0
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If qsys_top is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Intel IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Intel IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:52:56
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize variables
|
||||
if ![info exists SYSTEM_INSTANCE_NAME] {
|
||||
set SYSTEM_INSTANCE_NAME ""
|
||||
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
|
||||
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
|
||||
}
|
||||
|
||||
if ![info exists TOP_LEVEL_NAME] {
|
||||
set TOP_LEVEL_NAME "qsys_top.qsys_top"
|
||||
}
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_INSTALL_DIR] {
|
||||
set QUARTUS_INSTALL_DIR "/opt/altera_pro/26.1/quartus/"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_SIM_LIB_DIR] {
|
||||
set QUARTUS_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/eda/sim_lib/"
|
||||
}
|
||||
|
||||
if ![info exists DEVICES_SIM_LIB_DIR] {
|
||||
set DEVICES_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
|
||||
set USER_DEFINED_ELAB_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists SILENCE] {
|
||||
set SILENCE "false"
|
||||
}
|
||||
|
||||
if ![info exists PRECOMP_DEVICE_LIB_FILE] {
|
||||
set PRECOMP_DEVICE_LIB_FILE ""
|
||||
}
|
||||
|
||||
if ![info exists FORCE_MODELSIM_AE_SELECTION] {
|
||||
set FORCE_MODELSIM_AE_SELECTION "false"
|
||||
}
|
||||
if ![info exists ENABLE_QE_LIBRARY_COMPILATION] {
|
||||
set ENABLE_QE_LIBRARY_COMPILATION "false"
|
||||
}
|
||||
|
||||
#-------------------------------------------
|
||||
# read .tcl file to override initialized variables
|
||||
if { [info exists ::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)] && [file exist $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)] } {
|
||||
echo "Sourcing $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)"
|
||||
source $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)
|
||||
}
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Source Common Tcl File
|
||||
source $QSYS_SIMDIR/common/modelsim_files.tcl
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize simulation properties - DO NOT MODIFY!
|
||||
set ELAB_OPTIONS ""
|
||||
set SIM_OPTIONS ""
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
if { ![ string match "*-64 vsim*" [ vsimVersionString ] ] } {
|
||||
set SIMULATOR_TOOL_BITNESS "bit_32"
|
||||
} else {
|
||||
set SIMULATOR_TOOL_BITNESS "bit_64"
|
||||
}
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [qsys_top::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
if {[dict size $LD_LIBRARY_PATH] !=0 } {
|
||||
set LD_LIBRARY_PATH [subst [join [dict keys $LD_LIBRARY_PATH] ":"]]
|
||||
setenv LD_LIBRARY_PATH "$LD_LIBRARY_PATH"
|
||||
}
|
||||
append ELAB_OPTIONS [subst [qsys_top::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append SIM_OPTIONS [subst [qsys_top::get_sim_options $SIMULATOR_TOOL_BITNESS]]
|
||||
|
||||
proc check_precomp_device {precomp_device_lib_path force_select_modelsim_ae enable_qe_library_compilation} {
|
||||
set len [string length $precomp_device_lib_path]
|
||||
if {($len == 0) && ([string is false -strict [modelsim_ae_select $force_select_modelsim_ae]] || [string is true -strict $enable_qe_library_compilation])} {
|
||||
return 1
|
||||
}
|
||||
return 0
|
||||
|
||||
}
|
||||
|
||||
proc modelsim_ae_select {force_select_modelsim_ae} {
|
||||
if [string is true -strict $force_select_modelsim_ae] {
|
||||
return 1
|
||||
}
|
||||
return [string match -nocase "*Altera*FPGA*" [ vsimVersionString ]]
|
||||
|
||||
}
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Copy ROM/RAM files to simulation directory
|
||||
alias file_copy {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] file_copy"
|
||||
}
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [qsys_top::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
foreach file $memory_files {
|
||||
set itercount 0
|
||||
while {$itercount < 10 && [file type $file] eq "link"} {
|
||||
set nf [file readlink $file]
|
||||
if {[string index $nf 0] ne "/"} {
|
||||
set nf [file dirname $file]/$nf
|
||||
}
|
||||
set file $nf
|
||||
}
|
||||
set dest_file [file join ./ [file tail $file]]
|
||||
set normalized_src [qsys_top::normalize_path "$file"]
|
||||
set normalized_dest [qsys_top::normalize_path "$dest_file"]
|
||||
if { $normalized_src ne $normalized_dest } {
|
||||
file copy -force $file ./
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
# ----------------------------------------
|
||||
# Modify modelsim.ini if precompiled device libraries are in use
|
||||
if { $PRECOMP_DEVICE_LIB_FILE ne "" } {
|
||||
echo "Modifying modelsim.ini according to $PRECOMP_DEVICE_LIB_FILE"
|
||||
set PRECOMP_DEVICE_LIB_FILE [string trim $PRECOMP_DEVICE_LIB_FILE]
|
||||
if { [file exists $PRECOMP_DEVICE_LIB_FILE] && [string match [file tail $PRECOMP_DEVICE_LIB_FILE] "modelsim.ini" ] } {
|
||||
if { [file exists "modelsim.ini"] } {
|
||||
echo "modelsim.ini already exists, making backup modelsim.ini.bak"
|
||||
file copy -force "modelsim.ini" "modelsim.ini.bak"
|
||||
}
|
||||
echo "Copying modelsim.ini from $PRECOMP_DEVICE_LIB_FILE"
|
||||
file copy -force $PRECOMP_DEVICE_LIB_FILE ./
|
||||
} elseif { [file exists $PRECOMP_DEVICE_LIB_FILE] && [string match "*tcl" [file tail $PRECOMP_DEVICE_LIB_FILE] ] } {
|
||||
echo "Running $PRECOMP_DEVICE_LIB_FILE to generate device library mapping"
|
||||
source $PRECOMP_DEVICE_LIB_FILE
|
||||
} else {
|
||||
echo "Unable to use $PRECOMP_DEVICE_LIB_FILE for device library mapping. Switching back to local library compilation"
|
||||
set PRECOMP_DEVICE_LIB_FILE ""
|
||||
}
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Create compilation libraries
|
||||
|
||||
set logical_libraries [list "work" "work_lib" "lpm_ver" "sgate_ver" "altera_ver" "altera_mf_ver" "altera_lnsim_ver" "tennm_ver" "tennm_sm_hps_ver" "tennm_sm4_hssi_ver" "tennm_revb_hvio_ver" "tennm_revb_io96_ver" "lpm" "sgate" "altera" "altera_mf" "altera_lnsim" "tennm" "tennm_sm_hps" "tennm_sm4_hssi" "tennm_revb_hvio" "tennm_revb_io96"]
|
||||
|
||||
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
|
||||
ensure_lib ./libraries/
|
||||
ensure_lib ./libraries/work/
|
||||
vmap work ./libraries/work/
|
||||
vmap work_lib ./libraries/work/
|
||||
|
||||
# ----------------------------------------
|
||||
# get DPI libraries
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [qsys_top::get_dpi_libraries "$QSYS_SIMDIR"]]
|
||||
set dpi_libraries [dict values $libraries]
|
||||
|
||||
# ----------------------------------------
|
||||
# setup shared libraries
|
||||
set DPI_LIBRARIES_ELAB ""
|
||||
if { [llength $dpi_libraries] != 0 } {
|
||||
echo "Using DPI Library settings"
|
||||
foreach library $dpi_libraries {
|
||||
append DPI_LIBRARIES_ELAB "-sv_lib $library "
|
||||
}
|
||||
}
|
||||
|
||||
if [ check_precomp_device $PRECOMP_DEVICE_LIB_FILE $FORCE_MODELSIM_AE_SELECTION $ENABLE_QE_LIBRARY_COMPILATION ] {
|
||||
ensure_lib ./libraries/lpm_ver/
|
||||
vmap lpm_ver ./libraries/lpm_ver/
|
||||
ensure_lib ./libraries/sgate_ver/
|
||||
vmap sgate_ver ./libraries/sgate_ver/
|
||||
ensure_lib ./libraries/altera_ver/
|
||||
vmap altera_ver ./libraries/altera_ver/
|
||||
ensure_lib ./libraries/altera_mf_ver/
|
||||
vmap altera_mf_ver ./libraries/altera_mf_ver/
|
||||
ensure_lib ./libraries/altera_lnsim_ver/
|
||||
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
|
||||
ensure_lib ./libraries/tennm_ver/
|
||||
vmap tennm_ver ./libraries/tennm_ver/
|
||||
ensure_lib ./libraries/tennm_sm_hps_ver/
|
||||
vmap tennm_sm_hps_ver ./libraries/tennm_sm_hps_ver/
|
||||
ensure_lib ./libraries/tennm_sm4_hssi_ver/
|
||||
vmap tennm_sm4_hssi_ver ./libraries/tennm_sm4_hssi_ver/
|
||||
ensure_lib ./libraries/tennm_revb_hvio_ver/
|
||||
vmap tennm_revb_hvio_ver ./libraries/tennm_revb_hvio_ver/
|
||||
ensure_lib ./libraries/tennm_revb_io96_ver/
|
||||
vmap tennm_revb_io96_ver ./libraries/tennm_revb_io96_ver/
|
||||
ensure_lib ./libraries/lpm/
|
||||
vmap lpm ./libraries/lpm/
|
||||
ensure_lib ./libraries/sgate/
|
||||
vmap sgate ./libraries/sgate/
|
||||
ensure_lib ./libraries/altera/
|
||||
vmap altera ./libraries/altera/
|
||||
ensure_lib ./libraries/altera_mf/
|
||||
vmap altera_mf ./libraries/altera_mf/
|
||||
ensure_lib ./libraries/altera_lnsim/
|
||||
vmap altera_lnsim ./libraries/altera_lnsim/
|
||||
ensure_lib ./libraries/tennm/
|
||||
vmap tennm ./libraries/tennm/
|
||||
ensure_lib ./libraries/tennm_sm_hps/
|
||||
vmap tennm_sm_hps ./libraries/tennm_sm_hps/
|
||||
ensure_lib ./libraries/tennm_sm4_hssi/
|
||||
vmap tennm_sm4_hssi ./libraries/tennm_sm4_hssi/
|
||||
ensure_lib ./libraries/tennm_revb_hvio/
|
||||
vmap tennm_revb_hvio ./libraries/tennm_revb_hvio/
|
||||
ensure_lib ./libraries/tennm_revb_io96/
|
||||
vmap tennm_revb_io96 ./libraries/tennm_revb_io96/
|
||||
}
|
||||
set design_libraries [dict create]
|
||||
set design_libraries [dict merge $design_libraries [qsys_top::get_design_libraries]]
|
||||
set libraries [dict keys $design_libraries]
|
||||
foreach library $libraries {
|
||||
ensure_lib ./libraries/$library/
|
||||
vmap $library ./libraries/$library/
|
||||
lappend logical_libraries $library
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile device library files
|
||||
alias dev_com {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] dev_com"
|
||||
}
|
||||
if [ check_precomp_device $PRECOMP_DEVICE_LIB_FILE $FORCE_MODELSIM_AE_SELECTION $ENABLE_QE_LIBRARY_COMPILATION ] {
|
||||
eval qrun -compile -noautoorder -parallel -outdir ./libraries -vlog.options $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS -end \
|
||||
-vcom.options $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS -end \
|
||||
-vlog.ext=+.vo -vlog.ext=+.vt -vcom.ext=+.vho -sv -suppress 13338 \
|
||||
-makelib lpm_ver "$QUARTUS_SIM_LIB_DIR/220model.v" -end \
|
||||
-makelib sgate_ver "$QUARTUS_SIM_LIB_DIR/sgate.v" -end \
|
||||
-makelib altera_ver "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -end \
|
||||
-makelib altera_mf_ver "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -end \
|
||||
-makelib altera_lnsim_ver "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -end \
|
||||
-makelib tennm_ver "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -end \
|
||||
-makelib tennm_ver "$QUARTUS_SIM_LIB_DIR/mentor/tennm_atoms_ncrypt.sv" -end \
|
||||
-makelib tennm_ver "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -end \
|
||||
-makelib tennm_sm_hps_ver "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -end \
|
||||
-makelib tennm_sm_hps_ver "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -end \
|
||||
-makelib tennm_sm4_hssi_ver "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -end \
|
||||
-makelib tennm_sm4_hssi_ver "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -suppress 7061,2583,13314,2244,2283,2600,3691 -end \
|
||||
-makelib tennm_revb_hvio_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -end \
|
||||
-makelib tennm_revb_hvio_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -suppress 2583 -end \
|
||||
-makelib tennm_revb_io96_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -end \
|
||||
-makelib tennm_revb_io96_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -end \
|
||||
-makelib lpm "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -end \
|
||||
-makelib lpm "$QUARTUS_SIM_LIB_DIR/220model.vhd" -end \
|
||||
-makelib sgate "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -end \
|
||||
-makelib sgate "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -end \
|
||||
-makelib altera_mf "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -end \
|
||||
-makelib altera_mf "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -end \
|
||||
-makelib altera_lnsim "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -end \
|
||||
-makelib altera_lnsim "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -end \
|
||||
-makelib tennm "$QUARTUS_SIM_LIB_DIR/mentor/tennm_atoms_ncrypt.sv" -end \
|
||||
-makelib tennm "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -end \
|
||||
-makelib tennm "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -end \
|
||||
-makelib tennm_sm_hps "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -end \
|
||||
-makelib tennm_sm_hps "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -end \
|
||||
-makelib tennm_sm4_hssi "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -end \
|
||||
-makelib tennm_sm4_hssi "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -suppress 7061,2583,13314,2244,2283,2600,3691 -end \
|
||||
-makelib tennm_revb_hvio "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -end \
|
||||
-makelib tennm_revb_hvio "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -suppress 2583 -end \
|
||||
-makelib tennm_revb_io96 "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -end \
|
||||
-makelib tennm_revb_io96 "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -end \
|
||||
|
||||
}
|
||||
eval qrun -compile -noautoorder -parallel -outdir ./libraries -vlog.options $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS -end \
|
||||
-vcom.options $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS -end \
|
||||
-vlog.ext=+.vo -vlog.ext=+.vt -vcom.ext=+.vho -sv -suppress 13338 \
|
||||
-makelib work "$QUARTUS_SIM_LIB_DIR/simsf_dpi.cpp" -end \
|
||||
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile the design files in correct order
|
||||
alias com {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] com"
|
||||
}
|
||||
set common_design_files [dict values [qsys_top::get_common_design_files "$QSYS_SIMDIR"]]
|
||||
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [qsys_top::get_design_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
set files [concat $common_design_files $design_files ]
|
||||
set files [join $files " \\\n"]
|
||||
set com_file [open "modelsim_com.f" w+]
|
||||
puts $com_file $files
|
||||
close $com_file
|
||||
eval qrun -compile -noautoorder -parallel -outdir ./libraries -vlog.options $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS -end \
|
||||
-vcom.options $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS -end \
|
||||
-vlog.ext=+.vo -vlog.ext=+.vt -vcom.ext=+.vho -sv -suppress 13338 \
|
||||
-f modelsim_com.f
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate top level design
|
||||
alias elab {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] elab"
|
||||
}
|
||||
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
|
||||
foreach library $logical_libraries { append elabcommand " -L $library" }
|
||||
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
|
||||
eval vsim $elabcommand
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate the top level design with -voptargs=+acc option
|
||||
alias elab_debug {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] elab_debug"
|
||||
}
|
||||
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
|
||||
foreach library $logical_libraries { append elabcommand " -L $library" }
|
||||
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
|
||||
eval vsim -voptargs=+acc $elabcommand
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design
|
||||
alias ld "
|
||||
dev_com
|
||||
com
|
||||
elab
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design with -voptargs=+acc
|
||||
alias ld_debug "
|
||||
dev_com
|
||||
com
|
||||
elab_debug
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Print out user commmand line aliases
|
||||
alias h {
|
||||
echo "List Of Command Line Aliases"
|
||||
echo
|
||||
echo "file_copy -- Copy ROM/RAM files to simulation directory"
|
||||
echo
|
||||
echo "dev_com -- Compile device library files"
|
||||
echo
|
||||
echo "com -- Compile the design files in correct order"
|
||||
echo
|
||||
echo "elab -- Elaborate top level design"
|
||||
echo
|
||||
echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option"
|
||||
echo
|
||||
echo "ld -- Compile all the design files and elaborate the top level design"
|
||||
echo
|
||||
echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
|
||||
echo
|
||||
echo
|
||||
echo
|
||||
echo "List Of Variables"
|
||||
echo
|
||||
echo "TOP_LEVEL_NAME -- Top level module name."
|
||||
echo " For most designs, this should be overridden"
|
||||
echo " to enable the elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
|
||||
echo
|
||||
echo "QSYS_SIMDIR -- Qsys base simulation directory."
|
||||
echo
|
||||
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
|
||||
echo
|
||||
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. "
|
||||
echo
|
||||
echo "PRECOMP_DEVICE_LIB_FILE -- Precompiled device library file."
|
||||
echo " Use this variable to provide modelsim.ini or tcl containing device library mapping and dev_com will be skipped"
|
||||
echo " If value is empty, device libraries will be compiled local"
|
||||
echo
|
||||
echo "FORCE_MODELSIM_AE_SELECTION -- Set to true to force to select Modelsim AE always."
|
||||
echo
|
||||
echo "ENABLE_QE_LIBRARY_COMPILATION -- Set to true to enable device library compilation for Questa FE."
|
||||
}
|
||||
file_copy
|
||||
h
|
||||
@@ -0,0 +1,34 @@
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:52:56
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script run_msim_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to run the msim_setup.tcl script for the following IP detected in
|
||||
# your Quartus project:
|
||||
# qsys_top
|
||||
#
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script to compile, elab and run the design without any customization.
|
||||
# For customization, please follow the steps mentioned in msim_setup.tcl.
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
source $QSYS_SIMDIR/mentor/msim_setup.tcl
|
||||
ld
|
||||
run -all
|
||||
quit
|
||||
@@ -0,0 +1,542 @@
|
||||
// qsys_top.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module qsys_top (
|
||||
input wire clk_100_clk, // clk_100.clk
|
||||
input wire reset_reset_n, // reset.reset_n
|
||||
output wire ninit_done_ninit_done, // ninit_done.ninit_done
|
||||
output wire h2f_reset_reset, // h2f_reset.reset
|
||||
output wire [3:0] subsys_hps_hps2fpga_awid, // subsys_hps_hps2fpga.awid
|
||||
output wire [37:0] subsys_hps_hps2fpga_awaddr, // .awaddr
|
||||
output wire [7:0] subsys_hps_hps2fpga_awlen, // .awlen
|
||||
output wire [2:0] subsys_hps_hps2fpga_awsize, // .awsize
|
||||
output wire [1:0] subsys_hps_hps2fpga_awburst, // .awburst
|
||||
output wire subsys_hps_hps2fpga_awlock, // .awlock
|
||||
output wire [3:0] subsys_hps_hps2fpga_awcache, // .awcache
|
||||
output wire [2:0] subsys_hps_hps2fpga_awprot, // .awprot
|
||||
output wire subsys_hps_hps2fpga_awvalid, // .awvalid
|
||||
input wire subsys_hps_hps2fpga_awready, // .awready
|
||||
output wire [127:0] subsys_hps_hps2fpga_wdata, // .wdata
|
||||
output wire [15:0] subsys_hps_hps2fpga_wstrb, // .wstrb
|
||||
output wire subsys_hps_hps2fpga_wlast, // .wlast
|
||||
output wire subsys_hps_hps2fpga_wvalid, // .wvalid
|
||||
input wire subsys_hps_hps2fpga_wready, // .wready
|
||||
input wire [3:0] subsys_hps_hps2fpga_bid, // .bid
|
||||
input wire [1:0] subsys_hps_hps2fpga_bresp, // .bresp
|
||||
input wire subsys_hps_hps2fpga_bvalid, // .bvalid
|
||||
output wire subsys_hps_hps2fpga_bready, // .bready
|
||||
output wire [3:0] subsys_hps_hps2fpga_arid, // .arid
|
||||
output wire [37:0] subsys_hps_hps2fpga_araddr, // .araddr
|
||||
output wire [7:0] subsys_hps_hps2fpga_arlen, // .arlen
|
||||
output wire [2:0] subsys_hps_hps2fpga_arsize, // .arsize
|
||||
output wire [1:0] subsys_hps_hps2fpga_arburst, // .arburst
|
||||
output wire subsys_hps_hps2fpga_arlock, // .arlock
|
||||
output wire [3:0] subsys_hps_hps2fpga_arcache, // .arcache
|
||||
output wire [2:0] subsys_hps_hps2fpga_arprot, // .arprot
|
||||
output wire subsys_hps_hps2fpga_arvalid, // .arvalid
|
||||
input wire subsys_hps_hps2fpga_arready, // .arready
|
||||
input wire [3:0] subsys_hps_hps2fpga_rid, // .rid
|
||||
input wire [127:0] subsys_hps_hps2fpga_rdata, // .rdata
|
||||
input wire [1:0] subsys_hps_hps2fpga_rresp, // .rresp
|
||||
input wire subsys_hps_hps2fpga_rlast, // .rlast
|
||||
input wire subsys_hps_hps2fpga_rvalid, // .rvalid
|
||||
output wire subsys_hps_hps2fpga_rready, // .rready
|
||||
output wire subsys_hps_h2f_warm_reset_handshake_reset_req, // subsys_hps_h2f_warm_reset_handshake.reset_req
|
||||
input wire subsys_hps_h2f_warm_reset_handshake_reset_ack, // .reset_ack
|
||||
input wire hps_io_hps_osc_clk, // hps_io.hps_osc_clk
|
||||
inout wire hps_io_sdmmc_data0, // .sdmmc_data0
|
||||
inout wire hps_io_sdmmc_data1, // .sdmmc_data1
|
||||
output wire hps_io_sdmmc_cclk, // .sdmmc_cclk
|
||||
inout wire hps_io_sdmmc_data2, // .sdmmc_data2
|
||||
inout wire hps_io_sdmmc_data3, // .sdmmc_data3
|
||||
inout wire hps_io_sdmmc_cmd, // .sdmmc_cmd
|
||||
input wire hps_io_usb0_clk, // .usb0_clk
|
||||
output wire hps_io_usb0_stp, // .usb0_stp
|
||||
input wire hps_io_usb0_dir, // .usb0_dir
|
||||
inout wire hps_io_usb0_data0, // .usb0_data0
|
||||
inout wire hps_io_usb0_data1, // .usb0_data1
|
||||
input wire hps_io_usb0_nxt, // .usb0_nxt
|
||||
inout wire hps_io_usb0_data2, // .usb0_data2
|
||||
inout wire hps_io_usb0_data3, // .usb0_data3
|
||||
inout wire hps_io_usb0_data4, // .usb0_data4
|
||||
inout wire hps_io_usb0_data5, // .usb0_data5
|
||||
inout wire hps_io_usb0_data6, // .usb0_data6
|
||||
inout wire hps_io_usb0_data7, // .usb0_data7
|
||||
output wire hps_io_emac0_tx_clk, // .emac0_tx_clk
|
||||
output wire hps_io_emac0_tx_ctl, // .emac0_tx_ctl
|
||||
input wire hps_io_emac0_rx_clk, // .emac0_rx_clk
|
||||
input wire hps_io_emac0_rx_ctl, // .emac0_rx_ctl
|
||||
output wire hps_io_emac0_txd0, // .emac0_txd0
|
||||
output wire hps_io_emac0_txd1, // .emac0_txd1
|
||||
input wire hps_io_emac0_rxd0, // .emac0_rxd0
|
||||
input wire hps_io_emac0_rxd1, // .emac0_rxd1
|
||||
output wire hps_io_emac0_txd2, // .emac0_txd2
|
||||
output wire hps_io_emac0_txd3, // .emac0_txd3
|
||||
input wire hps_io_emac0_rxd2, // .emac0_rxd2
|
||||
input wire hps_io_emac0_rxd3, // .emac0_rxd3
|
||||
inout wire hps_io_mdio0_mdio, // .mdio0_mdio
|
||||
output wire hps_io_mdio0_mdc, // .mdio0_mdc
|
||||
output wire hps_io_uart1_tx, // .uart1_tx
|
||||
input wire hps_io_uart1_rx, // .uart1_rx
|
||||
inout wire hps_io_i2c1_sda, // .i2c1_sda
|
||||
inout wire hps_io_i2c1_scl, // .i2c1_scl
|
||||
inout wire hps_io_gpio28, // .gpio28
|
||||
inout wire hps_io_gpio34, // .gpio34
|
||||
inout wire hps_io_gpio40, // .gpio40
|
||||
inout wire hps_io_gpio41, // .gpio41
|
||||
input wire [31:0] f2h_irq1_in_irq, // f2h_irq1_in.irq
|
||||
input wire [31:0] f2sdram_araddr, // f2sdram.araddr
|
||||
input wire [1:0] f2sdram_arburst, // .arburst
|
||||
input wire [3:0] f2sdram_arcache, // .arcache
|
||||
input wire [4:0] f2sdram_arid, // .arid
|
||||
input wire [7:0] f2sdram_arlen, // .arlen
|
||||
input wire f2sdram_arlock, // .arlock
|
||||
input wire [2:0] f2sdram_arprot, // .arprot
|
||||
input wire [3:0] f2sdram_arqos, // .arqos
|
||||
output wire f2sdram_arready, // .arready
|
||||
input wire [2:0] f2sdram_arsize, // .arsize
|
||||
input wire f2sdram_arvalid, // .arvalid
|
||||
input wire [31:0] f2sdram_awaddr, // .awaddr
|
||||
input wire [1:0] f2sdram_awburst, // .awburst
|
||||
input wire [3:0] f2sdram_awcache, // .awcache
|
||||
input wire [4:0] f2sdram_awid, // .awid
|
||||
input wire [7:0] f2sdram_awlen, // .awlen
|
||||
input wire f2sdram_awlock, // .awlock
|
||||
input wire [2:0] f2sdram_awprot, // .awprot
|
||||
input wire [3:0] f2sdram_awqos, // .awqos
|
||||
output wire f2sdram_awready, // .awready
|
||||
input wire [2:0] f2sdram_awsize, // .awsize
|
||||
input wire f2sdram_awvalid, // .awvalid
|
||||
output wire [4:0] f2sdram_bid, // .bid
|
||||
input wire f2sdram_bready, // .bready
|
||||
output wire [1:0] f2sdram_bresp, // .bresp
|
||||
output wire f2sdram_bvalid, // .bvalid
|
||||
output wire [255:0] f2sdram_rdata, // .rdata
|
||||
output wire [4:0] f2sdram_rid, // .rid
|
||||
output wire f2sdram_rlast, // .rlast
|
||||
input wire f2sdram_rready, // .rready
|
||||
output wire [1:0] f2sdram_rresp, // .rresp
|
||||
output wire f2sdram_rvalid, // .rvalid
|
||||
input wire [255:0] f2sdram_wdata, // .wdata
|
||||
input wire f2sdram_wlast, // .wlast
|
||||
output wire f2sdram_wready, // .wready
|
||||
input wire [31:0] f2sdram_wstrb, // .wstrb
|
||||
input wire f2sdram_wvalid, // .wvalid
|
||||
input wire [7:0] f2sdram_aruser, // .aruser
|
||||
input wire [7:0] f2sdram_awuser, // .awuser
|
||||
input wire [7:0] f2sdram_wuser, // .wuser
|
||||
output wire [7:0] f2sdram_buser, // .buser
|
||||
input wire [3:0] f2sdram_arregion, // .arregion
|
||||
output wire [7:0] f2sdram_ruser, // .ruser
|
||||
input wire [3:0] f2sdram_awregion, // .awregion
|
||||
output wire [0:0] emif_hps_emif_mem_0_mem_cs, // emif_hps_emif_mem_0.mem_cs
|
||||
output wire [5:0] emif_hps_emif_mem_0_mem_ca, // .mem_ca
|
||||
output wire [0:0] emif_hps_emif_mem_0_mem_cke, // .mem_cke
|
||||
inout wire [31:0] emif_hps_emif_mem_0_mem_dq, // .mem_dq
|
||||
inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_t, // .mem_dqs_t
|
||||
inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_c, // .mem_dqs_c
|
||||
inout wire [3:0] emif_hps_emif_mem_0_mem_dmi, // .mem_dmi
|
||||
output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_t, // emif_hps_emif_mem_ck_0.mem_ck_t
|
||||
output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_c, // .mem_ck_c
|
||||
output wire emif_hps_emif_mem_reset_n_mem_reset_n, // emif_hps_emif_mem_reset_n.mem_reset_n
|
||||
input wire emif_hps_emif_oct_0_oct_rzqin, // emif_hps_emif_oct_0.oct_rzqin
|
||||
input wire emif_hps_emif_ref_clk_0_clk, // emif_hps_emif_ref_clk_0.clk
|
||||
input wire [3:0] button_pio_external_connection_export, // button_pio_external_connection.export
|
||||
input wire [3:0] dipsw_pio_external_connection_export, // dipsw_pio_external_connection.export
|
||||
input wire [2:0] led_pio_external_connection_in_port, // led_pio_external_connection.in_port
|
||||
output wire [2:0] led_pio_external_connection_out_port // .out_port
|
||||
);
|
||||
|
||||
wire clk_100_out_clk_clk; // clk_100:out_clk -> [mm_interconnect_0:clk_100_out_clk_clk, rst_controller:clk, subsys_hps:f2sdram_clk_clk, subsys_hps:hps2fpga_clk_clk, subsys_hps:lwhps2fpga_clk_clk, subsys_periph:clk_clk]
|
||||
wire rst_in_out_reset_reset; // rst_in:out_reset_n -> [rst_controller:reset_in0, subsys_hps:f2sdram_rst_reset, subsys_hps:hps2fpga_rst_reset, subsys_hps:lwhps2fpga_rst_reset, subsys_periph:reset_reset_n]
|
||||
wire [1:0] subsys_hps_lwhps2fpga_awburst; // subsys_hps:lwhps2fpga_awburst -> mm_interconnect_0:subsys_hps_lwhps2fpga_awburst
|
||||
wire [7:0] subsys_hps_lwhps2fpga_arlen; // subsys_hps:lwhps2fpga_arlen -> mm_interconnect_0:subsys_hps_lwhps2fpga_arlen
|
||||
wire [3:0] subsys_hps_lwhps2fpga_wstrb; // subsys_hps:lwhps2fpga_wstrb -> mm_interconnect_0:subsys_hps_lwhps2fpga_wstrb
|
||||
wire subsys_hps_lwhps2fpga_wready; // mm_interconnect_0:subsys_hps_lwhps2fpga_wready -> subsys_hps:lwhps2fpga_wready
|
||||
wire [3:0] subsys_hps_lwhps2fpga_rid; // mm_interconnect_0:subsys_hps_lwhps2fpga_rid -> subsys_hps:lwhps2fpga_rid
|
||||
wire subsys_hps_lwhps2fpga_rready; // subsys_hps:lwhps2fpga_rready -> mm_interconnect_0:subsys_hps_lwhps2fpga_rready
|
||||
wire [7:0] subsys_hps_lwhps2fpga_awlen; // subsys_hps:lwhps2fpga_awlen -> mm_interconnect_0:subsys_hps_lwhps2fpga_awlen
|
||||
wire [3:0] subsys_hps_lwhps2fpga_arcache; // subsys_hps:lwhps2fpga_arcache -> mm_interconnect_0:subsys_hps_lwhps2fpga_arcache
|
||||
wire subsys_hps_lwhps2fpga_wvalid; // subsys_hps:lwhps2fpga_wvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_wvalid
|
||||
wire [28:0] subsys_hps_lwhps2fpga_araddr; // subsys_hps:lwhps2fpga_araddr -> mm_interconnect_0:subsys_hps_lwhps2fpga_araddr
|
||||
wire [2:0] subsys_hps_lwhps2fpga_arprot; // subsys_hps:lwhps2fpga_arprot -> mm_interconnect_0:subsys_hps_lwhps2fpga_arprot
|
||||
wire [2:0] subsys_hps_lwhps2fpga_awprot; // subsys_hps:lwhps2fpga_awprot -> mm_interconnect_0:subsys_hps_lwhps2fpga_awprot
|
||||
wire [31:0] subsys_hps_lwhps2fpga_wdata; // subsys_hps:lwhps2fpga_wdata -> mm_interconnect_0:subsys_hps_lwhps2fpga_wdata
|
||||
wire subsys_hps_lwhps2fpga_arvalid; // subsys_hps:lwhps2fpga_arvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_arvalid
|
||||
wire [3:0] subsys_hps_lwhps2fpga_awcache; // subsys_hps:lwhps2fpga_awcache -> mm_interconnect_0:subsys_hps_lwhps2fpga_awcache
|
||||
wire [3:0] subsys_hps_lwhps2fpga_arid; // subsys_hps:lwhps2fpga_arid -> mm_interconnect_0:subsys_hps_lwhps2fpga_arid
|
||||
wire subsys_hps_lwhps2fpga_arlock; // subsys_hps:lwhps2fpga_arlock -> mm_interconnect_0:subsys_hps_lwhps2fpga_arlock
|
||||
wire subsys_hps_lwhps2fpga_awlock; // subsys_hps:lwhps2fpga_awlock -> mm_interconnect_0:subsys_hps_lwhps2fpga_awlock
|
||||
wire [28:0] subsys_hps_lwhps2fpga_awaddr; // subsys_hps:lwhps2fpga_awaddr -> mm_interconnect_0:subsys_hps_lwhps2fpga_awaddr
|
||||
wire [1:0] subsys_hps_lwhps2fpga_bresp; // mm_interconnect_0:subsys_hps_lwhps2fpga_bresp -> subsys_hps:lwhps2fpga_bresp
|
||||
wire subsys_hps_lwhps2fpga_arready; // mm_interconnect_0:subsys_hps_lwhps2fpga_arready -> subsys_hps:lwhps2fpga_arready
|
||||
wire [31:0] subsys_hps_lwhps2fpga_rdata; // mm_interconnect_0:subsys_hps_lwhps2fpga_rdata -> subsys_hps:lwhps2fpga_rdata
|
||||
wire subsys_hps_lwhps2fpga_awready; // mm_interconnect_0:subsys_hps_lwhps2fpga_awready -> subsys_hps:lwhps2fpga_awready
|
||||
wire [1:0] subsys_hps_lwhps2fpga_arburst; // subsys_hps:lwhps2fpga_arburst -> mm_interconnect_0:subsys_hps_lwhps2fpga_arburst
|
||||
wire [2:0] subsys_hps_lwhps2fpga_arsize; // subsys_hps:lwhps2fpga_arsize -> mm_interconnect_0:subsys_hps_lwhps2fpga_arsize
|
||||
wire subsys_hps_lwhps2fpga_bready; // subsys_hps:lwhps2fpga_bready -> mm_interconnect_0:subsys_hps_lwhps2fpga_bready
|
||||
wire subsys_hps_lwhps2fpga_rlast; // mm_interconnect_0:subsys_hps_lwhps2fpga_rlast -> subsys_hps:lwhps2fpga_rlast
|
||||
wire subsys_hps_lwhps2fpga_wlast; // subsys_hps:lwhps2fpga_wlast -> mm_interconnect_0:subsys_hps_lwhps2fpga_wlast
|
||||
wire [1:0] subsys_hps_lwhps2fpga_rresp; // mm_interconnect_0:subsys_hps_lwhps2fpga_rresp -> subsys_hps:lwhps2fpga_rresp
|
||||
wire [3:0] subsys_hps_lwhps2fpga_awid; // subsys_hps:lwhps2fpga_awid -> mm_interconnect_0:subsys_hps_lwhps2fpga_awid
|
||||
wire [3:0] subsys_hps_lwhps2fpga_bid; // mm_interconnect_0:subsys_hps_lwhps2fpga_bid -> subsys_hps:lwhps2fpga_bid
|
||||
wire subsys_hps_lwhps2fpga_bvalid; // mm_interconnect_0:subsys_hps_lwhps2fpga_bvalid -> subsys_hps:lwhps2fpga_bvalid
|
||||
wire [2:0] subsys_hps_lwhps2fpga_awsize; // subsys_hps:lwhps2fpga_awsize -> mm_interconnect_0:subsys_hps_lwhps2fpga_awsize
|
||||
wire subsys_hps_lwhps2fpga_awvalid; // subsys_hps:lwhps2fpga_awvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_awvalid
|
||||
wire subsys_hps_lwhps2fpga_rvalid; // mm_interconnect_0:subsys_hps_lwhps2fpga_rvalid -> subsys_hps:lwhps2fpga_rvalid
|
||||
wire [31:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata; // subsys_periph:pb_cpu_0_s0_readdata -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_readdata
|
||||
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest; // subsys_periph:pb_cpu_0_s0_waitrequest -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_waitrequest
|
||||
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_debugaccess -> subsys_periph:pb_cpu_0_s0_debugaccess
|
||||
wire [16:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_address -> subsys_periph:pb_cpu_0_s0_address
|
||||
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_read -> subsys_periph:pb_cpu_0_s0_read
|
||||
wire [3:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_byteenable -> subsys_periph:pb_cpu_0_s0_byteenable
|
||||
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid; // subsys_periph:pb_cpu_0_s0_readdatavalid -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_readdatavalid
|
||||
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_write -> subsys_periph:pb_cpu_0_s0_write
|
||||
wire [31:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_writedata -> subsys_periph:pb_cpu_0_s0_writedata
|
||||
wire [0:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_burstcount -> subsys_periph:pb_cpu_0_s0_burstcount
|
||||
wire irq_mapper_receiver0_irq; // subsys_periph:button_pio_irq_irq -> irq_mapper:receiver0_irq
|
||||
wire irq_mapper_receiver1_irq; // subsys_periph:dipsw_pio_irq_irq -> irq_mapper:receiver1_irq
|
||||
wire [31:0] subsys_hps_f2h_irq0_in_irq; // irq_mapper:sender_irq -> subsys_hps:f2h_irq0_in_irq
|
||||
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_0:subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset]
|
||||
|
||||
clk_100 clk_100 (
|
||||
.in_clk (clk_100_clk), // input, width = 1, in_clk.clk
|
||||
.out_clk (clk_100_out_clk_clk) // output, width = 1, out_clk.clk
|
||||
);
|
||||
|
||||
rst_in rst_in (
|
||||
.in_reset_n (reset_reset_n), // input, width = 1, in_reset.reset_n
|
||||
.out_reset_n (rst_in_out_reset_reset) // output, width = 1, out_reset.reset_n
|
||||
);
|
||||
|
||||
user_rst_clkgate_0 user_rst_clkgate_0 (
|
||||
.ninit_done (ninit_done_ninit_done) // output, width = 1, ninit_done.ninit_done
|
||||
);
|
||||
|
||||
hps_subsys subsys_hps (
|
||||
.h2f_reset_reset (h2f_reset_reset), // output, width = 1, h2f_reset.reset
|
||||
.hps2fpga_clk_clk (clk_100_out_clk_clk), // input, width = 1, hps2fpga_clk.clk
|
||||
.hps2fpga_rst_reset (~rst_in_out_reset_reset), // input, width = 1, hps2fpga_rst.reset
|
||||
.hps2fpga_awid (subsys_hps_hps2fpga_awid), // output, width = 4, hps2fpga.awid
|
||||
.hps2fpga_awaddr (subsys_hps_hps2fpga_awaddr), // output, width = 38, .awaddr
|
||||
.hps2fpga_awlen (subsys_hps_hps2fpga_awlen), // output, width = 8, .awlen
|
||||
.hps2fpga_awsize (subsys_hps_hps2fpga_awsize), // output, width = 3, .awsize
|
||||
.hps2fpga_awburst (subsys_hps_hps2fpga_awburst), // output, width = 2, .awburst
|
||||
.hps2fpga_awlock (subsys_hps_hps2fpga_awlock), // output, width = 1, .awlock
|
||||
.hps2fpga_awcache (subsys_hps_hps2fpga_awcache), // output, width = 4, .awcache
|
||||
.hps2fpga_awprot (subsys_hps_hps2fpga_awprot), // output, width = 3, .awprot
|
||||
.hps2fpga_awvalid (subsys_hps_hps2fpga_awvalid), // output, width = 1, .awvalid
|
||||
.hps2fpga_awready (subsys_hps_hps2fpga_awready), // input, width = 1, .awready
|
||||
.hps2fpga_wdata (subsys_hps_hps2fpga_wdata), // output, width = 128, .wdata
|
||||
.hps2fpga_wstrb (subsys_hps_hps2fpga_wstrb), // output, width = 16, .wstrb
|
||||
.hps2fpga_wlast (subsys_hps_hps2fpga_wlast), // output, width = 1, .wlast
|
||||
.hps2fpga_wvalid (subsys_hps_hps2fpga_wvalid), // output, width = 1, .wvalid
|
||||
.hps2fpga_wready (subsys_hps_hps2fpga_wready), // input, width = 1, .wready
|
||||
.hps2fpga_bid (subsys_hps_hps2fpga_bid), // input, width = 4, .bid
|
||||
.hps2fpga_bresp (subsys_hps_hps2fpga_bresp), // input, width = 2, .bresp
|
||||
.hps2fpga_bvalid (subsys_hps_hps2fpga_bvalid), // input, width = 1, .bvalid
|
||||
.hps2fpga_bready (subsys_hps_hps2fpga_bready), // output, width = 1, .bready
|
||||
.hps2fpga_arid (subsys_hps_hps2fpga_arid), // output, width = 4, .arid
|
||||
.hps2fpga_araddr (subsys_hps_hps2fpga_araddr), // output, width = 38, .araddr
|
||||
.hps2fpga_arlen (subsys_hps_hps2fpga_arlen), // output, width = 8, .arlen
|
||||
.hps2fpga_arsize (subsys_hps_hps2fpga_arsize), // output, width = 3, .arsize
|
||||
.hps2fpga_arburst (subsys_hps_hps2fpga_arburst), // output, width = 2, .arburst
|
||||
.hps2fpga_arlock (subsys_hps_hps2fpga_arlock), // output, width = 1, .arlock
|
||||
.hps2fpga_arcache (subsys_hps_hps2fpga_arcache), // output, width = 4, .arcache
|
||||
.hps2fpga_arprot (subsys_hps_hps2fpga_arprot), // output, width = 3, .arprot
|
||||
.hps2fpga_arvalid (subsys_hps_hps2fpga_arvalid), // output, width = 1, .arvalid
|
||||
.hps2fpga_arready (subsys_hps_hps2fpga_arready), // input, width = 1, .arready
|
||||
.hps2fpga_rid (subsys_hps_hps2fpga_rid), // input, width = 4, .rid
|
||||
.hps2fpga_rdata (subsys_hps_hps2fpga_rdata), // input, width = 128, .rdata
|
||||
.hps2fpga_rresp (subsys_hps_hps2fpga_rresp), // input, width = 2, .rresp
|
||||
.hps2fpga_rlast (subsys_hps_hps2fpga_rlast), // input, width = 1, .rlast
|
||||
.hps2fpga_rvalid (subsys_hps_hps2fpga_rvalid), // input, width = 1, .rvalid
|
||||
.hps2fpga_rready (subsys_hps_hps2fpga_rready), // output, width = 1, .rready
|
||||
.lwhps2fpga_clk_clk (clk_100_out_clk_clk), // input, width = 1, lwhps2fpga_clk.clk
|
||||
.lwhps2fpga_rst_reset (~rst_in_out_reset_reset), // input, width = 1, lwhps2fpga_rst.reset
|
||||
.lwhps2fpga_awid (subsys_hps_lwhps2fpga_awid), // output, width = 4, lwhps2fpga.awid
|
||||
.lwhps2fpga_awaddr (subsys_hps_lwhps2fpga_awaddr), // output, width = 29, .awaddr
|
||||
.lwhps2fpga_awlen (subsys_hps_lwhps2fpga_awlen), // output, width = 8, .awlen
|
||||
.lwhps2fpga_awsize (subsys_hps_lwhps2fpga_awsize), // output, width = 3, .awsize
|
||||
.lwhps2fpga_awburst (subsys_hps_lwhps2fpga_awburst), // output, width = 2, .awburst
|
||||
.lwhps2fpga_awlock (subsys_hps_lwhps2fpga_awlock), // output, width = 1, .awlock
|
||||
.lwhps2fpga_awcache (subsys_hps_lwhps2fpga_awcache), // output, width = 4, .awcache
|
||||
.lwhps2fpga_awprot (subsys_hps_lwhps2fpga_awprot), // output, width = 3, .awprot
|
||||
.lwhps2fpga_awvalid (subsys_hps_lwhps2fpga_awvalid), // output, width = 1, .awvalid
|
||||
.lwhps2fpga_awready (subsys_hps_lwhps2fpga_awready), // input, width = 1, .awready
|
||||
.lwhps2fpga_wdata (subsys_hps_lwhps2fpga_wdata), // output, width = 32, .wdata
|
||||
.lwhps2fpga_wstrb (subsys_hps_lwhps2fpga_wstrb), // output, width = 4, .wstrb
|
||||
.lwhps2fpga_wlast (subsys_hps_lwhps2fpga_wlast), // output, width = 1, .wlast
|
||||
.lwhps2fpga_wvalid (subsys_hps_lwhps2fpga_wvalid), // output, width = 1, .wvalid
|
||||
.lwhps2fpga_wready (subsys_hps_lwhps2fpga_wready), // input, width = 1, .wready
|
||||
.lwhps2fpga_bid (subsys_hps_lwhps2fpga_bid), // input, width = 4, .bid
|
||||
.lwhps2fpga_bresp (subsys_hps_lwhps2fpga_bresp), // input, width = 2, .bresp
|
||||
.lwhps2fpga_bvalid (subsys_hps_lwhps2fpga_bvalid), // input, width = 1, .bvalid
|
||||
.lwhps2fpga_bready (subsys_hps_lwhps2fpga_bready), // output, width = 1, .bready
|
||||
.lwhps2fpga_arid (subsys_hps_lwhps2fpga_arid), // output, width = 4, .arid
|
||||
.lwhps2fpga_araddr (subsys_hps_lwhps2fpga_araddr), // output, width = 29, .araddr
|
||||
.lwhps2fpga_arlen (subsys_hps_lwhps2fpga_arlen), // output, width = 8, .arlen
|
||||
.lwhps2fpga_arsize (subsys_hps_lwhps2fpga_arsize), // output, width = 3, .arsize
|
||||
.lwhps2fpga_arburst (subsys_hps_lwhps2fpga_arburst), // output, width = 2, .arburst
|
||||
.lwhps2fpga_arlock (subsys_hps_lwhps2fpga_arlock), // output, width = 1, .arlock
|
||||
.lwhps2fpga_arcache (subsys_hps_lwhps2fpga_arcache), // output, width = 4, .arcache
|
||||
.lwhps2fpga_arprot (subsys_hps_lwhps2fpga_arprot), // output, width = 3, .arprot
|
||||
.lwhps2fpga_arvalid (subsys_hps_lwhps2fpga_arvalid), // output, width = 1, .arvalid
|
||||
.lwhps2fpga_arready (subsys_hps_lwhps2fpga_arready), // input, width = 1, .arready
|
||||
.lwhps2fpga_rid (subsys_hps_lwhps2fpga_rid), // input, width = 4, .rid
|
||||
.lwhps2fpga_rdata (subsys_hps_lwhps2fpga_rdata), // input, width = 32, .rdata
|
||||
.lwhps2fpga_rresp (subsys_hps_lwhps2fpga_rresp), // input, width = 2, .rresp
|
||||
.lwhps2fpga_rlast (subsys_hps_lwhps2fpga_rlast), // input, width = 1, .rlast
|
||||
.lwhps2fpga_rvalid (subsys_hps_lwhps2fpga_rvalid), // input, width = 1, .rvalid
|
||||
.lwhps2fpga_rready (subsys_hps_lwhps2fpga_rready), // output, width = 1, .rready
|
||||
.h2f_warm_reset_handshake_reset_req (subsys_hps_h2f_warm_reset_handshake_reset_req), // output, width = 1, h2f_warm_reset_handshake.reset_req
|
||||
.h2f_warm_reset_handshake_reset_ack (subsys_hps_h2f_warm_reset_handshake_reset_ack), // input, width = 1, .reset_ack
|
||||
.hps_io_hps_osc_clk (hps_io_hps_osc_clk), // input, width = 1, hps_io.hps_osc_clk
|
||||
.hps_io_sdmmc_data0 (hps_io_sdmmc_data0), // inout, width = 1, .sdmmc_data0
|
||||
.hps_io_sdmmc_data1 (hps_io_sdmmc_data1), // inout, width = 1, .sdmmc_data1
|
||||
.hps_io_sdmmc_cclk (hps_io_sdmmc_cclk), // output, width = 1, .sdmmc_cclk
|
||||
.hps_io_sdmmc_data2 (hps_io_sdmmc_data2), // inout, width = 1, .sdmmc_data2
|
||||
.hps_io_sdmmc_data3 (hps_io_sdmmc_data3), // inout, width = 1, .sdmmc_data3
|
||||
.hps_io_sdmmc_cmd (hps_io_sdmmc_cmd), // inout, width = 1, .sdmmc_cmd
|
||||
.hps_io_usb0_clk (hps_io_usb0_clk), // input, width = 1, .usb0_clk
|
||||
.hps_io_usb0_stp (hps_io_usb0_stp), // output, width = 1, .usb0_stp
|
||||
.hps_io_usb0_dir (hps_io_usb0_dir), // input, width = 1, .usb0_dir
|
||||
.hps_io_usb0_data0 (hps_io_usb0_data0), // inout, width = 1, .usb0_data0
|
||||
.hps_io_usb0_data1 (hps_io_usb0_data1), // inout, width = 1, .usb0_data1
|
||||
.hps_io_usb0_nxt (hps_io_usb0_nxt), // input, width = 1, .usb0_nxt
|
||||
.hps_io_usb0_data2 (hps_io_usb0_data2), // inout, width = 1, .usb0_data2
|
||||
.hps_io_usb0_data3 (hps_io_usb0_data3), // inout, width = 1, .usb0_data3
|
||||
.hps_io_usb0_data4 (hps_io_usb0_data4), // inout, width = 1, .usb0_data4
|
||||
.hps_io_usb0_data5 (hps_io_usb0_data5), // inout, width = 1, .usb0_data5
|
||||
.hps_io_usb0_data6 (hps_io_usb0_data6), // inout, width = 1, .usb0_data6
|
||||
.hps_io_usb0_data7 (hps_io_usb0_data7), // inout, width = 1, .usb0_data7
|
||||
.hps_io_emac0_tx_clk (hps_io_emac0_tx_clk), // output, width = 1, .emac0_tx_clk
|
||||
.hps_io_emac0_tx_ctl (hps_io_emac0_tx_ctl), // output, width = 1, .emac0_tx_ctl
|
||||
.hps_io_emac0_rx_clk (hps_io_emac0_rx_clk), // input, width = 1, .emac0_rx_clk
|
||||
.hps_io_emac0_rx_ctl (hps_io_emac0_rx_ctl), // input, width = 1, .emac0_rx_ctl
|
||||
.hps_io_emac0_txd0 (hps_io_emac0_txd0), // output, width = 1, .emac0_txd0
|
||||
.hps_io_emac0_txd1 (hps_io_emac0_txd1), // output, width = 1, .emac0_txd1
|
||||
.hps_io_emac0_rxd0 (hps_io_emac0_rxd0), // input, width = 1, .emac0_rxd0
|
||||
.hps_io_emac0_rxd1 (hps_io_emac0_rxd1), // input, width = 1, .emac0_rxd1
|
||||
.hps_io_emac0_txd2 (hps_io_emac0_txd2), // output, width = 1, .emac0_txd2
|
||||
.hps_io_emac0_txd3 (hps_io_emac0_txd3), // output, width = 1, .emac0_txd3
|
||||
.hps_io_emac0_rxd2 (hps_io_emac0_rxd2), // input, width = 1, .emac0_rxd2
|
||||
.hps_io_emac0_rxd3 (hps_io_emac0_rxd3), // input, width = 1, .emac0_rxd3
|
||||
.hps_io_mdio0_mdio (hps_io_mdio0_mdio), // inout, width = 1, .mdio0_mdio
|
||||
.hps_io_mdio0_mdc (hps_io_mdio0_mdc), // output, width = 1, .mdio0_mdc
|
||||
.hps_io_uart1_tx (hps_io_uart1_tx), // output, width = 1, .uart1_tx
|
||||
.hps_io_uart1_rx (hps_io_uart1_rx), // input, width = 1, .uart1_rx
|
||||
.hps_io_i2c1_sda (hps_io_i2c1_sda), // inout, width = 1, .i2c1_sda
|
||||
.hps_io_i2c1_scl (hps_io_i2c1_scl), // inout, width = 1, .i2c1_scl
|
||||
.hps_io_gpio28 (hps_io_gpio28), // inout, width = 1, .gpio28
|
||||
.hps_io_gpio34 (hps_io_gpio34), // inout, width = 1, .gpio34
|
||||
.hps_io_gpio40 (hps_io_gpio40), // inout, width = 1, .gpio40
|
||||
.hps_io_gpio41 (hps_io_gpio41), // inout, width = 1, .gpio41
|
||||
.f2h_irq1_in_irq (f2h_irq1_in_irq), // input, width = 32, f2h_irq1_in.irq
|
||||
.f2h_irq0_in_irq (subsys_hps_f2h_irq0_in_irq), // input, width = 32, f2h_irq0_in.irq
|
||||
.f2sdram_clk_clk (clk_100_out_clk_clk), // input, width = 1, f2sdram_clk.clk
|
||||
.f2sdram_rst_reset (~rst_in_out_reset_reset), // input, width = 1, f2sdram_rst.reset
|
||||
.f2sdram_araddr (f2sdram_araddr), // input, width = 32, f2sdram.araddr
|
||||
.f2sdram_arburst (f2sdram_arburst), // input, width = 2, .arburst
|
||||
.f2sdram_arcache (f2sdram_arcache), // input, width = 4, .arcache
|
||||
.f2sdram_arid (f2sdram_arid), // input, width = 5, .arid
|
||||
.f2sdram_arlen (f2sdram_arlen), // input, width = 8, .arlen
|
||||
.f2sdram_arlock (f2sdram_arlock), // input, width = 1, .arlock
|
||||
.f2sdram_arprot (f2sdram_arprot), // input, width = 3, .arprot
|
||||
.f2sdram_arqos (f2sdram_arqos), // input, width = 4, .arqos
|
||||
.f2sdram_arready (f2sdram_arready), // output, width = 1, .arready
|
||||
.f2sdram_arsize (f2sdram_arsize), // input, width = 3, .arsize
|
||||
.f2sdram_arvalid (f2sdram_arvalid), // input, width = 1, .arvalid
|
||||
.f2sdram_awaddr (f2sdram_awaddr), // input, width = 32, .awaddr
|
||||
.f2sdram_awburst (f2sdram_awburst), // input, width = 2, .awburst
|
||||
.f2sdram_awcache (f2sdram_awcache), // input, width = 4, .awcache
|
||||
.f2sdram_awid (f2sdram_awid), // input, width = 5, .awid
|
||||
.f2sdram_awlen (f2sdram_awlen), // input, width = 8, .awlen
|
||||
.f2sdram_awlock (f2sdram_awlock), // input, width = 1, .awlock
|
||||
.f2sdram_awprot (f2sdram_awprot), // input, width = 3, .awprot
|
||||
.f2sdram_awqos (f2sdram_awqos), // input, width = 4, .awqos
|
||||
.f2sdram_awready (f2sdram_awready), // output, width = 1, .awready
|
||||
.f2sdram_awsize (f2sdram_awsize), // input, width = 3, .awsize
|
||||
.f2sdram_awvalid (f2sdram_awvalid), // input, width = 1, .awvalid
|
||||
.f2sdram_bid (f2sdram_bid), // output, width = 5, .bid
|
||||
.f2sdram_bready (f2sdram_bready), // input, width = 1, .bready
|
||||
.f2sdram_bresp (f2sdram_bresp), // output, width = 2, .bresp
|
||||
.f2sdram_bvalid (f2sdram_bvalid), // output, width = 1, .bvalid
|
||||
.f2sdram_rdata (f2sdram_rdata), // output, width = 256, .rdata
|
||||
.f2sdram_rid (f2sdram_rid), // output, width = 5, .rid
|
||||
.f2sdram_rlast (f2sdram_rlast), // output, width = 1, .rlast
|
||||
.f2sdram_rready (f2sdram_rready), // input, width = 1, .rready
|
||||
.f2sdram_rresp (f2sdram_rresp), // output, width = 2, .rresp
|
||||
.f2sdram_rvalid (f2sdram_rvalid), // output, width = 1, .rvalid
|
||||
.f2sdram_wdata (f2sdram_wdata), // input, width = 256, .wdata
|
||||
.f2sdram_wlast (f2sdram_wlast), // input, width = 1, .wlast
|
||||
.f2sdram_wready (f2sdram_wready), // output, width = 1, .wready
|
||||
.f2sdram_wstrb (f2sdram_wstrb), // input, width = 32, .wstrb
|
||||
.f2sdram_wvalid (f2sdram_wvalid), // input, width = 1, .wvalid
|
||||
.f2sdram_aruser (f2sdram_aruser), // input, width = 8, .aruser
|
||||
.f2sdram_awuser (f2sdram_awuser), // input, width = 8, .awuser
|
||||
.f2sdram_wuser (f2sdram_wuser), // input, width = 8, .wuser
|
||||
.f2sdram_buser (f2sdram_buser), // output, width = 8, .buser
|
||||
.f2sdram_arregion (f2sdram_arregion), // input, width = 4, .arregion
|
||||
.f2sdram_ruser (f2sdram_ruser), // output, width = 8, .ruser
|
||||
.f2sdram_awregion (f2sdram_awregion), // input, width = 4, .awregion
|
||||
.emif_hps_emif_mem_0_mem_cs (emif_hps_emif_mem_0_mem_cs), // output, width = 1, emif_hps_emif_mem_0.mem_cs
|
||||
.emif_hps_emif_mem_0_mem_ca (emif_hps_emif_mem_0_mem_ca), // output, width = 6, .mem_ca
|
||||
.emif_hps_emif_mem_0_mem_cke (emif_hps_emif_mem_0_mem_cke), // output, width = 1, .mem_cke
|
||||
.emif_hps_emif_mem_0_mem_dq (emif_hps_emif_mem_0_mem_dq), // inout, width = 32, .mem_dq
|
||||
.emif_hps_emif_mem_0_mem_dqs_t (emif_hps_emif_mem_0_mem_dqs_t), // inout, width = 4, .mem_dqs_t
|
||||
.emif_hps_emif_mem_0_mem_dqs_c (emif_hps_emif_mem_0_mem_dqs_c), // inout, width = 4, .mem_dqs_c
|
||||
.emif_hps_emif_mem_0_mem_dmi (emif_hps_emif_mem_0_mem_dmi), // inout, width = 4, .mem_dmi
|
||||
.emif_hps_emif_mem_ck_0_mem_ck_t (emif_hps_emif_mem_ck_0_mem_ck_t), // output, width = 1, emif_hps_emif_mem_ck_0.mem_ck_t
|
||||
.emif_hps_emif_mem_ck_0_mem_ck_c (emif_hps_emif_mem_ck_0_mem_ck_c), // output, width = 1, .mem_ck_c
|
||||
.emif_hps_emif_mem_reset_n_mem_reset_n (emif_hps_emif_mem_reset_n_mem_reset_n), // output, width = 1, emif_hps_emif_mem_reset_n.mem_reset_n
|
||||
.emif_hps_emif_oct_0_oct_rzqin (emif_hps_emif_oct_0_oct_rzqin), // input, width = 1, emif_hps_emif_oct_0.oct_rzqin
|
||||
.emif_hps_emif_ref_clk_clk (emif_hps_emif_ref_clk_0_clk) // input, width = 1, emif_hps_emif_ref_clk.clk
|
||||
);
|
||||
|
||||
peripheral_subsys subsys_periph (
|
||||
.button_pio_external_connection_export (button_pio_external_connection_export), // input, width = 4, button_pio_external_connection.export
|
||||
.button_pio_irq_irq (irq_mapper_receiver0_irq), // output, width = 1, button_pio_irq.irq
|
||||
.dipsw_pio_external_connection_export (dipsw_pio_external_connection_export), // input, width = 4, dipsw_pio_external_connection.export
|
||||
.dipsw_pio_irq_irq (irq_mapper_receiver1_irq), // output, width = 1, dipsw_pio_irq.irq
|
||||
.led_pio_external_connection_in_port (led_pio_external_connection_in_port), // input, width = 3, led_pio_external_connection.in_port
|
||||
.led_pio_external_connection_out_port (led_pio_external_connection_out_port), // output, width = 3, .out_port
|
||||
.pb_cpu_0_s0_waitrequest (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest), // output, width = 1, pb_cpu_0_s0.waitrequest
|
||||
.pb_cpu_0_s0_readdata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata), // output, width = 32, .readdata
|
||||
.pb_cpu_0_s0_readdatavalid (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid), // output, width = 1, .readdatavalid
|
||||
.pb_cpu_0_s0_burstcount (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount), // input, width = 1, .burstcount
|
||||
.pb_cpu_0_s0_writedata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata), // input, width = 32, .writedata
|
||||
.pb_cpu_0_s0_address (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address), // input, width = 17, .address
|
||||
.pb_cpu_0_s0_write (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write), // input, width = 1, .write
|
||||
.pb_cpu_0_s0_read (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read), // input, width = 1, .read
|
||||
.pb_cpu_0_s0_byteenable (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable), // input, width = 4, .byteenable
|
||||
.pb_cpu_0_s0_debugaccess (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess), // input, width = 1, .debugaccess
|
||||
.clk_clk (clk_100_out_clk_clk), // input, width = 1, clk.clk
|
||||
.reset_reset_n (rst_in_out_reset_reset) // input, width = 1, reset.reset_n
|
||||
);
|
||||
|
||||
qsys_top_altera_mm_interconnect_1920_ykfyxdi mm_interconnect_0 (
|
||||
.subsys_hps_lwhps2fpga_awid (subsys_hps_lwhps2fpga_awid), // input, width = 4, subsys_hps_lwhps2fpga.awid
|
||||
.subsys_hps_lwhps2fpga_awaddr (subsys_hps_lwhps2fpga_awaddr), // input, width = 29, .awaddr
|
||||
.subsys_hps_lwhps2fpga_awlen (subsys_hps_lwhps2fpga_awlen), // input, width = 8, .awlen
|
||||
.subsys_hps_lwhps2fpga_awsize (subsys_hps_lwhps2fpga_awsize), // input, width = 3, .awsize
|
||||
.subsys_hps_lwhps2fpga_awburst (subsys_hps_lwhps2fpga_awburst), // input, width = 2, .awburst
|
||||
.subsys_hps_lwhps2fpga_awlock (subsys_hps_lwhps2fpga_awlock), // input, width = 1, .awlock
|
||||
.subsys_hps_lwhps2fpga_awcache (subsys_hps_lwhps2fpga_awcache), // input, width = 4, .awcache
|
||||
.subsys_hps_lwhps2fpga_awprot (subsys_hps_lwhps2fpga_awprot), // input, width = 3, .awprot
|
||||
.subsys_hps_lwhps2fpga_awvalid (subsys_hps_lwhps2fpga_awvalid), // input, width = 1, .awvalid
|
||||
.subsys_hps_lwhps2fpga_awready (subsys_hps_lwhps2fpga_awready), // output, width = 1, .awready
|
||||
.subsys_hps_lwhps2fpga_wdata (subsys_hps_lwhps2fpga_wdata), // input, width = 32, .wdata
|
||||
.subsys_hps_lwhps2fpga_wstrb (subsys_hps_lwhps2fpga_wstrb), // input, width = 4, .wstrb
|
||||
.subsys_hps_lwhps2fpga_wlast (subsys_hps_lwhps2fpga_wlast), // input, width = 1, .wlast
|
||||
.subsys_hps_lwhps2fpga_wvalid (subsys_hps_lwhps2fpga_wvalid), // input, width = 1, .wvalid
|
||||
.subsys_hps_lwhps2fpga_wready (subsys_hps_lwhps2fpga_wready), // output, width = 1, .wready
|
||||
.subsys_hps_lwhps2fpga_bid (subsys_hps_lwhps2fpga_bid), // output, width = 4, .bid
|
||||
.subsys_hps_lwhps2fpga_bresp (subsys_hps_lwhps2fpga_bresp), // output, width = 2, .bresp
|
||||
.subsys_hps_lwhps2fpga_bvalid (subsys_hps_lwhps2fpga_bvalid), // output, width = 1, .bvalid
|
||||
.subsys_hps_lwhps2fpga_bready (subsys_hps_lwhps2fpga_bready), // input, width = 1, .bready
|
||||
.subsys_hps_lwhps2fpga_arid (subsys_hps_lwhps2fpga_arid), // input, width = 4, .arid
|
||||
.subsys_hps_lwhps2fpga_araddr (subsys_hps_lwhps2fpga_araddr), // input, width = 29, .araddr
|
||||
.subsys_hps_lwhps2fpga_arlen (subsys_hps_lwhps2fpga_arlen), // input, width = 8, .arlen
|
||||
.subsys_hps_lwhps2fpga_arsize (subsys_hps_lwhps2fpga_arsize), // input, width = 3, .arsize
|
||||
.subsys_hps_lwhps2fpga_arburst (subsys_hps_lwhps2fpga_arburst), // input, width = 2, .arburst
|
||||
.subsys_hps_lwhps2fpga_arlock (subsys_hps_lwhps2fpga_arlock), // input, width = 1, .arlock
|
||||
.subsys_hps_lwhps2fpga_arcache (subsys_hps_lwhps2fpga_arcache), // input, width = 4, .arcache
|
||||
.subsys_hps_lwhps2fpga_arprot (subsys_hps_lwhps2fpga_arprot), // input, width = 3, .arprot
|
||||
.subsys_hps_lwhps2fpga_arvalid (subsys_hps_lwhps2fpga_arvalid), // input, width = 1, .arvalid
|
||||
.subsys_hps_lwhps2fpga_arready (subsys_hps_lwhps2fpga_arready), // output, width = 1, .arready
|
||||
.subsys_hps_lwhps2fpga_rid (subsys_hps_lwhps2fpga_rid), // output, width = 4, .rid
|
||||
.subsys_hps_lwhps2fpga_rdata (subsys_hps_lwhps2fpga_rdata), // output, width = 32, .rdata
|
||||
.subsys_hps_lwhps2fpga_rresp (subsys_hps_lwhps2fpga_rresp), // output, width = 2, .rresp
|
||||
.subsys_hps_lwhps2fpga_rlast (subsys_hps_lwhps2fpga_rlast), // output, width = 1, .rlast
|
||||
.subsys_hps_lwhps2fpga_rvalid (subsys_hps_lwhps2fpga_rvalid), // output, width = 1, .rvalid
|
||||
.subsys_hps_lwhps2fpga_rready (subsys_hps_lwhps2fpga_rready), // input, width = 1, .rready
|
||||
.subsys_periph_pb_cpu_0_s0_address (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address), // output, width = 17, subsys_periph_pb_cpu_0_s0.address
|
||||
.subsys_periph_pb_cpu_0_s0_write (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write), // output, width = 1, .write
|
||||
.subsys_periph_pb_cpu_0_s0_read (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read), // output, width = 1, .read
|
||||
.subsys_periph_pb_cpu_0_s0_readdata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata), // input, width = 32, .readdata
|
||||
.subsys_periph_pb_cpu_0_s0_writedata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata), // output, width = 32, .writedata
|
||||
.subsys_periph_pb_cpu_0_s0_burstcount (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount), // output, width = 1, .burstcount
|
||||
.subsys_periph_pb_cpu_0_s0_byteenable (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable), // output, width = 4, .byteenable
|
||||
.subsys_periph_pb_cpu_0_s0_readdatavalid (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid), // input, width = 1, .readdatavalid
|
||||
.subsys_periph_pb_cpu_0_s0_waitrequest (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest), // input, width = 1, .waitrequest
|
||||
.subsys_periph_pb_cpu_0_s0_debugaccess (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess), // output, width = 1, .debugaccess
|
||||
.subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // input, width = 1, subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset.reset
|
||||
.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // input, width = 1, subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset.reset
|
||||
.clk_100_out_clk_clk (clk_100_out_clk_clk) // input, width = 1, clk_100_out_clk.clk
|
||||
);
|
||||
|
||||
qsys_top_altera_irq_mapper_2001_lp4cnei irq_mapper (
|
||||
.clk (), // input, width = 1, clk.clk
|
||||
.reset (), // input, width = 1, clk_reset.reset
|
||||
.receiver0_irq (irq_mapper_receiver0_irq), // input, width = 1, receiver0.irq
|
||||
.receiver1_irq (irq_mapper_receiver1_irq), // input, width = 1, receiver1.irq
|
||||
.sender_irq (subsys_hps_f2h_irq0_in_irq) // output, width = 32, sender.irq
|
||||
);
|
||||
|
||||
altera_reset_controller #(
|
||||
.NUM_RESET_INPUTS (1),
|
||||
.OUTPUT_RESET_SYNC_EDGES ("both"),
|
||||
.SYNC_DEPTH (2),
|
||||
.RESET_REQUEST_PRESENT (0),
|
||||
.RESET_REQ_WAIT_TIME (1),
|
||||
.MIN_RST_ASSERTION_TIME (3),
|
||||
.RESET_REQ_EARLY_DSRT_TIME (1),
|
||||
.USE_RESET_REQUEST_IN0 (0),
|
||||
.USE_RESET_REQUEST_IN1 (0),
|
||||
.USE_RESET_REQUEST_IN2 (0),
|
||||
.USE_RESET_REQUEST_IN3 (0),
|
||||
.USE_RESET_REQUEST_IN4 (0),
|
||||
.USE_RESET_REQUEST_IN5 (0),
|
||||
.USE_RESET_REQUEST_IN6 (0),
|
||||
.USE_RESET_REQUEST_IN7 (0),
|
||||
.USE_RESET_REQUEST_IN8 (0),
|
||||
.USE_RESET_REQUEST_IN9 (0),
|
||||
.USE_RESET_REQUEST_IN10 (0),
|
||||
.USE_RESET_REQUEST_IN11 (0),
|
||||
.USE_RESET_REQUEST_IN12 (0),
|
||||
.USE_RESET_REQUEST_IN13 (0),
|
||||
.USE_RESET_REQUEST_IN14 (0),
|
||||
.USE_RESET_REQUEST_IN15 (0),
|
||||
.ADAPT_RESET_REQUEST (0)
|
||||
) rst_controller (
|
||||
.reset_in0 (~rst_in_out_reset_reset), // input, width = 1, reset_in0.reset
|
||||
.clk (clk_100_out_clk_clk), // input, width = 1, clk.clk
|
||||
.reset_out (rst_controller_reset_out_reset), // output, width = 1, reset_out.reset
|
||||
.reset_req (), // (terminated),
|
||||
.reset_req_in0 (1'b0), // (terminated),
|
||||
.reset_in1 (1'b0), // (terminated),
|
||||
.reset_req_in1 (1'b0), // (terminated),
|
||||
.reset_in2 (1'b0), // (terminated),
|
||||
.reset_req_in2 (1'b0), // (terminated),
|
||||
.reset_in3 (1'b0), // (terminated),
|
||||
.reset_req_in3 (1'b0), // (terminated),
|
||||
.reset_in4 (1'b0), // (terminated),
|
||||
.reset_req_in4 (1'b0), // (terminated),
|
||||
.reset_in5 (1'b0), // (terminated),
|
||||
.reset_req_in5 (1'b0), // (terminated),
|
||||
.reset_in6 (1'b0), // (terminated),
|
||||
.reset_req_in6 (1'b0), // (terminated),
|
||||
.reset_in7 (1'b0), // (terminated),
|
||||
.reset_req_in7 (1'b0), // (terminated),
|
||||
.reset_in8 (1'b0), // (terminated),
|
||||
.reset_req_in8 (1'b0), // (terminated),
|
||||
.reset_in9 (1'b0), // (terminated),
|
||||
.reset_req_in9 (1'b0), // (terminated),
|
||||
.reset_in10 (1'b0), // (terminated),
|
||||
.reset_req_in10 (1'b0), // (terminated),
|
||||
.reset_in11 (1'b0), // (terminated),
|
||||
.reset_req_in11 (1'b0), // (terminated),
|
||||
.reset_in12 (1'b0), // (terminated),
|
||||
.reset_req_in12 (1'b0), // (terminated),
|
||||
.reset_in13 (1'b0), // (terminated),
|
||||
.reset_req_in13 (1'b0), // (terminated),
|
||||
.reset_in14 (1'b0), // (terminated),
|
||||
.reset_req_in14 (1'b0), // (terminated),
|
||||
.reset_in15 (1'b0), // (terminated),
|
||||
.reset_req_in15 (1'b0) // (terminated),
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,2 @@
|
||||
-- DONOT MODIFY
|
||||
-- Contains device library mapping
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
WORK > DEFAULT
|
||||
DEFAULT: ./libraries/work/
|
||||
work: ./libraries/work/
|
||||
altera_merlin_axi_translator_1987: ./libraries/altera_merlin_axi_translator_1987/
|
||||
altera_merlin_slave_translator_191: ./libraries/altera_merlin_slave_translator_191/
|
||||
altera_merlin_axi_master_ni_19117: ./libraries/altera_merlin_axi_master_ni_19117/
|
||||
altera_merlin_slave_agent_1930: ./libraries/altera_merlin_slave_agent_1930/
|
||||
altera_avalon_sc_fifo_1932: ./libraries/altera_avalon_sc_fifo_1932/
|
||||
altera_merlin_router_1921: ./libraries/altera_merlin_router_1921/
|
||||
altera_avalon_st_pipeline_stage_1930: ./libraries/altera_avalon_st_pipeline_stage_1930/
|
||||
altera_merlin_burst_adapter_1940: ./libraries/altera_merlin_burst_adapter_1940/
|
||||
altera_merlin_demultiplexer_1921: ./libraries/altera_merlin_demultiplexer_1921/
|
||||
altera_merlin_multiplexer_1922: ./libraries/altera_merlin_multiplexer_1922/
|
||||
altera_mm_interconnect_1920: ./libraries/altera_mm_interconnect_1920/
|
||||
altera_irq_mapper_2001: ./libraries/altera_irq_mapper_2001/
|
||||
altera_reset_controller_1924: ./libraries/altera_reset_controller_1924/
|
||||
qsys_top: ./libraries/qsys_top/
|
||||
OTHERS=_device_synopsys_sim.setup
|
||||
OTHERS=_default_synopsys_sim.setup
|
||||
LIBRARY_SCAN = TRUE
|
||||
+429
@@ -0,0 +1,429 @@
|
||||
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:52:56
|
||||
|
||||
# ----------------------------------------
|
||||
# vcsmx - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# qsys_top
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level shell script that compiles Intel simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
|
||||
#
|
||||
# You can also modify the simulation flow to suit your needs. Set the
|
||||
# following variables to 1 to disable their corresponding processes:
|
||||
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
|
||||
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
|
||||
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
|
||||
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator. In this case, you must also copy the generated library
|
||||
# # setup "synopsys_sim.setup" into the location from which you launch the
|
||||
# # simulator, or incorporate into any existing library setup.
|
||||
# #
|
||||
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
|
||||
# # simulation libraries and Quartus-generated IP simulation files, and copy
|
||||
# # any ROM/RAM initialization files to the simulation directory.
|
||||
# #
|
||||
# # - If necessary, specify any compilation options:
|
||||
# # USER_DEFINED_COMPILE_OPTIONS
|
||||
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
|
||||
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
|
||||
# SKIP_ELAB=1 \
|
||||
# SKIP_SIM=1 \
|
||||
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
|
||||
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
|
||||
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
|
||||
# QSYS_SIMDIR=<script generation output directory>
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the IP script)
|
||||
# #
|
||||
# vlogan <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
|
||||
# # testbench module/entity name.
|
||||
# #
|
||||
# # Run the IP script again to elaborate and simulate the top level:
|
||||
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
|
||||
# SKIP_FILE_COPY=1 \
|
||||
# SKIP_DEV_COM=1 \
|
||||
# SKIP_COM=1 \
|
||||
# TOP_LEVEL_NAME="'-top <simulation top>'" \
|
||||
# QSYS_SIMDIR=<script generation output directory> \
|
||||
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
|
||||
# DEFAULT_ELAB_OPTIONS=<default elaboration options for your design> \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If qsys_top is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Intel IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Intel IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:52:56
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="qsys_top.qsys_top"
|
||||
QSYS_SIMDIR="./../../"
|
||||
QUARTUS_INSTALL_DIR="/opt/altera_pro/26.1/quartus/"
|
||||
QUARTUS_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/eda/sim_lib/"
|
||||
DEVICES_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
SKIP_ELAB=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
DEFAULT_ELAB_OPTIONS=""
|
||||
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
|
||||
PRECOMP_DEVICE_LIB_FILE=""
|
||||
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
#-------------------------------------------
|
||||
# check tclsh version no earlier than 8.5
|
||||
version=$(echo "puts [package vcompare [info tclversion] 8.5]; exit" | tclsh)
|
||||
if [ $version -eq -1 ]; then
|
||||
echo "Error: Minimum required tcl package version is 8.5." >&2
|
||||
exit 1
|
||||
fi
|
||||
|
||||
#-------------------------------------------
|
||||
# read .sh file to override initialized variables
|
||||
if [ -n "${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}" ] && [ -f ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE} ]; then
|
||||
echo "Sourcing ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}"
|
||||
source ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error:: This file ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE} has invalid expression/s" >&2
|
||||
exit $?
|
||||
fi
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `vcs -platform` != *"amd64"* && `vcs -platform` != *"suse64"* && `vcs -platform` != *"linux64"* ]]; then
|
||||
SIMULATOR_TOOL_BITNESS="bit_32"
|
||||
else
|
||||
SIMULATOR_TOOL_BITNESS="bit_64"
|
||||
fi
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set SIMULATOR_TOOL_BITNESS [lindex $argv 2]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [qsys_top::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
if {[dict size $LD_LIBRARY_PATH] !=0 } {
|
||||
set LD_LIBRARY_PATH [join [dict keys $LD_LIBRARY_PATH] ":"]
|
||||
puts "LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\""
|
||||
}
|
||||
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [qsys_top::get_elab_options $SIMULATOR_TOOL_BITNESS]
|
||||
puts "ELAB_OPTIONS+=\"$ELAB_OPTIONS\""
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [qsys_top::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
puts "SIM_OPTIONS+=\"$SIM_OPTIONS\""
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" "$SIMULATOR_TOOL_BITNESS" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
eval $cmd_output
|
||||
|
||||
#-------------------------------------------
|
||||
# Decision to skip device compilation,
|
||||
# based on value of PRECOMP_DEVICE_LIB_FILE.
|
||||
# if PRECOMP_DEVICE_LIB_FILE is set, SKIP_DEV_COM will become true
|
||||
if [ ! -z "$PRECOMP_DEVICE_LIB_FILE" ] && [ -e $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
echo "Using $PRECOMP_DEVICE_LIB_FILE for device library mapping"
|
||||
SKIP_DEV_COM=1
|
||||
else
|
||||
PRECOMP_DEVICE_LIB_FILE=""
|
||||
fi
|
||||
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set libraries [dict create]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set libraries [dict merge $libraries [qsys_top::get_design_libraries]]
|
||||
set design_libraries [dict keys $libraries]
|
||||
foreach file $design_libraries { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
design_libraries=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# create compilation libraries
|
||||
device_libraries='lpm_ver sgate_ver altera_ver altera_mf_ver altera_lnsim_ver tennm_ver tennm_sm_hps_ver tennm_sm4_hssi_ver tennm_revb_hvio_ver tennm_revb_io96_ver lpm sgate altera altera_mf altera_lnsim tennm tennm_sm_hps tennm_sm4_hssi tennm_revb_hvio tennm_revb_io96 '
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
mkdir -p ./libraries/$library
|
||||
done
|
||||
fi
|
||||
|
||||
for library in $design_libraries
|
||||
do
|
||||
mkdir -p ./libraries/$library
|
||||
done
|
||||
mkdir -p ./libraries/work
|
||||
|
||||
#-------------------------------------------
|
||||
# write out _device_synopsys_sim.setup including all device libraries
|
||||
echo "--DONOT MODIFY" > _device_synopsys_sim.setup
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
echo "$library: ./libraries/$library" >> _device_synopsys_sim.setup
|
||||
done
|
||||
else
|
||||
echo "OTHERS=$PRECOMP_DEVICE_LIB_FILE" >> _device_synopsys_sim.setup
|
||||
fi
|
||||
#-------------------------------------------
|
||||
# write out _default_synopsys_sim.setup including all design libraries
|
||||
echo "-- DO NOT MODIFY " > _default_synopsys_sim.setup
|
||||
for library in $design_libraries
|
||||
do
|
||||
echo "$library: ./libraries/$library" >> _default_synopsys_sim.setup
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set QUARTUS_INSTALL_DIR [lindex $argv 2]
|
||||
set memory_files [list]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set memory_files [concat $memory_files [qsys_top::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
foreach file $memory_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
memory_files=$cmd_output
|
||||
if [ $SKIP_FILE_COPY -eq 0 ]; then
|
||||
for file in $memory_files
|
||||
do
|
||||
cp -f $file ./
|
||||
done
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile device library files
|
||||
if [ $SKIP_DEV_COM -eq 0 ]; then
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/synopsys/tennm_atoms_ncrypt.sv" -work tennm_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96_ver
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -work lpm
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.vhd" -work lpm
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -work sgate
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -work sgate
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -work altera_mf
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -work altera_mf
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -work altera_lnsim
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/synopsys/tennm_atoms_ncrypt.sv" -work tennm
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -work tennm
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -work tennm
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96
|
||||
fi
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# add device library elaboration and simulation properties
|
||||
ELAB_OPTIONS="$ELAB_OPTIONS $QUARTUS_INSTALL_DIR/eda/sim_lib/simsf_dpi.cpp"
|
||||
|
||||
# ----------------------------------------
|
||||
# get common system verilog package design files
|
||||
TCLSCRIPT='
|
||||
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
||||
set QSYS_SIMDIR [lindex $argv 4]
|
||||
set design_files [dict create]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set design_files [dict merge $design_files [qsys_top::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
|
||||
set common_design_files [dict values $design_files]
|
||||
foreach file $common_design_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
common_design_files=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# get design files
|
||||
TCLSCRIPT='
|
||||
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
||||
set QSYS_SIMDIR [lindex $argv 4]
|
||||
set QUARTUS_INSTALL_DIR [lindex $argv 5]
|
||||
set files [list]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set files [concat $files [qsys_top::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files $files
|
||||
foreach file $design_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
design_files=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# get DPI libraries
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set libraries [dict create]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set libraries [dict merge $libraries [qsys_top::get_dpi_libraries "$QSYS_SIMDIR"]]
|
||||
set dpi_libraries [dict values $libraries]
|
||||
foreach library $dpi_libraries { puts -nonewline "$library " }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
dpi_libraries=$cmd_output
|
||||
|
||||
if [ -n "$dpi_libraries" ]; then
|
||||
echo "Using DPI Library settings"
|
||||
LDFLAGS_LOCAL=""
|
||||
for library in $dpi_libraries; do
|
||||
library=$(readlink -m $library)
|
||||
FILENAME=${library##*/}
|
||||
LDFLAGS_LOCAL+=" -Wl,-rpath ${library%/*} -L ${library%/*} -l${FILENAME:3}"
|
||||
done
|
||||
export LDFLAGS="$LDFLAGS_LOCAL $LDFLAGS"
|
||||
ELAB_OPTIONS="$ELAB_OPTIONS -debug_access+r+w+nomemcbk"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile design files in correct order
|
||||
if [ $SKIP_COM -eq 0 ]; then
|
||||
eval "$common_design_files"
|
||||
eval "$design_files"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# elaborate top level design
|
||||
if [ $SKIP_ELAB -eq 0 ]; then
|
||||
vcs -lca -t ps -liblist_work $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $DEFAULT_ELAB_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
|
||||
fi
|
||||
@@ -0,0 +1,27 @@
|
||||
|
||||
DEFINE std $CDS_ROOT/tools/inca/files/STD/
|
||||
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
|
||||
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
|
||||
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
|
||||
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
|
||||
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
|
||||
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
|
||||
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
|
||||
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
|
||||
DEFINE work ./libraries/work/
|
||||
DEFINE altera_merlin_axi_translator_1987 ./libraries/altera_merlin_axi_translator_1987/
|
||||
DEFINE altera_merlin_slave_translator_191 ./libraries/altera_merlin_slave_translator_191/
|
||||
DEFINE altera_merlin_axi_master_ni_19117 ./libraries/altera_merlin_axi_master_ni_19117/
|
||||
DEFINE altera_merlin_slave_agent_1930 ./libraries/altera_merlin_slave_agent_1930/
|
||||
DEFINE altera_avalon_sc_fifo_1932 ./libraries/altera_avalon_sc_fifo_1932/
|
||||
DEFINE altera_merlin_router_1921 ./libraries/altera_merlin_router_1921/
|
||||
DEFINE altera_avalon_st_pipeline_stage_1930 ./libraries/altera_avalon_st_pipeline_stage_1930/
|
||||
DEFINE altera_merlin_burst_adapter_1940 ./libraries/altera_merlin_burst_adapter_1940/
|
||||
DEFINE altera_merlin_demultiplexer_1921 ./libraries/altera_merlin_demultiplexer_1921/
|
||||
DEFINE altera_merlin_multiplexer_1922 ./libraries/altera_merlin_multiplexer_1922/
|
||||
DEFINE altera_mm_interconnect_1920 ./libraries/altera_mm_interconnect_1920/
|
||||
DEFINE altera_irq_mapper_2001 ./libraries/altera_irq_mapper_2001/
|
||||
DEFINE altera_reset_controller_1924 ./libraries/altera_reset_controller_1924/
|
||||
DEFINE qsys_top ./libraries/qsys_top/
|
||||
SOFTINCLUDE _device.cds.lib
|
||||
INCLUDE _default.cds.lib
|
||||
@@ -0,0 +1,10 @@
|
||||
|
||||
DEFINE std $CDS_ROOT/tools/inca/files/STD/
|
||||
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
|
||||
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
|
||||
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
|
||||
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
|
||||
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
|
||||
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
|
||||
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
|
||||
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
|
||||
@@ -0,0 +1,2 @@
|
||||
|
||||
DEFINE WORK work
|
||||
Executable
+440
@@ -0,0 +1,440 @@
|
||||
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:52:56
|
||||
|
||||
# ----------------------------------------
|
||||
# xcelium - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# qsys_top
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# Xcelium Simulation Script.
|
||||
# To write a top-level shell script that compiles Intel simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "xcelium_sim.sh", and modify text as directed.
|
||||
#
|
||||
# You can also modify the simulation flow to suit your needs. Set the
|
||||
# following variables to 1 to disable their corresponding processes:
|
||||
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
|
||||
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
|
||||
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
|
||||
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator. In this case, you must also copy the generated files
|
||||
# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
|
||||
# # into the location from which you launch the simulator, or incorporate
|
||||
# # into any existing library setup.
|
||||
# #
|
||||
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
|
||||
# # simulation libraries and Quartus-generated IP simulation files, and copy
|
||||
# # any ROM/RAM initialization files to the simulation directory.
|
||||
# # - If necessary, specify any compilation options:
|
||||
# # USER_DEFINED_COMPILE_OPTIONS
|
||||
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
|
||||
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
|
||||
# #
|
||||
# source <script generation output directory>/xcelium/xcelium_setup.sh \
|
||||
# SKIP_ELAB=1 \
|
||||
# SKIP_SIM=1 \
|
||||
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
|
||||
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
|
||||
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
|
||||
# QSYS_SIMDIR=<script generation output directory>
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the IP script)
|
||||
# #
|
||||
# xmvlog <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
|
||||
# # testbench module/entity name.
|
||||
# #
|
||||
# # Run the IP script again to elaborate and simulate the top level:
|
||||
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# #
|
||||
# source <script generation output directory>/xcelium/xcelium_setup.sh \
|
||||
# SKIP_FILE_COPY=1 \
|
||||
# SKIP_DEV_COM=1 \
|
||||
# SKIP_COM=1 \
|
||||
# TOP_LEVEL_NAME=<simulation top> \
|
||||
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
|
||||
# DEFAULT_ELAB_OPTIONS=<default elaboration options for your design> \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If qsys_top is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Intel IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Intel IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:52:56
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="qsys_top.qsys_top"
|
||||
QSYS_SIMDIR="./../"
|
||||
QUARTUS_INSTALL_DIR="/opt/altera_pro/26.1/quartus/"
|
||||
QUARTUS_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/eda/sim_lib/"
|
||||
DEVICES_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
SKIP_ELAB=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
DEFAULT_ELAB_OPTIONS=" -access +w+r+c -update -namemap_mixgen +DISABLEGENCHK -relax"
|
||||
USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
|
||||
PRECOMP_DEVICE_LIB_FILE=""
|
||||
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
#-------------------------------------------
|
||||
# check tclsh version no earlier than 8.5
|
||||
version=$(echo "puts [package vcompare [info tclversion] 8.5]; exit" | tclsh)
|
||||
if [ $version -eq -1 ]; then
|
||||
echo "Error: Minimum required tcl package version is 8.5." >&2
|
||||
exit 1
|
||||
fi
|
||||
|
||||
#-------------------------------------------
|
||||
# read .sh file to override initialized variables
|
||||
if [ -n "${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}" ] && [ -f ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE} ]; then
|
||||
echo "Sourcing ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}"
|
||||
source ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error:: This file ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE} has invalid expression/s" >&2
|
||||
exit $?
|
||||
fi
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `xmsim -version` != *"xmsim(64)"* ]]; then
|
||||
SIMULATOR_TOOL_BITNESS="bit_32"
|
||||
else
|
||||
SIMULATOR_TOOL_BITNESS="bit_64"
|
||||
fi
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set SIMULATOR_TOOL_BITNESS [lindex $argv 2]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [qsys_top::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
if {[dict size $LD_LIBRARY_PATH] !=0 } {
|
||||
set LD_LIBRARY_PATH [join [dict keys $LD_LIBRARY_PATH] ":"]
|
||||
puts "LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\""
|
||||
}
|
||||
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [qsys_top::get_elab_options $SIMULATOR_TOOL_BITNESS]
|
||||
puts "ELAB_OPTIONS+=\"$ELAB_OPTIONS\""
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [qsys_top::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
puts "SIM_OPTIONS+=\"$SIM_OPTIONS\""
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" "$SIMULATOR_TOOL_BITNESS" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
eval $cmd_output
|
||||
|
||||
#-------------------------------------------
|
||||
# Decision to skip device compilation,
|
||||
# based on value of PRECOMP_DEVICE_LIB_FILE.
|
||||
# if PRECOMP_DEVICE_LIB_FILE is set, SKIP_DEV_COM will become true
|
||||
if [ ! -z "$PRECOMP_DEVICE_LIB_FILE" ] && [ -e $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
echo "Using $PRECOMP_DEVICE_LIB_FILE for device library mapping"
|
||||
SKIP_DEV_COM=1
|
||||
else
|
||||
PRECOMP_DEVICE_LIB_FILE=""
|
||||
fi
|
||||
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set libraries [dict create]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set libraries [dict merge $libraries [qsys_top::get_design_libraries]]
|
||||
set design_libraries [dict keys $libraries]
|
||||
foreach file $design_libraries { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
design_libraries=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# create compilation libraries
|
||||
device_libraries='lpm_ver sgate_ver altera_ver altera_mf_ver tennm_ver lpm sgate altera altera_mf altera_lnsim tennm tennm_sm_hps tennm_sm4_hssi tennm_revb_hvio tennm_revb_io96 '
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
mkdir -p ./libraries/$library
|
||||
done
|
||||
fi
|
||||
|
||||
for library in $design_libraries
|
||||
do
|
||||
mkdir -p ./libraries/$library
|
||||
done
|
||||
mkdir -p ./libraries/work
|
||||
|
||||
#-------------------------------------------
|
||||
# write out _device.cds.lib including all design libraries
|
||||
echo "# DO NOT MODIFY " > _device.cds.lib
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
echo "DEFINE $library ./libraries/$library" >> _device.cds.lib
|
||||
done
|
||||
else
|
||||
echo "INCLUDE $PRECOMP_DEVICE_LIB_FILE" >> _device.cds.lib
|
||||
fi
|
||||
|
||||
#-------------------------------------------
|
||||
# write out device.cds.lib including all design libraries
|
||||
echo "# DO NOT MODIFY " > ./cds_libs/device.cds.lib
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
echo "DEFINE $library ./../libraries/$library" >> ./cds_libs/device.cds.lib
|
||||
done
|
||||
else
|
||||
echo "INCLUDE $PRECOMP_DEVICE_LIB_FILE" >> ./cds_libs/device.cds.lib
|
||||
fi
|
||||
|
||||
#-------------------------------------------
|
||||
# write out _default.cds.lib including all design libraries
|
||||
echo "# DO NOT MODIFY " > _default.cds.lib
|
||||
for library in $design_libraries
|
||||
do
|
||||
echo "DEFINE $library ./libraries/$library" >> _default.cds.lib
|
||||
done
|
||||
|
||||
#-------------------------------------------
|
||||
# create cds_libs for each design library
|
||||
for library in $design_libraries
|
||||
do
|
||||
echo "INCLUDE simulator.cds.lib" > cds_libs/$library.cds.lib
|
||||
echo "INCLUDE device.cds.lib" >> cds_libs/$library.cds.lib
|
||||
if [[ $design_libraries =~ "altera_common_sv_packages" ]] && [[ $library != "altera_common_sv_packages" ]]; then
|
||||
echo "DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/" >> cds_libs/$library.cds.lib
|
||||
fi
|
||||
echo "DEFINE $library ./../libraries/$library" >> cds_libs/$library.cds.lib
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set QUARTUS_INSTALL_DIR [lindex $argv 2]
|
||||
set memory_files [list]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set memory_files [concat $memory_files [qsys_top::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
foreach file $memory_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
memory_files=$cmd_output
|
||||
if [ $SKIP_FILE_COPY -eq 0 ]; then
|
||||
for file in $memory_files
|
||||
do
|
||||
cp -f $file ./
|
||||
done
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile device library files
|
||||
if [ $SKIP_DEV_COM -eq 0 ]; then
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -work lpm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.vhd" -work lpm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -work sgate
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -work sgate
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -work altera_mf
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -work altera_mf
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -work altera_lnsim
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/cadence/tennm_atoms_ncrypt.sv" -work tennm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -work tennm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -work tennm
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96
|
||||
fi
|
||||
gcc -fPIC -g -shared -o libdpi.so -I/`ncroot`/tools/inca/include "$QUARTUS_SIM_LIB_DIR/simsf_dpi.cpp"
|
||||
|
||||
# ----------------------------------------
|
||||
# add device library elaboration and simulation properties
|
||||
|
||||
# ----------------------------------------
|
||||
# get common system verilog package design files
|
||||
TCLSCRIPT='
|
||||
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
||||
set QSYS_SIMDIR [lindex $argv 4]
|
||||
set design_files [dict create]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set design_files [dict merge $design_files [qsys_top::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
|
||||
set common_design_files [dict values $design_files]
|
||||
foreach file $common_design_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
common_design_files=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# get design files
|
||||
TCLSCRIPT='
|
||||
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
||||
set QSYS_SIMDIR [lindex $argv 4]
|
||||
set QUARTUS_INSTALL_DIR [lindex $argv 5]
|
||||
set files [list]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set files [concat $files [qsys_top::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files $files
|
||||
foreach file $design_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
design_files=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# get DPI libraries
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set libraries [dict create]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set libraries [dict merge $libraries [qsys_top::get_dpi_libraries "$QSYS_SIMDIR"]]
|
||||
set dpi_libraries [dict values $libraries]
|
||||
foreach library $dpi_libraries { puts -nonewline "$library " }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
dpi_libraries=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# compile design files in correct order
|
||||
if [ $SKIP_COM -eq 0 ]; then
|
||||
eval "$common_design_files"
|
||||
eval "$design_files"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# elaborate top level design
|
||||
if [ $SKIP_ELAB -eq 0 ]; then
|
||||
xmelab $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $DEFAULT_ELAB_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
if [ -n "$dpi_libraries" ]; then
|
||||
echo "Using DPI Library settings"
|
||||
FILES=""
|
||||
for library in $dpi_libraries; do
|
||||
FILES+="-sv_lib $library"
|
||||
done
|
||||
eval xmsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME $FILES
|
||||
else
|
||||
eval xmsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
fi
|
||||
Reference in New Issue
Block a user