thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
430 lines
21 KiB
Bash
Executable File
430 lines
21 KiB
Bash
Executable File
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# (C) 2001-2026 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions and
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# other software and tools, and its AMPP partner logic functions, and
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# any output files any of the foregoing (including device programming
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# or simulation files), and any associated documentation or information
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# are expressly subject to the terms and conditions of the Intel
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# Program License Subscription Agreement, Intel MegaCore Function
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# License Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Intel and sold by Intel
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# or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# ACDS 26.1 110 linux 2026.04.08.10:52:56
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# ----------------------------------------
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# vcsmx - auto-generated simulation script
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# ----------------------------------------
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# This script provides commands to simulate the following IP detected in
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# your Quartus project:
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# qsys_top
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#
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# Intel recommends that you source this Quartus-generated IP simulation
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# script from your own customized top-level script, and avoid editing this
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# generated script.
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#
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# To write a top-level shell script that compiles Intel simulation libraries
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# and the Quartus-generated IP in your project, along with your design and
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# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
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# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
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#
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# You can also modify the simulation flow to suit your needs. Set the
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# following variables to 1 to disable their corresponding processes:
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# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
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# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
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# - SKIP_COM: skip compiling Quartus-generated IP simulation files
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# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
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#
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# ----------------------------------------
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# # TOP-LEVEL TEMPLATE - BEGIN
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# #
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# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
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# # construct paths to the files required to simulate the IP in your Quartus
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# # project. By default, the IP script assumes that you are launching the
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# # simulator from the IP script location. If launching from another
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# # location, set QSYS_SIMDIR to the output directory you specified when you
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# # generated the IP script, relative to the directory from which you launch
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# # the simulator. In this case, you must also copy the generated library
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# # setup "synopsys_sim.setup" into the location from which you launch the
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# # simulator, or incorporate into any existing library setup.
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# #
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# # Run Quartus-generated IP simulation script once to compile Quartus EDA
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# # simulation libraries and Quartus-generated IP simulation files, and copy
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# # any ROM/RAM initialization files to the simulation directory.
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# #
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# # - If necessary, specify any compilation options:
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# # USER_DEFINED_COMPILE_OPTIONS
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# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
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# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
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# #
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# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
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# SKIP_ELAB=1 \
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# SKIP_SIM=1 \
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# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
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# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
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# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
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# QSYS_SIMDIR=<script generation output directory>
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# #
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# # Compile all design files and testbench files, including the top level.
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# # (These are all the files required for simulation other than the files
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# # compiled by the IP script)
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# #
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# vlogan <compilation options> <design and testbench files>
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# #
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# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
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# # testbench module/entity name.
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# #
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# # Run the IP script again to elaborate and simulate the top level:
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# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
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# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
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# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
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# #
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# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
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# SKIP_FILE_COPY=1 \
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# SKIP_DEV_COM=1 \
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# SKIP_COM=1 \
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# TOP_LEVEL_NAME="'-top <simulation top>'" \
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# QSYS_SIMDIR=<script generation output directory> \
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# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
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# DEFAULT_ELAB_OPTIONS=<default elaboration options for your design> \
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# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
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# #
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# # TOP-LEVEL TEMPLATE - END
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# ----------------------------------------
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#
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# IP SIMULATION SCRIPT
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# ----------------------------------------
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# If qsys_top is one of several IP cores in your
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# Quartus project, you can generate a simulation script
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# suitable for inclusion in your top-level simulation
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# script by running the following command line:
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#
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# ip-setup-simulation --quartus-project=<quartus project>
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#
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# ip-setup-simulation will discover the Intel IP
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# within the Quartus project, and generate a unified
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# script which supports all the Intel IP within the design.
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# ----------------------------------------
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# ACDS 26.1 110 linux 2026.04.08.10:52:56
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# ----------------------------------------
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# initialize variables
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TOP_LEVEL_NAME="qsys_top.qsys_top"
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QSYS_SIMDIR="./../../"
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QUARTUS_INSTALL_DIR="/opt/altera_pro/26.1/quartus/"
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QUARTUS_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/eda/sim_lib/"
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DEVICES_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
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SKIP_FILE_COPY=0
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SKIP_DEV_COM=0
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SKIP_COM=0
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SKIP_ELAB=0
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SKIP_SIM=0
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USER_DEFINED_ELAB_OPTIONS=""
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DEFAULT_ELAB_OPTIONS=""
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USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
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PRECOMP_DEVICE_LIB_FILE=""
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# ----------------------------------------
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# overwrite variables - DO NOT MODIFY!
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# This block evaluates each command line argument, typically used for
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# overwriting variables. An example usage:
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# sh <simulator>_setup.sh SKIP_SIM=1
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for expression in "$@"; do
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eval $expression
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if [ $? -ne 0 ]; then
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echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
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exit $?
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fi
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done
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#-------------------------------------------
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# check tclsh version no earlier than 8.5
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version=$(echo "puts [package vcompare [info tclversion] 8.5]; exit" | tclsh)
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if [ $version -eq -1 ]; then
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echo "Error: Minimum required tcl package version is 8.5." >&2
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exit 1
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fi
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#-------------------------------------------
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# read .sh file to override initialized variables
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if [ -n "${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}" ] && [ -f ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE} ]; then
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echo "Sourcing ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}"
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source ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}
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if [ $? -ne 0 ]; then
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echo "Error:: This file ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE} has invalid expression/s" >&2
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exit $?
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fi
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fi
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# ----------------------------------------
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# initialize simulation properties - DO NOT MODIFY!
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ELAB_OPTIONS=""
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SIM_OPTIONS=""
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if [[ `vcs -platform` != *"amd64"* && `vcs -platform` != *"suse64"* && `vcs -platform` != *"linux64"* ]]; then
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SIMULATOR_TOOL_BITNESS="bit_32"
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else
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SIMULATOR_TOOL_BITNESS="bit_64"
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fi
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TCLSCRIPT='
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set QSYS_SIMDIR [lindex $argv 1]
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set SIMULATOR_TOOL_BITNESS [lindex $argv 2]
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source $QSYS_SIMDIR/common/vcsmx_files.tcl
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set LD_LIBRARY_PATH [dict create]
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set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [qsys_top::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
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if {[dict size $LD_LIBRARY_PATH] !=0 } {
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set LD_LIBRARY_PATH [join [dict keys $LD_LIBRARY_PATH] ":"]
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puts "LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\""
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}
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set ELAB_OPTIONS ""
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append ELAB_OPTIONS [qsys_top::get_elab_options $SIMULATOR_TOOL_BITNESS]
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puts "ELAB_OPTIONS+=\"$ELAB_OPTIONS\""
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set SIM_OPTIONS ""
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append SIM_OPTIONS [qsys_top::get_sim_options $SIMULATOR_TOOL_BITNESS]
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puts "SIM_OPTIONS+=\"$SIM_OPTIONS\""
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exit 0
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'
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cmd_output=$(
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tclsh -args "$QSYS_SIMDIR" "$SIMULATOR_TOOL_BITNESS" << SCRIPT
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$TCLSCRIPT
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SCRIPT
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)
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eval $cmd_output
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#-------------------------------------------
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# Decision to skip device compilation,
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# based on value of PRECOMP_DEVICE_LIB_FILE.
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# if PRECOMP_DEVICE_LIB_FILE is set, SKIP_DEV_COM will become true
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if [ ! -z "$PRECOMP_DEVICE_LIB_FILE" ] && [ -e $PRECOMP_DEVICE_LIB_FILE ]; then
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echo "Using $PRECOMP_DEVICE_LIB_FILE for device library mapping"
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SKIP_DEV_COM=1
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else
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PRECOMP_DEVICE_LIB_FILE=""
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fi
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TCLSCRIPT='
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set QSYS_SIMDIR [lindex $argv 1]
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set libraries [dict create]
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source $QSYS_SIMDIR/common/vcsmx_files.tcl
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set libraries [dict merge $libraries [qsys_top::get_design_libraries]]
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set design_libraries [dict keys $libraries]
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foreach file $design_libraries { puts "$file" }
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exit 0
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'
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cmd_output=$(
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tclsh -args "$QSYS_SIMDIR" << SCRIPT
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$TCLSCRIPT
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SCRIPT
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)
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design_libraries=$cmd_output
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# ----------------------------------------
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# create compilation libraries
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device_libraries='lpm_ver sgate_ver altera_ver altera_mf_ver altera_lnsim_ver tennm_ver tennm_sm_hps_ver tennm_sm4_hssi_ver tennm_revb_hvio_ver tennm_revb_io96_ver lpm sgate altera altera_mf altera_lnsim tennm tennm_sm_hps tennm_sm4_hssi tennm_revb_hvio tennm_revb_io96 '
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if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
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for library in $device_libraries
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do
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mkdir -p ./libraries/$library
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done
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fi
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for library in $design_libraries
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do
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mkdir -p ./libraries/$library
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done
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mkdir -p ./libraries/work
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#-------------------------------------------
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# write out _device_synopsys_sim.setup including all device libraries
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echo "--DONOT MODIFY" > _device_synopsys_sim.setup
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if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
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for library in $device_libraries
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do
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echo "$library: ./libraries/$library" >> _device_synopsys_sim.setup
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done
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else
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echo "OTHERS=$PRECOMP_DEVICE_LIB_FILE" >> _device_synopsys_sim.setup
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fi
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#-------------------------------------------
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# write out _default_synopsys_sim.setup including all design libraries
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echo "-- DO NOT MODIFY " > _default_synopsys_sim.setup
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for library in $design_libraries
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do
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echo "$library: ./libraries/$library" >> _default_synopsys_sim.setup
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done
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# ----------------------------------------
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# copy RAM/ROM files to simulation directory
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TCLSCRIPT='
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set QSYS_SIMDIR [lindex $argv 1]
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set QUARTUS_INSTALL_DIR [lindex $argv 2]
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set memory_files [list]
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source $QSYS_SIMDIR/common/vcsmx_files.tcl
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set memory_files [concat $memory_files [qsys_top::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
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foreach file $memory_files { puts "$file" }
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exit 0
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'
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cmd_output=$(
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tclsh -args "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
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$TCLSCRIPT
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SCRIPT
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)
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memory_files=$cmd_output
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if [ $SKIP_FILE_COPY -eq 0 ]; then
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for file in $memory_files
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do
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cp -f $file ./
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done
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fi
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# ----------------------------------------
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# compile device library files
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if [ $SKIP_DEV_COM -eq 0 ]; then
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vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver
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vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver
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vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver
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vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/synopsys/tennm_atoms_ncrypt.sv" -work tennm_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96_ver
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96_ver
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -work lpm
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.vhd" -work lpm
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -work sgate
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -work sgate
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -work altera
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -work altera
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -work altera
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -work altera
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -work altera
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -work altera
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -work altera_mf
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -work altera_mf
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -work altera_lnsim
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/synopsys/tennm_atoms_ncrypt.sv" -work tennm
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -work tennm
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vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -work tennm
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi
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vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio
|
|
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio
|
|
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96
|
|
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96
|
|
fi
|
|
|
|
|
|
# ----------------------------------------
|
|
# add device library elaboration and simulation properties
|
|
ELAB_OPTIONS="$ELAB_OPTIONS $QUARTUS_INSTALL_DIR/eda/sim_lib/simsf_dpi.cpp"
|
|
|
|
# ----------------------------------------
|
|
# get common system verilog package design files
|
|
TCLSCRIPT='
|
|
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
|
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
|
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
|
set QSYS_SIMDIR [lindex $argv 4]
|
|
set design_files [dict create]
|
|
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
|
set design_files [dict merge $design_files [qsys_top::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
|
|
set common_design_files [dict values $design_files]
|
|
foreach file $common_design_files { puts "$file" }
|
|
exit 0
|
|
'
|
|
cmd_output=$(
|
|
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
|
|
$TCLSCRIPT
|
|
SCRIPT
|
|
)
|
|
|
|
common_design_files=$cmd_output
|
|
|
|
# ----------------------------------------
|
|
# get design files
|
|
TCLSCRIPT='
|
|
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
|
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
|
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
|
set QSYS_SIMDIR [lindex $argv 4]
|
|
set QUARTUS_INSTALL_DIR [lindex $argv 5]
|
|
set files [list]
|
|
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
|
set files [concat $files [qsys_top::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
|
set design_files $files
|
|
foreach file $design_files { puts "$file" }
|
|
exit 0
|
|
'
|
|
cmd_output=$(
|
|
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
|
|
$TCLSCRIPT
|
|
SCRIPT
|
|
)
|
|
|
|
design_files=$cmd_output
|
|
|
|
# ----------------------------------------
|
|
# get DPI libraries
|
|
TCLSCRIPT='
|
|
set QSYS_SIMDIR [lindex $argv 1]
|
|
set libraries [dict create]
|
|
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
|
set libraries [dict merge $libraries [qsys_top::get_dpi_libraries "$QSYS_SIMDIR"]]
|
|
set dpi_libraries [dict values $libraries]
|
|
foreach library $dpi_libraries { puts -nonewline "$library " }
|
|
exit 0
|
|
'
|
|
cmd_output=$(
|
|
tclsh -args "$QSYS_SIMDIR" << SCRIPT
|
|
$TCLSCRIPT
|
|
SCRIPT
|
|
)
|
|
|
|
dpi_libraries=$cmd_output
|
|
|
|
if [ -n "$dpi_libraries" ]; then
|
|
echo "Using DPI Library settings"
|
|
LDFLAGS_LOCAL=""
|
|
for library in $dpi_libraries; do
|
|
library=$(readlink -m $library)
|
|
FILENAME=${library##*/}
|
|
LDFLAGS_LOCAL+=" -Wl,-rpath ${library%/*} -L ${library%/*} -l${FILENAME:3}"
|
|
done
|
|
export LDFLAGS="$LDFLAGS_LOCAL $LDFLAGS"
|
|
ELAB_OPTIONS="$ELAB_OPTIONS -debug_access+r+w+nomemcbk"
|
|
fi
|
|
|
|
# ----------------------------------------
|
|
# compile design files in correct order
|
|
if [ $SKIP_COM -eq 0 ]; then
|
|
eval "$common_design_files"
|
|
eval "$design_files"
|
|
fi
|
|
|
|
# ----------------------------------------
|
|
# elaborate top level design
|
|
if [ $SKIP_ELAB -eq 0 ]; then
|
|
vcs -lca -t ps -liblist_work $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $DEFAULT_ELAB_OPTIONS $TOP_LEVEL_NAME
|
|
fi
|
|
|
|
# ----------------------------------------
|
|
# simulate
|
|
if [ $SKIP_SIM -eq 0 ]; then
|
|
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
|
|
fi
|