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Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

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RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
thejayman77
2026-06-29 20:10:50 -04:00
commit ec82764bef
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qsys/qsys_top/altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v
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qsys/qsys_top/altera_avalon_sc_fifo_1932/synth/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v
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qsys/qsys_top/altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/26.1/ip/iconnect/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2026/02/05 $
// $Author: psgswbuild $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
parameter SYNC_RESET = 0;
parameter BACKPRESSURE_DURING_RESET = 0;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk) begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
if (SYNC_RESET == 0) begin : async_rst0
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
full1 <= 1'b0;
end else begin
// out of reset.
if(~full1 & full0)begin
full0 <= 1'b0;
end
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end // async_rst0
else begin // sync_rst0
always @(posedge clk ) begin
if (internal_sclr) begin
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
full1 <= 1'b0;
end else begin
// out of reset.
if(~full1 & full0)begin
full0 <= 1'b0;
end
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end // sync_rst0
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
if (SYNC_RESET == 0) begin : async_rst1
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end // async_rst1
else begin // sync_rst1
always @(posedge clk ) begin
if (internal_sclr) begin
data1 <= 'b0;
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end // sync_rst1
end
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "G5I3YpoCXBJB615bV2r2gMjlqLnNMBjlz2IHpbFJcrIwatpnQBq0w6xgRawbwcYhtT8Bi7pW+71GhRzEnCQuQre2+enKubtY0F7Li98guTCkKwcqYqAMbCsAKNYuoV1MCy37Y0IFMQqSuFjec6QHj+m+L1hSx7OW0pZtmbnEVr6mG3FWyYPyobrPnEk5U9j/t9f5YWIrLfdwixx/s3z+Rxz6WBaR9gZefEC5zBeQpuEKFAc9bKa7Tunkm+qSnAOFIr/a8D8P1EWhTtglSCJlP6hsx05GhDev2v+J9J95vKgUqZGNyenqCVZdxr1X5gq/bp38IaNIGRCBdC5vX3yhPVCS5OKGXs5mNy9cZH/Yx3biQEzjxvjLmP4fyF92TIeNVZAFEkArHqC4M1aebIQsavAvy6AJRmaHQYmelMqkkNEnQQaUaV6/FSbqJt5kdsDw42IHMuEjLMeIHjQPH9pBV8GenQKNZ4dirJ57BDbizwj4Xb3CKzdTkxfTbjkU8W+xG2hIO+PtGy42+W0h72r7hHq74pw2gDLeAjVPbeF9QZN9PngCqnW+wZsJWvAYng//DmkVEX/X4+JE/XzfbRJ7qVH8UIOO5Gf+X0RrM0Uhn/Rnn4ivJaeZpcn4ubjlGtfJtlLEhrKiZ5D74b5A5qYbDoVCaF/WdHne8NwiShd5B7rp5NJ+KNBYZp8V0FJ186PhnmXvTwrhJ4DXSKE4Q0dWIc1KmqVZj3ux9b93QThDNE8UW+4fJ2Eox8zdY096iefb9cG9h30yZK+0gCMcFYvt1pduLn14bP0pzcPC5tB/SL18wQsaCVDeOrynrZnStrHNofKbaMCG0VXjRLB56D30nubmYzefiEpQCxd+nS6Ng6mGINOdvfinHWqmB7G+q9mmdgjW6bpe0ux9FnmCGbqa6/vK3b6DcCXQRNN5o6Lj4kqu/CtolxspG0z2xqWDnSK3NEiBtQssu8jDf/LaTmZO1bTiapOOkEiZgpQYvcSYKZ/r9RKv2V/DVl659mXwyQ8o"
`endif
qsys/qsys_top/altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq #(
parameter
USE_FIFO_IP = 0, // unsued at moment
SYMBOLS_PER_BEAT = 1,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
USE_EMPTY = 0,
PIPELINE_READY = 1,
SYNC_RESET = 0,
// Optional ST signal widths. Value "0" means no such port.
CHANNEL_WIDTH = 0,
ERROR_WIDTH = 0,
// Derived parameters
DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
PACKET_WIDTH = 0,
EMPTY_WIDTH = 0
)
(
input clk,
input reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
localparam
PAYLOAD_WIDTH =
DATA_WIDTH +
PACKET_WIDTH +
CHANNEL_WIDTH +
EMPTY_WIDTH +
ERROR_WIDTH;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// Assign in_data and other optional in_* interface signals to in_payload.
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (CHANNEL_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
] = in_empty;
end
// optional error input
if (ERROR_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
] = in_error;
end
endgenerate
localparam NUM_128BIT_SLOTS = (PAYLOAD_WIDTH / 128) + (((PAYLOAD_WIDTH % 128) == 0) ? 0 : 1);
localparam LAST_PAYLOAD_W = ((PAYLOAD_WIDTH % 128) == 0) ? 128 : (PAYLOAD_WIDTH % 128);
genvar i;
generate
for (i = 0; i < NUM_128BIT_SLOTS; i = i + 1) begin : gen_inst
if (i == NUM_128BIT_SLOTS - 1) begin
altera_avalon_st_pipeline_base #(
.SYMBOLS_PER_BEAT (LAST_PAYLOAD_W),
.BITS_PER_SYMBOL (1),
.PIPELINE_READY (PIPELINE_READY),
.SYNC_RESET (SYNC_RESET)
) core (
.clk (clk),
.reset (reset),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_payload[(i*128)+LAST_PAYLOAD_W-1:i*128]),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_payload[(i*128)+LAST_PAYLOAD_W-1:i*128])
);
end
else begin
altera_avalon_st_pipeline_base #(
.SYMBOLS_PER_BEAT (128),
.BITS_PER_SYMBOL (1),
.PIPELINE_READY (PIPELINE_READY),
.SYNC_RESET (SYNC_RESET)
) core (
.clk (clk),
.reset (reset),
.in_ready (),
.in_valid (in_valid),
.in_data (in_payload[(i+1)*128-1:i*128]),
.out_ready (out_ready),
.out_valid (),
.out_data (out_payload[(i+1)*128-1:i*128])
);
end
end
endgenerate
// Assign out_data and other optional out_* interface signals from out_payload.
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (PACKET_WIDTH) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// Avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (CHANNEL_WIDTH) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (ERROR_WIDTH) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
endmodule
qsys/qsys_top/altera_avalon_st_pipeline_stage_1930/synth/altera_avalon_st_pipeline_base.v
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/26.1/ip/iconnect/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2026/02/05 $
// $Author: psgswbuild $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
parameter SYNC_RESET = 0;
parameter BACKPRESSURE_DURING_RESET = 0;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk) begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
if (SYNC_RESET == 0) begin : async_rst0
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
full1 <= 1'b0;
end else begin
// out of reset.
if(~full1 & full0)begin
full0 <= 1'b0;
end
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end // async_rst0
else begin // sync_rst0
always @(posedge clk ) begin
if (internal_sclr) begin
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
full1 <= 1'b0;
end else begin
// out of reset.
if(~full1 & full0)begin
full0 <= 1'b0;
end
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end // sync_rst0
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
if (SYNC_RESET == 0) begin : async_rst1
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end // async_rst1
else begin // sync_rst1
always @(posedge clk ) begin
if (internal_sclr) begin
data1 <= 'b0;
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end // sync_rst1
end
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "G5I3YpoCXBJB615bV2r2gMjlqLnNMBjlz2IHpbFJcrIwatpnQBq0w6xgRawbwcYhtT8Bi7pW+71GhRzEnCQuQre2+enKubtY0F7Li98guTCkKwcqYqAMbCsAKNYuoV1MCy37Y0IFMQqSuFjec6QHj+m+L1hSx7OW0pZtmbnEVr6mG3FWyYPyobrPnEk5U9j/t9f5YWIrLfdwixx/s3z+Rxz6WBaR9gZefEC5zBeQpuEKFAc9bKa7Tunkm+qSnAOFIr/a8D8P1EWhTtglSCJlP6hsx05GhDev2v+J9J95vKgUqZGNyenqCVZdxr1X5gq/bp38IaNIGRCBdC5vX3yhPVCS5OKGXs5mNy9cZH/Yx3biQEzjxvjLmP4fyF92TIeNVZAFEkArHqC4M1aebIQsavAvy6AJRmaHQYmelMqkkNEnQQaUaV6/FSbqJt5kdsDw42IHMuEjLMeIHjQPH9pBV8GenQKNZ4dirJ57BDbizwj4Xb3CKzdTkxfTbjkU8W+xG2hIO+PtGy42+W0h72r7hHq74pw2gDLeAjVPbeF9QZN9PngCqnW+wZsJWvAYng//DmkVEX/X4+JE/XzfbRJ7qVH8UIOO5Gf+X0RrM0Uhn/Rnn4ivJaeZpcn4ubjlGtfJtlLEhrKiZ5D74b5A5qYbDoVCaF/WdHne8NwiShd5B7rp5NJ+KNBYZp8V0FJ186PhnmXvTwrhJ4DXSKE4Q0dWIc1KmqVZj3ux9b93QThDNE8UW+4fJ2Eox8zdY096iefb9cG9h30yZK+0gCMcFYvt1pduLn14bP0pzcPC5tB/SL18wQsaCVDeOrynrZnStrHNofKbaMCG0VXjRLB56D30nubmYzefiEpQCxd+nS6Ng6mGINOdvfinHWqmB7G+q9mmdgjW6bpe0ux9FnmCGbqa6/vK3b6DcCXQRNN5o6Lj4kqu/CtolxspG0z2xqWDnSK3NEiBtQssu8jDf/LaTmZO1bTiapOOkEiZgpQYvcSYKZ/r9RKv2V/DVl659mXwyQ8o"
`endif
qsys/qsys_top/altera_avalon_st_pipeline_stage_1930/synth/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq #(
parameter
USE_FIFO_IP = 0, // unsued at moment
SYMBOLS_PER_BEAT = 1,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
USE_EMPTY = 0,
PIPELINE_READY = 1,
SYNC_RESET = 0,
// Optional ST signal widths. Value "0" means no such port.
CHANNEL_WIDTH = 0,
ERROR_WIDTH = 0,
// Derived parameters
DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
PACKET_WIDTH = 0,
EMPTY_WIDTH = 0
)
(
input clk,
input reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
localparam
PAYLOAD_WIDTH =
DATA_WIDTH +
PACKET_WIDTH +
CHANNEL_WIDTH +
EMPTY_WIDTH +
ERROR_WIDTH;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// Assign in_data and other optional in_* interface signals to in_payload.
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (CHANNEL_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
] = in_empty;
end
// optional error input
if (ERROR_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
] = in_error;
end
endgenerate
localparam NUM_128BIT_SLOTS = (PAYLOAD_WIDTH / 128) + (((PAYLOAD_WIDTH % 128) == 0) ? 0 : 1);
localparam LAST_PAYLOAD_W = ((PAYLOAD_WIDTH % 128) == 0) ? 128 : (PAYLOAD_WIDTH % 128);
genvar i;
generate
for (i = 0; i < NUM_128BIT_SLOTS; i = i + 1) begin : gen_inst
if (i == NUM_128BIT_SLOTS - 1) begin
altera_avalon_st_pipeline_base #(
.SYMBOLS_PER_BEAT (LAST_PAYLOAD_W),
.BITS_PER_SYMBOL (1),
.PIPELINE_READY (PIPELINE_READY),
.SYNC_RESET (SYNC_RESET)
) core (
.clk (clk),
.reset (reset),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_payload[(i*128)+LAST_PAYLOAD_W-1:i*128]),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_payload[(i*128)+LAST_PAYLOAD_W-1:i*128])
);
end
else begin
altera_avalon_st_pipeline_base #(
.SYMBOLS_PER_BEAT (128),
.BITS_PER_SYMBOL (1),
.PIPELINE_READY (PIPELINE_READY),
.SYNC_RESET (SYNC_RESET)
) core (
.clk (clk),
.reset (reset),
.in_ready (),
.in_valid (in_valid),
.in_data (in_payload[(i+1)*128-1:i*128]),
.out_ready (out_ready),
.out_valid (),
.out_data (out_payload[(i+1)*128-1:i*128])
);
end
end
endgenerate
// Assign out_data and other optional out_* interface signals from out_payload.
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (PACKET_WIDTH) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// Avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (CHANNEL_WIDTH) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (ERROR_WIDTH) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
endmodule
qsys/qsys_top/altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -------------------------------------------------------
// Altera IRQ Mapper
//
// Parameters
// NUM_RCVRS : 2
// SENDER_IRW_WIDTH : 32
// IRQ_MAP : 0:1,1:0
//
// -------------------------------------------------------
`timescale 1 ns / 1 ns
module qsys_top_altera_irq_mapper_2001_lp4cnei
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[1] = receiver0_irq;
sender_irq[0] = receiver1_irq;
end
endmodule
qsys/qsys_top/altera_irq_mapper_2001/synth/qsys_top_altera_irq_mapper_2001_lp4cnei.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -------------------------------------------------------
// Altera IRQ Mapper
//
// Parameters
// NUM_RCVRS : 2
// SENDER_IRW_WIDTH : 32
// IRQ_MAP : 0:1,1:0
//
// -------------------------------------------------------
`timescale 1 ns / 1 ns
module qsys_top_altera_irq_mapper_2001_lp4cnei
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[1] = receiver0_irq;
sender_irq[0] = receiver1_irq;
end
endmodule
qsys/qsys_top/altera_merlin_axi_master_ni_19116/synth/altera_merlin_address_alignment.sv
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// (C) 2001-2025 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_axi_master_ni/address_alignment.sv#3 $
// $Revision: #3 $
// $Date: 2012/07/11 $
//-----------------------------------------
// Address alignment:
// This component will aglin input address with input size
// Support address increment with butst type and burstwrap value
//-----------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_address_alignment
#(
parameter
ADDR_W = 12,
BURSTWRAP_W = 12,
TYPE_W = 2,
SIZE_W = 3,
INCREMENT_ADDRESS = 1,
NUMSYMBOLS = 8,
SELECT_BITS = log2(NUMSYMBOLS),
IN_DATA_W = ADDR_W + (BURSTWRAP_W-1) + TYPE_W + SIZE_W,
OUT_DATA_W = ADDR_W + SELECT_BITS,
SYNC_RESET = 0
)
(
input clk,
input reset,
input [IN_DATA_W-1:0] in_data, // in_data = {wrap_boundary, address, type, size}
input in_valid,
//output in_ready,
input in_sop,
input in_eop,
output reg [OUT_DATA_W-1:0] out_data,
input out_ready
//output out_valid
);
typedef enum bit [1:0]
{
FIXED = 2'b00,
INCR = 2'b01,
WRAP = 2'b10,
RESERVED = 2'b11
} AxiBurstType;
//----------------------------------------------------
// AXSIZE decoding
//
// Turns the axsize value into the actual number of bytes
// being transferred.
// ---------------------------------------------------
function reg[9:0] bytes_in_transfer;
input [SIZE_W-1:0] axsize;
case (axsize)
4'b0000: bytes_in_transfer = 10'b0000000001;
4'b0001: bytes_in_transfer = 10'b0000000010;
4'b0010: bytes_in_transfer = 10'b0000000100;
4'b0011: bytes_in_transfer = 10'b0000001000;
4'b0100: bytes_in_transfer = 10'b0000010000;
4'b0101: bytes_in_transfer = 10'b0000100000;
4'b0110: bytes_in_transfer = 10'b0001000000;
4'b0111: bytes_in_transfer = 10'b0010000000;
4'b1000: bytes_in_transfer = 10'b0100000000;
4'b1001: bytes_in_transfer = 10'b1000000000;
default: bytes_in_transfer = 10'b0000000001;
endcase
endfunction
//--------------------------------------
// Burst type decode
//--------------------------------------
AxiBurstType write_burst_type;
function AxiBurstType burst_type_decode
(
input [1:0] axburst
);
AxiBurstType burst_type;
begin
case (axburst)
2'b00 : burst_type = FIXED;
2'b01 : burst_type = INCR;
2'b10 : burst_type = WRAP;
2'b11 : burst_type = RESERVED;
default : burst_type = INCR;
endcase
return burst_type;
end
endfunction
//----------------------------------------------------
// Ubiquitous, familiar log2 function
//----------------------------------------------------
function integer log2;
input integer value;
value = value - 1;
for(log2 = 0; value > 0; log2 = log2 + 1)
value = value >> 1;
endfunction
//------------------------------------------------------------------------
// This component will read address and size and check
// if this is aligned or not. If not then it will align this address to the size
// of the transfer:
// Check alignment:
// - With data width, can define maximun how many lower bits of address to indicate this
// address align to the size
// - Ex: 32 bits data => size can be: 1, 2, 4 bytes
// For 4 bytes: when 2 lower bits of address equal 0, this is aligned address
// addr=00|00| (0), 01|00| (4) => align to size of 4 bytes
// addr=00|01| (1) => start addr at 1, is not aligned to size 4 byte
// For 2 bytes: use last one bit to indicate algined or not
// addr=000|0| (0), 001|0| (2) => align to size of 2 bytes
// addr=000|1| (1), 001|1| (3) => not align to 2 bytes
// As size runtime change, creat mask and change accordingly to size, can detect address alignment
// and to align to size, apply this mask with zero to the address.
//-------------------------------------------------------------------------
// THe function return a vector which has width [(SELECT_BITS * 2) -1 : 0]
// in which the first part contains the mask to check if this address aligned or not
// second part contains the mast to mask address to align to size
function reg[(SELECT_BITS*2)-1 : 0] mask_select_and_align_address;
input [ADDR_W-1:0] address;
input [SIZE_W-1:0] size; // size is in AXI coding: 001 -> 2 bytes
integer i;
reg [SELECT_BITS-1:0] mask_address;
reg [SELECT_BITS-1:0] check_unaligned; // any bits =1 -> unalgined (except size = 0; 1 byte)
mask_address = '1;
check_unaligned = '0;
for(i = 0; i < SELECT_BITS ; i = i + 1) begin
if (i < size) begin
check_unaligned[i] = address[i];
mask_address[i] = 1'b0;
end
end
mask_select_and_align_address = {check_unaligned,mask_address};
endfunction
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= ~reset;
end
end
endgenerate
reg [ADDR_W-1 : 0] in_address;
reg [ADDR_W-1 : 0] first_address_aligned;
reg [SIZE_W-1 : 0] in_size;
reg [(SELECT_BITS*2)-1 : 0] output_masks;
// Extract information from input data
assign in_address = in_data[SIZE_W+ADDR_W-1 : SIZE_W];
assign in_size = in_data[SIZE_W-1 : 0];
// Generate the masks
always_comb
begin
output_masks = mask_select_and_align_address(in_address, in_size);
end
// Align address if needed
generate
// SELECT_BITS == 1: input packet has 1 NUMSYMBOLS (1 bytes), it is aligned
if (SELECT_BITS == 0)
assign first_address_aligned = in_address;
else begin
// SELECT_BITS ==1 :input packet 2 bytes (2 SYMBOLS)
wire [SELECT_BITS-1 : 0] aligned_address_bits;
if (SELECT_BITS == 1)
assign aligned_address_bits = in_address[0] & output_masks[0];
else
assign aligned_address_bits = in_address[SELECT_BITS-1:0] & output_masks[SELECT_BITS-1:0];
assign first_address_aligned = {in_address[ADDR_W-1 : SELECT_BITS], aligned_address_bits};
end
endgenerate
// Increment address base on size, first address keep the same
generate
if (INCREMENT_ADDRESS)
begin
reg [ADDR_W-1 : 0] increment_address;
reg [ADDR_W-1 : 0] out_aligned_address_burst;
reg [ADDR_W-1 : 0] address_burst;
reg [ADDR_W-1 : 0] base_address;
reg [9 : 0] number_bytes_transfer;
reg [ADDR_W-1 : 0] burstwrap_mask;
reg [ADDR_W-1 : 0] burst_address_high;
reg [ADDR_W-1 : 0] burst_address_low;
reg [BURSTWRAP_W-2 :0] in_burstwrap_boundary;
reg [TYPE_W-1 : 0] in_type;
//------------------------------------------------
// Use the extended burstwrap value to split the high (constant) and
// low (changing) part of the address
//-----------------------------------------------
assign in_type = in_data[SIZE_W+ADDR_W+TYPE_W-1 : SIZE_W+ADDR_W];
assign in_burstwrap_boundary = in_data[IN_DATA_W-1 : ADDR_W+TYPE_W+SIZE_W];
assign burstwrap_mask = {{(ADDR_W - BURSTWRAP_W){1'b0}}, in_burstwrap_boundary};
assign burst_address_high = out_aligned_address_burst & ~burstwrap_mask;
assign burst_address_low = out_aligned_address_burst;
assign number_bytes_transfer = bytes_in_transfer(in_size);
assign write_burst_type = burst_type_decode(in_type);
always @*
begin
if (in_sop)
begin
out_aligned_address_burst = in_address;
base_address = first_address_aligned;
end
else
begin
out_aligned_address_burst = address_burst;
base_address = out_aligned_address_burst;
end
case (write_burst_type)
INCR:
increment_address = base_address + number_bytes_transfer;
WRAP:
increment_address = ((burst_address_low + number_bytes_transfer) & burstwrap_mask) | burst_address_high;
FIXED:
increment_address = out_aligned_address_burst;
default:
increment_address = base_address + number_bytes_transfer;
endcase // case (write_burst_type)
end // always @ *
if (SYNC_RESET == 0) begin : async_rst0
always_ff @(posedge clk, negedge reset)
begin
if (!reset)
begin
address_burst <= '0;
end
else
begin
if (in_valid & out_ready)
address_burst <= increment_address;
end
end
end : async_rst0
else begin : sync_rst0
always_ff @(posedge clk)
begin
if (internal_sclr)
begin
address_burst <= '0;
end
else
begin
if (in_valid & out_ready)
address_burst <= increment_address;
end
end
end : sync_rst0
// send data to output with 2 part: [mask_t0_algin][address_aligned_increment]
// corner case when SELECT_BITS==0 - total bits in
// [SELECTS_BITS-1:0] ==> 1-:0 ==> 2 bits in total
// leads to warning
if (SELECT_BITS==0)
assign out_data = out_aligned_address_burst;
else
assign out_data = {output_masks[SELECT_BITS-1 : 0], out_aligned_address_burst};
end // if (INCREMENT_ADDRESS)
else
begin
// corner case when SELECT_BITS==0 - total bits in
// [SELECTS_BITS-1:0] ==> 1-:0 ==> 2 bits in total
// leads to warning
if (SELECT_BITS==0)
assign out_data = first_address_aligned;
else
assign out_data = {output_masks[SELECT_BITS-1 : 0], first_address_aligned};
end // else: !if(INCREMENT_ADDRESS)
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "O1RbwSTlvZs53b7ubokKp+Nk7rGuSTOkNpMjRzZzn5NMVGzd42p1NX9kuwZQA60j+tCIqS9NnHaG5nzqHtfgtp7fohrcsKUXqyIKIAKfWCed766cAct3k2ILUmpUJtEAqpV5zoOaD68srgPmTgspcQaHjNMcKROlo6DaChJ2qrvsYpyqCVhz03+4HB4j6BFEaOMRXt+UtJCkJjdgXGytUBlr6GVVsm6UQEV0q2hxPXrE0C82zNR6wSTy7MQf16v6VAeWC91qA/Up6CIftiy28iC+Fex8Ko/T1XK8TWO3mZgGjjDY7KQ6Lj1v77kgy1WI9j4AUs+7u6xM3o9f18jnbcyVTL4YPHQRAyJWztkCfh3hGl4v614jHGkYo3z0QMF91+RYwt1BsyN2rWaObFtDGTbVwVH7GtfEJ173NBCuNcKEg00WV5hHF6oyaRiL9r2GmjiC05Y754VsqBl+KrqMm1sf/oSGgvRnxdlrRZtToBmCZ6gIJbmgL/Jk81RiXkOpyIYYJd+7F3J+IRdSNVR1cFZH3Kgg3bGx0n3iJxpTJr1BgZLuD+FwznHrIjgdZFR+Jw2V8TVOLimJGQxjNcrbTofwxv2uw3g9BZpQz07p1wXYmwUPjzYLdiyfWT/62oJyBbhYH1GxdbbgpNwXpCM/Rz3zs8Nbe1ga8FmRLzcwha0qpRXhE/qZJA8H+TigapttrL6BUYvW5//JYA9r5heoJMWgLT1xIN2C4cQRnGH9kPDBa8fayL/6IvTTA2N5+s7Dn1tV9850eO1ZVWXmbF65swJFahPxFupV28F5J60fxnTGc+cOFCBrFgDoK3PAnkSCK9rlm+KZy+nVj1y16cbvMrHwHUJw+AY/CoKwXlgHs0SURxbmRx5t55TFD/uh0Dmg7vHWzCnSANYCLEpMg/PPfX2UZTkJzt0rV9Hd7T639+JMi5q/pCsJ4mqJ7sYvnigab/3L1RLTMdcKrd1C9eVBDV1NWJrSFAstrrg6j6mfPUhM3sehFdbaj2Y1WVBTH8Cm"
`endif
qsys/qsys_top/altera_merlin_axi_master_ni_19116/synth/qsys_top_altera_merlin_axi_master_ni_19116_f5viiry.sv
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qsys/qsys_top/altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_axi_master_ni/address_alignment.sv#3 $
// $Revision: #3 $
// $Date: 2012/07/11 $
//-----------------------------------------
// Address alignment:
// This component will aglin input address with input size
// Support address increment with butst type and burstwrap value
//-----------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_address_alignment
#(
parameter
ADDR_W = 12,
BURSTWRAP_W = 12,
TYPE_W = 2,
SIZE_W = 3,
INCREMENT_ADDRESS = 1,
NUMSYMBOLS = 8,
SELECT_BITS = log2(NUMSYMBOLS),
IN_DATA_W = ADDR_W + (BURSTWRAP_W-1) + TYPE_W + SIZE_W,
OUT_DATA_W = ADDR_W + SELECT_BITS,
SYNC_RESET = 0
)
(
input clk,
input reset,
input [IN_DATA_W-1:0] in_data, // in_data = {wrap_boundary, address, type, size}
input in_valid,
//output in_ready,
input in_sop,
input in_eop,
output reg [OUT_DATA_W-1:0] out_data,
input out_ready
//output out_valid
);
typedef enum bit [1:0]
{
FIXED = 2'b00,
INCR = 2'b01,
WRAP = 2'b10,
RESERVED = 2'b11
} AxiBurstType;
//----------------------------------------------------
// AXSIZE decoding
//
// Turns the axsize value into the actual number of bytes
// being transferred.
// ---------------------------------------------------
function reg[9:0] bytes_in_transfer;
input [SIZE_W-1:0] axsize;
case (axsize)
4'b0000: bytes_in_transfer = 10'b0000000001;
4'b0001: bytes_in_transfer = 10'b0000000010;
4'b0010: bytes_in_transfer = 10'b0000000100;
4'b0011: bytes_in_transfer = 10'b0000001000;
4'b0100: bytes_in_transfer = 10'b0000010000;
4'b0101: bytes_in_transfer = 10'b0000100000;
4'b0110: bytes_in_transfer = 10'b0001000000;
4'b0111: bytes_in_transfer = 10'b0010000000;
4'b1000: bytes_in_transfer = 10'b0100000000;
4'b1001: bytes_in_transfer = 10'b1000000000;
default: bytes_in_transfer = 10'b0000000001;
endcase
endfunction
//--------------------------------------
// Burst type decode
//--------------------------------------
AxiBurstType write_burst_type;
function AxiBurstType burst_type_decode
(
input [1:0] axburst
);
AxiBurstType burst_type;
begin
case (axburst)
2'b00 : burst_type = FIXED;
2'b01 : burst_type = INCR;
2'b10 : burst_type = WRAP;
2'b11 : burst_type = RESERVED;
default : burst_type = INCR;
endcase
return burst_type;
end
endfunction
//----------------------------------------------------
// Ubiquitous, familiar log2 function
//----------------------------------------------------
function integer log2;
input integer value;
value = value - 1;
for(log2 = 0; value > 0; log2 = log2 + 1)
value = value >> 1;
endfunction
//------------------------------------------------------------------------
// This component will read address and size and check
// if this is aligned or not. If not then it will align this address to the size
// of the transfer:
// Check alignment:
// - With data width, can define maximun how many lower bits of address to indicate this
// address align to the size
// - Ex: 32 bits data => size can be: 1, 2, 4 bytes
// For 4 bytes: when 2 lower bits of address equal 0, this is aligned address
// addr=00|00| (0), 01|00| (4) => align to size of 4 bytes
// addr=00|01| (1) => start addr at 1, is not aligned to size 4 byte
// For 2 bytes: use last one bit to indicate algined or not
// addr=000|0| (0), 001|0| (2) => align to size of 2 bytes
// addr=000|1| (1), 001|1| (3) => not align to 2 bytes
// As size runtime change, creat mask and change accordingly to size, can detect address alignment
// and to align to size, apply this mask with zero to the address.
//-------------------------------------------------------------------------
// THe function return a vector which has width [(SELECT_BITS * 2) -1 : 0]
// in which the first part contains the mask to check if this address aligned or not
// second part contains the mast to mask address to align to size
function reg[(SELECT_BITS*2)-1 : 0] mask_select_and_align_address;
input [ADDR_W-1:0] address;
input [SIZE_W-1:0] size; // size is in AXI coding: 001 -> 2 bytes
integer i;
reg [SELECT_BITS-1:0] mask_address;
reg [SELECT_BITS-1:0] check_unaligned; // any bits =1 -> unalgined (except size = 0; 1 byte)
mask_address = '1;
check_unaligned = '0;
for(i = 0; i < SELECT_BITS ; i = i + 1) begin
if (i < size) begin
check_unaligned[i] = address[i];
mask_address[i] = 1'b0;
end
end
mask_select_and_align_address = {check_unaligned,mask_address};
endfunction
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= ~reset;
end
end
endgenerate
reg [ADDR_W-1 : 0] in_address;
reg [ADDR_W-1 : 0] first_address_aligned;
reg [SIZE_W-1 : 0] in_size;
reg [(SELECT_BITS*2)-1 : 0] output_masks;
// Extract information from input data
assign in_address = in_data[SIZE_W+ADDR_W-1 : SIZE_W];
assign in_size = in_data[SIZE_W-1 : 0];
// Generate the masks
always_comb
begin
output_masks = mask_select_and_align_address(in_address, in_size);
end
// Align address if needed
generate
// SELECT_BITS == 1: input packet has 1 NUMSYMBOLS (1 bytes), it is aligned
if (SELECT_BITS == 0)
assign first_address_aligned = in_address;
else begin
// SELECT_BITS ==1 :input packet 2 bytes (2 SYMBOLS)
wire [SELECT_BITS-1 : 0] aligned_address_bits;
if (SELECT_BITS == 1)
assign aligned_address_bits = in_address[0] & output_masks[0];
else
assign aligned_address_bits = in_address[SELECT_BITS-1:0] & output_masks[SELECT_BITS-1:0];
assign first_address_aligned = {in_address[ADDR_W-1 : SELECT_BITS], aligned_address_bits};
end
endgenerate
// Increment address base on size, first address keep the same
generate
if (INCREMENT_ADDRESS)
begin
reg [ADDR_W-1 : 0] increment_address;
reg [ADDR_W-1 : 0] out_aligned_address_burst;
reg [ADDR_W-1 : 0] address_burst;
reg [ADDR_W-1 : 0] base_address;
reg [9 : 0] number_bytes_transfer;
reg [ADDR_W-1 : 0] burstwrap_mask;
reg [ADDR_W-1 : 0] burst_address_high;
reg [ADDR_W-1 : 0] burst_address_low;
reg [BURSTWRAP_W-2 :0] in_burstwrap_boundary;
reg [TYPE_W-1 : 0] in_type;
//------------------------------------------------
// Use the extended burstwrap value to split the high (constant) and
// low (changing) part of the address
//-----------------------------------------------
assign in_type = in_data[SIZE_W+ADDR_W+TYPE_W-1 : SIZE_W+ADDR_W];
assign in_burstwrap_boundary = in_data[IN_DATA_W-1 : ADDR_W+TYPE_W+SIZE_W];
assign burstwrap_mask = {{(ADDR_W - BURSTWRAP_W){1'b0}}, in_burstwrap_boundary};
assign burst_address_high = out_aligned_address_burst & ~burstwrap_mask;
assign burst_address_low = out_aligned_address_burst;
assign number_bytes_transfer = bytes_in_transfer(in_size);
assign write_burst_type = burst_type_decode(in_type);
always @*
begin
if (in_sop)
begin
out_aligned_address_burst = in_address;
base_address = first_address_aligned;
end
else
begin
out_aligned_address_burst = address_burst;
base_address = out_aligned_address_burst;
end
case (write_burst_type)
INCR:
increment_address = base_address + number_bytes_transfer;
WRAP:
increment_address = ((burst_address_low + number_bytes_transfer) & burstwrap_mask) | burst_address_high;
FIXED:
increment_address = out_aligned_address_burst;
default:
increment_address = base_address + number_bytes_transfer;
endcase // case (write_burst_type)
end // always @ *
if (SYNC_RESET == 0) begin : async_rst0
always_ff @(posedge clk, negedge reset)
begin
if (!reset)
begin
address_burst <= '0;
end
else
begin
if (in_valid & out_ready)
address_burst <= increment_address;
end
end
end : async_rst0
else begin : sync_rst0
always_ff @(posedge clk)
begin
if (internal_sclr)
begin
address_burst <= '0;
end
else
begin
if (in_valid & out_ready)
address_burst <= increment_address;
end
end
end : sync_rst0
// send data to output with 2 part: [mask_t0_algin][address_aligned_increment]
// corner case when SELECT_BITS==0 - total bits in
// [SELECTS_BITS-1:0] ==> 1-:0 ==> 2 bits in total
// leads to warning
if (SELECT_BITS==0)
assign out_data = out_aligned_address_burst;
else
assign out_data = {output_masks[SELECT_BITS-1 : 0], out_aligned_address_burst};
end // if (INCREMENT_ADDRESS)
else
begin
// corner case when SELECT_BITS==0 - total bits in
// [SELECTS_BITS-1:0] ==> 1-:0 ==> 2 bits in total
// leads to warning
if (SELECT_BITS==0)
assign out_data = first_address_aligned;
else
assign out_data = {output_masks[SELECT_BITS-1 : 0], first_address_aligned};
end // else: !if(INCREMENT_ADDRESS)
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZnuSxX8yXxnIFVWsgCk75Z0P+dtbDvmJdtQl1WjW4yFuhoOU6T348GM/xUHtJ4nzM+Ie8UNgnT16AXfoOSoZ6aw4EqtmutAt1g0WrS8Zo7lntdL4Ed4jMhrdzQ2wGXcukpdBXSOlxyVkCs8O5Bx5bsJHA8kY1r+dEjpFU6yRXbht/crFehVXoHCjTTZnCo6ONciQai4cPqisPuj4rwOI0P18Yry6OKgj6AYn8jpBhuXzb8sDJ3t4lulV43YetVoYKIdiLdg9MNtOudp0cdO7C9wiNkMhIPLI2VLiAgdsxlTZo0H7/klMzcS7oMYhgKBYj3rMGfIF8GIfjTv7DXR06ED3LZScux5eFxq7qC9RRhgCFd2O/5OwjkezW2Fe1fos97+/4c0SVIufbIeAiMRsYmglnEcMCPwWnhbxi/B4Q/YpYAH96gY/+ITpxiLlp7H+Wot7TKsR10cNB8FfVYrKfDgFm3aAGBtmVsUAz3X31S6DJdo/eXRPthu3tfuBI4BAB2tQptyaBZIqDMWE/TeUinC41fvbEAe/N84+in0g3XgKSMRshfZ8yKNB5HICw0eV/rxJsVyCdWVsaafsz31CT1ij2Mvr1H7LbAUmPVt546kJCR7d/o6inwycxcb5G7r8r7du8eigB4sXm3QEMQTpHFX0PXZW0KnyL4Dml+CXK43oRj2wIP58dXUWPsi8nphSGr64d8Zt0FlS2NO2Y0jv3ecZkOIjZu+9pPoWGxFSdPY/fBYS18Q736mwIEkGiruEglqw3eKurFsVAnQNbb/cn/1"
`endif
qsys/qsys_top/altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv
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qsys/qsys_top/altera_merlin_axi_master_ni_19117/synth/altera_merlin_address_alignment.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_axi_master_ni/address_alignment.sv#3 $
// $Revision: #3 $
// $Date: 2012/07/11 $
//-----------------------------------------
// Address alignment:
// This component will aglin input address with input size
// Support address increment with butst type and burstwrap value
//-----------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_address_alignment
#(
parameter
ADDR_W = 12,
BURSTWRAP_W = 12,
TYPE_W = 2,
SIZE_W = 3,
INCREMENT_ADDRESS = 1,
NUMSYMBOLS = 8,
SELECT_BITS = log2(NUMSYMBOLS),
IN_DATA_W = ADDR_W + (BURSTWRAP_W-1) + TYPE_W + SIZE_W,
OUT_DATA_W = ADDR_W + SELECT_BITS,
SYNC_RESET = 0
)
(
input clk,
input reset,
input [IN_DATA_W-1:0] in_data, // in_data = {wrap_boundary, address, type, size}
input in_valid,
//output in_ready,
input in_sop,
input in_eop,
output reg [OUT_DATA_W-1:0] out_data,
input out_ready
//output out_valid
);
typedef enum bit [1:0]
{
FIXED = 2'b00,
INCR = 2'b01,
WRAP = 2'b10,
RESERVED = 2'b11
} AxiBurstType;
//----------------------------------------------------
// AXSIZE decoding
//
// Turns the axsize value into the actual number of bytes
// being transferred.
// ---------------------------------------------------
function reg[9:0] bytes_in_transfer;
input [SIZE_W-1:0] axsize;
case (axsize)
4'b0000: bytes_in_transfer = 10'b0000000001;
4'b0001: bytes_in_transfer = 10'b0000000010;
4'b0010: bytes_in_transfer = 10'b0000000100;
4'b0011: bytes_in_transfer = 10'b0000001000;
4'b0100: bytes_in_transfer = 10'b0000010000;
4'b0101: bytes_in_transfer = 10'b0000100000;
4'b0110: bytes_in_transfer = 10'b0001000000;
4'b0111: bytes_in_transfer = 10'b0010000000;
4'b1000: bytes_in_transfer = 10'b0100000000;
4'b1001: bytes_in_transfer = 10'b1000000000;
default: bytes_in_transfer = 10'b0000000001;
endcase
endfunction
//--------------------------------------
// Burst type decode
//--------------------------------------
AxiBurstType write_burst_type;
function AxiBurstType burst_type_decode
(
input [1:0] axburst
);
AxiBurstType burst_type;
begin
case (axburst)
2'b00 : burst_type = FIXED;
2'b01 : burst_type = INCR;
2'b10 : burst_type = WRAP;
2'b11 : burst_type = RESERVED;
default : burst_type = INCR;
endcase
return burst_type;
end
endfunction
//----------------------------------------------------
// Ubiquitous, familiar log2 function
//----------------------------------------------------
function integer log2;
input integer value;
value = value - 1;
for(log2 = 0; value > 0; log2 = log2 + 1)
value = value >> 1;
endfunction
//------------------------------------------------------------------------
// This component will read address and size and check
// if this is aligned or not. If not then it will align this address to the size
// of the transfer:
// Check alignment:
// - With data width, can define maximun how many lower bits of address to indicate this
// address align to the size
// - Ex: 32 bits data => size can be: 1, 2, 4 bytes
// For 4 bytes: when 2 lower bits of address equal 0, this is aligned address
// addr=00|00| (0), 01|00| (4) => align to size of 4 bytes
// addr=00|01| (1) => start addr at 1, is not aligned to size 4 byte
// For 2 bytes: use last one bit to indicate algined or not
// addr=000|0| (0), 001|0| (2) => align to size of 2 bytes
// addr=000|1| (1), 001|1| (3) => not align to 2 bytes
// As size runtime change, creat mask and change accordingly to size, can detect address alignment
// and to align to size, apply this mask with zero to the address.
//-------------------------------------------------------------------------
// THe function return a vector which has width [(SELECT_BITS * 2) -1 : 0]
// in which the first part contains the mask to check if this address aligned or not
// second part contains the mast to mask address to align to size
function reg[(SELECT_BITS*2)-1 : 0] mask_select_and_align_address;
input [ADDR_W-1:0] address;
input [SIZE_W-1:0] size; // size is in AXI coding: 001 -> 2 bytes
integer i;
reg [SELECT_BITS-1:0] mask_address;
reg [SELECT_BITS-1:0] check_unaligned; // any bits =1 -> unalgined (except size = 0; 1 byte)
mask_address = '1;
check_unaligned = '0;
for(i = 0; i < SELECT_BITS ; i = i + 1) begin
if (i < size) begin
check_unaligned[i] = address[i];
mask_address[i] = 1'b0;
end
end
mask_select_and_align_address = {check_unaligned,mask_address};
endfunction
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= ~reset;
end
end
endgenerate
reg [ADDR_W-1 : 0] in_address;
reg [ADDR_W-1 : 0] first_address_aligned;
reg [SIZE_W-1 : 0] in_size;
reg [(SELECT_BITS*2)-1 : 0] output_masks;
// Extract information from input data
assign in_address = in_data[SIZE_W+ADDR_W-1 : SIZE_W];
assign in_size = in_data[SIZE_W-1 : 0];
// Generate the masks
always_comb
begin
output_masks = mask_select_and_align_address(in_address, in_size);
end
// Align address if needed
generate
// SELECT_BITS == 1: input packet has 1 NUMSYMBOLS (1 bytes), it is aligned
if (SELECT_BITS == 0)
assign first_address_aligned = in_address;
else begin
// SELECT_BITS ==1 :input packet 2 bytes (2 SYMBOLS)
wire [SELECT_BITS-1 : 0] aligned_address_bits;
if (SELECT_BITS == 1)
assign aligned_address_bits = in_address[0] & output_masks[0];
else
assign aligned_address_bits = in_address[SELECT_BITS-1:0] & output_masks[SELECT_BITS-1:0];
assign first_address_aligned = {in_address[ADDR_W-1 : SELECT_BITS], aligned_address_bits};
end
endgenerate
// Increment address base on size, first address keep the same
generate
if (INCREMENT_ADDRESS)
begin
reg [ADDR_W-1 : 0] increment_address;
reg [ADDR_W-1 : 0] out_aligned_address_burst;
reg [ADDR_W-1 : 0] address_burst;
reg [ADDR_W-1 : 0] base_address;
reg [9 : 0] number_bytes_transfer;
reg [ADDR_W-1 : 0] burstwrap_mask;
reg [ADDR_W-1 : 0] burst_address_high;
reg [ADDR_W-1 : 0] burst_address_low;
reg [BURSTWRAP_W-2 :0] in_burstwrap_boundary;
reg [TYPE_W-1 : 0] in_type;
//------------------------------------------------
// Use the extended burstwrap value to split the high (constant) and
// low (changing) part of the address
//-----------------------------------------------
assign in_type = in_data[SIZE_W+ADDR_W+TYPE_W-1 : SIZE_W+ADDR_W];
assign in_burstwrap_boundary = in_data[IN_DATA_W-1 : ADDR_W+TYPE_W+SIZE_W];
assign burstwrap_mask = {{(ADDR_W - BURSTWRAP_W){1'b0}}, in_burstwrap_boundary};
assign burst_address_high = out_aligned_address_burst & ~burstwrap_mask;
assign burst_address_low = out_aligned_address_burst;
assign number_bytes_transfer = bytes_in_transfer(in_size);
assign write_burst_type = burst_type_decode(in_type);
always @*
begin
if (in_sop)
begin
out_aligned_address_burst = in_address;
base_address = first_address_aligned;
end
else
begin
out_aligned_address_burst = address_burst;
base_address = out_aligned_address_burst;
end
case (write_burst_type)
INCR:
increment_address = base_address + number_bytes_transfer;
WRAP:
increment_address = ((burst_address_low + number_bytes_transfer) & burstwrap_mask) | burst_address_high;
FIXED:
increment_address = out_aligned_address_burst;
default:
increment_address = base_address + number_bytes_transfer;
endcase // case (write_burst_type)
end // always @ *
if (SYNC_RESET == 0) begin : async_rst0
always_ff @(posedge clk, negedge reset)
begin
if (!reset)
begin
address_burst <= '0;
end
else
begin
if (in_valid & out_ready)
address_burst <= increment_address;
end
end
end : async_rst0
else begin : sync_rst0
always_ff @(posedge clk)
begin
if (internal_sclr)
begin
address_burst <= '0;
end
else
begin
if (in_valid & out_ready)
address_burst <= increment_address;
end
end
end : sync_rst0
// send data to output with 2 part: [mask_t0_algin][address_aligned_increment]
// corner case when SELECT_BITS==0 - total bits in
// [SELECTS_BITS-1:0] ==> 1-:0 ==> 2 bits in total
// leads to warning
if (SELECT_BITS==0)
assign out_data = out_aligned_address_burst;
else
assign out_data = {output_masks[SELECT_BITS-1 : 0], out_aligned_address_burst};
end // if (INCREMENT_ADDRESS)
else
begin
// corner case when SELECT_BITS==0 - total bits in
// [SELECTS_BITS-1:0] ==> 1-:0 ==> 2 bits in total
// leads to warning
if (SELECT_BITS==0)
assign out_data = first_address_aligned;
else
assign out_data = {output_masks[SELECT_BITS-1 : 0], first_address_aligned};
end // else: !if(INCREMENT_ADDRESS)
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZnuSxX8yXxnIFVWsgCk75Z0P+dtbDvmJdtQl1WjW4yFuhoOU6T348GM/xUHtJ4nzM+Ie8UNgnT16AXfoOSoZ6aw4EqtmutAt1g0WrS8Zo7lntdL4Ed4jMhrdzQ2wGXcukpdBXSOlxyVkCs8O5Bx5bsJHA8kY1r+dEjpFU6yRXbht/crFehVXoHCjTTZnCo6ONciQai4cPqisPuj4rwOI0P18Yry6OKgj6AYn8jpBhuXzb8sDJ3t4lulV43YetVoYKIdiLdg9MNtOudp0cdO7C9wiNkMhIPLI2VLiAgdsxlTZo0H7/klMzcS7oMYhgKBYj3rMGfIF8GIfjTv7DXR06ED3LZScux5eFxq7qC9RRhgCFd2O/5OwjkezW2Fe1fos97+/4c0SVIufbIeAiMRsYmglnEcMCPwWnhbxi/B4Q/YpYAH96gY/+ITpxiLlp7H+Wot7TKsR10cNB8FfVYrKfDgFm3aAGBtmVsUAz3X31S6DJdo/eXRPthu3tfuBI4BAB2tQptyaBZIqDMWE/TeUinC41fvbEAe/N84+in0g3XgKSMRshfZ8yKNB5HICw0eV/rxJsVyCdWVsaafsz31CT1ij2Mvr1H7LbAUmPVt546kJCR7d/o6inwycxcb5G7r8r7du8eigB4sXm3QEMQTpHFX0PXZW0KnyL4Dml+CXK43oRj2wIP58dXUWPsi8nphSGr64d8Zt0FlS2NO2Y0jv3ecZkOIjZu+9pPoWGxFSdPY/fBYS18Q736mwIEkGiruEglqw3eKurFsVAnQNbb/cn/1"
`endif
qsys/qsys_top/altera_merlin_axi_master_ni_19117/synth/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv
+1338
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qsys/qsys_top/altera_merlin_axi_translator_1986/synth/qsys_top_altera_merlin_axi_translator_1986_4khp5ei.sv
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@@ -0,0 +1,952 @@
// (C) 2001-2025 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// AXI Translator
//
// Convert "incomplete" AXI4 interface to
// a "complete" AXI4 interface that connect to network side
//
// Adapts between an AXI master and slave that
// are almost symmetric, with the following
// exceptions:
//
// the master's address width >= the slave's address width
// the master's id width <= the slave's id width
//
// The s0 interface on this component connects to the master,
// and the m0 interface connects to the slave.
//
// The adaptation logic is minimal in these cases, so this
// component is used instead of the heavier network
// interfaces.
// -----------------------------------------
`timescale 1 ns / 1 ns
module qsys_top_altera_merlin_axi_translator_1986_4khp5ei
#(
// ----------------
// Interface parameters
// ----------------
parameter S0_ID_WIDTH = 4,
M0_ID_WIDTH = 8,
M0_ADDR_WIDTH = 32,
S0_ADDR_WIDTH = 32,
DATA_WIDTH = 32,
M0_SAI_WIDTH = 4,
S0_SAI_WIDTH = 4,
M0_USER_ADDRCHK_WIDTH = 4,
S0_USER_ADDRCHK_WIDTH = 4,
S0_WRITE_ADDR_USER_WIDTH = 64,
S0_READ_ADDR_USER_WIDTH = 64,
M0_WRITE_ADDR_USER_WIDTH = 64,
M0_READ_ADDR_USER_WIDTH = 64,
M0_WRITE_DATA_USER_WIDTH = 64,
M0_WRITE_RESPONSE_DATA_USER_WIDTH = 64,
M0_READ_DATA_USER_WIDTH = 64,
S0_WRITE_DATA_USER_WIDTH = 64,
S0_WRITE_RESPONSE_DATA_USER_WIDTH = 64,
S0_READ_DATA_USER_WIDTH = 64,
M0_ADDRCHK_WIDTH = M0_USER_ADDRCHK_WIDTH,
S0_ADDRCHK_WIDTH = S0_USER_ADDRCHK_WIDTH,
M0_AXI_VERSION = "AXI3",
S0_AXI_VERSION = "AXI3",
// ---------------
// Master parameters
// ---------------
USE_S0_AWUSER = 0,
USE_S0_ARUSER = 0,
USE_S0_WUSER = 0,
USE_S0_RUSER = 0,
USE_S0_BUSER = 0,
USE_S0_AWID = 0,
USE_S0_AWREGION = 0,
USE_S0_AWSIZE = 0,
USE_S0_AWBURST = 0,
USE_S0_AWLEN = 0,
USE_S0_AWLOCK = 0,
USE_S0_AWCACHE = 0,
USE_S0_AWQOS = 0,
USE_S0_AWPROT = 0,
USE_S0_WSTRB = 0,
USE_S0_WLAST = 0,
USE_S0_BID = 0,
USE_S0_BRESP = 0,
USE_S0_ARID = 0,
USE_S0_ARREGION = 0,
USE_S0_ARSIZE = 0,
USE_S0_ARBURST = 0,
USE_S0_ARLEN = 0,
USE_S0_ARLOCK = 0,
USE_S0_ARCACHE = 0,
USE_S0_ARQOS = 0,
USE_S0_ARPROT = 0,
USE_S0_RID = 0,
USE_S0_RRESP = 0,
USE_S0_RLAST = 0,
S0_BURST_LENGTH_WIDTH = 8,
S0_LOCK_WIDTH = 1,
//AXI5/AXI5-Lite new capabilites signals enables
USE_S0_RPOISON = 0,
USE_S0_WPOISON = 0,
USE_S0_AWTRACE = 0,
USE_S0_ARTRACE = 0,
USE_S0_WTRACE = 0,
USE_S0_BTRACE = 0,
USE_S0_RTRACE = 0,
USE_S0_WDATACHK = 0,
USE_S0_RDATACHK = 0,
USE_S0_AWAKEUP = 0,
//AXI-USER Global signals enables
USE_S0_AWUSER_ADDRCHK = 0,
USE_S0_AWUSER_SAI = 0,
USE_S0_ARUSER_SAI = 0,
USE_S0_ARUSER_ADDRCHK = 0,
USE_S0_WUSER_DATACHK = 0,
USE_S0_WUSER_DATA = 0,
USE_S0_WUSER_POISON = 0,
USE_S0_RUSER_DATACHK = 0,
USE_S0_RUSER_DATA = 0,
USE_S0_RUSER_POISON = 0,
USE_S0_AWUNIQUE = 1,
//ACE5-Lite signals
USE_S0_AWATOP = 0,
USE_S0_AWSTASHNID = 0,
USE_S0_AWSTASHNIDEN = 0,
USE_S0_AWSTASHLPID = 0,
USE_S0_AWSTASHLPIDEN = 0,
USE_S0_AWMMUSECSID = 0,
USE_S0_AWMMUSID = 0,
USE_S0_ARMMUSECSID = 0,
USE_S0_ARMMUSID = 0,
USE_S0_AWSNOOP = 1,
USE_S0_ARSNOOP = 1,
USE_S0_AWADDRCHK = 0,
USE_S0_ARADDRCHK = 0,
REGENERATE_ADDRCHK = 0,
ROLE_BASED_USER = 0,
//-----------------
// Slave parameters
//-----------------
USE_M0_AWUNIQUE = 1,
USE_M0_AWREGION = 1,
USE_M0_AWLOCK = 1,
USE_M0_AWPROT = 1,
USE_M0_AWCACHE = 1,
USE_M0_AWQOS = 1,
USE_M0_WLAST = 1,
USE_M0_BRESP = 1,
USE_M0_ARREGION = 1,
USE_M0_ARLOCK = 1,
USE_M0_ARPROT = 1,
USE_M0_ARCACHE = 1,
USE_M0_ARQOS = 1,
USE_M0_RRESP = 1,
USE_M0_AWUSER = 0,
USE_M0_ARUSER = 0,
USE_M0_WUSER = 0,
USE_M0_RUSER = 0,
USE_M0_BUSER = 0,
//AXI5/AXI5-Lite new capabilites signals enables
USE_M0_RPOISON = 0,
USE_M0_WPOISON = 0,
USE_M0_AWTRACE = 0,
USE_M0_ARTRACE = 0,
USE_M0_WTRACE = 0,
USE_M0_BTRACE = 0,
USE_M0_RTRACE = 0,
USE_M0_WDATACHK = 0,
USE_M0_RDATACHK = 0,
USE_M0_AWAKEUP = 0,
//AXI-USER Global signals enables
USE_M0_AWUSER_ADDRCHK = 0,
USE_M0_AWUSER_SAI = 0,
USE_M0_ARUSER_SAI = 0,
USE_M0_ARUSER_ADDRCHK = 0,
USE_M0_WUSER_DATACHK = 0,
USE_M0_WUSER_DATA = 0,
USE_M0_WUSER_POISON = 0,
USE_M0_RUSER_DATACHK = 0,
USE_M0_RUSER_DATA = 0,
USE_M0_RUSER_POISON = 0,
//ACE5-Lite signals
USE_M0_AWATOP = 0,
USE_M0_AWSTASHNID = 0,
USE_M0_AWSTASHNIDEN = 0,
USE_M0_AWSTASHLPID = 0,
USE_M0_AWSTASHLPIDEN = 0,
USE_M0_AWMMUSECSID = 0,
USE_M0_AWMMUSID = 0,
USE_M0_ARMMUSECSID = 0,
USE_M0_ARMMUSID = 0,
USE_M0_AWADDRCHK = 0,
USE_M0_ARADDRCHK = 0,
M0_BURST_LENGTH_WIDTH= 8,
M0_LOCK_WIDTH = 2,
ACE_LITE_SUPPORT = 0,
ACE5_LITE_SUPPORT = 0,
M0_SID_WIDTH = 16,
S0_SID_WIDTH = 16,
M0_AWSNOOP_WIDTH = 3,
S0_AWSNOOP_WIDTH = 3,
USER_DATA_WIDTH = 1,
// ----------------
// Derived parameters
// ----------------
// Parity check generation
// Rule: calcuate parity if input is invalid (terminated with 0s) and output is required
// Otherwise, just pass-thru the input
/* |----------+-------------+-------------| */
/* | Signal | input | output | */
/* |----------+-------------+-------------| */
/* | wuser_datachk | s0_wuser_datachk | m0_wuser_datachk | */
/* | ruser_datachk | m0_ruser_datachk | s0_ruser_datachk | */
/* |----------+-------------+-------------| */
CALCULATE_WUSER_DATACHK = USE_S0_WUSER_DATACHK==0 && USE_M0_WUSER_DATACHK ==1,
CALCULATE_RUSER_DATACHK = USE_S0_RUSER_DATACHK==1 && USE_M0_RUSER_DATACHK ==0,
//AXI5Lite/AXI5
CALCULATE_WDATACHK = USE_S0_WDATACHK==0 && USE_M0_WDATACHK ==1,
CALCULATE_RDATACHK = USE_S0_RDATACHK==1 && USE_M0_RDATACHK ==0,
CALCULATE_AWUSER_ADDRCHK = USE_S0_AWUSER_ADDRCHK==0 && USE_M0_AWUSER_ADDRCHK ==1,
CALCULATE_ARUSER_ADDRCHK = USE_S0_ARUSER_ADDRCHK==0 && USE_M0_ARUSER_ADDRCHK ==1,
SKIP_USER_ADDRCHK_CAL = ((M0_ADDR_WIDTH/8) - M0_USER_ADDRCHK_WIDTH > 1) ,
ADDRCHK_WIDTH = (S0_ADDR_WIDTH + 8 - 1)/8,
S0_PADDING_ZERO = (ADDRCHK_WIDTH*8) - S0_ADDR_WIDTH,
M0_PADDING_ZERO = (ADDRCHK_WIDTH*8) - M0_ADDR_WIDTH,
M0_PARITY_ADDR_WIDTH = M0_ADDR_WIDTH + M0_PADDING_ZERO,
DATACHK_WIDTH = DATA_WIDTH / 8,
POISON_WIDTH = (DATA_WIDTH + 64 -1) / 64, // ceil(DATA_WIDTH/64) workaround
STROBE_WIDTH = DATA_WIDTH / 8,
BURST_SIZE = $clog2(STROBE_WIDTH)
)
(
// ----------------
// Clock & reset
// ----------------
input aclk,
input aresetn,
input s0_awakeup,
output m0_awakeup,
// ----------------
// Master-facing AXI interface
// ----------------
input [S0_ID_WIDTH-1:0] s0_awid,
input [S0_ADDR_WIDTH-1:0] s0_awaddr,
input [S0_BURST_LENGTH_WIDTH-1:0] s0_awlen,
input [2:0] s0_awsize,
input [1:0] s0_awburst,
input [S0_LOCK_WIDTH-1:0] s0_awlock,
input [3:0] s0_awcache,
input [2:0] s0_awprot,
input [S0_WRITE_ADDR_USER_WIDTH-1:0] s0_awuser,
input [3:0] s0_awqos,
input [3:0] s0_awregion,
input s0_awvalid,
input s0_awtrace,
output s0_awready,
input [S0_ID_WIDTH-1:0] s0_wid,
input [DATA_WIDTH-1:0] s0_wdata,
input [STROBE_WIDTH-1:0] s0_wstrb,
input [DATACHK_WIDTH-1:0] s0_wdatachk,
input [POISON_WIDTH-1:0] s0_wpoison,
input s0_wtrace,
input s0_wlast,
input [S0_WRITE_DATA_USER_WIDTH-1:0] s0_wuser,
input s0_wvalid,
output s0_wready,
output reg [S0_ID_WIDTH-1:0] s0_bid,
output reg [1:0] s0_bresp,
output [S0_WRITE_RESPONSE_DATA_USER_WIDTH-1:0] s0_buser,
output s0_bvalid,
output s0_btrace,
input s0_bready,
input [S0_ID_WIDTH-1:0] s0_arid,
input [S0_ADDR_WIDTH-1:0] s0_araddr,
input [S0_BURST_LENGTH_WIDTH-1:0] s0_arlen,
input [2:0] s0_arsize,
input [1:0] s0_arburst,
input [S0_LOCK_WIDTH-1:0] s0_arlock,
input [3:0] s0_arcache,
input [2:0] s0_arprot,
input [3:0] s0_arqos,
input [3:0] s0_arregion,
input [S0_READ_ADDR_USER_WIDTH-1:0] s0_aruser,
input s0_arvalid,
input s0_artrace,
output s0_arready,
output reg [S0_ID_WIDTH-1:0] s0_rid,
output [DATA_WIDTH-1:0] s0_rdata,
output reg [1:0] s0_rresp,
output [DATACHK_WIDTH-1:0] s0_rdatachk,
output [POISON_WIDTH-1:0] s0_rpoison,
output s0_rtrace,
output reg s0_rlast,
output [S0_READ_DATA_USER_WIDTH-1:0] s0_ruser,
output s0_rvalid,
input s0_rready,
input [1:0] s0_ardomain,
input [3:0] s0_arsnoop,
input [1:0] s0_arbar,
input [1:0] s0_awdomain,
input [S0_AWSNOOP_WIDTH-1:0] s0_awsnoop,
input [1:0] s0_awbar,
input s0_awunique,
input [S0_USER_ADDRCHK_WIDTH-1:0] s0_awuser_addrchk,
input [S0_SAI_WIDTH-1:0] s0_awuser_sai,
input [S0_SAI_WIDTH-1:0] s0_aruser_sai,
input [S0_USER_ADDRCHK_WIDTH-1:0] s0_aruser_addrchk,
input [DATACHK_WIDTH-1:0] s0_wuser_datachk,
input [USER_DATA_WIDTH-1:0] s0_wuser_data,
input [POISON_WIDTH-1:0] s0_wuser_poison,
output [DATACHK_WIDTH-1:0] s0_ruser_datachk,
output [USER_DATA_WIDTH-1:0] s0_ruser_data,
output [POISON_WIDTH-1:0] s0_ruser_poison,
input [5:0] s0_awatop,
input [10:0] s0_awstashnid,
input s0_awstashniden,
input [4:0] s0_awstashlpid,
input s0_awstashlpiden,
input s0_awmmusecsid,
input [S0_SID_WIDTH-1:0] s0_awmmusid,
input s0_armmusecsid,
input [S0_SID_WIDTH-1:0] s0_armmusid,
input [S0_ADDRCHK_WIDTH-1:0] s0_awaddrchk,
input [S0_ADDRCHK_WIDTH-1:0] s0_araddrchk,
// ----------------
// Slave-facing AXI interface
// ----------------
output reg [M0_ID_WIDTH-1:0] m0_awid,
output [M0_ADDR_WIDTH-1:0] m0_awaddr,
output reg [M0_BURST_LENGTH_WIDTH-1:0] m0_awlen,
output reg [2:0] m0_awsize,
output reg [1:0] m0_awburst,
output reg [M0_LOCK_WIDTH-1:0] m0_awlock,
output reg [3:0] m0_awcache,
output reg [2:0] m0_awprot,
output reg [3:0] m0_awqos,
output reg [3:0] m0_awregion,
output m0_awvalid,
output [M0_WRITE_ADDR_USER_WIDTH-1:0] m0_awuser,
output m0_awtrace,
input m0_awready,
output reg [M0_ID_WIDTH-1:0] m0_wid,
output [DATA_WIDTH-1:0] m0_wdata,
output reg [STROBE_WIDTH-1:0] m0_wstrb,
output [DATACHK_WIDTH-1:0] m0_wdatachk,
output [POISON_WIDTH-1:0] m0_wpoison,
output m0_wtrace,
output reg m0_wlast,
output m0_wvalid,
output [M0_WRITE_DATA_USER_WIDTH-1:0] m0_wuser,
input m0_wready,
input [M0_ID_WIDTH-1:0] m0_bid,
input [1:0] m0_bresp,
input [M0_WRITE_RESPONSE_DATA_USER_WIDTH-1:0] m0_buser,
input m0_bvalid,
input m0_btrace,
output m0_bready,
output reg [M0_ID_WIDTH-1:0] m0_arid,
output [M0_ADDR_WIDTH-1:0] m0_araddr,
output reg [M0_BURST_LENGTH_WIDTH-1:0] m0_arlen,
output reg [2:0] m0_arsize,
output reg [1:0] m0_arburst,
output reg [M0_LOCK_WIDTH-1:0] m0_arlock,
output reg [3:0] m0_arcache,
output reg [3:0] m0_arqos,
output reg [3:0] m0_arregion,
output reg [2:0] m0_arprot,
output m0_arvalid,
output [M0_READ_ADDR_USER_WIDTH-1:0] m0_aruser,
output m0_artrace,
input m0_arready,
input [M0_ID_WIDTH-1:0] m0_rid,
input [DATA_WIDTH-1:0] m0_rdata,
input [1:0] m0_rresp,
input [DATACHK_WIDTH-1:0] m0_rdatachk,
input [POISON_WIDTH-1:0] m0_rpoison,
input m0_rtrace,
input [M0_READ_DATA_USER_WIDTH-1:0] m0_ruser,
input m0_rlast,
input m0_rvalid,
output m0_rready,
output [1:0] m0_ardomain,
output reg [3:0] m0_arsnoop,
output [1:0] m0_arbar,
output [1:0] m0_awdomain,
output reg [M0_AWSNOOP_WIDTH-1:0] m0_awsnoop,
output [1:0] m0_awbar,
output reg m0_awunique,
output [M0_USER_ADDRCHK_WIDTH-1:0] m0_awuser_addrchk,
output [M0_SAI_WIDTH-1:0] m0_awuser_sai,
output [M0_SAI_WIDTH-1:0] m0_aruser_sai,
output [M0_USER_ADDRCHK_WIDTH-1:0] m0_aruser_addrchk,
output [DATACHK_WIDTH-1:0] m0_wuser_datachk,
output [USER_DATA_WIDTH-1:0] m0_wuser_data,
output [POISON_WIDTH-1:0] m0_wuser_poison,
input [DATACHK_WIDTH-1:0] m0_ruser_datachk,
input [USER_DATA_WIDTH-1:0] m0_ruser_data,
input [POISON_WIDTH-1:0] m0_ruser_poison,
output [5:0] m0_awatop,
output [10:0] m0_awstashnid,
output m0_awstashniden,
output [4:0] m0_awstashlpid,
output m0_awstashlpiden,
output m0_awmmusecsid,
output [M0_SID_WIDTH-1:0] m0_awmmusid,
output m0_armmusecsid,
output [M0_SID_WIDTH-1:0] m0_armmusid,
output [M0_ADDRCHK_WIDTH-1:0] m0_awaddrchk,
output [M0_ADDRCHK_WIDTH-1:0] m0_araddrchk
);
wire ar_parity_status;
wire aw_parity_status;
// -----------------------------------------
// All we have to do is assign everything through,
// with special care for id and address.
// Along with optional signal from AXI4 master
// pass through or assign default value
// -----------------------------------------
// The AXI translator will need handle these cases
// with different interface at both side: (mostly in 1-1 connection)
// AXI3 <-> AXI3
// AXI3 <-> AXI4
// AXI4 <-> AXI4
// AXI4 Lite <-> AXI3/AXI4
// for other mxn with interconnect inserted
// the translator will have:
// AXI4/AXI4 Lite <-> "Full" AXI4
// -----------------------------------------
// All these checking condition below apply for AXI4
// in case AXI3, all parameters will be set and passed
// correctly from hw.tcl
// -----------------------------------------
always_comb
begin
if (S0_AXI_VERSION == "AXI3") begin
// 1-1 system: AXI3 master <-{translator}-> AXI3 slave:
// when master and slave size if translator
// is both AXI3: almost pass through every signals, care
// about ID width and address width
if (M0_AXI_VERSION == "AXI3") begin
m0_awlen = s0_awlen;
m0_awsize = s0_awsize;
m0_awburst = s0_awburst;
m0_awlock = s0_awlock;
m0_awcache = s0_awcache;
m0_awprot = s0_awprot;
m0_wid = s0_wid;
m0_wstrb = s0_wstrb;
m0_wlast = s0_wlast;
m0_arlen = s0_arlen;
m0_arsize = s0_arsize;
m0_arburst = s0_arburst;
m0_arcache = s0_arcache;
m0_arprot = s0_arprot;
m0_arlock = s0_arlock;
s0_bresp = m0_bresp;
s0_rresp = m0_rresp;
s0_rlast = m0_rlast;
// Avoid QIS warning
m0_awregion = '0;
m0_awqos = '0;
m0_arregion = '0;
m0_arqos = '0;
// ID
m0_awid = s0_awid;
m0_arid = s0_arid;
m0_wid = s0_wid;
// -----------------------------------------
// Only pass the lower bits of ID through
// -----------------------------------------
s0_bid = m0_bid[S0_ID_WIDTH - 1 : 0];
s0_rid = m0_rid[S0_ID_WIDTH - 1 : 0];
end
// 1-1 system: AXI3 master <-{translator}-> AXI4 slave
// do some checking on slave side and converstion from AXI3 to AXI4 if needed (ex lock signal width)
else begin
// Check option signals in slave side only
// Signals which are not avaible in AXI3 master, drive with default value
// These signals are not avaible in AXI3 master, so the translator just assign default value
// avoid QIS waraning as well
m0_awregion = '0;
m0_awqos = '0;
m0_arregion = '0;
m0_arqos = '0;
// Need some converstion for AXI3 and AXI4
// with: AXLOCK[1:0] =b10 => AXLOCK = 0
m0_awlock = s0_awlock[0];
m0_arlock = s0_arlock[0];
// Protection signals: just do assignemnt
// even the AXI4 slave doesnt use it to avoid QIS warning
// the Port has been terninated in hw.tcl
// and these port must be always exist in AXI3 master
m0_awprot = s0_awprot;
m0_arprot = s0_arprot;
m0_wlast = s0_wlast;
m0_awcache = s0_awcache;
m0_arcache = s0_arcache;
// Pass lower bits of ID
s0_bid = m0_bid[S0_ID_WIDTH-1:0];
s0_rid = m0_rid[S0_ID_WIDTH-1:0];
// Avoid QIS warning
s0_rlast = m0_rlast;
// Pass through
m0_awlen = s0_awlen;
m0_awid = s0_awid;
m0_arid = s0_arid;
m0_awburst = s0_awburst;
m0_arburst = s0_arburst;
m0_wstrb = s0_wstrb;
m0_awsize = s0_awsize;
m0_arsize = s0_arsize;
m0_arlen = s0_arlen;
// AXI3 has no idea about QOS, so set to default for all cases.
m0_awqos = '0;
m0_arqos = '0;
// AXI3 need WID, so just so it base on AXI3, the AXI4 slave wont read this
m0_wid = s0_wid;
if (USE_M0_BRESP)
s0_bresp = m0_bresp;
else
s0_bresp = 2'b00; //OKAY
if (USE_M0_RRESP)
s0_rresp = m0_rresp;
else
s0_rresp = 2'b00; //OKAY
end // else: !if(M0_AXI_VERSION == "AXI3")
end // if (S0_AXI_VERSION == "AXI3")
// AXI4 master <-{translator}-> AXI4 slave: cases
// a) not 1-1 system: the translator can be either "master translator" or "slave translator"
// This case, one side will be always as "complete" AXI4
// Ex: if translator is at master side: AXI4 master <-{translator}-> [Interconnect Network]
// at translator's interface side at Interconnect will be always complete AXI4
// So, the translator will take care of optional signals and default value of one side
// b) 1-1 system: special case: the translator need to check on optional signal for both side of
// interface
//
else begin
// Checking on signals that can be optional for both side
// NOTE: if slave side use that signal but master side does not
// then assign outpur as default value
// if slave side does not use that signal, not matter master side
// use this or not, just pass through the value (the port has been terminated in hw.tcl)
// in HDL file, the port still there, so assign to avoid QIS warning
// Same, if both use that signal -> assign through
// it helps to reduce if and avoid warning some signal not assigned value
if ((USE_M0_AWREGION) && (!USE_S0_AWREGION))
m0_awregion = '0; //default value
else
m0_awregion = s0_awregion;
if ((USE_M0_AWLOCK) && (!USE_S0_AWLOCK))
m0_awlock = '0;
else
m0_awlock = s0_awlock;
if ((USE_M0_AWCACHE) && (!USE_S0_AWCACHE))
m0_awcache = '0;
else
m0_awcache = s0_awcache;
if ((USE_M0_AWQOS) && (!USE_S0_AWQOS))
m0_awqos = '0;
else
m0_awqos = s0_awqos;
if ((USE_S0_BRESP) && (!USE_M0_BRESP))
s0_bresp = 2'b00; //OKAY
else
s0_bresp = m0_bresp;
if ((USE_M0_ARREGION) && (!USE_S0_ARREGION))
m0_arregion = '0; //default value
else
m0_arregion = s0_arregion;
if ((USE_M0_ARLOCK) && (!USE_S0_ARLOCK))
m0_arlock = '0;
else
m0_arlock = s0_arlock;
if ((USE_M0_ARCACHE) && (!USE_S0_ARCACHE))
m0_arcache = '0;
else
m0_arcache = s0_arcache;
if ((USE_M0_ARQOS) && (!USE_S0_ARQOS))
m0_arqos = '0;
else
m0_arqos = s0_arqos;
if ((USE_S0_RRESP) && (!USE_M0_RRESP))
s0_rresp = 2'b00; //OKAY
else
s0_rresp = m0_rresp;
// Check signal that secific to each side only
// -- Master side signals
if (USE_S0_AWID)
m0_awid = s0_awid;
else
m0_awid = '0;
if (USE_S0_AWLEN)
m0_awlen = s0_awlen;
else
m0_awlen = '0;
if (USE_S0_AWSIZE)
m0_awsize = s0_awsize;
else
m0_awsize = BURST_SIZE[2:0]; // Number of symbol
if (USE_S0_AWBURST)
m0_awburst = s0_awburst;
else
m0_awburst = 2'b01; // INCR
if (USE_S0_WSTRB)
m0_wstrb = s0_wstrb;
else
m0_wstrb = {STROBE_WIDTH{1'b1}};
if (USE_S0_ARID)
m0_arid = s0_arid;
else
m0_arid = '0;
if (USE_S0_ARLEN)
m0_arlen = s0_arlen;
else
m0_arlen = '0;
if (USE_S0_ARSIZE)
m0_arsize = s0_arsize;
else
m0_arsize = BURST_SIZE[2:0]; // Number of symbol
if (USE_S0_ARBURST)
m0_arburst = s0_arburst;
else
m0_arburst = 2'b01; // INCR
if (USE_S0_AWUNIQUE)
m0_awunique = s0_awunique;
else
m0_awunique = 1'h0;
if (USE_S0_AWSNOOP)
m0_awsnoop = s0_awsnoop;
else
m0_awsnoop = 'h0;
if (USE_S0_ARSNOOP)
m0_arsnoop = s0_arsnoop;
else
m0_arsnoop = 'h0;
// these just assign to avoid warning
s0_bid = m0_bid[S0_ID_WIDTH-1:0];
s0_rid = m0_rid[S0_ID_WIDTH-1:0];
s0_rlast = m0_rlast;
// AXI4 doesnt have WID but jsut assign a value to avoid QIS warning
// the port is terminated in hw.tcl
m0_wid = '0;
// Slave side signals
m0_awprot = s0_awprot;
m0_wlast = s0_wlast;
m0_arprot = s0_arprot;
end // else: !if(S0_AXI_VERSION == "AXI3")
// When master is AXI4Lite, the slave either AXI3 or AXI4, we need to set some default values for some signals
if (S0_AXI_VERSION == "AXI4Lite") begin
// write address channel
m0_awid = '0;
m0_awlen = '0; // non-bursting
m0_awburst = 2'b01; // INCR
m0_awsize = BURST_SIZE[2:0];
m0_awlock = '0;
m0_awcache = '0;
//m0_awprot = s0_awprot;
if (USE_S0_AWPROT == 0)
m0_awprot = '0;
else
m0_awprot = s0_awprot;
m0_awqos = '0;
m0_awregion = '0;
// write data channel
m0_wid = '0;
m0_wlast = 1'b1; // AXI4 lite always sets this to 1
//write response channel
s0_bid = m0_bid;
// read address channel
m0_arid = '0;
m0_arlen = '0;
m0_arsize = BURST_SIZE[2:0];
m0_arburst = 2'b01;
m0_arlock = '0;
m0_arcache = '0;
//m0_arprot = s0_arprot;
if (USE_S0_ARPROT == 0)
m0_arprot = '0;
else
m0_arprot = s0_arprot;
m0_arqos = '0;
m0_arregion = '0;
// read data channel
s0_rid = m0_rid;
s0_rlast = 1'b1;
end // if (S0_AXI_VERSION == "AXI4Lite")
else begin
// When slave is AXI4 lite, the other side of the translator will be full AXI4 (AXI3 no translator)
// Mostly all AXI4 lite signals will back thru, other we write default values
// Pass back all ID signal, normally AXI4 lite doest support ID but it is optional that it can have if.
//AXI5Lite Condition terp
// Pass only lower bits
s0_bid = m0_bid [S0_ID_WIDTH-1:0];
s0_rid = m0_rid [S0_ID_WIDTH-1:0];
end // else: !if(S0_AXI_VERSION == "AXI4Lite")
end // always_comb
// common signals assignment for all cases
assign m0_awvalid = s0_awvalid;
assign s0_awready = m0_awready;
assign m0_wdata = s0_wdata;
assign m0_wvalid = s0_wvalid;
assign s0_wready = m0_wready;
assign m0_arvalid = s0_arvalid;
assign s0_arready = m0_arready;
assign s0_bvalid = m0_bvalid;
assign m0_bready = s0_bready;
assign s0_rdata = m0_rdata;
assign s0_rvalid = m0_rvalid;
assign m0_rready = s0_rready;
// Avoid QIS warning, master address will be always same or larger than slave
// so only assign enough bit width from master to slave
assign m0_awaddr = s0_awaddr[M0_ADDR_WIDTH-1 :0];
assign m0_araddr = s0_araddr[M0_ADDR_WIDTH-1 :0];
assign m0_awuser = USE_S0_AWUSER ? s0_awuser : '0;
assign m0_aruser = USE_S0_ARUSER ? s0_aruser : '0;
assign m0_wuser = USE_S0_WUSER ? s0_wuser : '0;
assign s0_buser = USE_M0_BUSER ? m0_buser : '0;
assign s0_ruser = USE_M0_RUSER ? m0_ruser : '0;
assign m0_wuser_poison = (USE_S0_WUSER_POISON && ROLE_BASED_USER) ? s0_wuser_poison: 1'b0;
assign s0_ruser_poison = (USE_M0_RUSER_POISON && ROLE_BASED_USER) ? m0_ruser_poison: 1'b0;
assign m0_wuser_data = (USE_S0_WUSER_DATA && ROLE_BASED_USER) ? s0_wuser_data : 1'b0;
assign s0_ruser_data = (USE_M0_RUSER_DATA && ROLE_BASED_USER) ? m0_ruser_data : 1'b0;
assign m0_awuser_sai = (USE_S0_AWUSER_SAI && ROLE_BASED_USER) ? s0_awuser_sai: 'b0;
assign m0_aruser_sai = (USE_S0_ARUSER_SAI && ROLE_BASED_USER) ? s0_aruser_sai: 'b0;
//AXI5Lite Condition terp
assign m0_awakeup = '0;
assign m0_awtrace = '0;
assign m0_artrace = '0;
assign m0_wtrace = '0;
assign s0_btrace = '0;
assign s0_rtrace = '0;
assign m0_wpoison = '0;
assign s0_rpoison = '0;
assign m0_wdatachk = '0;
assign s0_rdatachk = '0;
assign m0_ardomain = s0_ardomain;
assign m0_arbar = s0_arbar;
assign m0_awdomain = s0_awdomain;
assign m0_awbar = s0_awbar;
assign m0_awatop = (USE_S0_AWATOP ) ? s0_awatop : '0;
assign m0_awstashnid = (USE_S0_AWSTASHNID ) ? s0_awstashnid : '0;
assign m0_awstashniden = (USE_S0_AWSTASHNIDEN ) ? s0_awstashniden : '0;
assign m0_awstashlpid = (USE_S0_AWSTASHLPID ) ? s0_awstashlpid : '0;
assign m0_awstashlpiden = (USE_S0_AWSTASHLPIDEN ) ? s0_awstashlpiden : '0;
assign m0_awmmusecsid = (USE_S0_AWMMUSECSID ) ? s0_awmmusecsid : '0;
assign m0_awmmusid = (USE_S0_AWMMUSID ) ? s0_awmmusid : '0;
assign m0_armmusecsid = (USE_S0_ARMMUSECSID ) ? s0_armmusecsid : '0;
assign m0_armmusid = (USE_S0_ARMMUSID ) ? s0_armmusid : '0;
assign m0_awaddrchk = (USE_S0_AWADDRCHK ) ? s0_awaddrchk : '0;
assign m0_araddrchk = (USE_S0_ARADDRCHK ) ? s0_araddrchk : '0;
generate
if (CALCULATE_WUSER_DATACHK && ROLE_BASED_USER) begin
assign m0_wuser_datachk = calcParity(s0_wdata);
end
else if(ROLE_BASED_USER && USE_S0_WUSER_DATACHK) begin
assign m0_wuser_datachk = s0_wuser_datachk;
end else begin
assign m0_wuser_datachk = '0;
end
if (CALCULATE_RUSER_DATACHK && ROLE_BASED_USER) begin
assign s0_ruser_datachk = calcParity(m0_rdata);
end else if(ROLE_BASED_USER && USE_M0_RUSER_DATACHK) begin
assign s0_ruser_datachk = m0_ruser_datachk;
end else begin
assign s0_ruser_datachk = '0;
end
if (CALCULATE_AWUSER_ADDRCHK && ROLE_BASED_USER) begin
assign ar_parity_status = 1'b0;
if(SKIP_USER_ADDRCHK_CAL) begin
assign m0_awuser_addrchk = '0;
end
else begin
assign m0_awuser_addrchk = addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_awaddr});
end
end else if(REGENERATE_ADDRCHK) begin
wire [S0_USER_ADDRCHK_WIDTH-1:0] expected_awuser_addrchk_parity;
assign expected_awuser_addrchk_parity = addrcalcParity ( {{S0_PADDING_ZERO{1'b0}},s0_awaddr });
assign aw_parity_status = (expected_awuser_addrchk_parity == s0_awuser_addrchk) ? 1'b0 : 1'b1;
assign m0_awuser_addrchk = aw_parity_status ? addrcalc_incorrectParity({{M0_PADDING_ZERO{1'b0}},m0_awaddr}): addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_awaddr});
end else if(ROLE_BASED_USER && USE_S0_AWUSER_ADDRCHK) begin
assign m0_awuser_addrchk = s0_awuser_addrchk;
assign ar_parity_status = 1'b0;
end else begin
assign m0_awuser_addrchk = '0;
assign ar_parity_status = 1'b0;
end
if (CALCULATE_ARUSER_ADDRCHK && ROLE_BASED_USER) begin
assign aw_parity_status = 1'b0;
if(SKIP_USER_ADDRCHK_CAL) begin
assign m0_awuser_addrchk = '0;
end
else begin
assign m0_aruser_addrchk = addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_araddr});
end
end else if(REGENERATE_ADDRCHK) begin
wire [S0_USER_ADDRCHK_WIDTH-1:0] expected_aruser_addrchk_parity;
assign ar_parity_status = (expected_aruser_addrchk_parity == s0_aruser_addrchk) ? 1'b0 : 1'b1;
assign expected_aruser_addrchk_parity = addrcalcParity ( {{S0_PADDING_ZERO{1'b0}},s0_araddr});
assign m0_aruser_addrchk = ar_parity_status ? addrcalc_incorrectParity({{M0_PADDING_ZERO{1'b0}},m0_araddr}): addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_araddr});
end else if(ROLE_BASED_USER && USE_S0_ARUSER_ADDRCHK) begin
assign ar_parity_status = 1'b0;
assign m0_aruser_addrchk = s0_aruser_addrchk;
end else begin
assign aw_parity_status = 1'b0;
assign m0_aruser_addrchk = '0;
end
endgenerate;
// --------------------------------------------------
//
// calcParity function: calculate byte-level parity of arbitrary-sized signal
//
// --------------------------------------------------
function reg [DATACHK_WIDTH-1:0] calcParity (
input [DATA_WIDTH-1:0] data
);
for (int i=0; i<DATACHK_WIDTH; i++)
calcParity[i] = ~(^ data[i*8 +:8]);
endfunction
//address parity generation logic
function reg [ADDRCHK_WIDTH-1:0] addrcalcParity (
input [M0_PARITY_ADDR_WIDTH-1:0] addr
);
for (int i=0; i<ADDRCHK_WIDTH; i++)
addrcalcParity[i] = ~(^ addr[i*8 +:8]);
endfunction
// --------------------------------------------------
// addrcalc_incorrectParity: calculates byte-level incorrect parity signal
// --------------------------------------------------
function reg [ADDRCHK_WIDTH-1:0] addrcalc_incorrectParity (
input [M0_PARITY_ADDR_WIDTH-1:0] addr
);
reg [ADDRCHK_WIDTH-1:0]addrcalcParity;
for (int i=0; i<ADDRCHK_WIDTH; i++)
addrcalcParity[i] = ~(^ addr[i*8 +:8]);
addrcalc_incorrectParity =~addrcalcParity;
endfunction
endmodule
qsys/qsys_top/altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv
+963
View File
@@ -0,0 +1,963 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// AXI Translator
//
// Convert "incomplete" AXI4 interface to
// a "complete" AXI4 interface that connect to network side
//
// Adapts between an AXI master and slave that
// are almost symmetric, with the following
// exceptions:
//
// the master's address width >= the slave's address width
// the master's id width <= the slave's id width
//
// The s0 interface on this component connects to the master,
// and the m0 interface connects to the slave.
//
// The adaptation logic is minimal in these cases, so this
// component is used instead of the heavier network
// interfaces.
// -----------------------------------------
`timescale 1 ns / 1 ns
module qsys_top_altera_merlin_axi_translator_1987_lty7xoq
#(
// ----------------
// Interface parameters
// ----------------
parameter S0_ID_WIDTH = 4,
M0_ID_WIDTH = 8,
M0_ADDR_WIDTH = 32,
S0_ADDR_WIDTH = 32,
DATA_WIDTH = 32,
M0_SAI_WIDTH = 4,
S0_SAI_WIDTH = 4,
M0_USER_ADDRCHK_WIDTH = 4,
S0_USER_ADDRCHK_WIDTH = 4,
S0_WRITE_ADDR_USER_WIDTH = 64,
S0_READ_ADDR_USER_WIDTH = 64,
M0_WRITE_ADDR_USER_WIDTH = 64,
M0_READ_ADDR_USER_WIDTH = 64,
M0_WRITE_DATA_USER_WIDTH = 64,
M0_WRITE_RESPONSE_DATA_USER_WIDTH = 64,
M0_READ_DATA_USER_WIDTH = 64,
S0_WRITE_DATA_USER_WIDTH = 64,
S0_WRITE_RESPONSE_DATA_USER_WIDTH = 64,
S0_READ_DATA_USER_WIDTH = 64,
M0_ADDRCHK_WIDTH = M0_USER_ADDRCHK_WIDTH,
S0_ADDRCHK_WIDTH = S0_USER_ADDRCHK_WIDTH,
M0_AXI_VERSION = "AXI3",
S0_AXI_VERSION = "AXI3",
TERMINATE_READ_CHANNEL =0,
TERMINATE_WRITE_CHANNEL =0,
// ---------------
// Master parameters
// ---------------
USE_S0_AWUSER = 0,
USE_S0_ARUSER = 0,
USE_S0_WUSER = 0,
USE_S0_RUSER = 0,
USE_S0_BUSER = 0,
USE_S0_AWID = 0,
USE_S0_AWREGION = 0,
USE_S0_AWSIZE = 0,
USE_S0_AWBURST = 0,
USE_S0_AWLEN = 0,
USE_S0_AWLOCK = 0,
USE_S0_AWCACHE = 0,
USE_S0_AWQOS = 0,
USE_S0_AWPROT = 0,
USE_S0_WSTRB = 0,
USE_S0_WLAST = 0,
USE_S0_BID = 0,
USE_S0_BRESP = 0,
USE_S0_ARID = 0,
USE_S0_ARREGION = 0,
USE_S0_ARSIZE = 0,
USE_S0_ARBURST = 0,
USE_S0_ARLEN = 0,
USE_S0_ARLOCK = 0,
USE_S0_ARCACHE = 0,
USE_S0_ARQOS = 0,
USE_S0_ARPROT = 0,
USE_S0_RID = 0,
USE_S0_RRESP = 0,
USE_S0_RLAST = 0,
S0_BURST_LENGTH_WIDTH = 8,
S0_LOCK_WIDTH = 1,
//AXI5/AXI5-Lite new capabilites signals enables
USE_S0_RPOISON = 0,
USE_S0_WPOISON = 0,
USE_S0_AWTRACE = 0,
USE_S0_ARTRACE = 0,
USE_S0_WTRACE = 0,
USE_S0_BTRACE = 0,
USE_S0_RTRACE = 0,
USE_S0_WDATACHK = 0,
USE_S0_RDATACHK = 0,
USE_S0_AWAKEUP = 0,
//AXI-USER Global signals enables
USE_S0_AWUSER_ADDRCHK = 0,
USE_S0_AWUSER_SAI = 0,
USE_S0_ARUSER_SAI = 0,
USE_S0_ARUSER_ADDRCHK = 0,
USE_S0_WUSER_DATACHK = 0,
USE_S0_WUSER_DATA = 0,
USE_S0_WUSER_POISON = 0,
USE_S0_RUSER_DATACHK = 0,
USE_S0_RUSER_DATA = 0,
USE_S0_RUSER_POISON = 0,
USE_S0_AWUNIQUE = 1,
//ACE5-Lite signals
USE_S0_AWATOP = 0,
USE_S0_AWSTASHNID = 0,
USE_S0_AWSTASHNIDEN = 0,
USE_S0_AWSTASHLPID = 0,
USE_S0_AWSTASHLPIDEN = 0,
USE_S0_AWMMUSECSID = 0,
USE_S0_AWMMUSID = 0,
USE_S0_ARMMUSECSID = 0,
USE_S0_ARMMUSID = 0,
USE_S0_AWSNOOP = 1,
USE_S0_ARSNOOP = 1,
USE_S0_AWADDRCHK = 0,
USE_S0_ARADDRCHK = 0,
REGENERATE_ADDRCHK = 0,
ROLE_BASED_USER = 0,
//-----------------
// Slave parameters
//-----------------
USE_M0_AWUNIQUE = 1,
USE_M0_AWREGION = 1,
USE_M0_AWLOCK = 1,
USE_M0_AWPROT = 1,
USE_M0_AWCACHE = 1,
USE_M0_AWQOS = 1,
USE_M0_WLAST = 1,
USE_M0_BRESP = 1,
USE_M0_ARREGION = 1,
USE_M0_ARLOCK = 1,
USE_M0_ARPROT = 1,
USE_M0_ARCACHE = 1,
USE_M0_ARQOS = 1,
USE_M0_RRESP = 1,
USE_M0_AWUSER = 0,
USE_M0_ARUSER = 0,
USE_M0_WUSER = 0,
USE_M0_RUSER = 0,
USE_M0_BUSER = 0,
//AXI5/AXI5-Lite new capabilites signals enables
USE_M0_RPOISON = 0,
USE_M0_WPOISON = 0,
USE_M0_AWTRACE = 0,
USE_M0_ARTRACE = 0,
USE_M0_WTRACE = 0,
USE_M0_BTRACE = 0,
USE_M0_RTRACE = 0,
USE_M0_WDATACHK = 0,
USE_M0_RDATACHK = 0,
USE_M0_AWAKEUP = 0,
//AXI-USER Global signals enables
USE_M0_AWUSER_ADDRCHK = 0,
USE_M0_AWUSER_SAI = 0,
USE_M0_ARUSER_SAI = 0,
USE_M0_ARUSER_ADDRCHK = 0,
USE_M0_WUSER_DATACHK = 0,
USE_M0_WUSER_DATA = 0,
USE_M0_WUSER_POISON = 0,
USE_M0_RUSER_DATACHK = 0,
USE_M0_RUSER_DATA = 0,
USE_M0_RUSER_POISON = 0,
//ACE5-Lite signals
USE_M0_AWATOP = 0,
USE_M0_AWSTASHNID = 0,
USE_M0_AWSTASHNIDEN = 0,
USE_M0_AWSTASHLPID = 0,
USE_M0_AWSTASHLPIDEN = 0,
USE_M0_AWMMUSECSID = 0,
USE_M0_AWMMUSID = 0,
USE_M0_ARMMUSECSID = 0,
USE_M0_ARMMUSID = 0,
USE_M0_AWADDRCHK = 0,
USE_M0_ARADDRCHK = 0,
M0_BURST_LENGTH_WIDTH= 8,
M0_LOCK_WIDTH = 2,
ACE_LITE_SUPPORT = 0,
ACE5_LITE_SUPPORT = 0,
M0_SID_WIDTH = 16,
S0_SID_WIDTH = 16,
M0_AWSNOOP_WIDTH = 3,
S0_AWSNOOP_WIDTH = 3,
USER_DATA_WIDTH = 1,
// ----------------
// Derived parameters
// ----------------
// Parity check generation
// Rule: calcuate parity if input is invalid (terminated with 0s) and output is required
// Otherwise, just pass-thru the input
/* |----------+-------------+-------------| */
/* | Signal | input | output | */
/* |----------+-------------+-------------| */
/* | wuser_datachk | s0_wuser_datachk | m0_wuser_datachk | */
/* | ruser_datachk | m0_ruser_datachk | s0_ruser_datachk | */
/* |----------+-------------+-------------| */
CALCULATE_WUSER_DATACHK = USE_S0_WUSER_DATACHK==0 && USE_M0_WUSER_DATACHK ==1,
CALCULATE_RUSER_DATACHK = USE_S0_RUSER_DATACHK==1 && USE_M0_RUSER_DATACHK ==0,
//AXI5Lite/AXI5
CALCULATE_WDATACHK = USE_S0_WDATACHK==0 && USE_M0_WDATACHK ==1,
CALCULATE_RDATACHK = USE_S0_RDATACHK==1 && USE_M0_RDATACHK ==0,
CALCULATE_AWUSER_ADDRCHK = USE_S0_AWUSER_ADDRCHK==0 && USE_M0_AWUSER_ADDRCHK ==1,
CALCULATE_ARUSER_ADDRCHK = USE_S0_ARUSER_ADDRCHK==0 && USE_M0_ARUSER_ADDRCHK ==1,
SKIP_USER_ADDRCHK_CAL = ((M0_ADDR_WIDTH/8) - M0_USER_ADDRCHK_WIDTH > 1) ,
ADDRCHK_WIDTH = (S0_ADDR_WIDTH + 8 - 1)/8,
S0_PADDING_ZERO = (ADDRCHK_WIDTH*8) - S0_ADDR_WIDTH,
M0_PADDING_ZERO = (ADDRCHK_WIDTH*8) - M0_ADDR_WIDTH,
M0_PARITY_ADDR_WIDTH = M0_ADDR_WIDTH + M0_PADDING_ZERO,
DATACHK_WIDTH = DATA_WIDTH / 8,
POISON_WIDTH = (DATA_WIDTH + 64 -1) / 64, // ceil(DATA_WIDTH/64) workaround
STROBE_WIDTH = DATA_WIDTH / 8,
BURST_SIZE = $clog2(STROBE_WIDTH)
)
(
// ----------------
// Clock & reset
// ----------------
input aclk,
input aresetn,
input s0_awakeup,
output m0_awakeup,
// ----------------
// Master-facing AXI interface
// ----------------
input [S0_ID_WIDTH-1:0] s0_awid,
input [S0_ADDR_WIDTH-1:0] s0_awaddr,
input [S0_BURST_LENGTH_WIDTH-1:0] s0_awlen,
input [2:0] s0_awsize,
input [1:0] s0_awburst,
input [S0_LOCK_WIDTH-1:0] s0_awlock,
input [3:0] s0_awcache,
input [2:0] s0_awprot,
input [S0_WRITE_ADDR_USER_WIDTH-1:0] s0_awuser,
input [3:0] s0_awqos,
input [3:0] s0_awregion,
input s0_awvalid,
input s0_awtrace,
output s0_awready,
input [S0_ID_WIDTH-1:0] s0_wid,
input [DATA_WIDTH-1:0] s0_wdata,
input [STROBE_WIDTH-1:0] s0_wstrb,
input [DATACHK_WIDTH-1:0] s0_wdatachk,
input [POISON_WIDTH-1:0] s0_wpoison,
input s0_wtrace,
input s0_wlast,
input [S0_WRITE_DATA_USER_WIDTH-1:0] s0_wuser,
input s0_wvalid,
output s0_wready,
output reg [S0_ID_WIDTH-1:0] s0_bid,
output reg [1:0] s0_bresp,
output [S0_WRITE_RESPONSE_DATA_USER_WIDTH-1:0] s0_buser,
output s0_bvalid,
output s0_btrace,
input s0_bready,
input [S0_ID_WIDTH-1:0] s0_arid,
input [S0_ADDR_WIDTH-1:0] s0_araddr,
input [S0_BURST_LENGTH_WIDTH-1:0] s0_arlen,
input [2:0] s0_arsize,
input [1:0] s0_arburst,
input [S0_LOCK_WIDTH-1:0] s0_arlock,
input [3:0] s0_arcache,
input [2:0] s0_arprot,
input [3:0] s0_arqos,
input [3:0] s0_arregion,
input [S0_READ_ADDR_USER_WIDTH-1:0] s0_aruser,
input s0_arvalid,
input s0_artrace,
output s0_arready,
output reg [S0_ID_WIDTH-1:0] s0_rid,
output [DATA_WIDTH-1:0] s0_rdata,
output reg [1:0] s0_rresp,
output [DATACHK_WIDTH-1:0] s0_rdatachk,
output [POISON_WIDTH-1:0] s0_rpoison,
output s0_rtrace,
output reg s0_rlast,
output [S0_READ_DATA_USER_WIDTH-1:0] s0_ruser,
output s0_rvalid,
input s0_rready,
input [1:0] s0_ardomain,
input [3:0] s0_arsnoop,
input [1:0] s0_arbar,
input [1:0] s0_awdomain,
input [S0_AWSNOOP_WIDTH-1:0] s0_awsnoop,
input [1:0] s0_awbar,
input s0_awunique,
input [S0_USER_ADDRCHK_WIDTH-1:0] s0_awuser_addrchk,
input [S0_SAI_WIDTH-1:0] s0_awuser_sai,
input [S0_SAI_WIDTH-1:0] s0_aruser_sai,
input [S0_USER_ADDRCHK_WIDTH-1:0] s0_aruser_addrchk,
input [DATACHK_WIDTH-1:0] s0_wuser_datachk,
input [USER_DATA_WIDTH-1:0] s0_wuser_data,
input [POISON_WIDTH-1:0] s0_wuser_poison,
output [DATACHK_WIDTH-1:0] s0_ruser_datachk,
output [USER_DATA_WIDTH-1:0] s0_ruser_data,
output [POISON_WIDTH-1:0] s0_ruser_poison,
input [5:0] s0_awatop,
input [10:0] s0_awstashnid,
input s0_awstashniden,
input [4:0] s0_awstashlpid,
input s0_awstashlpiden,
input s0_awmmusecsid,
input [S0_SID_WIDTH-1:0] s0_awmmusid,
input s0_armmusecsid,
input [S0_SID_WIDTH-1:0] s0_armmusid,
input [S0_ADDRCHK_WIDTH-1:0] s0_awaddrchk,
input [S0_ADDRCHK_WIDTH-1:0] s0_araddrchk,
// ----------------
// Slave-facing AXI interface
// ----------------
output reg [M0_ID_WIDTH-1:0] m0_awid,
output [M0_ADDR_WIDTH-1:0] m0_awaddr,
output reg [M0_BURST_LENGTH_WIDTH-1:0] m0_awlen,
output reg [2:0] m0_awsize,
output reg [1:0] m0_awburst,
output reg [M0_LOCK_WIDTH-1:0] m0_awlock,
output reg [3:0] m0_awcache,
output reg [2:0] m0_awprot,
output reg [3:0] m0_awqos,
output reg [3:0] m0_awregion,
output m0_awvalid,
output [M0_WRITE_ADDR_USER_WIDTH-1:0] m0_awuser,
output m0_awtrace,
input m0_awready,
output reg [M0_ID_WIDTH-1:0] m0_wid,
output [DATA_WIDTH-1:0] m0_wdata,
output reg [STROBE_WIDTH-1:0] m0_wstrb,
output [DATACHK_WIDTH-1:0] m0_wdatachk,
output [POISON_WIDTH-1:0] m0_wpoison,
output m0_wtrace,
output reg m0_wlast,
output m0_wvalid,
output [M0_WRITE_DATA_USER_WIDTH-1:0] m0_wuser,
input m0_wready,
input [M0_ID_WIDTH-1:0] m0_bid,
input [1:0] m0_bresp,
input [M0_WRITE_RESPONSE_DATA_USER_WIDTH-1:0] m0_buser,
input m0_bvalid,
input m0_btrace,
output m0_bready,
output reg [M0_ID_WIDTH-1:0] m0_arid,
output [M0_ADDR_WIDTH-1:0] m0_araddr,
output reg [M0_BURST_LENGTH_WIDTH-1:0] m0_arlen,
output reg [2:0] m0_arsize,
output reg [1:0] m0_arburst,
output reg [M0_LOCK_WIDTH-1:0] m0_arlock,
output reg [3:0] m0_arcache,
output reg [3:0] m0_arqos,
output reg [3:0] m0_arregion,
output reg [2:0] m0_arprot,
output m0_arvalid,
output [M0_READ_ADDR_USER_WIDTH-1:0] m0_aruser,
output m0_artrace,
input m0_arready,
input [M0_ID_WIDTH-1:0] m0_rid,
input [DATA_WIDTH-1:0] m0_rdata,
input [1:0] m0_rresp,
input [DATACHK_WIDTH-1:0] m0_rdatachk,
input [POISON_WIDTH-1:0] m0_rpoison,
input m0_rtrace,
input [M0_READ_DATA_USER_WIDTH-1:0] m0_ruser,
input m0_rlast,
input m0_rvalid,
output m0_rready,
output [1:0] m0_ardomain,
output reg [3:0] m0_arsnoop,
output [1:0] m0_arbar,
output [1:0] m0_awdomain,
output reg [M0_AWSNOOP_WIDTH-1:0] m0_awsnoop,
output [1:0] m0_awbar,
output reg m0_awunique,
output [M0_USER_ADDRCHK_WIDTH-1:0] m0_awuser_addrchk,
output [M0_SAI_WIDTH-1:0] m0_awuser_sai,
output [M0_SAI_WIDTH-1:0] m0_aruser_sai,
output [M0_USER_ADDRCHK_WIDTH-1:0] m0_aruser_addrchk,
output [DATACHK_WIDTH-1:0] m0_wuser_datachk,
output [USER_DATA_WIDTH-1:0] m0_wuser_data,
output [POISON_WIDTH-1:0] m0_wuser_poison,
input [DATACHK_WIDTH-1:0] m0_ruser_datachk,
input [USER_DATA_WIDTH-1:0] m0_ruser_data,
input [POISON_WIDTH-1:0] m0_ruser_poison,
output [5:0] m0_awatop,
output [10:0] m0_awstashnid,
output m0_awstashniden,
output [4:0] m0_awstashlpid,
output m0_awstashlpiden,
output m0_awmmusecsid,
output [M0_SID_WIDTH-1:0] m0_awmmusid,
output m0_armmusecsid,
output [M0_SID_WIDTH-1:0] m0_armmusid,
output [M0_ADDRCHK_WIDTH-1:0] m0_awaddrchk,
output [M0_ADDRCHK_WIDTH-1:0] m0_araddrchk
);
wire ar_parity_status;
wire aw_parity_status;
// -----------------------------------------
// All we have to do is assign everything through,
// with special care for id and address.
// Along with optional signal from AXI4 master
// pass through or assign default value
// -----------------------------------------
// The AXI translator will need handle these cases
// with different interface at both side: (mostly in 1-1 connection)
// AXI3 <-> AXI3
// AXI3 <-> AXI4
// AXI4 <-> AXI4
// AXI4 Lite <-> AXI3/AXI4
// for other mxn with interconnect inserted
// the translator will have:
// AXI4/AXI4 Lite <-> "Full" AXI4
// -----------------------------------------
// All these checking condition below apply for AXI4
// in case AXI3, all parameters will be set and passed
// correctly from hw.tcl
// -----------------------------------------
always_comb
begin
if (S0_AXI_VERSION == "AXI3") begin
// 1-1 system: AXI3 master <-{translator}-> AXI3 slave:
// when master and slave size if translator
// is both AXI3: almost pass through every signals, care
// about ID width and address width
if (M0_AXI_VERSION == "AXI3") begin
m0_awlen = s0_awlen;
m0_awsize = s0_awsize;
m0_awburst = s0_awburst;
m0_awlock = s0_awlock;
m0_awcache = s0_awcache;
m0_awprot = s0_awprot;
m0_wid = s0_wid;
m0_wstrb = s0_wstrb;
m0_wlast = s0_wlast;
m0_arlen = s0_arlen;
m0_arsize = s0_arsize;
m0_arburst = s0_arburst;
m0_arcache = s0_arcache;
m0_arprot = s0_arprot;
m0_arlock = s0_arlock;
s0_bresp = m0_bresp;
s0_rresp = m0_rresp;
s0_rlast = m0_rlast;
// Avoid QIS warning
m0_awregion = '0;
m0_awqos = '0;
m0_arregion = '0;
m0_arqos = '0;
// ID
m0_awid = s0_awid;
m0_arid = s0_arid;
m0_wid = s0_wid;
// -----------------------------------------
// Only pass the lower bits of ID through
// -----------------------------------------
s0_bid = m0_bid[S0_ID_WIDTH - 1 : 0];
s0_rid = m0_rid[S0_ID_WIDTH - 1 : 0];
end
// 1-1 system: AXI3 master <-{translator}-> AXI4 slave
// do some checking on slave side and converstion from AXI3 to AXI4 if needed (ex lock signal width)
else begin
// Check option signals in slave side only
// Signals which are not avaible in AXI3 master, drive with default value
// These signals are not avaible in AXI3 master, so the translator just assign default value
// avoid QIS waraning as well
m0_awregion = '0;
m0_awqos = '0;
m0_arregion = '0;
m0_arqos = '0;
// Need some converstion for AXI3 and AXI4
// with: AXLOCK[1:0] =b10 => AXLOCK = 0
m0_awlock = s0_awlock[0];
m0_arlock = s0_arlock[0];
// Protection signals: just do assignemnt
// even the AXI4 slave doesnt use it to avoid QIS warning
// the Port has been terninated in hw.tcl
// and these port must be always exist in AXI3 master
m0_awprot = s0_awprot;
m0_arprot = s0_arprot;
m0_wlast = s0_wlast;
m0_awcache = s0_awcache;
m0_arcache = s0_arcache;
// Pass lower bits of ID
s0_bid = m0_bid[S0_ID_WIDTH-1:0];
s0_rid = m0_rid[S0_ID_WIDTH-1:0];
// Avoid QIS warning
s0_rlast = m0_rlast;
// Pass through
m0_awlen = s0_awlen;
m0_awid = s0_awid;
m0_arid = s0_arid;
m0_awburst = s0_awburst;
m0_arburst = s0_arburst;
m0_wstrb = s0_wstrb;
m0_awsize = s0_awsize;
m0_arsize = s0_arsize;
m0_arlen = s0_arlen;
// AXI3 has no idea about QOS, so set to default for all cases.
m0_awqos = '0;
m0_arqos = '0;
// AXI3 need WID, so just so it base on AXI3, the AXI4 slave wont read this
m0_wid = s0_wid;
if (USE_M0_BRESP)
s0_bresp = m0_bresp;
else
s0_bresp = 2'b00; //OKAY
if (USE_M0_RRESP)
s0_rresp = m0_rresp;
else
s0_rresp = 2'b00; //OKAY
end // else: !if(M0_AXI_VERSION == "AXI3")
end // if (S0_AXI_VERSION == "AXI3")
// AXI4 master <-{translator}-> AXI4 slave: cases
// a) not 1-1 system: the translator can be either "master translator" or "slave translator"
// This case, one side will be always as "complete" AXI4
// Ex: if translator is at master side: AXI4 master <-{translator}-> [Interconnect Network]
// at translator's interface side at Interconnect will be always complete AXI4
// So, the translator will take care of optional signals and default value of one side
// b) 1-1 system: special case: the translator need to check on optional signal for both side of
// interface
//
else begin
// Checking on signals that can be optional for both side
// NOTE: if slave side use that signal but master side does not
// then assign outpur as default value
// if slave side does not use that signal, not matter master side
// use this or not, just pass through the value (the port has been terminated in hw.tcl)
// in HDL file, the port still there, so assign to avoid QIS warning
// Same, if both use that signal -> assign through
// it helps to reduce if and avoid warning some signal not assigned value
if ((USE_M0_AWREGION) && (!USE_S0_AWREGION))
m0_awregion = '0; //default value
else
m0_awregion = s0_awregion;
if ((USE_M0_AWLOCK) && (!USE_S0_AWLOCK))
m0_awlock = '0;
else
m0_awlock = s0_awlock;
if ((USE_M0_AWCACHE) && (!USE_S0_AWCACHE))
m0_awcache = '0;
else
m0_awcache = s0_awcache;
if ((USE_M0_AWQOS) && (!USE_S0_AWQOS))
m0_awqos = '0;
else
m0_awqos = s0_awqos;
if ((USE_S0_BRESP) && (!USE_M0_BRESP))
s0_bresp = 2'b00; //OKAY
else
s0_bresp = m0_bresp;
if ((USE_M0_ARREGION) && (!USE_S0_ARREGION))
m0_arregion = '0; //default value
else
m0_arregion = s0_arregion;
if ((USE_M0_ARLOCK) && (!USE_S0_ARLOCK))
m0_arlock = '0;
else
m0_arlock = s0_arlock;
if ((USE_M0_ARCACHE) && (!USE_S0_ARCACHE))
m0_arcache = '0;
else
m0_arcache = s0_arcache;
if ((USE_M0_ARQOS) && (!USE_S0_ARQOS))
m0_arqos = '0;
else
m0_arqos = s0_arqos;
if ((USE_S0_RRESP) && (!USE_M0_RRESP))
s0_rresp = 2'b00; //OKAY
else
s0_rresp = m0_rresp;
// Check signal that secific to each side only
// -- Master side signals
if (USE_S0_AWID)
m0_awid = s0_awid;
else
m0_awid = '0;
if (USE_S0_AWLEN)
m0_awlen = s0_awlen;
else
m0_awlen = '0;
if (USE_S0_AWSIZE)
m0_awsize = s0_awsize;
else
m0_awsize = BURST_SIZE[2:0]; // Number of symbol
if (USE_S0_AWBURST)
m0_awburst = s0_awburst;
else
m0_awburst = 2'b01; // INCR
if (USE_S0_WSTRB)
m0_wstrb = s0_wstrb;
else
m0_wstrb = {STROBE_WIDTH{1'b1}};
if (USE_S0_ARID)
m0_arid = s0_arid;
else
m0_arid = '0;
if (USE_S0_ARLEN)
m0_arlen = s0_arlen;
else
m0_arlen = '0;
if (USE_S0_ARSIZE)
m0_arsize = s0_arsize;
else
m0_arsize = BURST_SIZE[2:0]; // Number of symbol
if (USE_S0_ARBURST)
m0_arburst = s0_arburst;
else
m0_arburst = 2'b01; // INCR
if (USE_S0_AWUNIQUE)
m0_awunique = s0_awunique;
else
m0_awunique = 1'h0;
if (USE_S0_AWSNOOP)
m0_awsnoop = s0_awsnoop;
else
m0_awsnoop = 'h0;
if (USE_S0_ARSNOOP)
m0_arsnoop = s0_arsnoop;
else
m0_arsnoop = 'h0;
// these just assign to avoid warning
if (TERMINATE_WRITE_CHANNEL ==0 )
s0_bid = m0_bid[S0_ID_WIDTH-1:0];
else
s0_bid = 0;
if (TERMINATE_READ_CHANNEL ==0 ) begin
s0_rid = m0_rid[S0_ID_WIDTH-1:0];
s0_rlast = m0_rlast;
end else begin
s0_rid = 0;
s0_rlast = 0;
end
// AXI4 doesnt have WID but jsut assign a value to avoid QIS warning
// the port is terminated in hw.tcl
m0_wid = '0;
// Slave side signals
m0_awprot = s0_awprot;
m0_wlast = s0_wlast;
m0_arprot = s0_arprot;
end // else: !if(S0_AXI_VERSION == "AXI3")
// When master is AXI4Lite, the slave either AXI3 or AXI4, we need to set some default values for some signals
if (S0_AXI_VERSION == "AXI4Lite") begin
// write address channel
m0_awid = '0;
m0_awlen = '0; // non-bursting
m0_awburst = 2'b01; // INCR
m0_awsize = BURST_SIZE[2:0];
m0_awlock = '0;
m0_awcache = '0;
//m0_awprot = s0_awprot;
if (USE_S0_AWPROT == 0)
m0_awprot = '0;
else
m0_awprot = s0_awprot;
m0_awqos = '0;
m0_awregion = '0;
// write data channel
m0_wid = '0;
m0_wlast = 1'b1; // AXI4 lite always sets this to 1
//write response channel
s0_bid = m0_bid;
// read address channel
m0_arid = '0;
m0_arlen = '0;
m0_arsize = BURST_SIZE[2:0];
m0_arburst = 2'b01;
m0_arlock = '0;
m0_arcache = '0;
//m0_arprot = s0_arprot;
if (USE_S0_ARPROT == 0)
m0_arprot = '0;
else
m0_arprot = s0_arprot;
m0_arqos = '0;
m0_arregion = '0;
// read data channel
s0_rid = m0_rid;
s0_rlast = 1'b1;
end // if (S0_AXI_VERSION == "AXI4Lite")
else begin
// When slave is AXI4 lite, the other side of the translator will be full AXI4 (AXI3 no translator)
// Mostly all AXI4 lite signals will back thru, other we write default values
// Pass back all ID signal, normally AXI4 lite doest support ID but it is optional that it can have if.
//AXI5Lite Condition terp
// Pass only lower bits
s0_bid = m0_bid [S0_ID_WIDTH-1:0];
s0_rid = m0_rid [S0_ID_WIDTH-1:0];
end // else: !if(S0_AXI_VERSION == "AXI4Lite")
end // always_comb
// common signals assignment for all cases
assign m0_awvalid = s0_awvalid;
assign s0_awready = m0_awready;
assign m0_wdata = s0_wdata;
assign m0_wvalid = s0_wvalid;
assign s0_wready = m0_wready;
assign m0_arvalid = s0_arvalid;
assign s0_arready = m0_arready;
assign s0_bvalid = m0_bvalid;
assign m0_bready = s0_bready;
assign s0_rdata = m0_rdata;
assign s0_rvalid = m0_rvalid;
assign m0_rready = s0_rready;
// Avoid QIS warning, master address will be always same or larger than slave
// so only assign enough bit width from master to slave
assign m0_awaddr = s0_awaddr[M0_ADDR_WIDTH-1 :0];
assign m0_araddr = s0_araddr[M0_ADDR_WIDTH-1 :0];
assign m0_awuser = USE_S0_AWUSER ? s0_awuser : '0;
assign m0_aruser = USE_S0_ARUSER ? s0_aruser : '0;
assign m0_wuser = USE_S0_WUSER ? s0_wuser : '0;
assign s0_buser = USE_M0_BUSER ? m0_buser : '0;
assign s0_ruser = USE_M0_RUSER ? m0_ruser : '0;
assign m0_wuser_poison = (USE_S0_WUSER_POISON && ROLE_BASED_USER) ? s0_wuser_poison: 1'b0;
assign s0_ruser_poison = (USE_M0_RUSER_POISON && ROLE_BASED_USER) ? m0_ruser_poison: 1'b0;
assign m0_wuser_data = (USE_S0_WUSER_DATA && ROLE_BASED_USER) ? s0_wuser_data : 1'b0;
assign s0_ruser_data = (USE_M0_RUSER_DATA && ROLE_BASED_USER) ? m0_ruser_data : 1'b0;
assign m0_awuser_sai = (USE_S0_AWUSER_SAI && ROLE_BASED_USER) ? s0_awuser_sai: 'b0;
assign m0_aruser_sai = (USE_S0_ARUSER_SAI && ROLE_BASED_USER) ? s0_aruser_sai: 'b0;
//AXI5Lite Condition terp
assign m0_awakeup = '0;
assign m0_awtrace = '0;
assign m0_artrace = '0;
assign m0_wtrace = '0;
assign s0_btrace = '0;
assign s0_rtrace = '0;
assign m0_wpoison = '0;
assign s0_rpoison = '0;
assign m0_wdatachk = '0;
assign s0_rdatachk = '0;
assign m0_ardomain = s0_ardomain;
assign m0_arbar = s0_arbar;
assign m0_awdomain = s0_awdomain;
assign m0_awbar = s0_awbar;
assign m0_awatop = (USE_S0_AWATOP ) ? s0_awatop : '0;
assign m0_awstashnid = (USE_S0_AWSTASHNID ) ? s0_awstashnid : '0;
assign m0_awstashniden = (USE_S0_AWSTASHNIDEN ) ? s0_awstashniden : '0;
assign m0_awstashlpid = (USE_S0_AWSTASHLPID ) ? s0_awstashlpid : '0;
assign m0_awstashlpiden = (USE_S0_AWSTASHLPIDEN ) ? s0_awstashlpiden : '0;
assign m0_awmmusecsid = (USE_S0_AWMMUSECSID ) ? s0_awmmusecsid : '0;
assign m0_awmmusid = (USE_S0_AWMMUSID ) ? s0_awmmusid : '0;
assign m0_armmusecsid = (USE_S0_ARMMUSECSID ) ? s0_armmusecsid : '0;
assign m0_armmusid = (USE_S0_ARMMUSID ) ? s0_armmusid : '0;
assign m0_awaddrchk = (USE_S0_AWADDRCHK ) ? s0_awaddrchk : '0;
assign m0_araddrchk = (USE_S0_ARADDRCHK ) ? s0_araddrchk : '0;
generate
if (CALCULATE_WUSER_DATACHK && ROLE_BASED_USER) begin
assign m0_wuser_datachk = calcParity(s0_wdata);
end
else if(ROLE_BASED_USER && USE_S0_WUSER_DATACHK) begin
assign m0_wuser_datachk = s0_wuser_datachk;
end else begin
assign m0_wuser_datachk = '0;
end
if (CALCULATE_RUSER_DATACHK && ROLE_BASED_USER) begin
assign s0_ruser_datachk = calcParity(m0_rdata);
end else if(ROLE_BASED_USER && USE_M0_RUSER_DATACHK) begin
assign s0_ruser_datachk = m0_ruser_datachk;
end else begin
assign s0_ruser_datachk = '0;
end
if (CALCULATE_AWUSER_ADDRCHK && ROLE_BASED_USER) begin
assign ar_parity_status = 1'b0;
if(SKIP_USER_ADDRCHK_CAL) begin
assign m0_awuser_addrchk = '0;
end
else begin
assign m0_awuser_addrchk = addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_awaddr});
end
end else if(REGENERATE_ADDRCHK) begin
wire [S0_USER_ADDRCHK_WIDTH-1:0] expected_awuser_addrchk_parity;
assign expected_awuser_addrchk_parity = addrcalcParity ( {{S0_PADDING_ZERO{1'b0}},s0_awaddr });
assign aw_parity_status = (expected_awuser_addrchk_parity == s0_awuser_addrchk) ? 1'b0 : 1'b1;
assign m0_awuser_addrchk = aw_parity_status ? addrcalc_incorrectParity({{M0_PADDING_ZERO{1'b0}},m0_awaddr}): addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_awaddr});
end else if(ROLE_BASED_USER && USE_S0_AWUSER_ADDRCHK) begin
assign m0_awuser_addrchk = s0_awuser_addrchk;
assign ar_parity_status = 1'b0;
end else begin
assign m0_awuser_addrchk = '0;
assign ar_parity_status = 1'b0;
end
if (CALCULATE_ARUSER_ADDRCHK && ROLE_BASED_USER) begin
assign aw_parity_status = 1'b0;
if(SKIP_USER_ADDRCHK_CAL) begin
assign m0_awuser_addrchk = '0;
end
else begin
assign m0_aruser_addrchk = addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_araddr});
end
end else if(REGENERATE_ADDRCHK) begin
wire [S0_USER_ADDRCHK_WIDTH-1:0] expected_aruser_addrchk_parity;
assign ar_parity_status = (expected_aruser_addrchk_parity == s0_aruser_addrchk) ? 1'b0 : 1'b1;
assign expected_aruser_addrchk_parity = addrcalcParity ( {{S0_PADDING_ZERO{1'b0}},s0_araddr});
assign m0_aruser_addrchk = ar_parity_status ? addrcalc_incorrectParity({{M0_PADDING_ZERO{1'b0}},m0_araddr}): addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_araddr});
end else if(ROLE_BASED_USER && USE_S0_ARUSER_ADDRCHK) begin
assign ar_parity_status = 1'b0;
assign m0_aruser_addrchk = s0_aruser_addrchk;
end else begin
assign aw_parity_status = 1'b0;
assign m0_aruser_addrchk = '0;
end
endgenerate;
// --------------------------------------------------
//
// calcParity function: calculate byte-level parity of arbitrary-sized signal
//
// --------------------------------------------------
function reg [DATACHK_WIDTH-1:0] calcParity (
input [DATA_WIDTH-1:0] data
);
for (int i=0; i<DATACHK_WIDTH; i++)
calcParity[i] = ~(^ data[i*8 +:8]);
endfunction
//address parity generation logic
function reg [ADDRCHK_WIDTH-1:0] addrcalcParity (
input [M0_PARITY_ADDR_WIDTH-1:0] addr
);
for (int i=0; i<ADDRCHK_WIDTH; i++)
addrcalcParity[i] = ~(^ addr[i*8 +:8]);
endfunction
// --------------------------------------------------
// addrcalc_incorrectParity: calculates byte-level incorrect parity signal
// --------------------------------------------------
function reg [ADDRCHK_WIDTH-1:0] addrcalc_incorrectParity (
input [M0_PARITY_ADDR_WIDTH-1:0] addr
);
reg [ADDRCHK_WIDTH-1:0]addrcalcParity;
for (int i=0; i<ADDRCHK_WIDTH; i++)
addrcalcParity[i] = ~(^ addr[i*8 +:8]);
addrcalc_incorrectParity =~addrcalcParity;
endfunction
endmodule
qsys/qsys_top/altera_merlin_axi_translator_1987/synth/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv
+963
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@@ -0,0 +1,963 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// AXI Translator
//
// Convert "incomplete" AXI4 interface to
// a "complete" AXI4 interface that connect to network side
//
// Adapts between an AXI master and slave that
// are almost symmetric, with the following
// exceptions:
//
// the master's address width >= the slave's address width
// the master's id width <= the slave's id width
//
// The s0 interface on this component connects to the master,
// and the m0 interface connects to the slave.
//
// The adaptation logic is minimal in these cases, so this
// component is used instead of the heavier network
// interfaces.
// -----------------------------------------
`timescale 1 ns / 1 ns
module qsys_top_altera_merlin_axi_translator_1987_lty7xoq
#(
// ----------------
// Interface parameters
// ----------------
parameter S0_ID_WIDTH = 4,
M0_ID_WIDTH = 8,
M0_ADDR_WIDTH = 32,
S0_ADDR_WIDTH = 32,
DATA_WIDTH = 32,
M0_SAI_WIDTH = 4,
S0_SAI_WIDTH = 4,
M0_USER_ADDRCHK_WIDTH = 4,
S0_USER_ADDRCHK_WIDTH = 4,
S0_WRITE_ADDR_USER_WIDTH = 64,
S0_READ_ADDR_USER_WIDTH = 64,
M0_WRITE_ADDR_USER_WIDTH = 64,
M0_READ_ADDR_USER_WIDTH = 64,
M0_WRITE_DATA_USER_WIDTH = 64,
M0_WRITE_RESPONSE_DATA_USER_WIDTH = 64,
M0_READ_DATA_USER_WIDTH = 64,
S0_WRITE_DATA_USER_WIDTH = 64,
S0_WRITE_RESPONSE_DATA_USER_WIDTH = 64,
S0_READ_DATA_USER_WIDTH = 64,
M0_ADDRCHK_WIDTH = M0_USER_ADDRCHK_WIDTH,
S0_ADDRCHK_WIDTH = S0_USER_ADDRCHK_WIDTH,
M0_AXI_VERSION = "AXI3",
S0_AXI_VERSION = "AXI3",
TERMINATE_READ_CHANNEL =0,
TERMINATE_WRITE_CHANNEL =0,
// ---------------
// Master parameters
// ---------------
USE_S0_AWUSER = 0,
USE_S0_ARUSER = 0,
USE_S0_WUSER = 0,
USE_S0_RUSER = 0,
USE_S0_BUSER = 0,
USE_S0_AWID = 0,
USE_S0_AWREGION = 0,
USE_S0_AWSIZE = 0,
USE_S0_AWBURST = 0,
USE_S0_AWLEN = 0,
USE_S0_AWLOCK = 0,
USE_S0_AWCACHE = 0,
USE_S0_AWQOS = 0,
USE_S0_AWPROT = 0,
USE_S0_WSTRB = 0,
USE_S0_WLAST = 0,
USE_S0_BID = 0,
USE_S0_BRESP = 0,
USE_S0_ARID = 0,
USE_S0_ARREGION = 0,
USE_S0_ARSIZE = 0,
USE_S0_ARBURST = 0,
USE_S0_ARLEN = 0,
USE_S0_ARLOCK = 0,
USE_S0_ARCACHE = 0,
USE_S0_ARQOS = 0,
USE_S0_ARPROT = 0,
USE_S0_RID = 0,
USE_S0_RRESP = 0,
USE_S0_RLAST = 0,
S0_BURST_LENGTH_WIDTH = 8,
S0_LOCK_WIDTH = 1,
//AXI5/AXI5-Lite new capabilites signals enables
USE_S0_RPOISON = 0,
USE_S0_WPOISON = 0,
USE_S0_AWTRACE = 0,
USE_S0_ARTRACE = 0,
USE_S0_WTRACE = 0,
USE_S0_BTRACE = 0,
USE_S0_RTRACE = 0,
USE_S0_WDATACHK = 0,
USE_S0_RDATACHK = 0,
USE_S0_AWAKEUP = 0,
//AXI-USER Global signals enables
USE_S0_AWUSER_ADDRCHK = 0,
USE_S0_AWUSER_SAI = 0,
USE_S0_ARUSER_SAI = 0,
USE_S0_ARUSER_ADDRCHK = 0,
USE_S0_WUSER_DATACHK = 0,
USE_S0_WUSER_DATA = 0,
USE_S0_WUSER_POISON = 0,
USE_S0_RUSER_DATACHK = 0,
USE_S0_RUSER_DATA = 0,
USE_S0_RUSER_POISON = 0,
USE_S0_AWUNIQUE = 1,
//ACE5-Lite signals
USE_S0_AWATOP = 0,
USE_S0_AWSTASHNID = 0,
USE_S0_AWSTASHNIDEN = 0,
USE_S0_AWSTASHLPID = 0,
USE_S0_AWSTASHLPIDEN = 0,
USE_S0_AWMMUSECSID = 0,
USE_S0_AWMMUSID = 0,
USE_S0_ARMMUSECSID = 0,
USE_S0_ARMMUSID = 0,
USE_S0_AWSNOOP = 1,
USE_S0_ARSNOOP = 1,
USE_S0_AWADDRCHK = 0,
USE_S0_ARADDRCHK = 0,
REGENERATE_ADDRCHK = 0,
ROLE_BASED_USER = 0,
//-----------------
// Slave parameters
//-----------------
USE_M0_AWUNIQUE = 1,
USE_M0_AWREGION = 1,
USE_M0_AWLOCK = 1,
USE_M0_AWPROT = 1,
USE_M0_AWCACHE = 1,
USE_M0_AWQOS = 1,
USE_M0_WLAST = 1,
USE_M0_BRESP = 1,
USE_M0_ARREGION = 1,
USE_M0_ARLOCK = 1,
USE_M0_ARPROT = 1,
USE_M0_ARCACHE = 1,
USE_M0_ARQOS = 1,
USE_M0_RRESP = 1,
USE_M0_AWUSER = 0,
USE_M0_ARUSER = 0,
USE_M0_WUSER = 0,
USE_M0_RUSER = 0,
USE_M0_BUSER = 0,
//AXI5/AXI5-Lite new capabilites signals enables
USE_M0_RPOISON = 0,
USE_M0_WPOISON = 0,
USE_M0_AWTRACE = 0,
USE_M0_ARTRACE = 0,
USE_M0_WTRACE = 0,
USE_M0_BTRACE = 0,
USE_M0_RTRACE = 0,
USE_M0_WDATACHK = 0,
USE_M0_RDATACHK = 0,
USE_M0_AWAKEUP = 0,
//AXI-USER Global signals enables
USE_M0_AWUSER_ADDRCHK = 0,
USE_M0_AWUSER_SAI = 0,
USE_M0_ARUSER_SAI = 0,
USE_M0_ARUSER_ADDRCHK = 0,
USE_M0_WUSER_DATACHK = 0,
USE_M0_WUSER_DATA = 0,
USE_M0_WUSER_POISON = 0,
USE_M0_RUSER_DATACHK = 0,
USE_M0_RUSER_DATA = 0,
USE_M0_RUSER_POISON = 0,
//ACE5-Lite signals
USE_M0_AWATOP = 0,
USE_M0_AWSTASHNID = 0,
USE_M0_AWSTASHNIDEN = 0,
USE_M0_AWSTASHLPID = 0,
USE_M0_AWSTASHLPIDEN = 0,
USE_M0_AWMMUSECSID = 0,
USE_M0_AWMMUSID = 0,
USE_M0_ARMMUSECSID = 0,
USE_M0_ARMMUSID = 0,
USE_M0_AWADDRCHK = 0,
USE_M0_ARADDRCHK = 0,
M0_BURST_LENGTH_WIDTH= 8,
M0_LOCK_WIDTH = 2,
ACE_LITE_SUPPORT = 0,
ACE5_LITE_SUPPORT = 0,
M0_SID_WIDTH = 16,
S0_SID_WIDTH = 16,
M0_AWSNOOP_WIDTH = 3,
S0_AWSNOOP_WIDTH = 3,
USER_DATA_WIDTH = 1,
// ----------------
// Derived parameters
// ----------------
// Parity check generation
// Rule: calcuate parity if input is invalid (terminated with 0s) and output is required
// Otherwise, just pass-thru the input
/* |----------+-------------+-------------| */
/* | Signal | input | output | */
/* |----------+-------------+-------------| */
/* | wuser_datachk | s0_wuser_datachk | m0_wuser_datachk | */
/* | ruser_datachk | m0_ruser_datachk | s0_ruser_datachk | */
/* |----------+-------------+-------------| */
CALCULATE_WUSER_DATACHK = USE_S0_WUSER_DATACHK==0 && USE_M0_WUSER_DATACHK ==1,
CALCULATE_RUSER_DATACHK = USE_S0_RUSER_DATACHK==1 && USE_M0_RUSER_DATACHK ==0,
//AXI5Lite/AXI5
CALCULATE_WDATACHK = USE_S0_WDATACHK==0 && USE_M0_WDATACHK ==1,
CALCULATE_RDATACHK = USE_S0_RDATACHK==1 && USE_M0_RDATACHK ==0,
CALCULATE_AWUSER_ADDRCHK = USE_S0_AWUSER_ADDRCHK==0 && USE_M0_AWUSER_ADDRCHK ==1,
CALCULATE_ARUSER_ADDRCHK = USE_S0_ARUSER_ADDRCHK==0 && USE_M0_ARUSER_ADDRCHK ==1,
SKIP_USER_ADDRCHK_CAL = ((M0_ADDR_WIDTH/8) - M0_USER_ADDRCHK_WIDTH > 1) ,
ADDRCHK_WIDTH = (S0_ADDR_WIDTH + 8 - 1)/8,
S0_PADDING_ZERO = (ADDRCHK_WIDTH*8) - S0_ADDR_WIDTH,
M0_PADDING_ZERO = (ADDRCHK_WIDTH*8) - M0_ADDR_WIDTH,
M0_PARITY_ADDR_WIDTH = M0_ADDR_WIDTH + M0_PADDING_ZERO,
DATACHK_WIDTH = DATA_WIDTH / 8,
POISON_WIDTH = (DATA_WIDTH + 64 -1) / 64, // ceil(DATA_WIDTH/64) workaround
STROBE_WIDTH = DATA_WIDTH / 8,
BURST_SIZE = $clog2(STROBE_WIDTH)
)
(
// ----------------
// Clock & reset
// ----------------
input aclk,
input aresetn,
input s0_awakeup,
output m0_awakeup,
// ----------------
// Master-facing AXI interface
// ----------------
input [S0_ID_WIDTH-1:0] s0_awid,
input [S0_ADDR_WIDTH-1:0] s0_awaddr,
input [S0_BURST_LENGTH_WIDTH-1:0] s0_awlen,
input [2:0] s0_awsize,
input [1:0] s0_awburst,
input [S0_LOCK_WIDTH-1:0] s0_awlock,
input [3:0] s0_awcache,
input [2:0] s0_awprot,
input [S0_WRITE_ADDR_USER_WIDTH-1:0] s0_awuser,
input [3:0] s0_awqos,
input [3:0] s0_awregion,
input s0_awvalid,
input s0_awtrace,
output s0_awready,
input [S0_ID_WIDTH-1:0] s0_wid,
input [DATA_WIDTH-1:0] s0_wdata,
input [STROBE_WIDTH-1:0] s0_wstrb,
input [DATACHK_WIDTH-1:0] s0_wdatachk,
input [POISON_WIDTH-1:0] s0_wpoison,
input s0_wtrace,
input s0_wlast,
input [S0_WRITE_DATA_USER_WIDTH-1:0] s0_wuser,
input s0_wvalid,
output s0_wready,
output reg [S0_ID_WIDTH-1:0] s0_bid,
output reg [1:0] s0_bresp,
output [S0_WRITE_RESPONSE_DATA_USER_WIDTH-1:0] s0_buser,
output s0_bvalid,
output s0_btrace,
input s0_bready,
input [S0_ID_WIDTH-1:0] s0_arid,
input [S0_ADDR_WIDTH-1:0] s0_araddr,
input [S0_BURST_LENGTH_WIDTH-1:0] s0_arlen,
input [2:0] s0_arsize,
input [1:0] s0_arburst,
input [S0_LOCK_WIDTH-1:0] s0_arlock,
input [3:0] s0_arcache,
input [2:0] s0_arprot,
input [3:0] s0_arqos,
input [3:0] s0_arregion,
input [S0_READ_ADDR_USER_WIDTH-1:0] s0_aruser,
input s0_arvalid,
input s0_artrace,
output s0_arready,
output reg [S0_ID_WIDTH-1:0] s0_rid,
output [DATA_WIDTH-1:0] s0_rdata,
output reg [1:0] s0_rresp,
output [DATACHK_WIDTH-1:0] s0_rdatachk,
output [POISON_WIDTH-1:0] s0_rpoison,
output s0_rtrace,
output reg s0_rlast,
output [S0_READ_DATA_USER_WIDTH-1:0] s0_ruser,
output s0_rvalid,
input s0_rready,
input [1:0] s0_ardomain,
input [3:0] s0_arsnoop,
input [1:0] s0_arbar,
input [1:0] s0_awdomain,
input [S0_AWSNOOP_WIDTH-1:0] s0_awsnoop,
input [1:0] s0_awbar,
input s0_awunique,
input [S0_USER_ADDRCHK_WIDTH-1:0] s0_awuser_addrchk,
input [S0_SAI_WIDTH-1:0] s0_awuser_sai,
input [S0_SAI_WIDTH-1:0] s0_aruser_sai,
input [S0_USER_ADDRCHK_WIDTH-1:0] s0_aruser_addrchk,
input [DATACHK_WIDTH-1:0] s0_wuser_datachk,
input [USER_DATA_WIDTH-1:0] s0_wuser_data,
input [POISON_WIDTH-1:0] s0_wuser_poison,
output [DATACHK_WIDTH-1:0] s0_ruser_datachk,
output [USER_DATA_WIDTH-1:0] s0_ruser_data,
output [POISON_WIDTH-1:0] s0_ruser_poison,
input [5:0] s0_awatop,
input [10:0] s0_awstashnid,
input s0_awstashniden,
input [4:0] s0_awstashlpid,
input s0_awstashlpiden,
input s0_awmmusecsid,
input [S0_SID_WIDTH-1:0] s0_awmmusid,
input s0_armmusecsid,
input [S0_SID_WIDTH-1:0] s0_armmusid,
input [S0_ADDRCHK_WIDTH-1:0] s0_awaddrchk,
input [S0_ADDRCHK_WIDTH-1:0] s0_araddrchk,
// ----------------
// Slave-facing AXI interface
// ----------------
output reg [M0_ID_WIDTH-1:0] m0_awid,
output [M0_ADDR_WIDTH-1:0] m0_awaddr,
output reg [M0_BURST_LENGTH_WIDTH-1:0] m0_awlen,
output reg [2:0] m0_awsize,
output reg [1:0] m0_awburst,
output reg [M0_LOCK_WIDTH-1:0] m0_awlock,
output reg [3:0] m0_awcache,
output reg [2:0] m0_awprot,
output reg [3:0] m0_awqos,
output reg [3:0] m0_awregion,
output m0_awvalid,
output [M0_WRITE_ADDR_USER_WIDTH-1:0] m0_awuser,
output m0_awtrace,
input m0_awready,
output reg [M0_ID_WIDTH-1:0] m0_wid,
output [DATA_WIDTH-1:0] m0_wdata,
output reg [STROBE_WIDTH-1:0] m0_wstrb,
output [DATACHK_WIDTH-1:0] m0_wdatachk,
output [POISON_WIDTH-1:0] m0_wpoison,
output m0_wtrace,
output reg m0_wlast,
output m0_wvalid,
output [M0_WRITE_DATA_USER_WIDTH-1:0] m0_wuser,
input m0_wready,
input [M0_ID_WIDTH-1:0] m0_bid,
input [1:0] m0_bresp,
input [M0_WRITE_RESPONSE_DATA_USER_WIDTH-1:0] m0_buser,
input m0_bvalid,
input m0_btrace,
output m0_bready,
output reg [M0_ID_WIDTH-1:0] m0_arid,
output [M0_ADDR_WIDTH-1:0] m0_araddr,
output reg [M0_BURST_LENGTH_WIDTH-1:0] m0_arlen,
output reg [2:0] m0_arsize,
output reg [1:0] m0_arburst,
output reg [M0_LOCK_WIDTH-1:0] m0_arlock,
output reg [3:0] m0_arcache,
output reg [3:0] m0_arqos,
output reg [3:0] m0_arregion,
output reg [2:0] m0_arprot,
output m0_arvalid,
output [M0_READ_ADDR_USER_WIDTH-1:0] m0_aruser,
output m0_artrace,
input m0_arready,
input [M0_ID_WIDTH-1:0] m0_rid,
input [DATA_WIDTH-1:0] m0_rdata,
input [1:0] m0_rresp,
input [DATACHK_WIDTH-1:0] m0_rdatachk,
input [POISON_WIDTH-1:0] m0_rpoison,
input m0_rtrace,
input [M0_READ_DATA_USER_WIDTH-1:0] m0_ruser,
input m0_rlast,
input m0_rvalid,
output m0_rready,
output [1:0] m0_ardomain,
output reg [3:0] m0_arsnoop,
output [1:0] m0_arbar,
output [1:0] m0_awdomain,
output reg [M0_AWSNOOP_WIDTH-1:0] m0_awsnoop,
output [1:0] m0_awbar,
output reg m0_awunique,
output [M0_USER_ADDRCHK_WIDTH-1:0] m0_awuser_addrchk,
output [M0_SAI_WIDTH-1:0] m0_awuser_sai,
output [M0_SAI_WIDTH-1:0] m0_aruser_sai,
output [M0_USER_ADDRCHK_WIDTH-1:0] m0_aruser_addrchk,
output [DATACHK_WIDTH-1:0] m0_wuser_datachk,
output [USER_DATA_WIDTH-1:0] m0_wuser_data,
output [POISON_WIDTH-1:0] m0_wuser_poison,
input [DATACHK_WIDTH-1:0] m0_ruser_datachk,
input [USER_DATA_WIDTH-1:0] m0_ruser_data,
input [POISON_WIDTH-1:0] m0_ruser_poison,
output [5:0] m0_awatop,
output [10:0] m0_awstashnid,
output m0_awstashniden,
output [4:0] m0_awstashlpid,
output m0_awstashlpiden,
output m0_awmmusecsid,
output [M0_SID_WIDTH-1:0] m0_awmmusid,
output m0_armmusecsid,
output [M0_SID_WIDTH-1:0] m0_armmusid,
output [M0_ADDRCHK_WIDTH-1:0] m0_awaddrchk,
output [M0_ADDRCHK_WIDTH-1:0] m0_araddrchk
);
wire ar_parity_status;
wire aw_parity_status;
// -----------------------------------------
// All we have to do is assign everything through,
// with special care for id and address.
// Along with optional signal from AXI4 master
// pass through or assign default value
// -----------------------------------------
// The AXI translator will need handle these cases
// with different interface at both side: (mostly in 1-1 connection)
// AXI3 <-> AXI3
// AXI3 <-> AXI4
// AXI4 <-> AXI4
// AXI4 Lite <-> AXI3/AXI4
// for other mxn with interconnect inserted
// the translator will have:
// AXI4/AXI4 Lite <-> "Full" AXI4
// -----------------------------------------
// All these checking condition below apply for AXI4
// in case AXI3, all parameters will be set and passed
// correctly from hw.tcl
// -----------------------------------------
always_comb
begin
if (S0_AXI_VERSION == "AXI3") begin
// 1-1 system: AXI3 master <-{translator}-> AXI3 slave:
// when master and slave size if translator
// is both AXI3: almost pass through every signals, care
// about ID width and address width
if (M0_AXI_VERSION == "AXI3") begin
m0_awlen = s0_awlen;
m0_awsize = s0_awsize;
m0_awburst = s0_awburst;
m0_awlock = s0_awlock;
m0_awcache = s0_awcache;
m0_awprot = s0_awprot;
m0_wid = s0_wid;
m0_wstrb = s0_wstrb;
m0_wlast = s0_wlast;
m0_arlen = s0_arlen;
m0_arsize = s0_arsize;
m0_arburst = s0_arburst;
m0_arcache = s0_arcache;
m0_arprot = s0_arprot;
m0_arlock = s0_arlock;
s0_bresp = m0_bresp;
s0_rresp = m0_rresp;
s0_rlast = m0_rlast;
// Avoid QIS warning
m0_awregion = '0;
m0_awqos = '0;
m0_arregion = '0;
m0_arqos = '0;
// ID
m0_awid = s0_awid;
m0_arid = s0_arid;
m0_wid = s0_wid;
// -----------------------------------------
// Only pass the lower bits of ID through
// -----------------------------------------
s0_bid = m0_bid[S0_ID_WIDTH - 1 : 0];
s0_rid = m0_rid[S0_ID_WIDTH - 1 : 0];
end
// 1-1 system: AXI3 master <-{translator}-> AXI4 slave
// do some checking on slave side and converstion from AXI3 to AXI4 if needed (ex lock signal width)
else begin
// Check option signals in slave side only
// Signals which are not avaible in AXI3 master, drive with default value
// These signals are not avaible in AXI3 master, so the translator just assign default value
// avoid QIS waraning as well
m0_awregion = '0;
m0_awqos = '0;
m0_arregion = '0;
m0_arqos = '0;
// Need some converstion for AXI3 and AXI4
// with: AXLOCK[1:0] =b10 => AXLOCK = 0
m0_awlock = s0_awlock[0];
m0_arlock = s0_arlock[0];
// Protection signals: just do assignemnt
// even the AXI4 slave doesnt use it to avoid QIS warning
// the Port has been terninated in hw.tcl
// and these port must be always exist in AXI3 master
m0_awprot = s0_awprot;
m0_arprot = s0_arprot;
m0_wlast = s0_wlast;
m0_awcache = s0_awcache;
m0_arcache = s0_arcache;
// Pass lower bits of ID
s0_bid = m0_bid[S0_ID_WIDTH-1:0];
s0_rid = m0_rid[S0_ID_WIDTH-1:0];
// Avoid QIS warning
s0_rlast = m0_rlast;
// Pass through
m0_awlen = s0_awlen;
m0_awid = s0_awid;
m0_arid = s0_arid;
m0_awburst = s0_awburst;
m0_arburst = s0_arburst;
m0_wstrb = s0_wstrb;
m0_awsize = s0_awsize;
m0_arsize = s0_arsize;
m0_arlen = s0_arlen;
// AXI3 has no idea about QOS, so set to default for all cases.
m0_awqos = '0;
m0_arqos = '0;
// AXI3 need WID, so just so it base on AXI3, the AXI4 slave wont read this
m0_wid = s0_wid;
if (USE_M0_BRESP)
s0_bresp = m0_bresp;
else
s0_bresp = 2'b00; //OKAY
if (USE_M0_RRESP)
s0_rresp = m0_rresp;
else
s0_rresp = 2'b00; //OKAY
end // else: !if(M0_AXI_VERSION == "AXI3")
end // if (S0_AXI_VERSION == "AXI3")
// AXI4 master <-{translator}-> AXI4 slave: cases
// a) not 1-1 system: the translator can be either "master translator" or "slave translator"
// This case, one side will be always as "complete" AXI4
// Ex: if translator is at master side: AXI4 master <-{translator}-> [Interconnect Network]
// at translator's interface side at Interconnect will be always complete AXI4
// So, the translator will take care of optional signals and default value of one side
// b) 1-1 system: special case: the translator need to check on optional signal for both side of
// interface
//
else begin
// Checking on signals that can be optional for both side
// NOTE: if slave side use that signal but master side does not
// then assign outpur as default value
// if slave side does not use that signal, not matter master side
// use this or not, just pass through the value (the port has been terminated in hw.tcl)
// in HDL file, the port still there, so assign to avoid QIS warning
// Same, if both use that signal -> assign through
// it helps to reduce if and avoid warning some signal not assigned value
if ((USE_M0_AWREGION) && (!USE_S0_AWREGION))
m0_awregion = '0; //default value
else
m0_awregion = s0_awregion;
if ((USE_M0_AWLOCK) && (!USE_S0_AWLOCK))
m0_awlock = '0;
else
m0_awlock = s0_awlock;
if ((USE_M0_AWCACHE) && (!USE_S0_AWCACHE))
m0_awcache = '0;
else
m0_awcache = s0_awcache;
if ((USE_M0_AWQOS) && (!USE_S0_AWQOS))
m0_awqos = '0;
else
m0_awqos = s0_awqos;
if ((USE_S0_BRESP) && (!USE_M0_BRESP))
s0_bresp = 2'b00; //OKAY
else
s0_bresp = m0_bresp;
if ((USE_M0_ARREGION) && (!USE_S0_ARREGION))
m0_arregion = '0; //default value
else
m0_arregion = s0_arregion;
if ((USE_M0_ARLOCK) && (!USE_S0_ARLOCK))
m0_arlock = '0;
else
m0_arlock = s0_arlock;
if ((USE_M0_ARCACHE) && (!USE_S0_ARCACHE))
m0_arcache = '0;
else
m0_arcache = s0_arcache;
if ((USE_M0_ARQOS) && (!USE_S0_ARQOS))
m0_arqos = '0;
else
m0_arqos = s0_arqos;
if ((USE_S0_RRESP) && (!USE_M0_RRESP))
s0_rresp = 2'b00; //OKAY
else
s0_rresp = m0_rresp;
// Check signal that secific to each side only
// -- Master side signals
if (USE_S0_AWID)
m0_awid = s0_awid;
else
m0_awid = '0;
if (USE_S0_AWLEN)
m0_awlen = s0_awlen;
else
m0_awlen = '0;
if (USE_S0_AWSIZE)
m0_awsize = s0_awsize;
else
m0_awsize = BURST_SIZE[2:0]; // Number of symbol
if (USE_S0_AWBURST)
m0_awburst = s0_awburst;
else
m0_awburst = 2'b01; // INCR
if (USE_S0_WSTRB)
m0_wstrb = s0_wstrb;
else
m0_wstrb = {STROBE_WIDTH{1'b1}};
if (USE_S0_ARID)
m0_arid = s0_arid;
else
m0_arid = '0;
if (USE_S0_ARLEN)
m0_arlen = s0_arlen;
else
m0_arlen = '0;
if (USE_S0_ARSIZE)
m0_arsize = s0_arsize;
else
m0_arsize = BURST_SIZE[2:0]; // Number of symbol
if (USE_S0_ARBURST)
m0_arburst = s0_arburst;
else
m0_arburst = 2'b01; // INCR
if (USE_S0_AWUNIQUE)
m0_awunique = s0_awunique;
else
m0_awunique = 1'h0;
if (USE_S0_AWSNOOP)
m0_awsnoop = s0_awsnoop;
else
m0_awsnoop = 'h0;
if (USE_S0_ARSNOOP)
m0_arsnoop = s0_arsnoop;
else
m0_arsnoop = 'h0;
// these just assign to avoid warning
if (TERMINATE_WRITE_CHANNEL ==0 )
s0_bid = m0_bid[S0_ID_WIDTH-1:0];
else
s0_bid = 0;
if (TERMINATE_READ_CHANNEL ==0 ) begin
s0_rid = m0_rid[S0_ID_WIDTH-1:0];
s0_rlast = m0_rlast;
end else begin
s0_rid = 0;
s0_rlast = 0;
end
// AXI4 doesnt have WID but jsut assign a value to avoid QIS warning
// the port is terminated in hw.tcl
m0_wid = '0;
// Slave side signals
m0_awprot = s0_awprot;
m0_wlast = s0_wlast;
m0_arprot = s0_arprot;
end // else: !if(S0_AXI_VERSION == "AXI3")
// When master is AXI4Lite, the slave either AXI3 or AXI4, we need to set some default values for some signals
if (S0_AXI_VERSION == "AXI4Lite") begin
// write address channel
m0_awid = '0;
m0_awlen = '0; // non-bursting
m0_awburst = 2'b01; // INCR
m0_awsize = BURST_SIZE[2:0];
m0_awlock = '0;
m0_awcache = '0;
//m0_awprot = s0_awprot;
if (USE_S0_AWPROT == 0)
m0_awprot = '0;
else
m0_awprot = s0_awprot;
m0_awqos = '0;
m0_awregion = '0;
// write data channel
m0_wid = '0;
m0_wlast = 1'b1; // AXI4 lite always sets this to 1
//write response channel
s0_bid = m0_bid;
// read address channel
m0_arid = '0;
m0_arlen = '0;
m0_arsize = BURST_SIZE[2:0];
m0_arburst = 2'b01;
m0_arlock = '0;
m0_arcache = '0;
//m0_arprot = s0_arprot;
if (USE_S0_ARPROT == 0)
m0_arprot = '0;
else
m0_arprot = s0_arprot;
m0_arqos = '0;
m0_arregion = '0;
// read data channel
s0_rid = m0_rid;
s0_rlast = 1'b1;
end // if (S0_AXI_VERSION == "AXI4Lite")
else begin
// When slave is AXI4 lite, the other side of the translator will be full AXI4 (AXI3 no translator)
// Mostly all AXI4 lite signals will back thru, other we write default values
// Pass back all ID signal, normally AXI4 lite doest support ID but it is optional that it can have if.
//AXI5Lite Condition terp
// Pass only lower bits
s0_bid = m0_bid [S0_ID_WIDTH-1:0];
s0_rid = m0_rid [S0_ID_WIDTH-1:0];
end // else: !if(S0_AXI_VERSION == "AXI4Lite")
end // always_comb
// common signals assignment for all cases
assign m0_awvalid = s0_awvalid;
assign s0_awready = m0_awready;
assign m0_wdata = s0_wdata;
assign m0_wvalid = s0_wvalid;
assign s0_wready = m0_wready;
assign m0_arvalid = s0_arvalid;
assign s0_arready = m0_arready;
assign s0_bvalid = m0_bvalid;
assign m0_bready = s0_bready;
assign s0_rdata = m0_rdata;
assign s0_rvalid = m0_rvalid;
assign m0_rready = s0_rready;
// Avoid QIS warning, master address will be always same or larger than slave
// so only assign enough bit width from master to slave
assign m0_awaddr = s0_awaddr[M0_ADDR_WIDTH-1 :0];
assign m0_araddr = s0_araddr[M0_ADDR_WIDTH-1 :0];
assign m0_awuser = USE_S0_AWUSER ? s0_awuser : '0;
assign m0_aruser = USE_S0_ARUSER ? s0_aruser : '0;
assign m0_wuser = USE_S0_WUSER ? s0_wuser : '0;
assign s0_buser = USE_M0_BUSER ? m0_buser : '0;
assign s0_ruser = USE_M0_RUSER ? m0_ruser : '0;
assign m0_wuser_poison = (USE_S0_WUSER_POISON && ROLE_BASED_USER) ? s0_wuser_poison: 1'b0;
assign s0_ruser_poison = (USE_M0_RUSER_POISON && ROLE_BASED_USER) ? m0_ruser_poison: 1'b0;
assign m0_wuser_data = (USE_S0_WUSER_DATA && ROLE_BASED_USER) ? s0_wuser_data : 1'b0;
assign s0_ruser_data = (USE_M0_RUSER_DATA && ROLE_BASED_USER) ? m0_ruser_data : 1'b0;
assign m0_awuser_sai = (USE_S0_AWUSER_SAI && ROLE_BASED_USER) ? s0_awuser_sai: 'b0;
assign m0_aruser_sai = (USE_S0_ARUSER_SAI && ROLE_BASED_USER) ? s0_aruser_sai: 'b0;
//AXI5Lite Condition terp
assign m0_awakeup = '0;
assign m0_awtrace = '0;
assign m0_artrace = '0;
assign m0_wtrace = '0;
assign s0_btrace = '0;
assign s0_rtrace = '0;
assign m0_wpoison = '0;
assign s0_rpoison = '0;
assign m0_wdatachk = '0;
assign s0_rdatachk = '0;
assign m0_ardomain = s0_ardomain;
assign m0_arbar = s0_arbar;
assign m0_awdomain = s0_awdomain;
assign m0_awbar = s0_awbar;
assign m0_awatop = (USE_S0_AWATOP ) ? s0_awatop : '0;
assign m0_awstashnid = (USE_S0_AWSTASHNID ) ? s0_awstashnid : '0;
assign m0_awstashniden = (USE_S0_AWSTASHNIDEN ) ? s0_awstashniden : '0;
assign m0_awstashlpid = (USE_S0_AWSTASHLPID ) ? s0_awstashlpid : '0;
assign m0_awstashlpiden = (USE_S0_AWSTASHLPIDEN ) ? s0_awstashlpiden : '0;
assign m0_awmmusecsid = (USE_S0_AWMMUSECSID ) ? s0_awmmusecsid : '0;
assign m0_awmmusid = (USE_S0_AWMMUSID ) ? s0_awmmusid : '0;
assign m0_armmusecsid = (USE_S0_ARMMUSECSID ) ? s0_armmusecsid : '0;
assign m0_armmusid = (USE_S0_ARMMUSID ) ? s0_armmusid : '0;
assign m0_awaddrchk = (USE_S0_AWADDRCHK ) ? s0_awaddrchk : '0;
assign m0_araddrchk = (USE_S0_ARADDRCHK ) ? s0_araddrchk : '0;
generate
if (CALCULATE_WUSER_DATACHK && ROLE_BASED_USER) begin
assign m0_wuser_datachk = calcParity(s0_wdata);
end
else if(ROLE_BASED_USER && USE_S0_WUSER_DATACHK) begin
assign m0_wuser_datachk = s0_wuser_datachk;
end else begin
assign m0_wuser_datachk = '0;
end
if (CALCULATE_RUSER_DATACHK && ROLE_BASED_USER) begin
assign s0_ruser_datachk = calcParity(m0_rdata);
end else if(ROLE_BASED_USER && USE_M0_RUSER_DATACHK) begin
assign s0_ruser_datachk = m0_ruser_datachk;
end else begin
assign s0_ruser_datachk = '0;
end
if (CALCULATE_AWUSER_ADDRCHK && ROLE_BASED_USER) begin
assign ar_parity_status = 1'b0;
if(SKIP_USER_ADDRCHK_CAL) begin
assign m0_awuser_addrchk = '0;
end
else begin
assign m0_awuser_addrchk = addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_awaddr});
end
end else if(REGENERATE_ADDRCHK) begin
wire [S0_USER_ADDRCHK_WIDTH-1:0] expected_awuser_addrchk_parity;
assign expected_awuser_addrchk_parity = addrcalcParity ( {{S0_PADDING_ZERO{1'b0}},s0_awaddr });
assign aw_parity_status = (expected_awuser_addrchk_parity == s0_awuser_addrchk) ? 1'b0 : 1'b1;
assign m0_awuser_addrchk = aw_parity_status ? addrcalc_incorrectParity({{M0_PADDING_ZERO{1'b0}},m0_awaddr}): addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_awaddr});
end else if(ROLE_BASED_USER && USE_S0_AWUSER_ADDRCHK) begin
assign m0_awuser_addrchk = s0_awuser_addrchk;
assign ar_parity_status = 1'b0;
end else begin
assign m0_awuser_addrchk = '0;
assign ar_parity_status = 1'b0;
end
if (CALCULATE_ARUSER_ADDRCHK && ROLE_BASED_USER) begin
assign aw_parity_status = 1'b0;
if(SKIP_USER_ADDRCHK_CAL) begin
assign m0_awuser_addrchk = '0;
end
else begin
assign m0_aruser_addrchk = addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_araddr});
end
end else if(REGENERATE_ADDRCHK) begin
wire [S0_USER_ADDRCHK_WIDTH-1:0] expected_aruser_addrchk_parity;
assign ar_parity_status = (expected_aruser_addrchk_parity == s0_aruser_addrchk) ? 1'b0 : 1'b1;
assign expected_aruser_addrchk_parity = addrcalcParity ( {{S0_PADDING_ZERO{1'b0}},s0_araddr});
assign m0_aruser_addrchk = ar_parity_status ? addrcalc_incorrectParity({{M0_PADDING_ZERO{1'b0}},m0_araddr}): addrcalcParity({{M0_PADDING_ZERO{1'b0}},m0_araddr});
end else if(ROLE_BASED_USER && USE_S0_ARUSER_ADDRCHK) begin
assign ar_parity_status = 1'b0;
assign m0_aruser_addrchk = s0_aruser_addrchk;
end else begin
assign aw_parity_status = 1'b0;
assign m0_aruser_addrchk = '0;
end
endgenerate;
// --------------------------------------------------
//
// calcParity function: calculate byte-level parity of arbitrary-sized signal
//
// --------------------------------------------------
function reg [DATACHK_WIDTH-1:0] calcParity (
input [DATA_WIDTH-1:0] data
);
for (int i=0; i<DATACHK_WIDTH; i++)
calcParity[i] = ~(^ data[i*8 +:8]);
endfunction
//address parity generation logic
function reg [ADDRCHK_WIDTH-1:0] addrcalcParity (
input [M0_PARITY_ADDR_WIDTH-1:0] addr
);
for (int i=0; i<ADDRCHK_WIDTH; i++)
addrcalcParity[i] = ~(^ addr[i*8 +:8]);
endfunction
// --------------------------------------------------
// addrcalc_incorrectParity: calculates byte-level incorrect parity signal
// --------------------------------------------------
function reg [ADDRCHK_WIDTH-1:0] addrcalc_incorrectParity (
input [M0_PARITY_ADDR_WIDTH-1:0] addr
);
reg [ADDRCHK_WIDTH-1:0]addrcalcParity;
for (int i=0; i<ADDRCHK_WIDTH; i++)
addrcalcParity[i] = ~(^ addr[i*8 +:8]);
addrcalc_incorrectParity =~addrcalcParity;
endfunction
endmodule
qsys/qsys_top/altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv
+278
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@@ -0,0 +1,278 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_burst_adapter/new_source/altera_default_burst_converter.sv#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// --------------------------------------------
// Default Burst Converter
// Notes:
// 1) If burst type FIXED and slave is AXI,
// passthrough the transaction.
// 2) Else, converts burst into non-bursting
// transactions (length of 1).
// --------------------------------------------
`timescale 1 ns / 1 ns
module altera_default_burst_converter
#(
parameter PKT_BURST_TYPE_W = 2,
parameter PKT_BURSTWRAP_W = 5,
parameter PKT_ADDR_W = 12,
parameter PKT_BURST_SIZE_W = 3,
parameter IS_AXI_SLAVE = 0,
parameter LEN_W = 2,
parameter SYNC_RESET = 0
)
(
input clk,
input reset,
input enable,
input [PKT_BURST_TYPE_W - 1 : 0] in_bursttype,
input [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_reg,
input [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_value,
input [PKT_ADDR_W - 1 : 0] in_addr,
input [PKT_ADDR_W - 1 : 0] in_addr_reg,
input [LEN_W - 1 : 0] in_len,
input [PKT_BURST_SIZE_W - 1 : 0] in_size_value,
input in_is_write,
output reg [PKT_ADDR_W - 1 : 0] out_addr,
output reg [LEN_W - 1 : 0] out_len,
output reg new_burst
);
// ---------------------------------------------------
// AXI Burst Type Encoding
// ---------------------------------------------------
typedef enum bit [1:0]
{
FIXED = 2'b00,
INCR = 2'b01,
WRAP = 2'b10,
RESERVED = 2'b11
} AxiBurstType;
// -------------------------------------------
// Internal Signals
// -------------------------------------------
wire [LEN_W - 1 : 0] unit_len = {{LEN_W - 1 {1'b0}}, 1'b1};
reg [LEN_W - 1 : 0] next_len;
reg [LEN_W - 1 : 0] remaining_len;
reg [PKT_ADDR_W - 1 : 0] next_incr_addr;
reg [PKT_ADDR_W - 1 : 0] incr_wrapped_addr;
reg [PKT_ADDR_W - 1 : 0] extended_burstwrap_value;
reg [PKT_ADDR_W - 1 : 0] addr_incr_variable_size_value;
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
// -------------------------------------------
// Byte Count Converter
// -------------------------------------------
// Avalon Slave: Read/Write, the out_len is always 1 (unit_len).
// AXI Slave: Read/Write, the out_len is always the in_len (pass through) of a given cycle.
// If bursttype RESERVED, out_len is always 1 (unit_len).
generate if (IS_AXI_SLAVE == 1)
begin : axi_slave_out_len
always_ff @(posedge clk) begin
if (enable) begin
out_len <= (in_bursttype == FIXED) ? in_len : unit_len;
end
end
//if (SYNC_RESET == 0 ) begin : async_rst1
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// out_len <= {LEN_W{1'b0}};
// end
// else if (enable) begin
// out_len <= (in_bursttype == FIXED) ? in_len : unit_len;
// end
// end
//end // async_rst1
//else begin // sync_rst1
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// out_len <= {LEN_W{1'b0}};
// end
// else if (enable) begin
// out_len <= (in_bursttype == FIXED) ? in_len : unit_len;
// end
// end
//end // sync_rst1
end
else // IS_AXI_SLAVE == 0
begin : non_axi_slave_out_len
always_comb begin
out_len = unit_len;
end
end
endgenerate
always_comb begin : proc_extend_burstwrap
extended_burstwrap_value = {{(PKT_ADDR_W - PKT_BURSTWRAP_W){in_burstwrap_reg[PKT_BURSTWRAP_W - 1]}}, in_burstwrap_value};
addr_incr_variable_size_value = {{(PKT_ADDR_W - 1){1'b0}}, 1'b1} << in_size_value;
end
// -------------------------------------------
// Address Converter
// -------------------------------------------
// Write: out_addr = in_addr at every cycle (pass through).
// Read: out_addr = in_addr at every new_burst. Subsequent addresses calculated by converter.
always_ff @(posedge clk) begin
if (enable) begin
next_incr_addr <= next_incr_addr + addr_incr_variable_size_value;
if (new_burst) begin
next_incr_addr <= in_addr + addr_incr_variable_size_value;
end
out_addr <= incr_wrapped_addr;
end
end
//generate
//if (SYNC_RESET == 0) begin : async_rst2
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// next_incr_addr <= {PKT_ADDR_W{1'b0}};
// out_addr <= {PKT_ADDR_W{1'b0}};
// end
// else if (enable) begin
// next_incr_addr <= next_incr_addr + addr_incr_variable_size_value;
// if (new_burst) begin
// next_incr_addr <= in_addr + addr_incr_variable_size_value;
// end
// out_addr <= incr_wrapped_addr;
// end
// end
// end // async_rst2
// else begin // sync_rst2
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// next_incr_addr <= {PKT_ADDR_W{1'b0}};
// out_addr <= {PKT_ADDR_W{1'b0}};
// end
// else if (enable) begin
// next_incr_addr <= next_incr_addr + addr_incr_variable_size_value;
// if (new_burst) begin
// next_incr_addr <= in_addr + addr_incr_variable_size_value;
// end
// out_addr <= incr_wrapped_addr;
// end
// end
// end // sync_rst2
//endgenerate
always_comb begin
incr_wrapped_addr = in_addr;
if (!new_burst) begin
// This formula calculates addresses of WRAP bursts and works perfectly fine for other burst types too.
incr_wrapped_addr = (in_addr_reg & ~extended_burstwrap_value) | (next_incr_addr & extended_burstwrap_value);
end
end
// -------------------------------------------
// Control Signals
// -------------------------------------------
// Determine the min_len.
// 1) FIXED read to AXI slave: One-time passthrough, therefore the min_len == in_len.
// 2) FIXED write to AXI slave: min_len == 1.
// 3) FIXED read/write to Avalon slave: min_len == 1.
// 4) RESERVED read/write to AXI/Avalon slave: min_len == 1.
wire [LEN_W - 1 : 0] min_len;
generate if (IS_AXI_SLAVE == 1)
begin : axi_slave_min_len
assign min_len = (!in_is_write && (in_bursttype == FIXED)) ? in_len : unit_len;
end
else // IS_AXI_SLAVE == 0
begin : non_axi_slave_min_len
assign min_len = unit_len;
end
endgenerate
// last_beat calculation.
wire last_beat = (remaining_len == min_len);
// next_len calculation.
always_comb begin
remaining_len = in_len;
if (!new_burst) remaining_len = next_len;
end
always_ff @(posedge clk) begin
if (enable) begin
next_len <= remaining_len - unit_len;
end
end
generate
if (SYNC_RESET == 0) begin : async_rst3
//always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// next_len <= 1'b0;
// end
// else if (enable) begin
// next_len <= remaining_len - unit_len;
// end
//end
// new_burst calculation.
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
new_burst <= 1'b1;
end
else if (enable) begin
new_burst <= last_beat;
end
end
end // async_rst3
else begin // sync_rst3
//always_ff @(posedge clk) begin
// if (internal_sclr) begin
// next_len <= 1'b0;
// end
// else if (enable) begin
// next_len <= remaining_len - unit_len;
// end
//end
// new_burst calculation.
always_ff @(posedge clk) begin
if (internal_sclr) begin
new_burst <= 1'b1;
end
else if (enable) begin
new_burst <= last_beat;
end
end
end // sync_rst3
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZnXzCebnCKJTsi823h62YzED9giUrsXJJm305Cxwn/ZRLE5PqwZtvf+8ZAVJE55kNVZaV60bWlN1N0XZR9KM1WwQkKYejedngoMHZ5SvtJeJU4qT4/oQOvKek5HLy5M6ATeo0EfJB3ak4qOC206cHdjo6jQaq4jVeRzd4W9l5Hk/MsscWd3wt993nAf88yhZUaJ1/mBpRC35cYTaXNnFY84PO+FW8JiMxDjLScLm/9k8wCnKRnF0Hs5P4VIY630mFMHoKoejOV1LqpqaU/cjYNnrlSYDmB49HKeYpESgUpAw/F+kYpWqck871iv0EzYP3Z3dhwLSf70SFr5f6Z0TDE3Gr4JfN9KPx6CcPDKeGzYK+fFSJSbCsCPgEl2xC4MI7ISbMJHOcc/V7ZbFLP6r5n8kZlPYOE9L8TJoc1Vcg8UxGcxzW9pE8AgMTFCoLGmA77bKOzo4BwadS0t585NPOjoR4cRPJfC3+2qNG4cdNvwrKBS2VUO7341urJcK/l9J0S9BxiN6U+1HjmDuBCgG09cqLR8+cnmDRKpiIky8laAqXEDKzhWqlD1ganoZi7z4DWtAwMN8P+YVycreBGZgwssabwyo2LmDpP+Uitsy15PbNMCdOJfMK8bkzkIMh2N67/N3Z4HkFKETIcGtbr7Le7scupVRRszgiRj7sZNNULEGcrKiPlFzfAsmzIiqX9N0klWvUcO95LliNP8e+CZZdzfGcKxZVSLsedLYpqEWGn8MBt0cTrRUPAriDk6XjdkPIN9frlNlJ/d6l4jzxLrmAnT"
`endif
qsys/qsys_top/altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv
+520
View File
@@ -0,0 +1,520 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_burst_adapter/new_source/altera_incr_burst_converter.sv#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// ----------------------------------------------------------
// This component is used for INCR Avalon slave
// (slave which only supports INCR) or AXI slave.
// It converts burst length of input packet
// to match slave burst.
// ----------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_incr_burst_converter
#(
parameter
// ----------------------------------------
// Burst length Parameters
// (real burst length value, not bytecount)
// ----------------------------------------
MAX_IN_LEN = 16,
MAX_OUT_LEN = 4,
NUM_SYMBOLS = 4,
ADDR_WIDTH = 12,
BNDRY_WIDTH = 12,
BURSTSIZE_WIDTH = 3,
IN_NARROW_SIZE = 0,
PURELY_INCR_AVL_SYS = 0,
SYNC_RESET = 0,
// ------------------
// Derived Parameters
// ------------------
LEN_WIDTH = log2ceil(MAX_IN_LEN) + 1,
OUT_LEN_WIDTH = log2ceil(MAX_OUT_LEN) + 1,
LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS)
)
(
input clk,
input reset,
input enable,
input is_write,
input [LEN_WIDTH - 1 : 0] in_len,
input in_sop,
input [ADDR_WIDTH - 1 : 0] in_addr,
input [ADDR_WIDTH - 1 : 0] in_addr_reg,
input [BNDRY_WIDTH - 1 : 0] in_burstwrap_reg,
input [BURSTSIZE_WIDTH - 1 : 0] in_size_t,
input [BURSTSIZE_WIDTH - 1 : 0] in_size_reg,
// converted output length
// out_len : compressed burst, read
// uncompressed_len: uncompressed, write
output reg [LEN_WIDTH - 1 : 0] out_len,
output reg [LEN_WIDTH - 1 : 0] uncompr_out_len,
// Compressed address output
output reg [ADDR_WIDTH - 1 : 0] out_addr,
output reg new_burst_export
);
// ----------------------------------------
// Signals for wrapping support
// ----------------------------------------
reg [LEN_WIDTH - 1 : 0] remaining_len;
reg [LEN_WIDTH - 1 : 0] next_out_len;
reg [LEN_WIDTH - 1 : 0] next_rem_len;
reg [LEN_WIDTH - 1 : 0] uncompr_remaining_len;
reg [LEN_WIDTH - 1 : 0] next_uncompr_remaining_len;
reg [LEN_WIDTH - 1 : 0] next_uncompr_rem_len;
reg new_burst;
reg uncompr_sub_burst;
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
// Avoid QIS warning
wire [OUT_LEN_WIDTH - 1 : 0] max_out_length;
assign max_out_length = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0];
always_comb begin
new_burst_export = new_burst;
end
// -------------------------------------------
// length remaining calculation
// -------------------------------------------
always_comb begin : proc_uncompressed_remaining_len
if ((in_len <= max_out_length) && is_write) begin
uncompr_remaining_len = in_len;
end else begin
uncompr_remaining_len = max_out_length;
end
if (uncompr_sub_burst)
uncompr_remaining_len = next_uncompr_rem_len;
end
always_ff @(posedge clk) begin
if (enable) begin
next_uncompr_rem_len <= uncompr_remaining_len - 1'b1; // in term of length, it just reduces 1
end
end
//generate
// if (SYNC_RESET == 0) begin : async_rst1
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// next_uncompr_rem_len <= 0;
// end
// else if (enable) begin
// next_uncompr_rem_len <= uncompr_remaining_len - 1'b1; // in term of length, it just reduces 1
// end
// end
// end // async_rst1
// else begin // sync_rst1
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// next_uncompr_rem_len <= 0;
// end
// else if (enable) begin
// next_uncompr_rem_len <= uncompr_remaining_len - 1'b1; // in term of length, it just reduces 1
// end
// end
// end // sync_rst1
//endgenerate
always_comb begin : proc_compressed_remaining_len
remaining_len = in_len;
if (!new_burst)
remaining_len = next_rem_len;
end
always_ff@(posedge clk) begin : proc_next_uncompressed_remaining_len
if (enable) begin
if (in_sop) begin
next_uncompr_remaining_len <= in_len - max_out_length;
end
else if (!uncompr_sub_burst)
next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
end
end
//generate
// if (SYNC_RESET == 0) begin : async_rst2
// always_ff@(posedge clk or posedge reset) begin : proc_next_uncompressed_remaining_len
// if(reset) begin
// next_uncompr_remaining_len <= '0;
// end
// else if (enable) begin
// if (in_sop) begin
// next_uncompr_remaining_len <= in_len - max_out_length;
// end
// else if (!uncompr_sub_burst)
// next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
// end
// end
// end // async_rst2
// else begin // sync_rst2
// always_ff@(posedge clk ) begin : proc_next_uncompressed_remaining_len
// if(internal_sclr) begin
// next_uncompr_remaining_len <= '0;
// end
// else if (enable) begin
// if (in_sop) begin
// next_uncompr_remaining_len <= in_len - max_out_length;
// end
// else if (!uncompr_sub_burst)
// next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
// end
// end
// end // sync_rst2
//endgenerate
always_comb begin
next_out_len = max_out_length;
if (remaining_len < max_out_length) begin
next_out_len = remaining_len;
end
end // always_comb
// --------------------------------------------------
// Length remaining calculation : compressed
// --------------------------------------------------
// length remaining for compressed transaction
// for wrap, need special handling for first out length
always_ff @(posedge clk) begin
if (enable) begin
if (new_burst)
next_rem_len <= in_len - max_out_length;
else
next_rem_len <= next_rem_len - max_out_length;
end
end
generate
if (SYNC_RESET == 0) begin: async_rst3
//always_ff @(posedge clk, posedge reset) begin
// if (reset)
// next_rem_len <= 0;
// else if (enable) begin
// if (new_burst)
// next_rem_len <= in_len - max_out_length;
// else
// next_rem_len <= next_rem_len - max_out_length;
// end
//end
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
uncompr_sub_burst <= 0;
end
else if (enable && is_write) begin
uncompr_sub_burst <= (uncompr_remaining_len > 1'b1);
end
end
end // async_rst3
else begin // sync_rst3
//always_ff @(posedge clk) begin
// if (internal_sclr)
// next_rem_len <= 0;
// else if (enable) begin
// if (new_burst)
// next_rem_len <= in_len - max_out_length;
// else
// next_rem_len <= next_rem_len - max_out_length;
// end
//end
always_ff @(posedge clk) begin
if (internal_sclr) begin
uncompr_sub_burst <= 0;
end
else if (enable && is_write) begin
uncompr_sub_burst <= (uncompr_remaining_len > 1'b1);
end
end
end // sync_rst3
endgenerate
// --------------------------------------------------
// Control signals
// --------------------------------------------------
wire end_compressed_sub_burst;
assign end_compressed_sub_burst = (remaining_len == next_out_len);
// new_burst:
// the converter takes in_len for new calculation
generate
if (SYNC_RESET == 0) begin : async_rst4
always_ff @(posedge clk, posedge reset) begin
if (reset)
new_burst <= 1;
else if (enable)
new_burst <= end_compressed_sub_burst;
end
end // async_rst4
else begin // sync_rst4
always_ff @(posedge clk) begin
if (internal_sclr)
new_burst <= 1;
else if (enable)
new_burst <= end_compressed_sub_burst;
end
end
endgenerate
// --------------------------------------------------
// Output length
// --------------------------------------------------
// register out_len for compressed trans
always_ff @(posedge clk) begin
if (enable) begin
out_len <= next_out_len;
end
end
// register uncompr_out_len for uncompressed trans
always_ff @(posedge clk) begin
if (enable) begin
uncompr_out_len <= uncompr_remaining_len;
end
end
//generate
// if (SYNC_RESET == 0) begin : async_rst5
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// out_len <= 0;
// end
// else if (enable) begin
// out_len <= next_out_len;
// end
// end
// // register uncompr_out_len for uncompressed trans
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// uncompr_out_len <= '0;
// end
// else if (enable) begin
// uncompr_out_len <= uncompr_remaining_len;
// end
// end
//end // async_rst5
//else begin // sync_rst5
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// out_len <= 0;
// end
// else if (enable) begin
// out_len <= next_out_len;
// end
// end
// // register uncompr_out_len for uncompressed trans
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// uncompr_out_len <= '0;
// end
// else if (enable) begin
// uncompr_out_len <= uncompr_remaining_len;
// end
// end
//end //sync_rst5
//endgenerate
// --------------------------------------------------
// Address Calculation
// --------------------------------------------------
reg [ADDR_WIDTH - 1 : 0] addr_incr_sel;
reg [ADDR_WIDTH - 1 : 0] addr_incr_sel_reg;
reg [ADDR_WIDTH - 1 : 0] addr_incr_full_size;
localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS;
generate
if (IN_NARROW_SIZE) begin : narrow_addr_incr
reg [ADDR_WIDTH - 1 : 0] addr_incr_variable_size;
reg [ADDR_WIDTH - 1 : 0] addr_incr_variable_size_reg;
assign addr_incr_variable_size = MAX_OUT_LEN << in_size_t;
assign addr_incr_variable_size_reg = MAX_OUT_LEN << in_size_reg;
assign addr_incr_sel = addr_incr_variable_size;
assign addr_incr_sel_reg = addr_incr_variable_size_reg;
end
else begin : full_addr_incr
assign addr_incr_full_size = ADDR_INCR[ADDR_WIDTH - 1 : 0];
assign addr_incr_sel = addr_incr_full_size;
assign addr_incr_sel_reg = addr_incr_full_size;
end
endgenerate
reg [ADDR_WIDTH - 1 : 0] next_out_addr;
reg [ADDR_WIDTH - 1 : 0] incremented_addr;
always_ff @(posedge clk) begin
if (enable) begin
out_addr <= (next_out_addr);
end
end
//generate
// if (SYNC_RESET == 0) begin : async_rst6
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// out_addr <= '0;
// end else begin
// if (enable) begin
// out_addr <= (next_out_addr);
// end
// end
// end
// end // async_rst6
// else begin // sync_rst6
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// out_addr <= '0;
// end else begin
// if (enable) begin
// out_addr <= (next_out_addr);
// end
// end
// end
// end // sync_rst6
// endgenerate
generate
if (!PURELY_INCR_AVL_SYS) begin : incremented_addr_normal
always_ff @(posedge clk) begin
if (enable) begin
if (new_burst) begin
incremented_addr <= (next_out_addr + addr_incr_sel);
end
else begin
incremented_addr <= (next_out_addr + addr_incr_sel_reg);
end
end
end // always_ff @
//if (SYNC_RESET == 0) begin : async_rst7
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// incremented_addr <= '0;
// end
// else if (enable) begin
// incremented_addr <= (next_out_addr + addr_incr_sel_reg);
// if (new_burst) begin
// incremented_addr <= (next_out_addr + addr_incr_sel);
// end
// end
// end // always_ff @
//end // async_rst7
//else begin // sync_rst7
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// incremented_addr <= '0;
// end
// else if (enable) begin
// incremented_addr <= (next_out_addr + addr_incr_sel_reg);
// if (new_burst) begin
// incremented_addr <= (next_out_addr + addr_incr_sel);
// end
// end
// end // always_ff @
//end // sync_rst7
always_comb begin
next_out_addr = in_addr;
if (!new_burst) begin
next_out_addr = incremented_addr;
end
end
end
else begin : incremented_addr_pure_av
always_ff @(posedge clk) begin
if (enable) begin
incremented_addr <= (next_out_addr + addr_incr_sel_reg);
end
end // always_ff @
//if (SYNC_RESET == 0) begin : async_rst8
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// incremented_addr <= '0;
// end
// else if (enable) begin
// incremented_addr <= (next_out_addr + addr_incr_sel_reg);
// end
// end // always_ff @
//end // async_rst8
//else begin // sync_rst8
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// incremented_addr <= '0;
// end
// else if (enable) begin
// incremented_addr <= (next_out_addr + addr_incr_sel_reg);
// end
// end // always_ff @
// end // sync_rst8
always_comb begin
next_out_addr = in_addr;
if (!new_burst) begin
next_out_addr = (incremented_addr);
end
end
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZm2VnW9Jup+rO8tHn46ia+m1jd1lvf4qalDbWMpZ7/iR078F3NbXmSfszSWG0PYb1O/+IcoZgGEBa4thPbK141luDnU00je40S0l+dVi8sQRSkZ06QX7VOV1HZ58TwdhajcQDrYTBrJ/wnghIvibweYzsQp21UeRH1tHdQb9EX/90LIxErNs9qZn6FdE/wU7Nnk0BApTSHa5j7Oq6whWnvIJLoY+NDfNdmguQ5c5E6FNiZBIhwP/gOXHb/Xm2fDPcMvXcyokY7FuDYoM8BdoUJ+OVZhbg6kE3dGqlFzZ60/+I5AYaHj1YtiTy6zGO1WlQnC9Sov4dHl/nkN231hsVmVVehUnm0X9f6djXsXUCx2V4JBRqjfGugv+XBeZ7HMoK6LH9u4KSTlqLlNrvhPX1VXe6UjwtOzHxYGUWqvESIeNAxWo/4NsdiISuU7Ut75o/3SMGjSlAM7UYSVvfIKi5vhCIKKXWh8sv0pKKrscZmZZ/OnnKio2r2xi88/64nRWpeQLYbzJvOmzzD5662ckE9n2faDKveVDFd+hpDfzkxyJ1LcqlVbHGqIMMAyPaTibmi0MV3Rd4tFFycrgcfYSW2I2CZTl8Rl/mstykAJ+vOi233Cy2RN1EviSi9EtnimDziOtUfW0sHScrdN1sEWY0xL2HM3oZBGMXvTOYwRGqobo4r/v6rfvRDKjzYBDzylQrvPRTibwXUKTDizbO7CXOL30RYfG/EAFhOqWFZBz89zBGyL8kCGAD5mh8/7pcdM1Y52JOHLbDLceUAQRV+5n0po"
`endif
qsys/qsys_top/altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv
+305
View File
@@ -0,0 +1,305 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_axi_master_ni/address_alignment.sv#3 $
// $Revision: #3 $
// $Date: 2012/07/11 $
//-----------------------------------------
// Address alignment:
// This component will aglin input address with input size
// Support address increment with butst type and burstwrap value
//-----------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_address_alignment
#(
parameter
ADDR_W = 12,
BURSTWRAP_W = 12,
TYPE_W = 2,
SIZE_W = 3,
INCREMENT_ADDRESS = 1,
NUMSYMBOLS = 8,
SELECT_BITS = log2(NUMSYMBOLS),
IN_DATA_W = ADDR_W + (BURSTWRAP_W-1) + TYPE_W + SIZE_W,
OUT_DATA_W = ADDR_W + SELECT_BITS,
SYNC_RESET = 0
)
(
input clk,
input reset,
input [IN_DATA_W-1:0] in_data, // in_data = {wrap_boundary, address, type, size}
input in_valid,
//output in_ready,
input in_sop,
input in_eop,
output reg [OUT_DATA_W-1:0] out_data,
input out_ready
//output out_valid
);
typedef enum bit [1:0]
{
FIXED = 2'b00,
INCR = 2'b01,
WRAP = 2'b10,
RESERVED = 2'b11
} AxiBurstType;
//----------------------------------------------------
// AXSIZE decoding
//
// Turns the axsize value into the actual number of bytes
// being transferred.
// ---------------------------------------------------
function reg[9:0] bytes_in_transfer;
input [SIZE_W-1:0] axsize;
case (axsize)
4'b0000: bytes_in_transfer = 10'b0000000001;
4'b0001: bytes_in_transfer = 10'b0000000010;
4'b0010: bytes_in_transfer = 10'b0000000100;
4'b0011: bytes_in_transfer = 10'b0000001000;
4'b0100: bytes_in_transfer = 10'b0000010000;
4'b0101: bytes_in_transfer = 10'b0000100000;
4'b0110: bytes_in_transfer = 10'b0001000000;
4'b0111: bytes_in_transfer = 10'b0010000000;
4'b1000: bytes_in_transfer = 10'b0100000000;
4'b1001: bytes_in_transfer = 10'b1000000000;
default: bytes_in_transfer = 10'b0000000001;
endcase
endfunction
//--------------------------------------
// Burst type decode
//--------------------------------------
AxiBurstType write_burst_type;
function AxiBurstType burst_type_decode
(
input [1:0] axburst
);
AxiBurstType burst_type;
begin
case (axburst)
2'b00 : burst_type = FIXED;
2'b01 : burst_type = INCR;
2'b10 : burst_type = WRAP;
2'b11 : burst_type = RESERVED;
default : burst_type = INCR;
endcase
return burst_type;
end
endfunction
//----------------------------------------------------
// Ubiquitous, familiar log2 function
//----------------------------------------------------
function integer log2;
input integer value;
value = value - 1;
for(log2 = 0; value > 0; log2 = log2 + 1)
value = value >> 1;
endfunction
//------------------------------------------------------------------------
// This component will read address and size and check
// if this is aligned or not. If not then it will align this address to the size
// of the transfer:
// Check alignment:
// - With data width, can define maximun how many lower bits of address to indicate this
// address align to the size
// - Ex: 32 bits data => size can be: 1, 2, 4 bytes
// For 4 bytes: when 2 lower bits of address equal 0, this is aligned address
// addr=00|00| (0), 01|00| (4) => align to size of 4 bytes
// addr=00|01| (1) => start addr at 1, is not aligned to size 4 byte
// For 2 bytes: use last one bit to indicate algined or not
// addr=000|0| (0), 001|0| (2) => align to size of 2 bytes
// addr=000|1| (1), 001|1| (3) => not align to 2 bytes
// As size runtime change, creat mask and change accordingly to size, can detect address alignment
// and to align to size, apply this mask with zero to the address.
//-------------------------------------------------------------------------
// THe function return a vector which has width [(SELECT_BITS * 2) -1 : 0]
// in which the first part contains the mask to check if this address aligned or not
// second part contains the mast to mask address to align to size
function reg[(SELECT_BITS*2)-1 : 0] mask_select_and_align_address;
input [ADDR_W-1:0] address;
input [SIZE_W-1:0] size; // size is in AXI coding: 001 -> 2 bytes
integer i;
reg [SELECT_BITS-1:0] mask_address;
reg [SELECT_BITS-1:0] check_unaligned; // any bits =1 -> unalgined (except size = 0; 1 byte)
mask_address = '1;
check_unaligned = '0;
for(i = 0; i < SELECT_BITS ; i = i + 1) begin
if (i < size) begin
check_unaligned[i] = address[i];
mask_address[i] = 1'b0;
end
end
mask_select_and_align_address = {check_unaligned,mask_address};
endfunction
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= ~reset;
end
end
endgenerate
reg [ADDR_W-1 : 0] in_address;
reg [ADDR_W-1 : 0] first_address_aligned;
reg [SIZE_W-1 : 0] in_size;
reg [(SELECT_BITS*2)-1 : 0] output_masks;
// Extract information from input data
assign in_address = in_data[SIZE_W+ADDR_W-1 : SIZE_W];
assign in_size = in_data[SIZE_W-1 : 0];
// Generate the masks
always_comb
begin
output_masks = mask_select_and_align_address(in_address, in_size);
end
// Align address if needed
generate
// SELECT_BITS == 1: input packet has 1 NUMSYMBOLS (1 bytes), it is aligned
if (SELECT_BITS == 0)
assign first_address_aligned = in_address;
else begin
// SELECT_BITS ==1 :input packet 2 bytes (2 SYMBOLS)
wire [SELECT_BITS-1 : 0] aligned_address_bits;
if (SELECT_BITS == 1)
assign aligned_address_bits = in_address[0] & output_masks[0];
else
assign aligned_address_bits = in_address[SELECT_BITS-1:0] & output_masks[SELECT_BITS-1:0];
assign first_address_aligned = {in_address[ADDR_W-1 : SELECT_BITS], aligned_address_bits};
end
endgenerate
// Increment address base on size, first address keep the same
generate
if (INCREMENT_ADDRESS)
begin
reg [ADDR_W-1 : 0] increment_address;
reg [ADDR_W-1 : 0] out_aligned_address_burst;
reg [ADDR_W-1 : 0] address_burst;
reg [ADDR_W-1 : 0] base_address;
reg [9 : 0] number_bytes_transfer;
reg [ADDR_W-1 : 0] burstwrap_mask;
reg [ADDR_W-1 : 0] burst_address_high;
reg [ADDR_W-1 : 0] burst_address_low;
reg [BURSTWRAP_W-2 :0] in_burstwrap_boundary;
reg [TYPE_W-1 : 0] in_type;
//------------------------------------------------
// Use the extended burstwrap value to split the high (constant) and
// low (changing) part of the address
//-----------------------------------------------
assign in_type = in_data[SIZE_W+ADDR_W+TYPE_W-1 : SIZE_W+ADDR_W];
assign in_burstwrap_boundary = in_data[IN_DATA_W-1 : ADDR_W+TYPE_W+SIZE_W];
assign burstwrap_mask = {{(ADDR_W - BURSTWRAP_W){1'b0}}, in_burstwrap_boundary};
assign burst_address_high = out_aligned_address_burst & ~burstwrap_mask;
assign burst_address_low = out_aligned_address_burst;
assign number_bytes_transfer = bytes_in_transfer(in_size);
assign write_burst_type = burst_type_decode(in_type);
always @*
begin
if (in_sop)
begin
out_aligned_address_burst = in_address;
base_address = first_address_aligned;
end
else
begin
out_aligned_address_burst = address_burst;
base_address = out_aligned_address_burst;
end
case (write_burst_type)
INCR:
increment_address = base_address + number_bytes_transfer;
WRAP:
increment_address = ((burst_address_low + number_bytes_transfer) & burstwrap_mask) | burst_address_high;
FIXED:
increment_address = out_aligned_address_burst;
default:
increment_address = base_address + number_bytes_transfer;
endcase // case (write_burst_type)
end // always @ *
if (SYNC_RESET == 0) begin : async_rst0
always_ff @(posedge clk, negedge reset)
begin
if (!reset)
begin
address_burst <= '0;
end
else
begin
if (in_valid & out_ready)
address_burst <= increment_address;
end
end
end : async_rst0
else begin : sync_rst0
always_ff @(posedge clk)
begin
if (internal_sclr)
begin
address_burst <= '0;
end
else
begin
if (in_valid & out_ready)
address_burst <= increment_address;
end
end
end : sync_rst0
// send data to output with 2 part: [mask_t0_algin][address_aligned_increment]
// corner case when SELECT_BITS==0 - total bits in
// [SELECTS_BITS-1:0] ==> 1-:0 ==> 2 bits in total
// leads to warning
if (SELECT_BITS==0)
assign out_data = out_aligned_address_burst;
else
assign out_data = {output_masks[SELECT_BITS-1 : 0], out_aligned_address_burst};
end // if (INCREMENT_ADDRESS)
else
begin
// corner case when SELECT_BITS==0 - total bits in
// [SELECTS_BITS-1:0] ==> 1-:0 ==> 2 bits in total
// leads to warning
if (SELECT_BITS==0)
assign out_data = first_address_aligned;
else
assign out_data = {output_masks[SELECT_BITS-1 : 0], first_address_aligned};
end // else: !if(INCREMENT_ADDRESS)
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZnuSxX8yXxnIFVWsgCk75Z0P+dtbDvmJdtQl1WjW4yFuhoOU6T348GM/xUHtJ4nzM+Ie8UNgnT16AXfoOSoZ6aw4EqtmutAt1g0WrS8Zo7lntdL4Ed4jMhrdzQ2wGXcukpdBXSOlxyVkCs8O5Bx5bsJHA8kY1r+dEjpFU6yRXbht/crFehVXoHCjTTZnCo6ONciQai4cPqisPuj4rwOI0P18Yry6OKgj6AYn8jpBhuXzb8sDJ3t4lulV43YetVoYKIdiLdg9MNtOudp0cdO7C9wiNkMhIPLI2VLiAgdsxlTZo0H7/klMzcS7oMYhgKBYj3rMGfIF8GIfjTv7DXR06ED3LZScux5eFxq7qC9RRhgCFd2O/5OwjkezW2Fe1fos97+/4c0SVIufbIeAiMRsYmglnEcMCPwWnhbxi/B4Q/YpYAH96gY/+ITpxiLlp7H+Wot7TKsR10cNB8FfVYrKfDgFm3aAGBtmVsUAz3X31S6DJdo/eXRPthu3tfuBI4BAB2tQptyaBZIqDMWE/TeUinC41fvbEAe/N84+in0g3XgKSMRshfZ8yKNB5HICw0eV/rxJsVyCdWVsaafsz31CT1ij2Mvr1H7LbAUmPVt546kJCR7d/o6inwycxcb5G7r8r7du8eigB4sXm3QEMQTpHFX0PXZW0KnyL4Dml+CXK43oRj2wIP58dXUWPsi8nphSGr64d8Zt0FlS2NO2Y0jv3ecZkOIjZu+9pPoWGxFSdPY/fBYS18Q736mwIEkGiruEglqw3eKurFsVAnQNbb/cn/1"
`endif
qsys/qsys_top/altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv
+1536
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qsys/qsys_top/altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv
+2293
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qsys/qsys_top/altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv
+96
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@@ -0,0 +1,96 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter.sv#68 $
// $Revision: #68 $
// $Date: 2014/01/23 $
`timescale 1 ns / 1 ns
// -------------------------------------------------------
// Adapter for uncompressed transactions only. This adapter will
// typically be used to adapt burst length for non-bursting
// wide to narrow Avalon links.
// -------------------------------------------------------
module altera_merlin_burst_adapter_uncompressed_only
#(
parameter
PKT_BYTE_CNT_H = 5,
PKT_BYTE_CNT_L = 0,
PKT_BYTEEN_H = 83,
PKT_BYTEEN_L = 80,
ST_DATA_W = 84,
ST_CHANNEL_W = 8
)
(
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink0_valid,
input [ST_DATA_W-1 : 0] sink0_data,
input [ST_CHANNEL_W-1 : 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output reg sink0_ready,
// -------------------
// Command Source (Output)
// -------------------
output reg source0_valid,
output reg [ST_DATA_W-1 : 0] source0_data,
output reg [ST_CHANNEL_W-1 : 0] source0_channel,
output reg source0_startofpacket,
output reg source0_endofpacket,
input source0_ready
);
localparam
PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
NUM_SYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
wire [PKT_BYTE_CNT_W - 1 : 0] num_symbols_sig = NUM_SYMBOLS[PKT_BYTE_CNT_W - 1 : 0];
always_comb begin : source0_data_assignments
source0_valid = sink0_valid;
source0_channel = sink0_channel;
source0_startofpacket = sink0_startofpacket;
source0_endofpacket = sink0_endofpacket;
source0_data = sink0_data;
source0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = num_symbols_sig;
sink0_ready = source0_ready;
end
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZlEl7U1mwDa2foPMdSqYqEvxrVPv0jMzxA0aRf5GvKemQQYiAUmoPZ/yty49qVq2u4nCWeBwiIOIWm7gDC9G7PUqb6tQOwrlINch7TSLyDBSTQRE9hXc7SldcwRHZbphJdXk8dLtmihOMDJFCjqPdl3yLIyPr7YL6350GrMmyAi0VBnzeb3PXYeJ774WH1+ABTda662GekklRXGy8DtIgPk0IIg3Oj1dwRb3pFTN66nlIPiZBgL8gjO0CYauPX/q9nMQFGeoQZr4+5e98MGAqbEcnhgooJzrOeQs2tRxgUiChvubqPONnP1A1YFtubOn7CcIC2RelzTbXvuG7xBL8BFrgyCRg/DB4902JDspTPYHKTGnATpyW9IaQ1niNwNhdHAEqiIUKBD/YZXcjnXVgHmwCUait0N//YwiEJonwrRzUsNWzXI1Hqd95q5Iyv88LJIqRopX6GB7QDDG42Z8rlNeHcFQnyJKEV5BhNCL8p3A8ygXqZ6pjUDwYOR+Dgarpg9ij6TIXQQHiiEozYHxBY0fcHtNb8FfenfODkF3XaHFzJciEYDrjHK2q3Ns7fTAp+HkmKgxb/S/s3qrHnpl3GVY+nokliANaXmDBgv4PGyFDfOm5ZifW3H7XSXvHNPSnpKxGuEoZt2v0zN2gZIcCaS5smLpTK+Lh0uks2gCvA/v1P41pbHzy/7CM/JZiP8V8q0zQ0ELX/oWMYwC/t43xkpbirj8nuULPIQPAupetsXyCnaz2p2/DdsSsbGj3kyXN8JLoZV990Dl5M4UL/HzKhw"
`endif
qsys/qsys_top/altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv
+545
View File
@@ -0,0 +1,545 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_burst_adapter/new_source/altera_wrap_burst_converter.sv#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// ------------------------------------------------------
// This component is specially for Wrapping Avalon slave.
// It converts burst length of input packet
// to match slave burst.
// ------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_wrap_burst_converter
#(
parameter
// ----------------------------------------
// Burst length Parameters
// (real burst length value, not bytecount)
// ----------------------------------------
MAX_IN_LEN = 16,
MAX_OUT_LEN = 4,
ADDR_WIDTH = 12,
BNDRY_WIDTH = 12,
NUM_SYMBOLS = 4,
AXI_SLAVE = 0,
OPTIMIZE_WRITE_BURST = 0,
SYNC_RESET = 0,
// ------------------
// Derived Parameters
// ------------------
LEN_WIDTH = log2ceil(MAX_IN_LEN) + 1,
OUT_LEN_WIDTH = log2ceil(MAX_OUT_LEN) + 1,
LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS)
)
(
input clk,
input reset,
input enable_write,
input enable_read,
input [LEN_WIDTH - 1 : 0] in_len,
input [LEN_WIDTH - 1 : 0] first_len,
input in_sop,
input [ADDR_WIDTH - 1 : 0] in_addr,
input [ADDR_WIDTH - 1 : 0] in_addr_reg,
input [BNDRY_WIDTH - 1 : 0] in_boundary,
input [BNDRY_WIDTH - 1 : 0] in_burstwrap,
input [BNDRY_WIDTH - 1 : 0] in_burstwrap_reg,
// converted output length
// out_len : compressed burst, read
// uncompressed_len: uncompressed, write
output reg [LEN_WIDTH - 1 : 0] out_len,
output reg [LEN_WIDTH - 1 : 0] uncompr_out_len,
// Compressed address output
output reg [ADDR_WIDTH - 1 : 0] out_addr,
output reg new_burst_export
);
// ------------------------------
// Local parameters
// ------------------------------
localparam
OUT_BOUNDARY = MAX_OUT_LEN * NUM_SYMBOLS,
ADDR_SEL = log2ceil(OUT_BOUNDARY);
// ----------------------------------------
// Signals for wrapping support
// ----------------------------------------
reg [LEN_WIDTH - 1 : 0] remaining_len;
reg [LEN_WIDTH - 1 : 0] next_out_len;
reg [LEN_WIDTH - 1 : 0] next_rem_len;
reg [LEN_WIDTH - 1 : 0] uncompr_remaining_len;
reg new_burst;
reg uncompr_sub_burst;
reg [LEN_WIDTH - 1 : 0] next_uncompr_out_len;
reg [LEN_WIDTH - 1 : 0] next_uncompr_sub_len;
// Avoid QIS warning
wire [OUT_LEN_WIDTH - 1 : 0] max_out_length;
assign max_out_length = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0];
// ----------------------------------------
// Calculate aligned length for WRAP burst
// ----------------------------------------
reg [ADDR_WIDTH - 1 : 0] extended_burstwrap;
reg [ADDR_WIDTH - 1 : 0] extended_burstwrap_reg;
always_comb begin
extended_burstwrap = {{(ADDR_WIDTH - BNDRY_WIDTH) {in_burstwrap[BNDRY_WIDTH - 1]}}, in_burstwrap};
extended_burstwrap_reg = {{(ADDR_WIDTH - BNDRY_WIDTH) {in_burstwrap_reg[BNDRY_WIDTH - 1]}}, in_burstwrap_reg};
new_burst_export = new_burst;
end
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
// -------------------------------------------
// length calculation
// -------------------------------------------
reg [LEN_WIDTH -1 : 0] next_uncompr_remaining_len;
always_comb begin
// Signals name
// *_uncompr_* --> uncompressed transaction
// -------------------------------------------
// Always use max_out_length as possible.
// Else use the remaining length.
// If in length smaller and not cross bndry or same, pass thru.
if (in_sop) begin
uncompr_remaining_len = in_len;
end
else begin
uncompr_remaining_len = next_uncompr_remaining_len;
end
end // always_comb
// compressed transactions
always_comb begin : proc_compressed_read
remaining_len = in_len;
if (!new_burst)
remaining_len = next_rem_len;
end
always_comb begin
next_uncompr_out_len = first_len;
if (in_sop) begin
next_uncompr_out_len = first_len;
end
else begin
if (uncompr_sub_burst)
next_uncompr_out_len = next_uncompr_sub_len;
else begin
if (uncompr_remaining_len < max_out_length)
next_uncompr_out_len = uncompr_remaining_len;
else
next_uncompr_out_len = max_out_length;
end
end
end
// Compressed transaction: Always try to send MAX out_len then remaining length.
// Seperate it as the main difference is the first out len.
// For a WRAP burst, the first beat is the aligned length, then similar to INCR.
always_comb begin
if (new_burst) begin
next_out_len = first_len;
end
else begin
next_out_len = max_out_length;
if (remaining_len < max_out_length) begin
next_out_len = remaining_len;
end
end
end // always_comb
// --------------------------------------------------
// Length remaining calculation : Compressed
// --------------------------------------------------
// length remaining for compressed transaction
// for wrap, need special handling for first out length
always_ff @(posedge clk) begin
if (enable_read) begin
if (new_burst)
next_rem_len <= in_len - first_len;
else
next_rem_len <= next_rem_len - max_out_length;
end
end // always_ff @
//generate
// if (SYNC_RESET == 0) begin : async_rst1
// always_ff @(posedge clk, posedge reset) begin
// if (reset)
// next_rem_len <= 0;
// else if (enable_read) begin
// if (new_burst)
// next_rem_len <= in_len - first_len;
// else
// next_rem_len <= next_rem_len - max_out_length;
// end
// end // always_ff @
// end // async_rst1
// else begin // sync_rst1
// always_ff @(posedge clk) begin
// if (internal_sclr)
// next_rem_len <= 0;
// else if (enable_read) begin
// if (new_burst)
// next_rem_len <= in_len - first_len;
// else
// next_rem_len <= next_rem_len - max_out_length;
// end
// end // always_ff @
// end // sync_rst1
// endgenerate
// --------------------------------------------------
// Length remaining calculation : Uncompressed
// --------------------------------------------------
always_ff @(posedge clk) begin
if (enable_write) begin
if (in_sop)
next_uncompr_remaining_len <= in_len - first_len;
else if (!uncompr_sub_burst)
next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
end
end // always_ff @
// length for each sub-burst if it needs to chop the burst
always_ff @(posedge clk) begin
if (enable_write) begin
next_uncompr_sub_len <= next_uncompr_out_len - 1'b1; // in term of length, it just reduces 1
end
end
generate
if (SYNC_RESET == 0) begin : async_rst2
//always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// next_uncompr_remaining_len <= 0;
// end
// else if (enable_write) begin
// if (in_sop)
// next_uncompr_remaining_len <= in_len - first_len;
// else if (!uncompr_sub_burst)
// next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
// end
//end // always_ff @
//// length for each sub-burst if it needs to chop the burst
//always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// next_uncompr_sub_len <= 0;
// end
// else if (enable_write) begin
// next_uncompr_sub_len <= next_uncompr_out_len - 1'b1; // in term of length, it just reduces 1
// end
//end
// the sub-burst still active
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
uncompr_sub_burst <= 0;
end
else if (enable_write) begin
uncompr_sub_burst <= (next_uncompr_out_len > 1'b1);
end
end
end // async_rst1
else begin // sync_rst2
//always_ff @(posedge clk) begin
// if (internal_sclr) begin
// next_uncompr_remaining_len <= 0;
// end
// else if (enable_write) begin
// if (in_sop)
// next_uncompr_remaining_len <= in_len - first_len;
// else if (!uncompr_sub_burst)
// next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
// end
//end // always_ff @
//
//// length for each sub-burst if it needs to chop the burst
//always_ff @(posedge clk) begin
// if (internal_sclr) begin
// next_uncompr_sub_len <= 0;
// end
// else if (enable_write) begin
// next_uncompr_sub_len <= next_uncompr_out_len - 1'b1; // in term of length, it just reduces 1
// end
//end
// the sub-burst still active
always_ff @(posedge clk) begin
if (internal_sclr) begin
uncompr_sub_burst <= 0;
end
else if (enable_write) begin
uncompr_sub_burst <= (next_uncompr_out_len > 1'b1);
end
end
end // sync_rst2
endgenerate
// --------------------------------------------------
// Control signals
// --------------------------------------------------
wire end_compressed_sub_burst;
assign end_compressed_sub_burst = (remaining_len == next_out_len);
// new_burst:
// the converter takes in_len for new caculation
generate
if (SYNC_RESET == 0) begin : async_rst3
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
new_burst <= 1;
end
else if (enable_read) begin
new_burst <= end_compressed_sub_burst;
end
end
end // async_rst3
else begin // sync_rst3
always_ff @(posedge clk) begin
if (internal_sclr) begin
new_burst <= 1;
end
else if (enable_read) begin
new_burst <= end_compressed_sub_burst;
end
end
end // sync_rst3
endgenerate
// --------------------------------------------------
// Output length
// --------------------------------------------------
// register out_len for compressed trans
always_ff @(posedge clk) begin
if (enable_read) begin
out_len <= next_out_len;
end
end
//generate
// if (SYNC_RESET == 0) begin : async_rst4
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// out_len <= 0;
// end
// else if (enable_read) begin
// out_len <= next_out_len;
// end
// end
// end // async_rst4
// else begin // sync_rst4
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// out_len <= 0;
// end
// else if (enable_read) begin
// out_len <= next_out_len;
// end
// end
// end // sync_rst4
//endgenerate
// register uncompr_out_len for uncompressed trans
generate
if (OPTIMIZE_WRITE_BURST) begin : optimized_write_burst_len
always_ff @(posedge clk) begin
if (enable_read) begin
uncompr_out_len <= first_len;
end
end
//if (SYNC_RESET == 0) begin : async_rst5
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// uncompr_out_len <= '0;
// end
// //else if (enable_write) begin
// else if (enable_read) begin
// uncompr_out_len <= first_len;
// end
// end
//end // async_rst5
//else begin // sync_rst5
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// uncompr_out_len <= '0;
// end
// //else if (enable_write) begin
// else if (enable_read) begin
// uncompr_out_len <= first_len;
// end
// end
//end // sync_rst5
end
else begin : unoptimized_write_burst_len
always_ff @(posedge clk) begin
if (enable_write) begin
uncompr_out_len <= next_uncompr_out_len;
end
end
//if (SYNC_RESET == 0) begin : async_rst6
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// uncompr_out_len <= '0;
// end
// else if (enable_write) begin
// uncompr_out_len <= next_uncompr_out_len;
// end
// end
// end // async_rst6
// else begin // sync_rst6
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// uncompr_out_len <= '0;
// end
// else if (enable_write) begin
// uncompr_out_len <= next_uncompr_out_len;
// end
// end
// end // sync_rst6
end // else unoptimized
endgenerate
// --------------------------------------------------
// Address calculation
// --------------------------------------------------
reg [ADDR_WIDTH - 1 : 0] addr_incr;
localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS;
assign addr_incr = ADDR_INCR[ADDR_WIDTH - 1 : 0];
reg [ADDR_WIDTH - 1 : 0] next_out_addr;
reg [ADDR_WIDTH - 1 : 0] incremented_addr;
always_ff @(posedge clk) begin
if (enable_read) begin
out_addr <= (next_out_addr);
end
end // always_ff @
//generate
// if (SYNC_RESET == 0) begin : async_rst7
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// out_addr <= '0;
// end
// else begin
// if (enable_read) begin
// out_addr <= (next_out_addr);
// end
// end
// end // always_ff @
// end // async_rst7
// else begin // sync_rst7
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// out_addr <= '0;
// end
// else begin
// if (enable_read) begin
// out_addr <= (next_out_addr);
// end
// end
// end // always_ff @
// end // sync_rst7
// endgenerate
// use burstwrap/burstwrap_reg to calculate address incrementing
always_ff @(posedge clk) begin
if (enable_read) begin
incremented_addr <= ((next_out_addr + addr_incr) & extended_burstwrap_reg);
if (new_burst) begin
incremented_addr <= ((next_out_addr + (first_len << LOG2_NUMSYMBOLS)) & extended_burstwrap); //byte address
end
end
end // always_ff @
//generate
// if (SYNC_RESET == 0) begin : async_rst8
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// incremented_addr <= '0;
// end
// else if (enable_read) begin
// incremented_addr <= ((next_out_addr + addr_incr) & extended_burstwrap_reg);
// if (new_burst) begin
// incremented_addr <= ((next_out_addr + (first_len << LOG2_NUMSYMBOLS)) & extended_burstwrap); //byte address
// end
// end
// end // always_ff @
// end // async_rst8
// else begin // sync_rst8
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// incremented_addr <= '0;
// end
// else if (enable_read) begin
// incremented_addr <= ((next_out_addr + addr_incr) & extended_burstwrap_reg);
// if (new_burst) begin
// incremented_addr <= ((next_out_addr + (first_len << LOG2_NUMSYMBOLS)) & extended_burstwrap); //byte address
// end
// end
// end // always_ff @
// end // sync_rst8
// endgenerate
always_comb begin
next_out_addr = in_addr;
if (!new_burst) begin
next_out_addr = in_addr_reg & ~extended_burstwrap_reg | incremented_addr;
end
end
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZllKnWAX9N5dw2ADgRBGnFz2jF7qT9llBrp2SnRSqQQqPwDlEJk2UeGJPg3ES1cQXyK7KIOLJhXnkePUfQ+bKASdNX8T7B/JBvWmq4yvDwftVX9k5+DhxB4OJiOiGMqZKtpOPRfmNUafND1njfnIo2+Il2fpo21b+lm2UGn2crz+4Ezg30kTMwDWGkjPxTpP+2w7tTrZzHLDzMZ89zy8rTRiEFhl1zRMzfRBlxZEdr8KZeO1XX5rQSctBdRLCrIlqVgsWi3TEoSoxumsqHaOLlStKdjywMkU8JDDdO6voRm5WiU/LSmcDRdX/TQX9Ml2MORWtmZi32gRfAxwBnIj8Gi3bWIbi4v9r55CeoZqWe2dia2mOA6SwlKOd1EnFKwLwNrUsR2ia05vFXplhOCqXNZPp0BEo7XnkZjZ5dtrHxxGrr7g08uOjFbYbAd38T3KlaPDq41azfwlaky8agCeG50E5Vq0me3pK7xJBMr5JAACNM1tlbLvx+CtxMrVouByfc6xI/1b9Az/bxjsHy0MHAYHq4PPn5FlFDrk1iOBUD7zef+6Dy0a1pN7+YgZIw19YBJo2i9FTEcRCEt4qTdjY9z4N2KltJPRl5OFjEONQnCrTLlZcJJHzuHoW3RbnWyk6bdJ+OnsHUq+R7dIBiuetQcIcAw5nICBm106qEL6rTdp4xSX4a5uMgRvkm22XjXE1nbADFmkPKafOWwnPFon9mLQnL6a2qObBM3miUYE8VCVI/iTtB8oWJ9/SnA6EEyCHYZ6crWU3hwkln3/4RQRXw6"
`endif
qsys/qsys_top/altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv
+361
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ns / 1 ns
// -----------------------------------------------------
// Top level for the burst adapter. This selects the
// implementation for the adapter, based on the
// parameterization.
// -----------------------------------------------------
module qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy
#(
parameter
// Indicates the implementation to instantiate:
// "13.1" means the slow, inexpensive generic burst converter.
// "new" means the fast, expensive per-burst converter.
ADAPTER_VERSION = "13.1",
// Indicates if this adapter needs to support read bursts
// (almost always true).
COMPRESSED_READ_SUPPORT = 1,
// Standard Merlin packet parameters that indicate
// field position within the packet
PKT_BEGIN_BURST = 81,
PKT_ADDR_H = 79,
PKT_ADDR_L = 48,
PKT_BYTE_CNT_H = 5,
PKT_BYTE_CNT_L = 0,
PKT_BURSTWRAP_H = 11,
PKT_BURSTWRAP_L = 6,
PKT_TRANS_COMPRESSED_READ = 14,
PKT_TRANS_WRITE = 13,
PKT_TRANS_READ = 12,
PKT_BYTEEN_H = 83,
PKT_BYTEEN_L = 80,
PKT_BURST_TYPE_H = 88,
PKT_BURST_TYPE_L = 87,
PKT_BURST_SIZE_H = 86,
PKT_BURST_SIZE_L = 84,
PKT_SAI_H = 89,
PKT_SAI_L = 89,
PKT_EOP_OOO = 90,
PKT_SOP_OOO = 91,
ST_DATA_W = 92,
ST_CHANNEL_W = 8,
ROLE_BASED_USER = 0,
ENABLE_AXI5 = 0,
ENABLE_OOO = 0,
// Component-specific parameters. Explained
// in the implementation levels
IN_NARROW_SIZE = 0,
NO_WRAP_SUPPORT = 0,
INCOMPLETE_WRAP_SUPPORT = 1,
BURSTWRAP_CONST_MASK = 0,
BURSTWRAP_CONST_VALUE = 2147483647, //equivalent to {31{1'b1}} -- ncsim does not like negative values (-1), or the replication format
OUT_NARROW_SIZE = 0,
OUT_FIXED = 0,
OUT_COMPLETE_WRAP = 0,
BYTEENABLE_SYNTHESIS = 0,
PIPE_INPUTS = 0,
OUT_BYTE_CNT_H = 5,
OUT_BURSTWRAP_H = 11,
SYNC_RESET = 0
)
(
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink0_valid,
input [ST_DATA_W-1 : 0] sink0_data,
input [ST_CHANNEL_W-1 : 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output reg sink0_ready,
// -------------------
// Command Source (Output)
// -------------------
output wire source0_valid,
output wire [ST_DATA_W-1 : 0] source0_data,
output wire [ST_CHANNEL_W-1 : 0] source0_channel,
output wire source0_startofpacket,
output wire source0_endofpacket,
input source0_ready
);
localparam PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
generate if (COMPRESSED_READ_SUPPORT == 0) begin : altera_merlin_burst_adapter_uncompressed_only
// -------------------------------------------------------------------
// The reduced version of the adapter is only meant to be used on
// non-bursting wide to narrow links.
// -------------------------------------------------------------------
altera_merlin_burst_adapter_uncompressed_only #(
.PKT_BYTE_CNT_H (PKT_BYTE_CNT_H),
.PKT_BYTE_CNT_L (PKT_BYTE_CNT_L),
.PKT_BYTEEN_H (PKT_BYTEEN_H),
.PKT_BYTEEN_L (PKT_BYTEEN_L),
.ST_DATA_W (ST_DATA_W),
.ST_CHANNEL_W (ST_CHANNEL_W)
) burst_adapter (
.clk (clk),
.reset (reset),
.sink0_valid (sink0_valid),
.sink0_data (sink0_data),
.sink0_channel (sink0_channel),
.sink0_startofpacket (sink0_startofpacket),
.sink0_endofpacket (sink0_endofpacket),
.sink0_ready (sink0_ready),
.source0_valid (source0_valid),
.source0_data (source0_data),
.source0_channel (source0_channel),
.source0_startofpacket (source0_startofpacket),
.source0_endofpacket (source0_endofpacket),
.source0_ready (source0_ready)
);
end
else if (ADAPTER_VERSION == "13.1") begin : altera_merlin_burst_adapter_13_1
// -----------------------------------------------------
// This is the generic converter implementation, which attempts
// to convert all burst types with a generalized conversion
// function. This results in low area, but low fmax.
// -----------------------------------------------------
altera_merlin_burst_adapter_13_1 #(
.PKT_BEGIN_BURST (PKT_BEGIN_BURST),
.PKT_ADDR_H (PKT_ADDR_H ),
.PKT_ADDR_L (PKT_ADDR_L),
.PKT_BYTE_CNT_H (PKT_BYTE_CNT_H),
.PKT_BYTE_CNT_L (PKT_BYTE_CNT_L ),
.PKT_BURSTWRAP_H (PKT_BURSTWRAP_H),
.PKT_BURSTWRAP_L (PKT_BURSTWRAP_L),
.PKT_TRANS_COMPRESSED_READ (PKT_TRANS_COMPRESSED_READ),
.PKT_TRANS_WRITE (PKT_TRANS_WRITE),
.PKT_TRANS_READ (PKT_TRANS_READ),
.PKT_BYTEEN_H (PKT_BYTEEN_H),
.PKT_BYTEEN_L (PKT_BYTEEN_L),
.PKT_BURST_TYPE_H (PKT_BURST_TYPE_H),
.PKT_BURST_TYPE_L (PKT_BURST_TYPE_L),
.PKT_BURST_SIZE_H (PKT_BURST_SIZE_H),
.PKT_BURST_SIZE_L (PKT_BURST_SIZE_L),
.PKT_SAI_H (PKT_SAI_H),
.PKT_SAI_L (PKT_SAI_L),
.PKT_EOP_OOO (PKT_EOP_OOO),
.PKT_SOP_OOO (PKT_SOP_OOO),
.ENABLE_OOO (ENABLE_OOO),
.IN_NARROW_SIZE (IN_NARROW_SIZE),
.BYTEENABLE_SYNTHESIS (BYTEENABLE_SYNTHESIS),
.OUT_NARROW_SIZE (OUT_NARROW_SIZE),
.OUT_FIXED (OUT_FIXED),
.OUT_COMPLETE_WRAP (OUT_COMPLETE_WRAP),
.ST_DATA_W (ST_DATA_W),
.ST_CHANNEL_W (ST_CHANNEL_W),
.ROLE_BASED_USER (ROLE_BASED_USER),
.ENABLE_AXI5 (ENABLE_AXI5),
.BURSTWRAP_CONST_MASK (BURSTWRAP_CONST_MASK),
.BURSTWRAP_CONST_VALUE (BURSTWRAP_CONST_VALUE),
.PIPE_INPUTS (PIPE_INPUTS),
.NO_WRAP_SUPPORT (NO_WRAP_SUPPORT),
.OUT_BYTE_CNT_H (OUT_BYTE_CNT_H),
.OUT_BURSTWRAP_H (OUT_BURSTWRAP_H),
.SYNC_RESET (SYNC_RESET)
) burst_adapter (
.clk (clk),
.reset (reset),
.sink0_valid (sink0_valid),
.sink0_data (sink0_data),
.sink0_channel (sink0_channel),
.sink0_startofpacket (sink0_startofpacket),
.sink0_endofpacket (sink0_endofpacket),
.sink0_ready (sink0_ready),
.source0_valid (source0_valid),
.source0_data (source0_data),
.source0_channel (source0_channel),
.source0_startofpacket (source0_startofpacket),
.source0_endofpacket (source0_endofpacket),
.source0_ready (source0_ready)
);
end
else begin : altera_merlin_burst_adapter_new
wire sink0_pipe_valid;
wire [ST_DATA_W - 1 : 0] sink0_pipe_data;
wire [ST_CHANNEL_W - 1 : 0] sink0_pipe_channel;
wire sink0_pipe_sop;
wire sink0_pipe_eop;
wire sink0_pipe_ready;
// -----------------------------------------------------
// This is the per-burst-type converter implementation. This attempts
// to convert bursts with specialized functions for each burst
// type. This typically results in higher area, but higher fmax.
// -----------------------------------------------------
altera_merlin_burst_adapter_new #(
.PKT_BEGIN_BURST (PKT_BEGIN_BURST),
.PKT_ADDR_H (PKT_ADDR_H ),
.PKT_ADDR_L (PKT_ADDR_L),
.PKT_BYTE_CNT_H (PKT_BYTE_CNT_H),
.PKT_BYTE_CNT_L (PKT_BYTE_CNT_L ),
.PKT_BURSTWRAP_H (PKT_BURSTWRAP_H),
.PKT_BURSTWRAP_L (PKT_BURSTWRAP_L),
.PKT_TRANS_COMPRESSED_READ (PKT_TRANS_COMPRESSED_READ),
.PKT_TRANS_WRITE (PKT_TRANS_WRITE),
.PKT_TRANS_READ (PKT_TRANS_READ),
.PKT_BYTEEN_H (PKT_BYTEEN_H),
.PKT_BYTEEN_L (PKT_BYTEEN_L),
.PKT_BURST_TYPE_H (PKT_BURST_TYPE_H),
.PKT_BURST_TYPE_L (PKT_BURST_TYPE_L),
.PKT_BURST_SIZE_H (PKT_BURST_SIZE_H),
.PKT_BURST_SIZE_L (PKT_BURST_SIZE_L),
.PKT_SAI_H (PKT_SAI_H),
.PKT_SAI_L (PKT_SAI_L),
.PKT_EOP_OOO (PKT_EOP_OOO),
.PKT_SOP_OOO (PKT_SOP_OOO),
.ENABLE_OOO (ENABLE_OOO),
.IN_NARROW_SIZE (IN_NARROW_SIZE),
.BYTEENABLE_SYNTHESIS (BYTEENABLE_SYNTHESIS),
.OUT_NARROW_SIZE (OUT_NARROW_SIZE),
.OUT_FIXED (OUT_FIXED),
.OUT_COMPLETE_WRAP (OUT_COMPLETE_WRAP),
.ST_DATA_W (ST_DATA_W),
.ROLE_BASED_USER (ROLE_BASED_USER),
.ENABLE_AXI5 (ENABLE_AXI5),
.ST_CHANNEL_W (ST_CHANNEL_W),
.BURSTWRAP_CONST_MASK (BURSTWRAP_CONST_MASK),
.BURSTWRAP_CONST_VALUE (BURSTWRAP_CONST_VALUE),
.PIPE_INPUTS (PIPE_INPUTS),
.NO_WRAP_SUPPORT (NO_WRAP_SUPPORT),
.INCOMPLETE_WRAP_SUPPORT (INCOMPLETE_WRAP_SUPPORT),
.OUT_BYTE_CNT_H (OUT_BYTE_CNT_H),
.OUT_BURSTWRAP_H (OUT_BURSTWRAP_H),
.SYNC_RESET (SYNC_RESET)
) burst_adapter (
.clk (clk),
.reset (reset),
.sink0_valid (sink0_pipe_valid),
.sink0_data (sink0_pipe_data),
.sink0_channel (sink0_pipe_channel),
.sink0_startofpacket (sink0_pipe_sop),
.sink0_endofpacket (sink0_pipe_eop),
.sink0_ready (sink0_pipe_ready),
.source0_valid (source0_valid),
.source0_data (source0_data),
.source0_channel (source0_channel),
.source0_startofpacket (source0_startofpacket),
.source0_endofpacket (source0_endofpacket),
.source0_ready (source0_ready)
);
if(PIPE_INPUTS == 1) begin: pipe_inputs
qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di # (
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (ST_DATA_W),
.USE_PACKETS (1),
.USE_EMPTY (0),
.EMPTY_WIDTH (0),
.CHANNEL_WIDTH (ST_CHANNEL_W),
.PACKET_WIDTH (2),
.ERROR_WIDTH (0),
.PIPELINE_READY (1),
.SYNC_RESET (SYNC_RESET)
) pipe_stage (
.clk (clk),
.reset (reset),
.in_ready (sink0_ready),
.in_valid (sink0_valid),
.in_startofpacket (sink0_startofpacket),
.in_endofpacket (sink0_endofpacket),
.in_data (sink0_data),
.in_channel (sink0_channel),
.out_ready (sink0_pipe_ready),
.out_valid (sink0_pipe_valid),
.out_startofpacket (sink0_pipe_sop),
.out_endofpacket (sink0_pipe_eop),
.out_data (sink0_pipe_data),
.out_channel (sink0_pipe_channel)
);
end
else begin : no_input_pipeline
assign sink0_pipe_valid = sink0_valid;
assign sink0_pipe_data = sink0_data;
assign sink0_pipe_channel = sink0_channel;
assign sink0_pipe_sop = sink0_startofpacket;
assign sink0_pipe_eop = sink0_endofpacket;
assign sink0_ready = sink0_pipe_ready;
end
end
endgenerate
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
// synthesis translate_off
// -----------------------------------------------------
// Simulation-only check for incoming burstwrap values inconsistent with
// BURSTWRAP_CONST_MASK, which would indicate a paramerization error.
//
// Should be turned into an assertion, really.
// -----------------------------------------------------
generate
if (SYNC_RESET == 0) begin : async_rst0
always @(posedge clk or posedge reset) begin
if (reset) begin
end
else if (sink0_valid &&
BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0] &
(BURSTWRAP_CONST_VALUE[PKT_BURSTWRAP_W - 1:0] ^ sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L])
) begin
$display("%t: %m: Error: burstwrap value %X is inconsistent with BURSTWRAP_CONST_MASK value %X", $time(), sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L], BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0]);
end
end
end : async_rst0
else begin : sync_rst0
always @(posedge clk ) begin
if ((internal_sclr == 1'b0) && sink0_valid &&
BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0] &
(BURSTWRAP_CONST_VALUE[PKT_BURSTWRAP_W - 1:0] ^ sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L])
) begin
$display("%t: %m: Error: burstwrap value %X is inconsistent with BURSTWRAP_CONST_MASK value %X", $time(), sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L], BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0]);
end
end
end : sync_rst0
endgenerate
// synthesis translate_on
endmodule
qsys/qsys_top/altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v
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// qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v
// Generated using ACDS version 26.1 110
`timescale 1 ps / 1 ps
module qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di #(
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 171,
parameter USE_PACKETS = 1,
parameter USE_EMPTY = 0,
parameter EMPTY_WIDTH = 0,
parameter CHANNEL_WIDTH = 2,
parameter PACKET_WIDTH = 2,
parameter ERROR_WIDTH = 0,
parameter PIPELINE_READY = 1,
parameter SYNC_RESET = 1
) (
input wire clk, // cr0.clk, Clock input
input wire reset, // cr0_reset.reset, Reset input
output wire in_ready, // sink0.ready, Ready port of Avalon Streaming Sink Interface; indicates when sink interface is ready to receive data
input wire in_valid, // .valid, Valid data port of Avalon Streaming Sink Interface; high when input data is valid
input wire in_startofpacket, // .startofpacket, Start of packet port of Avalon Streaming Sink Interface;Indicates start of incoming packet
input wire in_endofpacket, // .endofpacket, End of packet port of Avalon Streaming Sink Interface; Indicates end of incoming packet
input wire [170:0] in_data, // .data, Input Data port of Avalon Streaming Sink Interface
input wire [1:0] in_channel, // .channel, Channel input port of Avalon Streaming Sink Interface
input wire out_ready, // source0.ready, Ready port of Avalon Streaming Source Interface; indicates to source that data can be sent
output wire out_valid, // .valid, Valid data port of Avalon Streaming Source Interface; high when output data is valid
output wire out_startofpacket, // .startofpacket, Start of packet port of Avalon Streaming Source Interface; Indicates start of outgoing packet
output wire out_endofpacket, // .endofpacket, End of packet port of Avalon Streaming Source Interface; Indicates end of outgoing packet
output wire [170:0] out_data, // .data, Output Data port of Avalon Streaming Source Interface
output wire [1:0] out_channel // .channel, Channel output port of Avalon Streaming Source Interface
);
qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq #(
.SYMBOLS_PER_BEAT (SYMBOLS_PER_BEAT),
.BITS_PER_SYMBOL (BITS_PER_SYMBOL),
.USE_PACKETS (USE_PACKETS),
.USE_EMPTY (USE_EMPTY),
.EMPTY_WIDTH (EMPTY_WIDTH),
.CHANNEL_WIDTH (CHANNEL_WIDTH),
.PACKET_WIDTH (PACKET_WIDTH),
.ERROR_WIDTH (ERROR_WIDTH),
.PIPELINE_READY (PIPELINE_READY),
.SYNC_RESET (SYNC_RESET)
) my_altera_avalon_st_pipeline_stage (
.clk (clk), // input, width = 1, cr0.clk
.reset (reset), // input, width = 1, cr0_reset.reset
.in_ready (in_ready), // output, width = 1, sink0.ready
.in_valid (in_valid), // input, width = 1, .valid
.in_startofpacket (in_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (in_endofpacket), // input, width = 1, .endofpacket
.in_data (in_data), // input, width = 171, .data
.in_channel (in_channel), // input, width = 2, .channel
.out_ready (out_ready), // input, width = 1, source0.ready
.out_valid (out_valid), // output, width = 1, .valid
.out_startofpacket (out_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (out_endofpacket), // output, width = 1, .endofpacket
.out_data (out_data), // output, width = 171, .data
.out_channel (out_channel), // output, width = 2, .channel
.in_empty (1'b0), // (terminated),
.out_empty (), // (terminated),
.out_error (), // (terminated),
.in_error (1'b0) // (terminated),
);
endmodule
qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_default_burst_converter.sv
+278
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_burst_adapter/new_source/altera_default_burst_converter.sv#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// --------------------------------------------
// Default Burst Converter
// Notes:
// 1) If burst type FIXED and slave is AXI,
// passthrough the transaction.
// 2) Else, converts burst into non-bursting
// transactions (length of 1).
// --------------------------------------------
`timescale 1 ns / 1 ns
module altera_default_burst_converter
#(
parameter PKT_BURST_TYPE_W = 2,
parameter PKT_BURSTWRAP_W = 5,
parameter PKT_ADDR_W = 12,
parameter PKT_BURST_SIZE_W = 3,
parameter IS_AXI_SLAVE = 0,
parameter LEN_W = 2,
parameter SYNC_RESET = 0
)
(
input clk,
input reset,
input enable,
input [PKT_BURST_TYPE_W - 1 : 0] in_bursttype,
input [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_reg,
input [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_value,
input [PKT_ADDR_W - 1 : 0] in_addr,
input [PKT_ADDR_W - 1 : 0] in_addr_reg,
input [LEN_W - 1 : 0] in_len,
input [PKT_BURST_SIZE_W - 1 : 0] in_size_value,
input in_is_write,
output reg [PKT_ADDR_W - 1 : 0] out_addr,
output reg [LEN_W - 1 : 0] out_len,
output reg new_burst
);
// ---------------------------------------------------
// AXI Burst Type Encoding
// ---------------------------------------------------
typedef enum bit [1:0]
{
FIXED = 2'b00,
INCR = 2'b01,
WRAP = 2'b10,
RESERVED = 2'b11
} AxiBurstType;
// -------------------------------------------
// Internal Signals
// -------------------------------------------
wire [LEN_W - 1 : 0] unit_len = {{LEN_W - 1 {1'b0}}, 1'b1};
reg [LEN_W - 1 : 0] next_len;
reg [LEN_W - 1 : 0] remaining_len;
reg [PKT_ADDR_W - 1 : 0] next_incr_addr;
reg [PKT_ADDR_W - 1 : 0] incr_wrapped_addr;
reg [PKT_ADDR_W - 1 : 0] extended_burstwrap_value;
reg [PKT_ADDR_W - 1 : 0] addr_incr_variable_size_value;
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
// -------------------------------------------
// Byte Count Converter
// -------------------------------------------
// Avalon Slave: Read/Write, the out_len is always 1 (unit_len).
// AXI Slave: Read/Write, the out_len is always the in_len (pass through) of a given cycle.
// If bursttype RESERVED, out_len is always 1 (unit_len).
generate if (IS_AXI_SLAVE == 1)
begin : axi_slave_out_len
always_ff @(posedge clk) begin
if (enable) begin
out_len <= (in_bursttype == FIXED) ? in_len : unit_len;
end
end
//if (SYNC_RESET == 0 ) begin : async_rst1
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// out_len <= {LEN_W{1'b0}};
// end
// else if (enable) begin
// out_len <= (in_bursttype == FIXED) ? in_len : unit_len;
// end
// end
//end // async_rst1
//else begin // sync_rst1
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// out_len <= {LEN_W{1'b0}};
// end
// else if (enable) begin
// out_len <= (in_bursttype == FIXED) ? in_len : unit_len;
// end
// end
//end // sync_rst1
end
else // IS_AXI_SLAVE == 0
begin : non_axi_slave_out_len
always_comb begin
out_len = unit_len;
end
end
endgenerate
always_comb begin : proc_extend_burstwrap
extended_burstwrap_value = {{(PKT_ADDR_W - PKT_BURSTWRAP_W){in_burstwrap_reg[PKT_BURSTWRAP_W - 1]}}, in_burstwrap_value};
addr_incr_variable_size_value = {{(PKT_ADDR_W - 1){1'b0}}, 1'b1} << in_size_value;
end
// -------------------------------------------
// Address Converter
// -------------------------------------------
// Write: out_addr = in_addr at every cycle (pass through).
// Read: out_addr = in_addr at every new_burst. Subsequent addresses calculated by converter.
always_ff @(posedge clk) begin
if (enable) begin
next_incr_addr <= next_incr_addr + addr_incr_variable_size_value;
if (new_burst) begin
next_incr_addr <= in_addr + addr_incr_variable_size_value;
end
out_addr <= incr_wrapped_addr;
end
end
//generate
//if (SYNC_RESET == 0) begin : async_rst2
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// next_incr_addr <= {PKT_ADDR_W{1'b0}};
// out_addr <= {PKT_ADDR_W{1'b0}};
// end
// else if (enable) begin
// next_incr_addr <= next_incr_addr + addr_incr_variable_size_value;
// if (new_burst) begin
// next_incr_addr <= in_addr + addr_incr_variable_size_value;
// end
// out_addr <= incr_wrapped_addr;
// end
// end
// end // async_rst2
// else begin // sync_rst2
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// next_incr_addr <= {PKT_ADDR_W{1'b0}};
// out_addr <= {PKT_ADDR_W{1'b0}};
// end
// else if (enable) begin
// next_incr_addr <= next_incr_addr + addr_incr_variable_size_value;
// if (new_burst) begin
// next_incr_addr <= in_addr + addr_incr_variable_size_value;
// end
// out_addr <= incr_wrapped_addr;
// end
// end
// end // sync_rst2
//endgenerate
always_comb begin
incr_wrapped_addr = in_addr;
if (!new_burst) begin
// This formula calculates addresses of WRAP bursts and works perfectly fine for other burst types too.
incr_wrapped_addr = (in_addr_reg & ~extended_burstwrap_value) | (next_incr_addr & extended_burstwrap_value);
end
end
// -------------------------------------------
// Control Signals
// -------------------------------------------
// Determine the min_len.
// 1) FIXED read to AXI slave: One-time passthrough, therefore the min_len == in_len.
// 2) FIXED write to AXI slave: min_len == 1.
// 3) FIXED read/write to Avalon slave: min_len == 1.
// 4) RESERVED read/write to AXI/Avalon slave: min_len == 1.
wire [LEN_W - 1 : 0] min_len;
generate if (IS_AXI_SLAVE == 1)
begin : axi_slave_min_len
assign min_len = (!in_is_write && (in_bursttype == FIXED)) ? in_len : unit_len;
end
else // IS_AXI_SLAVE == 0
begin : non_axi_slave_min_len
assign min_len = unit_len;
end
endgenerate
// last_beat calculation.
wire last_beat = (remaining_len == min_len);
// next_len calculation.
always_comb begin
remaining_len = in_len;
if (!new_burst) remaining_len = next_len;
end
always_ff @(posedge clk) begin
if (enable) begin
next_len <= remaining_len - unit_len;
end
end
generate
if (SYNC_RESET == 0) begin : async_rst3
//always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// next_len <= 1'b0;
// end
// else if (enable) begin
// next_len <= remaining_len - unit_len;
// end
//end
// new_burst calculation.
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
new_burst <= 1'b1;
end
else if (enable) begin
new_burst <= last_beat;
end
end
end // async_rst3
else begin // sync_rst3
//always_ff @(posedge clk) begin
// if (internal_sclr) begin
// next_len <= 1'b0;
// end
// else if (enable) begin
// next_len <= remaining_len - unit_len;
// end
//end
// new_burst calculation.
always_ff @(posedge clk) begin
if (internal_sclr) begin
new_burst <= 1'b1;
end
else if (enable) begin
new_burst <= last_beat;
end
end
end // sync_rst3
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZnXzCebnCKJTsi823h62YzED9giUrsXJJm305Cxwn/ZRLE5PqwZtvf+8ZAVJE55kNVZaV60bWlN1N0XZR9KM1WwQkKYejedngoMHZ5SvtJeJU4qT4/oQOvKek5HLy5M6ATeo0EfJB3ak4qOC206cHdjo6jQaq4jVeRzd4W9l5Hk/MsscWd3wt993nAf88yhZUaJ1/mBpRC35cYTaXNnFY84PO+FW8JiMxDjLScLm/9k8wCnKRnF0Hs5P4VIY630mFMHoKoejOV1LqpqaU/cjYNnrlSYDmB49HKeYpESgUpAw/F+kYpWqck871iv0EzYP3Z3dhwLSf70SFr5f6Z0TDE3Gr4JfN9KPx6CcPDKeGzYK+fFSJSbCsCPgEl2xC4MI7ISbMJHOcc/V7ZbFLP6r5n8kZlPYOE9L8TJoc1Vcg8UxGcxzW9pE8AgMTFCoLGmA77bKOzo4BwadS0t585NPOjoR4cRPJfC3+2qNG4cdNvwrKBS2VUO7341urJcK/l9J0S9BxiN6U+1HjmDuBCgG09cqLR8+cnmDRKpiIky8laAqXEDKzhWqlD1ganoZi7z4DWtAwMN8P+YVycreBGZgwssabwyo2LmDpP+Uitsy15PbNMCdOJfMK8bkzkIMh2N67/N3Z4HkFKETIcGtbr7Le7scupVRRszgiRj7sZNNULEGcrKiPlFzfAsmzIiqX9N0klWvUcO95LliNP8e+CZZdzfGcKxZVSLsedLYpqEWGn8MBt0cTrRUPAriDk6XjdkPIN9frlNlJ/d6l4jzxLrmAnT"
`endif
qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_incr_burst_converter.sv
+520
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@@ -0,0 +1,520 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_burst_adapter/new_source/altera_incr_burst_converter.sv#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// ----------------------------------------------------------
// This component is used for INCR Avalon slave
// (slave which only supports INCR) or AXI slave.
// It converts burst length of input packet
// to match slave burst.
// ----------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_incr_burst_converter
#(
parameter
// ----------------------------------------
// Burst length Parameters
// (real burst length value, not bytecount)
// ----------------------------------------
MAX_IN_LEN = 16,
MAX_OUT_LEN = 4,
NUM_SYMBOLS = 4,
ADDR_WIDTH = 12,
BNDRY_WIDTH = 12,
BURSTSIZE_WIDTH = 3,
IN_NARROW_SIZE = 0,
PURELY_INCR_AVL_SYS = 0,
SYNC_RESET = 0,
// ------------------
// Derived Parameters
// ------------------
LEN_WIDTH = log2ceil(MAX_IN_LEN) + 1,
OUT_LEN_WIDTH = log2ceil(MAX_OUT_LEN) + 1,
LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS)
)
(
input clk,
input reset,
input enable,
input is_write,
input [LEN_WIDTH - 1 : 0] in_len,
input in_sop,
input [ADDR_WIDTH - 1 : 0] in_addr,
input [ADDR_WIDTH - 1 : 0] in_addr_reg,
input [BNDRY_WIDTH - 1 : 0] in_burstwrap_reg,
input [BURSTSIZE_WIDTH - 1 : 0] in_size_t,
input [BURSTSIZE_WIDTH - 1 : 0] in_size_reg,
// converted output length
// out_len : compressed burst, read
// uncompressed_len: uncompressed, write
output reg [LEN_WIDTH - 1 : 0] out_len,
output reg [LEN_WIDTH - 1 : 0] uncompr_out_len,
// Compressed address output
output reg [ADDR_WIDTH - 1 : 0] out_addr,
output reg new_burst_export
);
// ----------------------------------------
// Signals for wrapping support
// ----------------------------------------
reg [LEN_WIDTH - 1 : 0] remaining_len;
reg [LEN_WIDTH - 1 : 0] next_out_len;
reg [LEN_WIDTH - 1 : 0] next_rem_len;
reg [LEN_WIDTH - 1 : 0] uncompr_remaining_len;
reg [LEN_WIDTH - 1 : 0] next_uncompr_remaining_len;
reg [LEN_WIDTH - 1 : 0] next_uncompr_rem_len;
reg new_burst;
reg uncompr_sub_burst;
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
// Avoid QIS warning
wire [OUT_LEN_WIDTH - 1 : 0] max_out_length;
assign max_out_length = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0];
always_comb begin
new_burst_export = new_burst;
end
// -------------------------------------------
// length remaining calculation
// -------------------------------------------
always_comb begin : proc_uncompressed_remaining_len
if ((in_len <= max_out_length) && is_write) begin
uncompr_remaining_len = in_len;
end else begin
uncompr_remaining_len = max_out_length;
end
if (uncompr_sub_burst)
uncompr_remaining_len = next_uncompr_rem_len;
end
always_ff @(posedge clk) begin
if (enable) begin
next_uncompr_rem_len <= uncompr_remaining_len - 1'b1; // in term of length, it just reduces 1
end
end
//generate
// if (SYNC_RESET == 0) begin : async_rst1
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// next_uncompr_rem_len <= 0;
// end
// else if (enable) begin
// next_uncompr_rem_len <= uncompr_remaining_len - 1'b1; // in term of length, it just reduces 1
// end
// end
// end // async_rst1
// else begin // sync_rst1
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// next_uncompr_rem_len <= 0;
// end
// else if (enable) begin
// next_uncompr_rem_len <= uncompr_remaining_len - 1'b1; // in term of length, it just reduces 1
// end
// end
// end // sync_rst1
//endgenerate
always_comb begin : proc_compressed_remaining_len
remaining_len = in_len;
if (!new_burst)
remaining_len = next_rem_len;
end
always_ff@(posedge clk) begin : proc_next_uncompressed_remaining_len
if (enable) begin
if (in_sop) begin
next_uncompr_remaining_len <= in_len - max_out_length;
end
else if (!uncompr_sub_burst)
next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
end
end
//generate
// if (SYNC_RESET == 0) begin : async_rst2
// always_ff@(posedge clk or posedge reset) begin : proc_next_uncompressed_remaining_len
// if(reset) begin
// next_uncompr_remaining_len <= '0;
// end
// else if (enable) begin
// if (in_sop) begin
// next_uncompr_remaining_len <= in_len - max_out_length;
// end
// else if (!uncompr_sub_burst)
// next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
// end
// end
// end // async_rst2
// else begin // sync_rst2
// always_ff@(posedge clk ) begin : proc_next_uncompressed_remaining_len
// if(internal_sclr) begin
// next_uncompr_remaining_len <= '0;
// end
// else if (enable) begin
// if (in_sop) begin
// next_uncompr_remaining_len <= in_len - max_out_length;
// end
// else if (!uncompr_sub_burst)
// next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
// end
// end
// end // sync_rst2
//endgenerate
always_comb begin
next_out_len = max_out_length;
if (remaining_len < max_out_length) begin
next_out_len = remaining_len;
end
end // always_comb
// --------------------------------------------------
// Length remaining calculation : compressed
// --------------------------------------------------
// length remaining for compressed transaction
// for wrap, need special handling for first out length
always_ff @(posedge clk) begin
if (enable) begin
if (new_burst)
next_rem_len <= in_len - max_out_length;
else
next_rem_len <= next_rem_len - max_out_length;
end
end
generate
if (SYNC_RESET == 0) begin: async_rst3
//always_ff @(posedge clk, posedge reset) begin
// if (reset)
// next_rem_len <= 0;
// else if (enable) begin
// if (new_burst)
// next_rem_len <= in_len - max_out_length;
// else
// next_rem_len <= next_rem_len - max_out_length;
// end
//end
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
uncompr_sub_burst <= 0;
end
else if (enable && is_write) begin
uncompr_sub_burst <= (uncompr_remaining_len > 1'b1);
end
end
end // async_rst3
else begin // sync_rst3
//always_ff @(posedge clk) begin
// if (internal_sclr)
// next_rem_len <= 0;
// else if (enable) begin
// if (new_burst)
// next_rem_len <= in_len - max_out_length;
// else
// next_rem_len <= next_rem_len - max_out_length;
// end
//end
always_ff @(posedge clk) begin
if (internal_sclr) begin
uncompr_sub_burst <= 0;
end
else if (enable && is_write) begin
uncompr_sub_burst <= (uncompr_remaining_len > 1'b1);
end
end
end // sync_rst3
endgenerate
// --------------------------------------------------
// Control signals
// --------------------------------------------------
wire end_compressed_sub_burst;
assign end_compressed_sub_burst = (remaining_len == next_out_len);
// new_burst:
// the converter takes in_len for new calculation
generate
if (SYNC_RESET == 0) begin : async_rst4
always_ff @(posedge clk, posedge reset) begin
if (reset)
new_burst <= 1;
else if (enable)
new_burst <= end_compressed_sub_burst;
end
end // async_rst4
else begin // sync_rst4
always_ff @(posedge clk) begin
if (internal_sclr)
new_burst <= 1;
else if (enable)
new_burst <= end_compressed_sub_burst;
end
end
endgenerate
// --------------------------------------------------
// Output length
// --------------------------------------------------
// register out_len for compressed trans
always_ff @(posedge clk) begin
if (enable) begin
out_len <= next_out_len;
end
end
// register uncompr_out_len for uncompressed trans
always_ff @(posedge clk) begin
if (enable) begin
uncompr_out_len <= uncompr_remaining_len;
end
end
//generate
// if (SYNC_RESET == 0) begin : async_rst5
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// out_len <= 0;
// end
// else if (enable) begin
// out_len <= next_out_len;
// end
// end
// // register uncompr_out_len for uncompressed trans
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// uncompr_out_len <= '0;
// end
// else if (enable) begin
// uncompr_out_len <= uncompr_remaining_len;
// end
// end
//end // async_rst5
//else begin // sync_rst5
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// out_len <= 0;
// end
// else if (enable) begin
// out_len <= next_out_len;
// end
// end
// // register uncompr_out_len for uncompressed trans
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// uncompr_out_len <= '0;
// end
// else if (enable) begin
// uncompr_out_len <= uncompr_remaining_len;
// end
// end
//end //sync_rst5
//endgenerate
// --------------------------------------------------
// Address Calculation
// --------------------------------------------------
reg [ADDR_WIDTH - 1 : 0] addr_incr_sel;
reg [ADDR_WIDTH - 1 : 0] addr_incr_sel_reg;
reg [ADDR_WIDTH - 1 : 0] addr_incr_full_size;
localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS;
generate
if (IN_NARROW_SIZE) begin : narrow_addr_incr
reg [ADDR_WIDTH - 1 : 0] addr_incr_variable_size;
reg [ADDR_WIDTH - 1 : 0] addr_incr_variable_size_reg;
assign addr_incr_variable_size = MAX_OUT_LEN << in_size_t;
assign addr_incr_variable_size_reg = MAX_OUT_LEN << in_size_reg;
assign addr_incr_sel = addr_incr_variable_size;
assign addr_incr_sel_reg = addr_incr_variable_size_reg;
end
else begin : full_addr_incr
assign addr_incr_full_size = ADDR_INCR[ADDR_WIDTH - 1 : 0];
assign addr_incr_sel = addr_incr_full_size;
assign addr_incr_sel_reg = addr_incr_full_size;
end
endgenerate
reg [ADDR_WIDTH - 1 : 0] next_out_addr;
reg [ADDR_WIDTH - 1 : 0] incremented_addr;
always_ff @(posedge clk) begin
if (enable) begin
out_addr <= (next_out_addr);
end
end
//generate
// if (SYNC_RESET == 0) begin : async_rst6
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// out_addr <= '0;
// end else begin
// if (enable) begin
// out_addr <= (next_out_addr);
// end
// end
// end
// end // async_rst6
// else begin // sync_rst6
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// out_addr <= '0;
// end else begin
// if (enable) begin
// out_addr <= (next_out_addr);
// end
// end
// end
// end // sync_rst6
// endgenerate
generate
if (!PURELY_INCR_AVL_SYS) begin : incremented_addr_normal
always_ff @(posedge clk) begin
if (enable) begin
if (new_burst) begin
incremented_addr <= (next_out_addr + addr_incr_sel);
end
else begin
incremented_addr <= (next_out_addr + addr_incr_sel_reg);
end
end
end // always_ff @
//if (SYNC_RESET == 0) begin : async_rst7
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// incremented_addr <= '0;
// end
// else if (enable) begin
// incremented_addr <= (next_out_addr + addr_incr_sel_reg);
// if (new_burst) begin
// incremented_addr <= (next_out_addr + addr_incr_sel);
// end
// end
// end // always_ff @
//end // async_rst7
//else begin // sync_rst7
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// incremented_addr <= '0;
// end
// else if (enable) begin
// incremented_addr <= (next_out_addr + addr_incr_sel_reg);
// if (new_burst) begin
// incremented_addr <= (next_out_addr + addr_incr_sel);
// end
// end
// end // always_ff @
//end // sync_rst7
always_comb begin
next_out_addr = in_addr;
if (!new_burst) begin
next_out_addr = incremented_addr;
end
end
end
else begin : incremented_addr_pure_av
always_ff @(posedge clk) begin
if (enable) begin
incremented_addr <= (next_out_addr + addr_incr_sel_reg);
end
end // always_ff @
//if (SYNC_RESET == 0) begin : async_rst8
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// incremented_addr <= '0;
// end
// else if (enable) begin
// incremented_addr <= (next_out_addr + addr_incr_sel_reg);
// end
// end // always_ff @
//end // async_rst8
//else begin // sync_rst8
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// incremented_addr <= '0;
// end
// else if (enable) begin
// incremented_addr <= (next_out_addr + addr_incr_sel_reg);
// end
// end // always_ff @
// end // sync_rst8
always_comb begin
next_out_addr = in_addr;
if (!new_burst) begin
next_out_addr = (incremented_addr);
end
end
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZm2VnW9Jup+rO8tHn46ia+m1jd1lvf4qalDbWMpZ7/iR078F3NbXmSfszSWG0PYb1O/+IcoZgGEBa4thPbK141luDnU00je40S0l+dVi8sQRSkZ06QX7VOV1HZ58TwdhajcQDrYTBrJ/wnghIvibweYzsQp21UeRH1tHdQb9EX/90LIxErNs9qZn6FdE/wU7Nnk0BApTSHa5j7Oq6whWnvIJLoY+NDfNdmguQ5c5E6FNiZBIhwP/gOXHb/Xm2fDPcMvXcyokY7FuDYoM8BdoUJ+OVZhbg6kE3dGqlFzZ60/+I5AYaHj1YtiTy6zGO1WlQnC9Sov4dHl/nkN231hsVmVVehUnm0X9f6djXsXUCx2V4JBRqjfGugv+XBeZ7HMoK6LH9u4KSTlqLlNrvhPX1VXe6UjwtOzHxYGUWqvESIeNAxWo/4NsdiISuU7Ut75o/3SMGjSlAM7UYSVvfIKi5vhCIKKXWh8sv0pKKrscZmZZ/OnnKio2r2xi88/64nRWpeQLYbzJvOmzzD5662ckE9n2faDKveVDFd+hpDfzkxyJ1LcqlVbHGqIMMAyPaTibmi0MV3Rd4tFFycrgcfYSW2I2CZTl8Rl/mstykAJ+vOi233Cy2RN1EviSi9EtnimDziOtUfW0sHScrdN1sEWY0xL2HM3oZBGMXvTOYwRGqobo4r/v6rfvRDKjzYBDzylQrvPRTibwXUKTDizbO7CXOL30RYfG/EAFhOqWFZBz89zBGyL8kCGAD5mh8/7pcdM1Y52JOHLbDLceUAQRV+5n0po"
`endif
qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_address_alignment.sv
+305
View File
@@ -0,0 +1,305 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_axi_master_ni/address_alignment.sv#3 $
// $Revision: #3 $
// $Date: 2012/07/11 $
//-----------------------------------------
// Address alignment:
// This component will aglin input address with input size
// Support address increment with butst type and burstwrap value
//-----------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_address_alignment
#(
parameter
ADDR_W = 12,
BURSTWRAP_W = 12,
TYPE_W = 2,
SIZE_W = 3,
INCREMENT_ADDRESS = 1,
NUMSYMBOLS = 8,
SELECT_BITS = log2(NUMSYMBOLS),
IN_DATA_W = ADDR_W + (BURSTWRAP_W-1) + TYPE_W + SIZE_W,
OUT_DATA_W = ADDR_W + SELECT_BITS,
SYNC_RESET = 0
)
(
input clk,
input reset,
input [IN_DATA_W-1:0] in_data, // in_data = {wrap_boundary, address, type, size}
input in_valid,
//output in_ready,
input in_sop,
input in_eop,
output reg [OUT_DATA_W-1:0] out_data,
input out_ready
//output out_valid
);
typedef enum bit [1:0]
{
FIXED = 2'b00,
INCR = 2'b01,
WRAP = 2'b10,
RESERVED = 2'b11
} AxiBurstType;
//----------------------------------------------------
// AXSIZE decoding
//
// Turns the axsize value into the actual number of bytes
// being transferred.
// ---------------------------------------------------
function reg[9:0] bytes_in_transfer;
input [SIZE_W-1:0] axsize;
case (axsize)
4'b0000: bytes_in_transfer = 10'b0000000001;
4'b0001: bytes_in_transfer = 10'b0000000010;
4'b0010: bytes_in_transfer = 10'b0000000100;
4'b0011: bytes_in_transfer = 10'b0000001000;
4'b0100: bytes_in_transfer = 10'b0000010000;
4'b0101: bytes_in_transfer = 10'b0000100000;
4'b0110: bytes_in_transfer = 10'b0001000000;
4'b0111: bytes_in_transfer = 10'b0010000000;
4'b1000: bytes_in_transfer = 10'b0100000000;
4'b1001: bytes_in_transfer = 10'b1000000000;
default: bytes_in_transfer = 10'b0000000001;
endcase
endfunction
//--------------------------------------
// Burst type decode
//--------------------------------------
AxiBurstType write_burst_type;
function AxiBurstType burst_type_decode
(
input [1:0] axburst
);
AxiBurstType burst_type;
begin
case (axburst)
2'b00 : burst_type = FIXED;
2'b01 : burst_type = INCR;
2'b10 : burst_type = WRAP;
2'b11 : burst_type = RESERVED;
default : burst_type = INCR;
endcase
return burst_type;
end
endfunction
//----------------------------------------------------
// Ubiquitous, familiar log2 function
//----------------------------------------------------
function integer log2;
input integer value;
value = value - 1;
for(log2 = 0; value > 0; log2 = log2 + 1)
value = value >> 1;
endfunction
//------------------------------------------------------------------------
// This component will read address and size and check
// if this is aligned or not. If not then it will align this address to the size
// of the transfer:
// Check alignment:
// - With data width, can define maximun how many lower bits of address to indicate this
// address align to the size
// - Ex: 32 bits data => size can be: 1, 2, 4 bytes
// For 4 bytes: when 2 lower bits of address equal 0, this is aligned address
// addr=00|00| (0), 01|00| (4) => align to size of 4 bytes
// addr=00|01| (1) => start addr at 1, is not aligned to size 4 byte
// For 2 bytes: use last one bit to indicate algined or not
// addr=000|0| (0), 001|0| (2) => align to size of 2 bytes
// addr=000|1| (1), 001|1| (3) => not align to 2 bytes
// As size runtime change, creat mask and change accordingly to size, can detect address alignment
// and to align to size, apply this mask with zero to the address.
//-------------------------------------------------------------------------
// THe function return a vector which has width [(SELECT_BITS * 2) -1 : 0]
// in which the first part contains the mask to check if this address aligned or not
// second part contains the mast to mask address to align to size
function reg[(SELECT_BITS*2)-1 : 0] mask_select_and_align_address;
input [ADDR_W-1:0] address;
input [SIZE_W-1:0] size; // size is in AXI coding: 001 -> 2 bytes
integer i;
reg [SELECT_BITS-1:0] mask_address;
reg [SELECT_BITS-1:0] check_unaligned; // any bits =1 -> unalgined (except size = 0; 1 byte)
mask_address = '1;
check_unaligned = '0;
for(i = 0; i < SELECT_BITS ; i = i + 1) begin
if (i < size) begin
check_unaligned[i] = address[i];
mask_address[i] = 1'b0;
end
end
mask_select_and_align_address = {check_unaligned,mask_address};
endfunction
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= ~reset;
end
end
endgenerate
reg [ADDR_W-1 : 0] in_address;
reg [ADDR_W-1 : 0] first_address_aligned;
reg [SIZE_W-1 : 0] in_size;
reg [(SELECT_BITS*2)-1 : 0] output_masks;
// Extract information from input data
assign in_address = in_data[SIZE_W+ADDR_W-1 : SIZE_W];
assign in_size = in_data[SIZE_W-1 : 0];
// Generate the masks
always_comb
begin
output_masks = mask_select_and_align_address(in_address, in_size);
end
// Align address if needed
generate
// SELECT_BITS == 1: input packet has 1 NUMSYMBOLS (1 bytes), it is aligned
if (SELECT_BITS == 0)
assign first_address_aligned = in_address;
else begin
// SELECT_BITS ==1 :input packet 2 bytes (2 SYMBOLS)
wire [SELECT_BITS-1 : 0] aligned_address_bits;
if (SELECT_BITS == 1)
assign aligned_address_bits = in_address[0] & output_masks[0];
else
assign aligned_address_bits = in_address[SELECT_BITS-1:0] & output_masks[SELECT_BITS-1:0];
assign first_address_aligned = {in_address[ADDR_W-1 : SELECT_BITS], aligned_address_bits};
end
endgenerate
// Increment address base on size, first address keep the same
generate
if (INCREMENT_ADDRESS)
begin
reg [ADDR_W-1 : 0] increment_address;
reg [ADDR_W-1 : 0] out_aligned_address_burst;
reg [ADDR_W-1 : 0] address_burst;
reg [ADDR_W-1 : 0] base_address;
reg [9 : 0] number_bytes_transfer;
reg [ADDR_W-1 : 0] burstwrap_mask;
reg [ADDR_W-1 : 0] burst_address_high;
reg [ADDR_W-1 : 0] burst_address_low;
reg [BURSTWRAP_W-2 :0] in_burstwrap_boundary;
reg [TYPE_W-1 : 0] in_type;
//------------------------------------------------
// Use the extended burstwrap value to split the high (constant) and
// low (changing) part of the address
//-----------------------------------------------
assign in_type = in_data[SIZE_W+ADDR_W+TYPE_W-1 : SIZE_W+ADDR_W];
assign in_burstwrap_boundary = in_data[IN_DATA_W-1 : ADDR_W+TYPE_W+SIZE_W];
assign burstwrap_mask = {{(ADDR_W - BURSTWRAP_W){1'b0}}, in_burstwrap_boundary};
assign burst_address_high = out_aligned_address_burst & ~burstwrap_mask;
assign burst_address_low = out_aligned_address_burst;
assign number_bytes_transfer = bytes_in_transfer(in_size);
assign write_burst_type = burst_type_decode(in_type);
always @*
begin
if (in_sop)
begin
out_aligned_address_burst = in_address;
base_address = first_address_aligned;
end
else
begin
out_aligned_address_burst = address_burst;
base_address = out_aligned_address_burst;
end
case (write_burst_type)
INCR:
increment_address = base_address + number_bytes_transfer;
WRAP:
increment_address = ((burst_address_low + number_bytes_transfer) & burstwrap_mask) | burst_address_high;
FIXED:
increment_address = out_aligned_address_burst;
default:
increment_address = base_address + number_bytes_transfer;
endcase // case (write_burst_type)
end // always @ *
if (SYNC_RESET == 0) begin : async_rst0
always_ff @(posedge clk, negedge reset)
begin
if (!reset)
begin
address_burst <= '0;
end
else
begin
if (in_valid & out_ready)
address_burst <= increment_address;
end
end
end : async_rst0
else begin : sync_rst0
always_ff @(posedge clk)
begin
if (internal_sclr)
begin
address_burst <= '0;
end
else
begin
if (in_valid & out_ready)
address_burst <= increment_address;
end
end
end : sync_rst0
// send data to output with 2 part: [mask_t0_algin][address_aligned_increment]
// corner case when SELECT_BITS==0 - total bits in
// [SELECTS_BITS-1:0] ==> 1-:0 ==> 2 bits in total
// leads to warning
if (SELECT_BITS==0)
assign out_data = out_aligned_address_burst;
else
assign out_data = {output_masks[SELECT_BITS-1 : 0], out_aligned_address_burst};
end // if (INCREMENT_ADDRESS)
else
begin
// corner case when SELECT_BITS==0 - total bits in
// [SELECTS_BITS-1:0] ==> 1-:0 ==> 2 bits in total
// leads to warning
if (SELECT_BITS==0)
assign out_data = first_address_aligned;
else
assign out_data = {output_masks[SELECT_BITS-1 : 0], first_address_aligned};
end // else: !if(INCREMENT_ADDRESS)
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZnuSxX8yXxnIFVWsgCk75Z0P+dtbDvmJdtQl1WjW4yFuhoOU6T348GM/xUHtJ4nzM+Ie8UNgnT16AXfoOSoZ6aw4EqtmutAt1g0WrS8Zo7lntdL4Ed4jMhrdzQ2wGXcukpdBXSOlxyVkCs8O5Bx5bsJHA8kY1r+dEjpFU6yRXbht/crFehVXoHCjTTZnCo6ONciQai4cPqisPuj4rwOI0P18Yry6OKgj6AYn8jpBhuXzb8sDJ3t4lulV43YetVoYKIdiLdg9MNtOudp0cdO7C9wiNkMhIPLI2VLiAgdsxlTZo0H7/klMzcS7oMYhgKBYj3rMGfIF8GIfjTv7DXR06ED3LZScux5eFxq7qC9RRhgCFd2O/5OwjkezW2Fe1fos97+/4c0SVIufbIeAiMRsYmglnEcMCPwWnhbxi/B4Q/YpYAH96gY/+ITpxiLlp7H+Wot7TKsR10cNB8FfVYrKfDgFm3aAGBtmVsUAz3X31S6DJdo/eXRPthu3tfuBI4BAB2tQptyaBZIqDMWE/TeUinC41fvbEAe/N84+in0g3XgKSMRshfZ8yKNB5HICw0eV/rxJsVyCdWVsaafsz31CT1ij2Mvr1H7LbAUmPVt546kJCR7d/o6inwycxcb5G7r8r7du8eigB4sXm3QEMQTpHFX0PXZW0KnyL4Dml+CXK43oRj2wIP58dXUWPsi8nphSGr64d8Zt0FlS2NO2Y0jv3ecZkOIjZu+9pPoWGxFSdPY/fBYS18Q736mwIEkGiruEglqw3eKurFsVAnQNbb/cn/1"
`endif
qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_13_1.sv
+1536
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File diff suppressed because it is too large Load Diff
qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_new.sv
+2293
View File
File diff suppressed because it is too large Load Diff
qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_uncmpr.sv
+96
View File
@@ -0,0 +1,96 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter.sv#68 $
// $Revision: #68 $
// $Date: 2014/01/23 $
`timescale 1 ns / 1 ns
// -------------------------------------------------------
// Adapter for uncompressed transactions only. This adapter will
// typically be used to adapt burst length for non-bursting
// wide to narrow Avalon links.
// -------------------------------------------------------
module altera_merlin_burst_adapter_uncompressed_only
#(
parameter
PKT_BYTE_CNT_H = 5,
PKT_BYTE_CNT_L = 0,
PKT_BYTEEN_H = 83,
PKT_BYTEEN_L = 80,
ST_DATA_W = 84,
ST_CHANNEL_W = 8
)
(
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink0_valid,
input [ST_DATA_W-1 : 0] sink0_data,
input [ST_CHANNEL_W-1 : 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output reg sink0_ready,
// -------------------
// Command Source (Output)
// -------------------
output reg source0_valid,
output reg [ST_DATA_W-1 : 0] source0_data,
output reg [ST_CHANNEL_W-1 : 0] source0_channel,
output reg source0_startofpacket,
output reg source0_endofpacket,
input source0_ready
);
localparam
PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
NUM_SYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
wire [PKT_BYTE_CNT_W - 1 : 0] num_symbols_sig = NUM_SYMBOLS[PKT_BYTE_CNT_W - 1 : 0];
always_comb begin : source0_data_assignments
source0_valid = sink0_valid;
source0_channel = sink0_channel;
source0_startofpacket = sink0_startofpacket;
source0_endofpacket = sink0_endofpacket;
source0_data = sink0_data;
source0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = num_symbols_sig;
sink0_ready = source0_ready;
end
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZlEl7U1mwDa2foPMdSqYqEvxrVPv0jMzxA0aRf5GvKemQQYiAUmoPZ/yty49qVq2u4nCWeBwiIOIWm7gDC9G7PUqb6tQOwrlINch7TSLyDBSTQRE9hXc7SldcwRHZbphJdXk8dLtmihOMDJFCjqPdl3yLIyPr7YL6350GrMmyAi0VBnzeb3PXYeJ774WH1+ABTda662GekklRXGy8DtIgPk0IIg3Oj1dwRb3pFTN66nlIPiZBgL8gjO0CYauPX/q9nMQFGeoQZr4+5e98MGAqbEcnhgooJzrOeQs2tRxgUiChvubqPONnP1A1YFtubOn7CcIC2RelzTbXvuG7xBL8BFrgyCRg/DB4902JDspTPYHKTGnATpyW9IaQ1niNwNhdHAEqiIUKBD/YZXcjnXVgHmwCUait0N//YwiEJonwrRzUsNWzXI1Hqd95q5Iyv88LJIqRopX6GB7QDDG42Z8rlNeHcFQnyJKEV5BhNCL8p3A8ygXqZ6pjUDwYOR+Dgarpg9ij6TIXQQHiiEozYHxBY0fcHtNb8FfenfODkF3XaHFzJciEYDrjHK2q3Ns7fTAp+HkmKgxb/S/s3qrHnpl3GVY+nokliANaXmDBgv4PGyFDfOm5ZifW3H7XSXvHNPSnpKxGuEoZt2v0zN2gZIcCaS5smLpTK+Lh0uks2gCvA/v1P41pbHzy/7CM/JZiP8V8q0zQ0ELX/oWMYwC/t43xkpbirj8nuULPIQPAupetsXyCnaz2p2/DdsSsbGj3kyXN8JLoZV990Dl5M4UL/HzKhw"
`endif
qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_wrap_burst_converter.sv
+545
View File
@@ -0,0 +1,545 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_burst_adapter/new_source/altera_wrap_burst_converter.sv#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// ------------------------------------------------------
// This component is specially for Wrapping Avalon slave.
// It converts burst length of input packet
// to match slave burst.
// ------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_wrap_burst_converter
#(
parameter
// ----------------------------------------
// Burst length Parameters
// (real burst length value, not bytecount)
// ----------------------------------------
MAX_IN_LEN = 16,
MAX_OUT_LEN = 4,
ADDR_WIDTH = 12,
BNDRY_WIDTH = 12,
NUM_SYMBOLS = 4,
AXI_SLAVE = 0,
OPTIMIZE_WRITE_BURST = 0,
SYNC_RESET = 0,
// ------------------
// Derived Parameters
// ------------------
LEN_WIDTH = log2ceil(MAX_IN_LEN) + 1,
OUT_LEN_WIDTH = log2ceil(MAX_OUT_LEN) + 1,
LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS)
)
(
input clk,
input reset,
input enable_write,
input enable_read,
input [LEN_WIDTH - 1 : 0] in_len,
input [LEN_WIDTH - 1 : 0] first_len,
input in_sop,
input [ADDR_WIDTH - 1 : 0] in_addr,
input [ADDR_WIDTH - 1 : 0] in_addr_reg,
input [BNDRY_WIDTH - 1 : 0] in_boundary,
input [BNDRY_WIDTH - 1 : 0] in_burstwrap,
input [BNDRY_WIDTH - 1 : 0] in_burstwrap_reg,
// converted output length
// out_len : compressed burst, read
// uncompressed_len: uncompressed, write
output reg [LEN_WIDTH - 1 : 0] out_len,
output reg [LEN_WIDTH - 1 : 0] uncompr_out_len,
// Compressed address output
output reg [ADDR_WIDTH - 1 : 0] out_addr,
output reg new_burst_export
);
// ------------------------------
// Local parameters
// ------------------------------
localparam
OUT_BOUNDARY = MAX_OUT_LEN * NUM_SYMBOLS,
ADDR_SEL = log2ceil(OUT_BOUNDARY);
// ----------------------------------------
// Signals for wrapping support
// ----------------------------------------
reg [LEN_WIDTH - 1 : 0] remaining_len;
reg [LEN_WIDTH - 1 : 0] next_out_len;
reg [LEN_WIDTH - 1 : 0] next_rem_len;
reg [LEN_WIDTH - 1 : 0] uncompr_remaining_len;
reg new_burst;
reg uncompr_sub_burst;
reg [LEN_WIDTH - 1 : 0] next_uncompr_out_len;
reg [LEN_WIDTH - 1 : 0] next_uncompr_sub_len;
// Avoid QIS warning
wire [OUT_LEN_WIDTH - 1 : 0] max_out_length;
assign max_out_length = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0];
// ----------------------------------------
// Calculate aligned length for WRAP burst
// ----------------------------------------
reg [ADDR_WIDTH - 1 : 0] extended_burstwrap;
reg [ADDR_WIDTH - 1 : 0] extended_burstwrap_reg;
always_comb begin
extended_burstwrap = {{(ADDR_WIDTH - BNDRY_WIDTH) {in_burstwrap[BNDRY_WIDTH - 1]}}, in_burstwrap};
extended_burstwrap_reg = {{(ADDR_WIDTH - BNDRY_WIDTH) {in_burstwrap_reg[BNDRY_WIDTH - 1]}}, in_burstwrap_reg};
new_burst_export = new_burst;
end
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
// -------------------------------------------
// length calculation
// -------------------------------------------
reg [LEN_WIDTH -1 : 0] next_uncompr_remaining_len;
always_comb begin
// Signals name
// *_uncompr_* --> uncompressed transaction
// -------------------------------------------
// Always use max_out_length as possible.
// Else use the remaining length.
// If in length smaller and not cross bndry or same, pass thru.
if (in_sop) begin
uncompr_remaining_len = in_len;
end
else begin
uncompr_remaining_len = next_uncompr_remaining_len;
end
end // always_comb
// compressed transactions
always_comb begin : proc_compressed_read
remaining_len = in_len;
if (!new_burst)
remaining_len = next_rem_len;
end
always_comb begin
next_uncompr_out_len = first_len;
if (in_sop) begin
next_uncompr_out_len = first_len;
end
else begin
if (uncompr_sub_burst)
next_uncompr_out_len = next_uncompr_sub_len;
else begin
if (uncompr_remaining_len < max_out_length)
next_uncompr_out_len = uncompr_remaining_len;
else
next_uncompr_out_len = max_out_length;
end
end
end
// Compressed transaction: Always try to send MAX out_len then remaining length.
// Seperate it as the main difference is the first out len.
// For a WRAP burst, the first beat is the aligned length, then similar to INCR.
always_comb begin
if (new_burst) begin
next_out_len = first_len;
end
else begin
next_out_len = max_out_length;
if (remaining_len < max_out_length) begin
next_out_len = remaining_len;
end
end
end // always_comb
// --------------------------------------------------
// Length remaining calculation : Compressed
// --------------------------------------------------
// length remaining for compressed transaction
// for wrap, need special handling for first out length
always_ff @(posedge clk) begin
if (enable_read) begin
if (new_burst)
next_rem_len <= in_len - first_len;
else
next_rem_len <= next_rem_len - max_out_length;
end
end // always_ff @
//generate
// if (SYNC_RESET == 0) begin : async_rst1
// always_ff @(posedge clk, posedge reset) begin
// if (reset)
// next_rem_len <= 0;
// else if (enable_read) begin
// if (new_burst)
// next_rem_len <= in_len - first_len;
// else
// next_rem_len <= next_rem_len - max_out_length;
// end
// end // always_ff @
// end // async_rst1
// else begin // sync_rst1
// always_ff @(posedge clk) begin
// if (internal_sclr)
// next_rem_len <= 0;
// else if (enable_read) begin
// if (new_burst)
// next_rem_len <= in_len - first_len;
// else
// next_rem_len <= next_rem_len - max_out_length;
// end
// end // always_ff @
// end // sync_rst1
// endgenerate
// --------------------------------------------------
// Length remaining calculation : Uncompressed
// --------------------------------------------------
always_ff @(posedge clk) begin
if (enable_write) begin
if (in_sop)
next_uncompr_remaining_len <= in_len - first_len;
else if (!uncompr_sub_burst)
next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
end
end // always_ff @
// length for each sub-burst if it needs to chop the burst
always_ff @(posedge clk) begin
if (enable_write) begin
next_uncompr_sub_len <= next_uncompr_out_len - 1'b1; // in term of length, it just reduces 1
end
end
generate
if (SYNC_RESET == 0) begin : async_rst2
//always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// next_uncompr_remaining_len <= 0;
// end
// else if (enable_write) begin
// if (in_sop)
// next_uncompr_remaining_len <= in_len - first_len;
// else if (!uncompr_sub_burst)
// next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
// end
//end // always_ff @
//// length for each sub-burst if it needs to chop the burst
//always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// next_uncompr_sub_len <= 0;
// end
// else if (enable_write) begin
// next_uncompr_sub_len <= next_uncompr_out_len - 1'b1; // in term of length, it just reduces 1
// end
//end
// the sub-burst still active
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
uncompr_sub_burst <= 0;
end
else if (enable_write) begin
uncompr_sub_burst <= (next_uncompr_out_len > 1'b1);
end
end
end // async_rst1
else begin // sync_rst2
//always_ff @(posedge clk) begin
// if (internal_sclr) begin
// next_uncompr_remaining_len <= 0;
// end
// else if (enable_write) begin
// if (in_sop)
// next_uncompr_remaining_len <= in_len - first_len;
// else if (!uncompr_sub_burst)
// next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
// end
//end // always_ff @
//
//// length for each sub-burst if it needs to chop the burst
//always_ff @(posedge clk) begin
// if (internal_sclr) begin
// next_uncompr_sub_len <= 0;
// end
// else if (enable_write) begin
// next_uncompr_sub_len <= next_uncompr_out_len - 1'b1; // in term of length, it just reduces 1
// end
//end
// the sub-burst still active
always_ff @(posedge clk) begin
if (internal_sclr) begin
uncompr_sub_burst <= 0;
end
else if (enable_write) begin
uncompr_sub_burst <= (next_uncompr_out_len > 1'b1);
end
end
end // sync_rst2
endgenerate
// --------------------------------------------------
// Control signals
// --------------------------------------------------
wire end_compressed_sub_burst;
assign end_compressed_sub_burst = (remaining_len == next_out_len);
// new_burst:
// the converter takes in_len for new caculation
generate
if (SYNC_RESET == 0) begin : async_rst3
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
new_burst <= 1;
end
else if (enable_read) begin
new_burst <= end_compressed_sub_burst;
end
end
end // async_rst3
else begin // sync_rst3
always_ff @(posedge clk) begin
if (internal_sclr) begin
new_burst <= 1;
end
else if (enable_read) begin
new_burst <= end_compressed_sub_burst;
end
end
end // sync_rst3
endgenerate
// --------------------------------------------------
// Output length
// --------------------------------------------------
// register out_len for compressed trans
always_ff @(posedge clk) begin
if (enable_read) begin
out_len <= next_out_len;
end
end
//generate
// if (SYNC_RESET == 0) begin : async_rst4
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// out_len <= 0;
// end
// else if (enable_read) begin
// out_len <= next_out_len;
// end
// end
// end // async_rst4
// else begin // sync_rst4
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// out_len <= 0;
// end
// else if (enable_read) begin
// out_len <= next_out_len;
// end
// end
// end // sync_rst4
//endgenerate
// register uncompr_out_len for uncompressed trans
generate
if (OPTIMIZE_WRITE_BURST) begin : optimized_write_burst_len
always_ff @(posedge clk) begin
if (enable_read) begin
uncompr_out_len <= first_len;
end
end
//if (SYNC_RESET == 0) begin : async_rst5
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// uncompr_out_len <= '0;
// end
// //else if (enable_write) begin
// else if (enable_read) begin
// uncompr_out_len <= first_len;
// end
// end
//end // async_rst5
//else begin // sync_rst5
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// uncompr_out_len <= '0;
// end
// //else if (enable_write) begin
// else if (enable_read) begin
// uncompr_out_len <= first_len;
// end
// end
//end // sync_rst5
end
else begin : unoptimized_write_burst_len
always_ff @(posedge clk) begin
if (enable_write) begin
uncompr_out_len <= next_uncompr_out_len;
end
end
//if (SYNC_RESET == 0) begin : async_rst6
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// uncompr_out_len <= '0;
// end
// else if (enable_write) begin
// uncompr_out_len <= next_uncompr_out_len;
// end
// end
// end // async_rst6
// else begin // sync_rst6
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// uncompr_out_len <= '0;
// end
// else if (enable_write) begin
// uncompr_out_len <= next_uncompr_out_len;
// end
// end
// end // sync_rst6
end // else unoptimized
endgenerate
// --------------------------------------------------
// Address calculation
// --------------------------------------------------
reg [ADDR_WIDTH - 1 : 0] addr_incr;
localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS;
assign addr_incr = ADDR_INCR[ADDR_WIDTH - 1 : 0];
reg [ADDR_WIDTH - 1 : 0] next_out_addr;
reg [ADDR_WIDTH - 1 : 0] incremented_addr;
always_ff @(posedge clk) begin
if (enable_read) begin
out_addr <= (next_out_addr);
end
end // always_ff @
//generate
// if (SYNC_RESET == 0) begin : async_rst7
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// out_addr <= '0;
// end
// else begin
// if (enable_read) begin
// out_addr <= (next_out_addr);
// end
// end
// end // always_ff @
// end // async_rst7
// else begin // sync_rst7
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// out_addr <= '0;
// end
// else begin
// if (enable_read) begin
// out_addr <= (next_out_addr);
// end
// end
// end // always_ff @
// end // sync_rst7
// endgenerate
// use burstwrap/burstwrap_reg to calculate address incrementing
always_ff @(posedge clk) begin
if (enable_read) begin
incremented_addr <= ((next_out_addr + addr_incr) & extended_burstwrap_reg);
if (new_burst) begin
incremented_addr <= ((next_out_addr + (first_len << LOG2_NUMSYMBOLS)) & extended_burstwrap); //byte address
end
end
end // always_ff @
//generate
// if (SYNC_RESET == 0) begin : async_rst8
// always_ff @(posedge clk, posedge reset) begin
// if (reset) begin
// incremented_addr <= '0;
// end
// else if (enable_read) begin
// incremented_addr <= ((next_out_addr + addr_incr) & extended_burstwrap_reg);
// if (new_burst) begin
// incremented_addr <= ((next_out_addr + (first_len << LOG2_NUMSYMBOLS)) & extended_burstwrap); //byte address
// end
// end
// end // always_ff @
// end // async_rst8
// else begin // sync_rst8
// always_ff @(posedge clk) begin
// if (internal_sclr) begin
// incremented_addr <= '0;
// end
// else if (enable_read) begin
// incremented_addr <= ((next_out_addr + addr_incr) & extended_burstwrap_reg);
// if (new_burst) begin
// incremented_addr <= ((next_out_addr + (first_len << LOG2_NUMSYMBOLS)) & extended_burstwrap); //byte address
// end
// end
// end // always_ff @
// end // sync_rst8
// endgenerate
always_comb begin
next_out_addr = in_addr;
if (!new_burst) begin
next_out_addr = in_addr_reg & ~extended_burstwrap_reg | incremented_addr;
end
end
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZllKnWAX9N5dw2ADgRBGnFz2jF7qT9llBrp2SnRSqQQqPwDlEJk2UeGJPg3ES1cQXyK7KIOLJhXnkePUfQ+bKASdNX8T7B/JBvWmq4yvDwftVX9k5+DhxB4OJiOiGMqZKtpOPRfmNUafND1njfnIo2+Il2fpo21b+lm2UGn2crz+4Ezg30kTMwDWGkjPxTpP+2w7tTrZzHLDzMZ89zy8rTRiEFhl1zRMzfRBlxZEdr8KZeO1XX5rQSctBdRLCrIlqVgsWi3TEoSoxumsqHaOLlStKdjywMkU8JDDdO6voRm5WiU/LSmcDRdX/TQX9Ml2MORWtmZi32gRfAxwBnIj8Gi3bWIbi4v9r55CeoZqWe2dia2mOA6SwlKOd1EnFKwLwNrUsR2ia05vFXplhOCqXNZPp0BEo7XnkZjZ5dtrHxxGrr7g08uOjFbYbAd38T3KlaPDq41azfwlaky8agCeG50E5Vq0me3pK7xJBMr5JAACNM1tlbLvx+CtxMrVouByfc6xI/1b9Az/bxjsHy0MHAYHq4PPn5FlFDrk1iOBUD7zef+6Dy0a1pN7+YgZIw19YBJo2i9FTEcRCEt4qTdjY9z4N2KltJPRl5OFjEONQnCrTLlZcJJHzuHoW3RbnWyk6bdJ+OnsHUq+R7dIBiuetQcIcAw5nICBm106qEL6rTdp4xSX4a5uMgRvkm22XjXE1nbADFmkPKafOWwnPFon9mLQnL6a2qObBM3miUYE8VCVI/iTtB8oWJ9/SnA6EEyCHYZ6crWU3hwkln3/4RQRXw6"
`endif
qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv
+361
View File
@@ -0,0 +1,361 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ns / 1 ns
// -----------------------------------------------------
// Top level for the burst adapter. This selects the
// implementation for the adapter, based on the
// parameterization.
// -----------------------------------------------------
module qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy
#(
parameter
// Indicates the implementation to instantiate:
// "13.1" means the slow, inexpensive generic burst converter.
// "new" means the fast, expensive per-burst converter.
ADAPTER_VERSION = "13.1",
// Indicates if this adapter needs to support read bursts
// (almost always true).
COMPRESSED_READ_SUPPORT = 1,
// Standard Merlin packet parameters that indicate
// field position within the packet
PKT_BEGIN_BURST = 81,
PKT_ADDR_H = 79,
PKT_ADDR_L = 48,
PKT_BYTE_CNT_H = 5,
PKT_BYTE_CNT_L = 0,
PKT_BURSTWRAP_H = 11,
PKT_BURSTWRAP_L = 6,
PKT_TRANS_COMPRESSED_READ = 14,
PKT_TRANS_WRITE = 13,
PKT_TRANS_READ = 12,
PKT_BYTEEN_H = 83,
PKT_BYTEEN_L = 80,
PKT_BURST_TYPE_H = 88,
PKT_BURST_TYPE_L = 87,
PKT_BURST_SIZE_H = 86,
PKT_BURST_SIZE_L = 84,
PKT_SAI_H = 89,
PKT_SAI_L = 89,
PKT_EOP_OOO = 90,
PKT_SOP_OOO = 91,
ST_DATA_W = 92,
ST_CHANNEL_W = 8,
ROLE_BASED_USER = 0,
ENABLE_AXI5 = 0,
ENABLE_OOO = 0,
// Component-specific parameters. Explained
// in the implementation levels
IN_NARROW_SIZE = 0,
NO_WRAP_SUPPORT = 0,
INCOMPLETE_WRAP_SUPPORT = 1,
BURSTWRAP_CONST_MASK = 0,
BURSTWRAP_CONST_VALUE = 2147483647, //equivalent to {31{1'b1}} -- ncsim does not like negative values (-1), or the replication format
OUT_NARROW_SIZE = 0,
OUT_FIXED = 0,
OUT_COMPLETE_WRAP = 0,
BYTEENABLE_SYNTHESIS = 0,
PIPE_INPUTS = 0,
OUT_BYTE_CNT_H = 5,
OUT_BURSTWRAP_H = 11,
SYNC_RESET = 0
)
(
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink0_valid,
input [ST_DATA_W-1 : 0] sink0_data,
input [ST_CHANNEL_W-1 : 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output reg sink0_ready,
// -------------------
// Command Source (Output)
// -------------------
output wire source0_valid,
output wire [ST_DATA_W-1 : 0] source0_data,
output wire [ST_CHANNEL_W-1 : 0] source0_channel,
output wire source0_startofpacket,
output wire source0_endofpacket,
input source0_ready
);
localparam PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
generate if (COMPRESSED_READ_SUPPORT == 0) begin : altera_merlin_burst_adapter_uncompressed_only
// -------------------------------------------------------------------
// The reduced version of the adapter is only meant to be used on
// non-bursting wide to narrow links.
// -------------------------------------------------------------------
altera_merlin_burst_adapter_uncompressed_only #(
.PKT_BYTE_CNT_H (PKT_BYTE_CNT_H),
.PKT_BYTE_CNT_L (PKT_BYTE_CNT_L),
.PKT_BYTEEN_H (PKT_BYTEEN_H),
.PKT_BYTEEN_L (PKT_BYTEEN_L),
.ST_DATA_W (ST_DATA_W),
.ST_CHANNEL_W (ST_CHANNEL_W)
) burst_adapter (
.clk (clk),
.reset (reset),
.sink0_valid (sink0_valid),
.sink0_data (sink0_data),
.sink0_channel (sink0_channel),
.sink0_startofpacket (sink0_startofpacket),
.sink0_endofpacket (sink0_endofpacket),
.sink0_ready (sink0_ready),
.source0_valid (source0_valid),
.source0_data (source0_data),
.source0_channel (source0_channel),
.source0_startofpacket (source0_startofpacket),
.source0_endofpacket (source0_endofpacket),
.source0_ready (source0_ready)
);
end
else if (ADAPTER_VERSION == "13.1") begin : altera_merlin_burst_adapter_13_1
// -----------------------------------------------------
// This is the generic converter implementation, which attempts
// to convert all burst types with a generalized conversion
// function. This results in low area, but low fmax.
// -----------------------------------------------------
altera_merlin_burst_adapter_13_1 #(
.PKT_BEGIN_BURST (PKT_BEGIN_BURST),
.PKT_ADDR_H (PKT_ADDR_H ),
.PKT_ADDR_L (PKT_ADDR_L),
.PKT_BYTE_CNT_H (PKT_BYTE_CNT_H),
.PKT_BYTE_CNT_L (PKT_BYTE_CNT_L ),
.PKT_BURSTWRAP_H (PKT_BURSTWRAP_H),
.PKT_BURSTWRAP_L (PKT_BURSTWRAP_L),
.PKT_TRANS_COMPRESSED_READ (PKT_TRANS_COMPRESSED_READ),
.PKT_TRANS_WRITE (PKT_TRANS_WRITE),
.PKT_TRANS_READ (PKT_TRANS_READ),
.PKT_BYTEEN_H (PKT_BYTEEN_H),
.PKT_BYTEEN_L (PKT_BYTEEN_L),
.PKT_BURST_TYPE_H (PKT_BURST_TYPE_H),
.PKT_BURST_TYPE_L (PKT_BURST_TYPE_L),
.PKT_BURST_SIZE_H (PKT_BURST_SIZE_H),
.PKT_BURST_SIZE_L (PKT_BURST_SIZE_L),
.PKT_SAI_H (PKT_SAI_H),
.PKT_SAI_L (PKT_SAI_L),
.PKT_EOP_OOO (PKT_EOP_OOO),
.PKT_SOP_OOO (PKT_SOP_OOO),
.ENABLE_OOO (ENABLE_OOO),
.IN_NARROW_SIZE (IN_NARROW_SIZE),
.BYTEENABLE_SYNTHESIS (BYTEENABLE_SYNTHESIS),
.OUT_NARROW_SIZE (OUT_NARROW_SIZE),
.OUT_FIXED (OUT_FIXED),
.OUT_COMPLETE_WRAP (OUT_COMPLETE_WRAP),
.ST_DATA_W (ST_DATA_W),
.ST_CHANNEL_W (ST_CHANNEL_W),
.ROLE_BASED_USER (ROLE_BASED_USER),
.ENABLE_AXI5 (ENABLE_AXI5),
.BURSTWRAP_CONST_MASK (BURSTWRAP_CONST_MASK),
.BURSTWRAP_CONST_VALUE (BURSTWRAP_CONST_VALUE),
.PIPE_INPUTS (PIPE_INPUTS),
.NO_WRAP_SUPPORT (NO_WRAP_SUPPORT),
.OUT_BYTE_CNT_H (OUT_BYTE_CNT_H),
.OUT_BURSTWRAP_H (OUT_BURSTWRAP_H),
.SYNC_RESET (SYNC_RESET)
) burst_adapter (
.clk (clk),
.reset (reset),
.sink0_valid (sink0_valid),
.sink0_data (sink0_data),
.sink0_channel (sink0_channel),
.sink0_startofpacket (sink0_startofpacket),
.sink0_endofpacket (sink0_endofpacket),
.sink0_ready (sink0_ready),
.source0_valid (source0_valid),
.source0_data (source0_data),
.source0_channel (source0_channel),
.source0_startofpacket (source0_startofpacket),
.source0_endofpacket (source0_endofpacket),
.source0_ready (source0_ready)
);
end
else begin : altera_merlin_burst_adapter_new
wire sink0_pipe_valid;
wire [ST_DATA_W - 1 : 0] sink0_pipe_data;
wire [ST_CHANNEL_W - 1 : 0] sink0_pipe_channel;
wire sink0_pipe_sop;
wire sink0_pipe_eop;
wire sink0_pipe_ready;
// -----------------------------------------------------
// This is the per-burst-type converter implementation. This attempts
// to convert bursts with specialized functions for each burst
// type. This typically results in higher area, but higher fmax.
// -----------------------------------------------------
altera_merlin_burst_adapter_new #(
.PKT_BEGIN_BURST (PKT_BEGIN_BURST),
.PKT_ADDR_H (PKT_ADDR_H ),
.PKT_ADDR_L (PKT_ADDR_L),
.PKT_BYTE_CNT_H (PKT_BYTE_CNT_H),
.PKT_BYTE_CNT_L (PKT_BYTE_CNT_L ),
.PKT_BURSTWRAP_H (PKT_BURSTWRAP_H),
.PKT_BURSTWRAP_L (PKT_BURSTWRAP_L),
.PKT_TRANS_COMPRESSED_READ (PKT_TRANS_COMPRESSED_READ),
.PKT_TRANS_WRITE (PKT_TRANS_WRITE),
.PKT_TRANS_READ (PKT_TRANS_READ),
.PKT_BYTEEN_H (PKT_BYTEEN_H),
.PKT_BYTEEN_L (PKT_BYTEEN_L),
.PKT_BURST_TYPE_H (PKT_BURST_TYPE_H),
.PKT_BURST_TYPE_L (PKT_BURST_TYPE_L),
.PKT_BURST_SIZE_H (PKT_BURST_SIZE_H),
.PKT_BURST_SIZE_L (PKT_BURST_SIZE_L),
.PKT_SAI_H (PKT_SAI_H),
.PKT_SAI_L (PKT_SAI_L),
.PKT_EOP_OOO (PKT_EOP_OOO),
.PKT_SOP_OOO (PKT_SOP_OOO),
.ENABLE_OOO (ENABLE_OOO),
.IN_NARROW_SIZE (IN_NARROW_SIZE),
.BYTEENABLE_SYNTHESIS (BYTEENABLE_SYNTHESIS),
.OUT_NARROW_SIZE (OUT_NARROW_SIZE),
.OUT_FIXED (OUT_FIXED),
.OUT_COMPLETE_WRAP (OUT_COMPLETE_WRAP),
.ST_DATA_W (ST_DATA_W),
.ROLE_BASED_USER (ROLE_BASED_USER),
.ENABLE_AXI5 (ENABLE_AXI5),
.ST_CHANNEL_W (ST_CHANNEL_W),
.BURSTWRAP_CONST_MASK (BURSTWRAP_CONST_MASK),
.BURSTWRAP_CONST_VALUE (BURSTWRAP_CONST_VALUE),
.PIPE_INPUTS (PIPE_INPUTS),
.NO_WRAP_SUPPORT (NO_WRAP_SUPPORT),
.INCOMPLETE_WRAP_SUPPORT (INCOMPLETE_WRAP_SUPPORT),
.OUT_BYTE_CNT_H (OUT_BYTE_CNT_H),
.OUT_BURSTWRAP_H (OUT_BURSTWRAP_H),
.SYNC_RESET (SYNC_RESET)
) burst_adapter (
.clk (clk),
.reset (reset),
.sink0_valid (sink0_pipe_valid),
.sink0_data (sink0_pipe_data),
.sink0_channel (sink0_pipe_channel),
.sink0_startofpacket (sink0_pipe_sop),
.sink0_endofpacket (sink0_pipe_eop),
.sink0_ready (sink0_pipe_ready),
.source0_valid (source0_valid),
.source0_data (source0_data),
.source0_channel (source0_channel),
.source0_startofpacket (source0_startofpacket),
.source0_endofpacket (source0_endofpacket),
.source0_ready (source0_ready)
);
if(PIPE_INPUTS == 1) begin: pipe_inputs
qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di # (
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (ST_DATA_W),
.USE_PACKETS (1),
.USE_EMPTY (0),
.EMPTY_WIDTH (0),
.CHANNEL_WIDTH (ST_CHANNEL_W),
.PACKET_WIDTH (2),
.ERROR_WIDTH (0),
.PIPELINE_READY (1),
.SYNC_RESET (SYNC_RESET)
) pipe_stage (
.clk (clk),
.reset (reset),
.in_ready (sink0_ready),
.in_valid (sink0_valid),
.in_startofpacket (sink0_startofpacket),
.in_endofpacket (sink0_endofpacket),
.in_data (sink0_data),
.in_channel (sink0_channel),
.out_ready (sink0_pipe_ready),
.out_valid (sink0_pipe_valid),
.out_startofpacket (sink0_pipe_sop),
.out_endofpacket (sink0_pipe_eop),
.out_data (sink0_pipe_data),
.out_channel (sink0_pipe_channel)
);
end
else begin : no_input_pipeline
assign sink0_pipe_valid = sink0_valid;
assign sink0_pipe_data = sink0_data;
assign sink0_pipe_channel = sink0_channel;
assign sink0_pipe_sop = sink0_startofpacket;
assign sink0_pipe_eop = sink0_endofpacket;
assign sink0_ready = sink0_pipe_ready;
end
end
endgenerate
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
// synthesis translate_off
// -----------------------------------------------------
// Simulation-only check for incoming burstwrap values inconsistent with
// BURSTWRAP_CONST_MASK, which would indicate a paramerization error.
//
// Should be turned into an assertion, really.
// -----------------------------------------------------
generate
if (SYNC_RESET == 0) begin : async_rst0
always @(posedge clk or posedge reset) begin
if (reset) begin
end
else if (sink0_valid &&
BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0] &
(BURSTWRAP_CONST_VALUE[PKT_BURSTWRAP_W - 1:0] ^ sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L])
) begin
$display("%t: %m: Error: burstwrap value %X is inconsistent with BURSTWRAP_CONST_MASK value %X", $time(), sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L], BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0]);
end
end
end : async_rst0
else begin : sync_rst0
always @(posedge clk ) begin
if ((internal_sclr == 1'b0) && sink0_valid &&
BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0] &
(BURSTWRAP_CONST_VALUE[PKT_BURSTWRAP_W - 1:0] ^ sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L])
) begin
$display("%t: %m: Error: burstwrap value %X is inconsistent with BURSTWRAP_CONST_MASK value %X", $time(), sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L], BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0]);
end
end
end : sync_rst0
endgenerate
// synthesis translate_on
endmodule
qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v
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// qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v
// Generated using ACDS version 26.1 110
`timescale 1 ps / 1 ps
module qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di #(
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 171,
parameter USE_PACKETS = 1,
parameter USE_EMPTY = 0,
parameter EMPTY_WIDTH = 0,
parameter CHANNEL_WIDTH = 2,
parameter PACKET_WIDTH = 2,
parameter ERROR_WIDTH = 0,
parameter PIPELINE_READY = 1,
parameter SYNC_RESET = 1
) (
input wire clk, // cr0.clk, Clock input
input wire reset, // cr0_reset.reset, Reset input
output wire in_ready, // sink0.ready, Ready port of Avalon Streaming Sink Interface; indicates when sink interface is ready to receive data
input wire in_valid, // .valid, Valid data port of Avalon Streaming Sink Interface; high when input data is valid
input wire in_startofpacket, // .startofpacket, Start of packet port of Avalon Streaming Sink Interface;Indicates start of incoming packet
input wire in_endofpacket, // .endofpacket, End of packet port of Avalon Streaming Sink Interface; Indicates end of incoming packet
input wire [170:0] in_data, // .data, Input Data port of Avalon Streaming Sink Interface
input wire [1:0] in_channel, // .channel, Channel input port of Avalon Streaming Sink Interface
input wire out_ready, // source0.ready, Ready port of Avalon Streaming Source Interface; indicates to source that data can be sent
output wire out_valid, // .valid, Valid data port of Avalon Streaming Source Interface; high when output data is valid
output wire out_startofpacket, // .startofpacket, Start of packet port of Avalon Streaming Source Interface; Indicates start of outgoing packet
output wire out_endofpacket, // .endofpacket, End of packet port of Avalon Streaming Source Interface; Indicates end of outgoing packet
output wire [170:0] out_data, // .data, Output Data port of Avalon Streaming Source Interface
output wire [1:0] out_channel // .channel, Channel output port of Avalon Streaming Source Interface
);
qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq #(
.SYMBOLS_PER_BEAT (SYMBOLS_PER_BEAT),
.BITS_PER_SYMBOL (BITS_PER_SYMBOL),
.USE_PACKETS (USE_PACKETS),
.USE_EMPTY (USE_EMPTY),
.EMPTY_WIDTH (EMPTY_WIDTH),
.CHANNEL_WIDTH (CHANNEL_WIDTH),
.PACKET_WIDTH (PACKET_WIDTH),
.ERROR_WIDTH (ERROR_WIDTH),
.PIPELINE_READY (PIPELINE_READY),
.SYNC_RESET (SYNC_RESET)
) my_altera_avalon_st_pipeline_stage (
.clk (clk), // input, width = 1, cr0.clk
.reset (reset), // input, width = 1, cr0_reset.reset
.in_ready (in_ready), // output, width = 1, sink0.ready
.in_valid (in_valid), // input, width = 1, .valid
.in_startofpacket (in_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (in_endofpacket), // input, width = 1, .endofpacket
.in_data (in_data), // input, width = 171, .data
.in_channel (in_channel), // input, width = 2, .channel
.out_ready (out_ready), // input, width = 1, source0.ready
.out_valid (out_valid), // output, width = 1, .valid
.out_startofpacket (out_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (out_endofpacket), // output, width = 1, .endofpacket
.out_data (out_data), // output, width = 171, .data
.out_channel (out_channel), // output, width = 2, .channel
.in_empty (1'b0), // (terminated),
.out_empty (), // (terminated),
.out_error (), // (terminated),
.in_error (1'b0) // (terminated),
);
endmodule
qsys/qsys_top/altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -------------------------------------
// Merlin Demultiplexer
//
// Asserts valid on the appropriate output
// given a one-hot channel signal.
// -------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
// ST_DATA_W: 171
// ST_CHANNEL_W: 2
// NUM_OUTPUTS: 1
// VALID_WIDTH: 1
// ------------------------------------------
//------------------------------------------
// Message Supression Used
// QIS Warnings
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
//------------------------------------------
// altera message_off 16753
module qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [171-1 : 0] sink_data, // ST_DATA_W=171
input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [171-1 : 0] src0_data, // ST_DATA_W=171
output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule
qsys/qsys_top/altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -------------------------------------
// Merlin Demultiplexer
//
// Asserts valid on the appropriate output
// given a one-hot channel signal.
// -------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: qsys_top_altera_merlin_demultiplexer_1921_qyizksq
// ST_DATA_W: 171
// ST_CHANNEL_W: 2
// NUM_OUTPUTS: 2
// VALID_WIDTH: 1
// ------------------------------------------
//------------------------------------------
// Message Supression Used
// QIS Warnings
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
//------------------------------------------
// altera message_off 16753
module qsys_top_altera_merlin_demultiplexer_1921_qyizksq
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [171-1 : 0] sink_data, // ST_DATA_W=171
input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [171-1 : 0] src0_data, // ST_DATA_W=171
output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [171-1 : 0] src1_data, // ST_DATA_W=171
output reg [2-1 : 0] src1_channel, // ST_CHANNEL_W=2
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule
qsys/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -------------------------------------
// Merlin Demultiplexer
//
// Asserts valid on the appropriate output
// given a one-hot channel signal.
// -------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
// ST_DATA_W: 171
// ST_CHANNEL_W: 2
// NUM_OUTPUTS: 1
// VALID_WIDTH: 1
// ------------------------------------------
//------------------------------------------
// Message Supression Used
// QIS Warnings
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
//------------------------------------------
// altera message_off 16753
module qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [171-1 : 0] sink_data, // ST_DATA_W=171
input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [171-1 : 0] src0_data, // ST_DATA_W=171
output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule
qsys/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -------------------------------------
// Merlin Demultiplexer
//
// Asserts valid on the appropriate output
// given a one-hot channel signal.
// -------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: qsys_top_altera_merlin_demultiplexer_1921_qyizksq
// ST_DATA_W: 171
// ST_CHANNEL_W: 2
// NUM_OUTPUTS: 2
// VALID_WIDTH: 1
// ------------------------------------------
//------------------------------------------
// Message Supression Used
// QIS Warnings
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
//------------------------------------------
// altera message_off 16753
module qsys_top_altera_merlin_demultiplexer_1921_qyizksq
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [171-1 : 0] sink_data, // ST_DATA_W=171
input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [171-1 : 0] src0_data, // ST_DATA_W=171
output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [171-1 : 0] src1_data, // ST_DATA_W=171
output reg [2-1 : 0] src1_channel, // ST_CHANNEL_W=2
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule
qsys/qsys_top/altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
// $Revision: #3 $
// $Date: 2010/07/07 $
/* -----------------------------------------------------------------------
Round-robin/fixed arbitration implementation.
Q: how do you find the least-significant set-bit in an n-bit binary number, X?
A: M = X & (~X + 1)
Example: X = 101000100
101000100 &
010111011 + 1 =
101000100 &
010111100 =
-----------
000000100
The method can be generalized to find the first set-bit
at a bit index no lower than bit-index N, simply by adding
2**N rather than 1.
Q: how does this relate to round-robin arbitration?
A:
Let X be the concatenation of all request signals.
Let the number to be added to X (hereafter called the
top_priority) initialize to 1, and be assigned from the
concatenation of the previous saved-grant, left-rotated
by one position, each time arbitration occurs. The
concatenation of grants is then M.
Problem: consider this case:
top_priority = 010000
request = 001001
~request + top_priority = 000110
next_grant = 000000 <- no one is granted!
There was no "set bit at a bit index no lower than bit-index 4", so
the result was 0.
We need to propagate the carry out from (~request + top_priority) to the LSB, so
that the sum becomes 000111, and next_grant is 000001. This operation could be
called a "circular add".
A bit of experimentation on the circular add reveals a significant amount of
delay in exiting and re-entering the carry chain - this will vary with device
family. Quartus also reports a combinational loop warning. Finally,
Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But
Modelsim _doesn't_ report a combinational loop!)
An alternate solution: concatenate the request vector with itself, and OR
corresponding bits from the top and bottom halves to determine next_grant.
Example:
top_priority = 010000
{request, request} = 001001 001001
{~request, ~request} + top_priority = 110111 000110
result of & operation = 000001 000000
next_grant = 000001
Notice that if request = 0, the sum operation will overflow, but we can ignore
this; the next_grant result is 0 (no one granted), as you might expect.
In the implementation, the last-granted value must be maintained as
a non-zero value - best probably simply not to update it when no requests
occur.
----------------------------------------------------------------------- */
`timescale 1 ns / 1 ns
module altera_merlin_arbitrator
#(
parameter NUM_REQUESTERS = 8,
// --------------------------------------
// Implemented schemes
// "round-robin"
// "fixed-priority"
// "no-arb"
// --------------------------------------
parameter SCHEME = "round-robin",
parameter PIPELINE = 0,
parameter SYNC_RESET = 0
)
(
input clk,
input reset,
// --------------------------------------
// Requests
// --------------------------------------
input [NUM_REQUESTERS-1:0] request,
// --------------------------------------
// Grants
// --------------------------------------
output [NUM_REQUESTERS-1:0] grant,
// --------------------------------------
// Control Signals
// --------------------------------------
input increment_top_priority,
input save_top_priority
);
// --------------------------------------
// Signals
// --------------------------------------
wire [NUM_REQUESTERS-1:0] top_priority;
reg [NUM_REQUESTERS-1:0] top_priority_reg;
reg [NUM_REQUESTERS-1:0] last_grant;
wire [2*NUM_REQUESTERS-1:0] result;
// --------------------------------------
// Scheme Selection
// --------------------------------------
generate
if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
assign top_priority = top_priority_reg;
end
else begin
// Fixed arbitration (or single-requester corner case)
assign top_priority = 1'b1;
end
endgenerate
// --------------------------------------
// Decision Logic
// --------------------------------------
altera_merlin_arb_adder
#(
.WIDTH (2 * NUM_REQUESTERS)
)
adder
(
.a ({ ~request, ~request }),
.b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
.sum (result)
);
generate if (SCHEME == "no-arb") begin
// --------------------------------------
// No arbitration: just wire request directly to grant
// --------------------------------------
assign grant = request;
end else begin
// Do the math in double-vector domain
wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
assign grant_double_vector = {request, request} & result;
// --------------------------------------
// Extract grant from the top and bottom halves
// of the double vector.
// --------------------------------------
assign grant =
grant_double_vector[NUM_REQUESTERS - 1 : 0] |
grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
end
endgenerate
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
// --------------------------------------
// Left-rotate the last grant vector to create top_priority.
// --------------------------------------
generate
if (SYNC_RESET == 0) begin : async_rst0
always @(posedge clk or posedge reset) begin
if (reset) begin
top_priority_reg <= 1'b1;
end
else begin
if (PIPELINE) begin
if (increment_top_priority) begin
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1]} : top_priority_reg;
end
end else begin
if (increment_top_priority) begin
if (|request)
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1] };
else
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
end
else if (save_top_priority) begin
top_priority_reg <= grant;
end
end
end
end
end : async_rst0
else begin : sync_rst0
always @(posedge clk) begin
if (internal_sclr) begin
top_priority_reg <= 1'b1;
end
else begin
if (PIPELINE) begin
if (increment_top_priority) begin
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1]} : top_priority_reg;
end
end else begin
if (increment_top_priority) begin
if (|request)
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1] };
else
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
end
else if (save_top_priority) begin
top_priority_reg <= grant;
end
end
end
end
end : sync_rst0
endgenerate
endmodule
// ----------------------------------------------
// Adder for the standard arbitrator
// ----------------------------------------------
module altera_merlin_arb_adder
#(
parameter WIDTH = 8
)
(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [WIDTH-1:0] sum
);
wire [WIDTH:0] sum_lint;
// ----------------------------------------------
// Benchmarks indicate that for small widths, the full
// adder has higher fmax because synthesis can merge
// it with the mux, allowing partial decisions to be
// made early.
//
// The magic number is 4 requesters, which means an
// 8 bit adder.
// ----------------------------------------------
genvar i;
generate if (WIDTH <= 8) begin : full_adder
wire cout[WIDTH-1:0];
assign sum[0] = (a[0] ^ b[0]);
assign cout[0] = (a[0] & b[0]);
for (i = 1; i < WIDTH; i = i+1) begin : arb
assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
end
end else begin : carry_chain
assign sum_lint = a + b;
assign sum = sum_lint[WIDTH-1:0];
end
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZksjE5n06Mr0l/mBb60LrSgvPpMlNZxUqD9txpIj9hsezCwdfrrBRPOQT+QES/Nm3nommPpmIP8JAWSJX80lL83RGMKvGdWsS0ob3gO+7su5fOK9OUtmaVpnjnoiW1RorD6TGvfnjxd1duZAHt8lhP9BHlNFN099Msvu0Y2zdsWuLxA3YjCI3uRFf3UoZ37za/sca50uYkldtw82BfyKa8kz3RCprWyI4U91BNA6cwaffNaD/aWR+AFLyipXcmdpYo3Io0ytZJpq3pdedrEWsRXJqeDkpymOtDAF+VwTkJpMvSItOuEV1RpKs4u0S/fMiOBt4sPMBDxfVWmKWprM1wDuKjmuZZEcpSfp6AvwKZFHVKiACSojJG8vUyy3+tViHjyAxJ+5yeswhU6/FCKMR6xc4j5fyKZeRQQ8mRvXjehudvtOAc21ct9OrhtO1p8v5CPsKpTzOhScA3oGxPYdYG2jAtCEbtlnPEFfO+2TAtakrU3lwCZjvjwY3I0/DQj41lVp72CukLsr/q0GIuLl3o7A9jNb3rQsmnzfq8DyiJ28CAbLkxfpfEf8gfWV9bh5rSW5bWWXgjDEsuoTyfv3tTGQHfnMss1BWigGG7XfonCmncvg2nIZsLuAACqKfpfvH3lG8dmbwWw+691yoh8WgiQIlG/sbNwu4y/ly8l6B+lWnDzVrKE34TapwYhOeHGb7RKRotkQGOM2uRkDQ5wUx+t/ZO0Ty2wY7IHRGLPLjG1irHxZPHQ+b4yJ2bsPoHnaHTOyMvBXsm6oiciFOz6NdR2"
`endif
qsys/qsys_top/altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv
+339
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// ------------------------------------------
// Merlin Multiplexer
// ------------------------------------------
// altera message_off 13448
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: qsys_top_altera_merlin_multiplexer_1922_666s25q
// NUM_INPUTS: 2
// ARBITRATION_SHARES: 1 1
// ARBITRATION_SCHEME "round-robin"
// PIPELINE_ARB: 1
// PKT_TRANS_LOCK: 69 (arbitration locking enabled)
// ST_DATA_W: 171
// ST_CHANNEL_W: 2
// ------------------------------------------
module qsys_top_altera_merlin_multiplexer_1922_666s25q
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [171-1 : 0] sink0_data,
input [2-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [171-1 : 0] sink1_data,
input [2-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output reg src_valid,
output [171-1 : 0] src_data,
output [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 171 + 2 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 171;
localparam ST_CHANNEL_W = 2;
localparam PKT_TRANS_LOCK = 69;
localparam SYNC_RESET = 1;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
reg internal_sclr;
always @(posedge clk) begin
internal_sclr <= reset;
end
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[69];
lock[1] = sink1_data[69];
end
reg [NUM_INPUTS - 1 : 0] locked;
always @(posedge clk) begin
if (internal_sclr) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk ) begin
if (internal_sclr) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk ) begin
if (internal_sclr) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end // @always
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk) begin
if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk) begin
if (internal_sclr)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1),
.SYNC_RESET (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
always @ (*) begin
case(1) // synthesis parallel_case
grant[0] : begin
src_valid = valid[0];
src_payload = sink0_payload;
end
grant[1] : begin
src_valid = valid[1];
src_payload = sink1_payload;
end
default : begin
src_valid = 1'b0;
src_payload = {PAYLOAD_W{1'b0}};
end
endcase
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
qsys/qsys_top/altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// ------------------------------------------
// Merlin Multiplexer
// ------------------------------------------
// altera message_off 13448
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: qsys_top_altera_merlin_multiplexer_1922_yjgptii
// NUM_INPUTS: 1
// ARBITRATION_SHARES: 1
// ARBITRATION_SCHEME "no-arb"
// PIPELINE_ARB: 0
// PKT_TRANS_LOCK: 69 (arbitration locking enabled)
// ST_DATA_W: 171
// ST_CHANNEL_W: 2
// ------------------------------------------
module qsys_top_altera_merlin_multiplexer_1922_yjgptii
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [171-1 : 0] sink0_data,
input [2-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output reg src_valid,
output [171-1 : 0] src_data,
output [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 171 + 2 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 171;
localparam ST_CHANNEL_W = 2;
localparam PKT_TRANS_LOCK = 69;
localparam SYNC_RESET = 1;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule
qsys/qsys_top/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv
+314
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
// $Revision: #3 $
// $Date: 2010/07/07 $
/* -----------------------------------------------------------------------
Round-robin/fixed arbitration implementation.
Q: how do you find the least-significant set-bit in an n-bit binary number, X?
A: M = X & (~X + 1)
Example: X = 101000100
101000100 &
010111011 + 1 =
101000100 &
010111100 =
-----------
000000100
The method can be generalized to find the first set-bit
at a bit index no lower than bit-index N, simply by adding
2**N rather than 1.
Q: how does this relate to round-robin arbitration?
A:
Let X be the concatenation of all request signals.
Let the number to be added to X (hereafter called the
top_priority) initialize to 1, and be assigned from the
concatenation of the previous saved-grant, left-rotated
by one position, each time arbitration occurs. The
concatenation of grants is then M.
Problem: consider this case:
top_priority = 010000
request = 001001
~request + top_priority = 000110
next_grant = 000000 <- no one is granted!
There was no "set bit at a bit index no lower than bit-index 4", so
the result was 0.
We need to propagate the carry out from (~request + top_priority) to the LSB, so
that the sum becomes 000111, and next_grant is 000001. This operation could be
called a "circular add".
A bit of experimentation on the circular add reveals a significant amount of
delay in exiting and re-entering the carry chain - this will vary with device
family. Quartus also reports a combinational loop warning. Finally,
Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But
Modelsim _doesn't_ report a combinational loop!)
An alternate solution: concatenate the request vector with itself, and OR
corresponding bits from the top and bottom halves to determine next_grant.
Example:
top_priority = 010000
{request, request} = 001001 001001
{~request, ~request} + top_priority = 110111 000110
result of & operation = 000001 000000
next_grant = 000001
Notice that if request = 0, the sum operation will overflow, but we can ignore
this; the next_grant result is 0 (no one granted), as you might expect.
In the implementation, the last-granted value must be maintained as
a non-zero value - best probably simply not to update it when no requests
occur.
----------------------------------------------------------------------- */
`timescale 1 ns / 1 ns
module altera_merlin_arbitrator
#(
parameter NUM_REQUESTERS = 8,
// --------------------------------------
// Implemented schemes
// "round-robin"
// "fixed-priority"
// "no-arb"
// --------------------------------------
parameter SCHEME = "round-robin",
parameter PIPELINE = 0,
parameter SYNC_RESET = 0
)
(
input clk,
input reset,
// --------------------------------------
// Requests
// --------------------------------------
input [NUM_REQUESTERS-1:0] request,
// --------------------------------------
// Grants
// --------------------------------------
output [NUM_REQUESTERS-1:0] grant,
// --------------------------------------
// Control Signals
// --------------------------------------
input increment_top_priority,
input save_top_priority
);
// --------------------------------------
// Signals
// --------------------------------------
wire [NUM_REQUESTERS-1:0] top_priority;
reg [NUM_REQUESTERS-1:0] top_priority_reg;
reg [NUM_REQUESTERS-1:0] last_grant;
wire [2*NUM_REQUESTERS-1:0] result;
// --------------------------------------
// Scheme Selection
// --------------------------------------
generate
if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
assign top_priority = top_priority_reg;
end
else begin
// Fixed arbitration (or single-requester corner case)
assign top_priority = 1'b1;
end
endgenerate
// --------------------------------------
// Decision Logic
// --------------------------------------
altera_merlin_arb_adder
#(
.WIDTH (2 * NUM_REQUESTERS)
)
adder
(
.a ({ ~request, ~request }),
.b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
.sum (result)
);
generate if (SCHEME == "no-arb") begin
// --------------------------------------
// No arbitration: just wire request directly to grant
// --------------------------------------
assign grant = request;
end else begin
// Do the math in double-vector domain
wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
assign grant_double_vector = {request, request} & result;
// --------------------------------------
// Extract grant from the top and bottom halves
// of the double vector.
// --------------------------------------
assign grant =
grant_double_vector[NUM_REQUESTERS - 1 : 0] |
grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
end
endgenerate
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
// --------------------------------------
// Left-rotate the last grant vector to create top_priority.
// --------------------------------------
generate
if (SYNC_RESET == 0) begin : async_rst0
always @(posedge clk or posedge reset) begin
if (reset) begin
top_priority_reg <= 1'b1;
end
else begin
if (PIPELINE) begin
if (increment_top_priority) begin
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1]} : top_priority_reg;
end
end else begin
if (increment_top_priority) begin
if (|request)
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1] };
else
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
end
else if (save_top_priority) begin
top_priority_reg <= grant;
end
end
end
end
end : async_rst0
else begin : sync_rst0
always @(posedge clk) begin
if (internal_sclr) begin
top_priority_reg <= 1'b1;
end
else begin
if (PIPELINE) begin
if (increment_top_priority) begin
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1]} : top_priority_reg;
end
end else begin
if (increment_top_priority) begin
if (|request)
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1] };
else
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
end
else if (save_top_priority) begin
top_priority_reg <= grant;
end
end
end
end
end : sync_rst0
endgenerate
endmodule
// ----------------------------------------------
// Adder for the standard arbitrator
// ----------------------------------------------
module altera_merlin_arb_adder
#(
parameter WIDTH = 8
)
(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [WIDTH-1:0] sum
);
wire [WIDTH:0] sum_lint;
// ----------------------------------------------
// Benchmarks indicate that for small widths, the full
// adder has higher fmax because synthesis can merge
// it with the mux, allowing partial decisions to be
// made early.
//
// The magic number is 4 requesters, which means an
// 8 bit adder.
// ----------------------------------------------
genvar i;
generate if (WIDTH <= 8) begin : full_adder
wire cout[WIDTH-1:0];
assign sum[0] = (a[0] ^ b[0]);
assign cout[0] = (a[0] & b[0]);
for (i = 1; i < WIDTH; i = i+1) begin : arb
assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
end
end else begin : carry_chain
assign sum_lint = a + b;
assign sum = sum_lint[WIDTH-1:0];
end
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZksjE5n06Mr0l/mBb60LrSgvPpMlNZxUqD9txpIj9hsezCwdfrrBRPOQT+QES/Nm3nommPpmIP8JAWSJX80lL83RGMKvGdWsS0ob3gO+7su5fOK9OUtmaVpnjnoiW1RorD6TGvfnjxd1duZAHt8lhP9BHlNFN099Msvu0Y2zdsWuLxA3YjCI3uRFf3UoZ37za/sca50uYkldtw82BfyKa8kz3RCprWyI4U91BNA6cwaffNaD/aWR+AFLyipXcmdpYo3Io0ytZJpq3pdedrEWsRXJqeDkpymOtDAF+VwTkJpMvSItOuEV1RpKs4u0S/fMiOBt4sPMBDxfVWmKWprM1wDuKjmuZZEcpSfp6AvwKZFHVKiACSojJG8vUyy3+tViHjyAxJ+5yeswhU6/FCKMR6xc4j5fyKZeRQQ8mRvXjehudvtOAc21ct9OrhtO1p8v5CPsKpTzOhScA3oGxPYdYG2jAtCEbtlnPEFfO+2TAtakrU3lwCZjvjwY3I0/DQj41lVp72CukLsr/q0GIuLl3o7A9jNb3rQsmnzfq8DyiJ28CAbLkxfpfEf8gfWV9bh5rSW5bWWXgjDEsuoTyfv3tTGQHfnMss1BWigGG7XfonCmncvg2nIZsLuAACqKfpfvH3lG8dmbwWw+691yoh8WgiQIlG/sbNwu4y/ly8l6B+lWnDzVrKE34TapwYhOeHGb7RKRotkQGOM2uRkDQ5wUx+t/ZO0Ty2wY7IHRGLPLjG1irHxZPHQ+b4yJ2bsPoHnaHTOyMvBXsm6oiciFOz6NdR2"
`endif
qsys/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// ------------------------------------------
// Merlin Multiplexer
// ------------------------------------------
// altera message_off 13448
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: qsys_top_altera_merlin_multiplexer_1922_666s25q
// NUM_INPUTS: 2
// ARBITRATION_SHARES: 1 1
// ARBITRATION_SCHEME "round-robin"
// PIPELINE_ARB: 1
// PKT_TRANS_LOCK: 69 (arbitration locking enabled)
// ST_DATA_W: 171
// ST_CHANNEL_W: 2
// ------------------------------------------
module qsys_top_altera_merlin_multiplexer_1922_666s25q
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [171-1 : 0] sink0_data,
input [2-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [171-1 : 0] sink1_data,
input [2-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output reg src_valid,
output [171-1 : 0] src_data,
output [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 171 + 2 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 171;
localparam ST_CHANNEL_W = 2;
localparam PKT_TRANS_LOCK = 69;
localparam SYNC_RESET = 1;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
reg internal_sclr;
always @(posedge clk) begin
internal_sclr <= reset;
end
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[69];
lock[1] = sink1_data[69];
end
reg [NUM_INPUTS - 1 : 0] locked;
always @(posedge clk) begin
if (internal_sclr) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk ) begin
if (internal_sclr) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk ) begin
if (internal_sclr) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end // @always
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk) begin
if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk) begin
if (internal_sclr)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1),
.SYNC_RESET (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
always @ (*) begin
case(1) // synthesis parallel_case
grant[0] : begin
src_valid = valid[0];
src_payload = sink0_payload;
end
grant[1] : begin
src_valid = valid[1];
src_payload = sink1_payload;
end
default : begin
src_valid = 1'b0;
src_payload = {PAYLOAD_W{1'b0}};
end
endcase
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
qsys/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// ------------------------------------------
// Merlin Multiplexer
// ------------------------------------------
// altera message_off 13448
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: qsys_top_altera_merlin_multiplexer_1922_yjgptii
// NUM_INPUTS: 1
// ARBITRATION_SHARES: 1
// ARBITRATION_SCHEME "no-arb"
// PIPELINE_ARB: 0
// PKT_TRANS_LOCK: 69 (arbitration locking enabled)
// ST_DATA_W: 171
// ST_CHANNEL_W: 2
// ------------------------------------------
module qsys_top_altera_merlin_multiplexer_1922_yjgptii
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [171-1 : 0] sink0_data,
input [2-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output reg src_valid,
output [171-1 : 0] src_data,
output [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 171 + 2 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 171;
localparam ST_CHANNEL_W = 2;
localparam PKT_TRANS_LOCK = 69;
localparam SYNC_RESET = 1;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule
qsys/qsys_top/altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv
+234
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -------------------------------------------------------
// Merlin Router
//
// Asserts the appropriate one-hot encoded channel based on
// the address.
//
// Also sets the binary-encoded destination id.
// -------------------------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// decoder_type 0 (address decoder)
// default_channel 0
// default_destid 0
// default_rd_channel -1
// default_wr_channel -1
// has_default_slave 0
// memory_aliasing_decode 0
// output_name qsys_top_altera_merlin_router_1921_ox5xuhq
// pkt_addr_h 64
// pkt_addr_l 36
// pkt_dest_id_h 102
// pkt_dest_id_l 102
// pkt_protection_h 109
// pkt_protection_l 107
// pkt_trans_read 68
// pkt_trans_write 67
// slaves_info 0:1:0x0:0x20000:both:1:0:0:1
// st_channel_w 2
// st_data_w 171
// ------------------------------------------
module qsys_top_altera_merlin_router_1921_ox5xuhq_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [102 - 102 : 0] default_destination_id,
output [2-1 : 0] default_wr_channel,
output [2-1 : 0] default_rd_channel,
output [2-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[102 - 102 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
module qsys_top_altera_merlin_router_1921_ox5xuhq
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [171-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [171-1 : 0] src_data,
output reg [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 64;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 102;
localparam PKT_DEST_ID_L = 102;
localparam PKT_PROTECTION_H = 109;
localparam PKT_PROTECTION_L = 107;
localparam ST_DATA_W = 171;
localparam ST_CHANNEL_W = 2;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 67;
localparam PKT_TRANS_READ = 68;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h20000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [2-1 : 0] default_src_channel;
qsys_top_altera_merlin_router_1921_ox5xuhq_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// slave 0: [0x0, 0x20000)
src_channel = 2'b1;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// --------------------------------------------------
// Ceil(log2()) function
// It's the 21st century. Consider using $clog2().
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
qsys/qsys_top/altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -------------------------------------------------------
// Merlin Router
//
// Asserts the appropriate one-hot encoded channel based on
// the dest id.
//
// -------------------------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// decoder_type 1 (dest id decoder)
// default_channel -1
// default_destid 0
// default_rd_channel 1
// default_wr_channel 0
// has_default_slave 0
// memory_aliasing_decode 0
// output_name qsys_top_altera_merlin_router_1921_sxavatq
// pkt_addr_h 64
// pkt_addr_l 36
// pkt_dest_id_h 102
// pkt_dest_id_l 102
// pkt_protection_h 109
// pkt_protection_l 107
// pkt_trans_read 68
// pkt_trans_write 67
// slaves_info 0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1
// st_channel_w 2
// st_data_w 171
// ------------------------------------------
module qsys_top_altera_merlin_router_1921_sxavatq_default_decode
#(
parameter DEFAULT_CHANNEL = -1,
DEFAULT_WR_CHANNEL = 0,
DEFAULT_RD_CHANNEL = 1,
DEFAULT_DESTID = 0
)
(output [102 - 102 : 0] default_destination_id,
output [2-1 : 0] default_wr_channel,
output [2-1 : 0] default_rd_channel,
output [2-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[102 - 102 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
module qsys_top_altera_merlin_router_1921_sxavatq
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [171-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [171-1 : 0] src_data,
output reg [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 64;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 102;
localparam PKT_DEST_ID_L = 102;
localparam PKT_PROTECTION_H = 109;
localparam PKT_PROTECTION_L = 107;
localparam ST_DATA_W = 171;
localparam ST_CHANNEL_W = 2;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 67;
localparam PKT_TRANS_READ = 68;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [2-1 : 0] default_rd_channel;
wire [2-1 : 0] default_wr_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire write_transaction;
assign write_transaction = sink_data[PKT_TRANS_WRITE];
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
qsys_top_altera_merlin_router_1921_sxavatq_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (default_wr_channel),
.default_rd_channel (default_rd_channel),
.default_src_channel ()
);
always @* begin
src_data = sink_data;
src_channel = write_transaction ? default_wr_channel : default_rd_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 && write_transaction) begin
src_channel = 2'b01;
end
if (destid == 0 && read_transaction) begin
src_channel = 2'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// It's the 21st century. Consider using $clog2().
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
qsys/qsys_top/altera_merlin_router_1921/synth/qsys_top_altera_merlin_router_1921_ox5xuhq.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -------------------------------------------------------
// Merlin Router
//
// Asserts the appropriate one-hot encoded channel based on
// the address.
//
// Also sets the binary-encoded destination id.
// -------------------------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// decoder_type 0 (address decoder)
// default_channel 0
// default_destid 0
// default_rd_channel -1
// default_wr_channel -1
// has_default_slave 0
// memory_aliasing_decode 0
// output_name qsys_top_altera_merlin_router_1921_ox5xuhq
// pkt_addr_h 64
// pkt_addr_l 36
// pkt_dest_id_h 102
// pkt_dest_id_l 102
// pkt_protection_h 109
// pkt_protection_l 107
// pkt_trans_read 68
// pkt_trans_write 67
// slaves_info 0:1:0x0:0x20000:both:1:0:0:1
// st_channel_w 2
// st_data_w 171
// ------------------------------------------
module qsys_top_altera_merlin_router_1921_ox5xuhq_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [102 - 102 : 0] default_destination_id,
output [2-1 : 0] default_wr_channel,
output [2-1 : 0] default_rd_channel,
output [2-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[102 - 102 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
module qsys_top_altera_merlin_router_1921_ox5xuhq
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [171-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [171-1 : 0] src_data,
output reg [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 64;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 102;
localparam PKT_DEST_ID_L = 102;
localparam PKT_PROTECTION_H = 109;
localparam PKT_PROTECTION_L = 107;
localparam ST_DATA_W = 171;
localparam ST_CHANNEL_W = 2;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 67;
localparam PKT_TRANS_READ = 68;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h20000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [2-1 : 0] default_src_channel;
qsys_top_altera_merlin_router_1921_ox5xuhq_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// slave 0: [0x0, 0x20000)
src_channel = 2'b1;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// --------------------------------------------------
// Ceil(log2()) function
// It's the 21st century. Consider using $clog2().
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
qsys/qsys_top/altera_merlin_router_1921/synth/qsys_top_altera_merlin_router_1921_sxavatq.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -------------------------------------------------------
// Merlin Router
//
// Asserts the appropriate one-hot encoded channel based on
// the dest id.
//
// -------------------------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// decoder_type 1 (dest id decoder)
// default_channel -1
// default_destid 0
// default_rd_channel 1
// default_wr_channel 0
// has_default_slave 0
// memory_aliasing_decode 0
// output_name qsys_top_altera_merlin_router_1921_sxavatq
// pkt_addr_h 64
// pkt_addr_l 36
// pkt_dest_id_h 102
// pkt_dest_id_l 102
// pkt_protection_h 109
// pkt_protection_l 107
// pkt_trans_read 68
// pkt_trans_write 67
// slaves_info 0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1
// st_channel_w 2
// st_data_w 171
// ------------------------------------------
module qsys_top_altera_merlin_router_1921_sxavatq_default_decode
#(
parameter DEFAULT_CHANNEL = -1,
DEFAULT_WR_CHANNEL = 0,
DEFAULT_RD_CHANNEL = 1,
DEFAULT_DESTID = 0
)
(output [102 - 102 : 0] default_destination_id,
output [2-1 : 0] default_wr_channel,
output [2-1 : 0] default_rd_channel,
output [2-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[102 - 102 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
module qsys_top_altera_merlin_router_1921_sxavatq
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [171-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [171-1 : 0] src_data,
output reg [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 64;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 102;
localparam PKT_DEST_ID_L = 102;
localparam PKT_PROTECTION_H = 109;
localparam PKT_PROTECTION_L = 107;
localparam ST_DATA_W = 171;
localparam ST_CHANNEL_W = 2;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 67;
localparam PKT_TRANS_READ = 68;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [2-1 : 0] default_rd_channel;
wire [2-1 : 0] default_wr_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire write_transaction;
assign write_transaction = sink_data[PKT_TRANS_WRITE];
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
qsys_top_altera_merlin_router_1921_sxavatq_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (default_wr_channel),
.default_rd_channel (default_rd_channel),
.default_src_channel ()
);
always @* begin
src_data = sink_data;
src_channel = write_transaction ? default_wr_channel : default_rd_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 && write_transaction) begin
src_channel = 2'b01;
end
if (destid == 0 && read_transaction) begin
src_channel = 2'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// It's the 21st century. Consider using $clog2().
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
qsys/qsys_top/altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// ------------------------------------------
// Merlin Burst Uncompressor
//
// Compressed read bursts -> uncompressed
// ------------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_burst_uncompressor
#(
parameter ADDR_W = 16,
parameter BURSTWRAP_W = 3,
parameter BYTE_CNT_W = 4,
parameter PKT_SYMBOLS = 4,
parameter BURST_SIZE_W = 3,
parameter SYNC_RESET = 0,
parameter USED_IN_WIDTH_ADAPTER = 0
)
(
input clk,
input reset,
// sink ST signals
input sink_startofpacket,
input sink_endofpacket,
input sink_valid,
output sink_ready,
// sink ST "data"
input [ADDR_W - 1: 0] sink_addr,
input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
input sink_is_compressed,
input [BURST_SIZE_W-1 : 0] sink_burstsize,
// source ST signals
output source_startofpacket,
output source_endofpacket,
output source_valid,
input source_ready,
// source ST "data"
output [ADDR_W - 1: 0] source_addr,
output [BURSTWRAP_W - 1 : 0] source_burstwrap,
output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
// Note: in the slave agent, the output should always be uncompressed. In
// other applications, it may be required to leave-compressed or not. How to
// control? Seems like a simple mux - pass-through if no uncompression is
// required.
output source_is_compressed,
output [BURST_SIZE_W-1 : 0] source_burstsize
);
//----------------------------------------------------
// AXSIZE decoding
//
// Turns the axsize value into the actual number of bytes
// being transferred.
// ---------------------------------------------------
function reg[63:0] bytes_in_transfer;
input [BURST_SIZE_W-1:0] axsize;
case (axsize)
4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
endcase
endfunction
localparam LG_PKT_SYMBOLS = $clog2(PKT_SYMBOLS);
// num_symbols is PKT_SYMBOLS, appropriately sized.
wire [31:0] int_num_symbols;
if(USED_IN_WIDTH_ADAPTER)
assign int_num_symbols = (|sink_burstsize) ? PKT_SYMBOLS:1;
else
assign int_num_symbols = PKT_SYMBOLS;
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
// def: Burst Compression. In a merlin network, a compressed burst is one
// which is transmitted in a single beat. Example: read burst. In
// constrast, an uncompressed burst (example: write burst) is transmitted in
// one beat per writedata item.
//
// For compressed bursts which require response packets, burst
// uncompression is required. Concrete example: a read burst of size 8
// occupies one response-fifo position. When that fifo position reaches the
// front of the FIFO, the slave starts providing the required 8 readdatavalid
// pulses. The 8 return response beats must be provided in a single packet,
// with incrementing address and decrementing byte_cnt fields. Upon receipt
// of the final readdata item of the burst, the response FIFO item is
// retired.
// Burst uncompression logic provides:
// a) 2-state FSM (idle, busy)
// reset to idle state
// transition to busy state for 2nd and subsequent rdv pulses
// - a single-cycle burst (aka non-burst read) causes no transition to
// busy state.
// b) response startofpacket/endofpacket logic. The response FIFO item
// will have sop asserted, and may have eop asserted. (In the case of
// multiple read bursts transmit in the command fabric in a single packet,
// the eop assertion will come in a later FIFO item.) To support packet
// conservation, and emit a well-formed packet on the response fabric,
// i) response fabric startofpacket is asserted only for the first resp.
// beat;
// ii) response fabric endofpacket is asserted only for the last resp.
// beat.
// c) response address field. The response address field contains an
// incrementing sequence, such that each readdata item is associated with
// its slave-map location. N.b. a) computing the address correctly requires
// knowledge of burstwrap behavior b) there may be no clients of the address
// field, which makes this field a good target for optimization. See
// burst_uncompress_address_counter below.
// d) response byte_cnt field. The response byte_cnt field contains a
// decrementing sequence, such that each beat of the response contains the
// count of bytes to follow. In the case of sub-bursts in a single packet,
// the byte_cnt field may decrement down to num_symbols, then back up to
// some value, multiple times in the packet.
reg burst_uncompress_busy;
reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
wire first_packet_beat;
wire last_packet_beat;
assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
always @ (posedge clk) begin
if (source_valid & source_ready & sink_valid) begin
if(burst_uncompress_busy) begin
burst_uncompress_byte_counter_lint <= burst_uncompress_byte_counter_lint-num_symbols;
end else begin
burst_uncompress_byte_counter_lint <= sink_byte_cnt - num_symbols;
end
end
end
// First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
// the output.
assign source_byte_cnt =
first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
assign source_valid = sink_valid;
// Last packet beat is set throughout receipt of an uncompressed read burst
// from the response FIFO - this forces all the burst uncompression machinery
// idle.
assign last_packet_beat = ~sink_is_compressed |
(
burst_uncompress_busy ?
(sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
sink_valid & (sink_byte_cnt == num_symbols)
);
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
generate
if (SYNC_RESET == 0) begin : async_rst0
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_busy <= '0;
end
else begin
if (source_valid & source_ready & sink_valid) begin
// No matter what the current state, last_packet_beat leads to
// idle.
if (last_packet_beat) begin
burst_uncompress_busy <= '0;
end
else begin
burst_uncompress_busy <= 1'b1;
end
end
end
end
end // async_rst0
else begin // sync_rst0
always @(posedge clk ) begin
if (internal_sclr) begin
burst_uncompress_busy <= '0;
end
else begin
if (source_valid & source_ready & sink_valid) begin
// No matter what the current state, last_packet_beat leads to
// idle.
if (last_packet_beat) begin
burst_uncompress_busy <= '0;
end
else begin
burst_uncompress_busy <= 1'b1;
end
end
end
end
end // sync_rst0
endgenerate
//always @ (posedge clk) begin
// if (source_valid & source_ready & sink_valid) begin
// // No matter what the current state, last_packet_beat leads to
// // idle.
// if (last_packet_beat) begin
// burst_uncompress_byte_counter <= '0;
// end
// else begin
// if (burst_uncompress_busy) begin
// burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ?
// (burst_uncompress_byte_counter_lint[BYTE_CNT_W-1:LG_PKT_SYMBOLS] - num_symbols[BYTE_CNT_W-1:LG_PKT_SYMBOLS]) :
// (sink_byte_cnt[BYTE_CNT_W-1:LG_PKT_SYMBOLS] - num_symbols[BYTE_CNT_W-1:LG_PKT_SYMBOLS]);
// end
// else begin // not busy, at least one more beat to go
// burst_uncompress_byte_counter <= sink_byte_cnt[BYTE_CNT_W-1:LG_PKT_SYMBOLS] - num_symbols[BYTE_CNT_W-1:LG_PKT_SYMBOLS];
// // To do: should busy go true for numsymbols-size compressed
// // bursts?
// end
// end
// end
//end
reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
wire [63:0] decoded_burstsize_wire;
wire [ADDR_W-1:0] decoded_burstsize;
localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
// The input burstwrap value can be used as a mask against address values,
// but with one caveat: the address width may be (probably is) wider than
// the burstwrap width. The spec says: extend the msb of the burstwrap
// value out over the entire address width (but only if the address width
// actually is wider than the burstwrap width; otherwise it's a 0-width or
// negative range and concatenation multiplier).
generate
if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
// Sign-extend, just wires:
assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
{(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
end
else begin
assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
end
endgenerate
always @(posedge clk) begin
if (first_packet_beat & source_ready) begin
burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
end
end
//always @(posedge clk or posedge reset) begin
// if (reset) begin
// burst_uncompress_address_base <= '0;
// end
// else if (first_packet_beat & source_ready) begin
// burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
// end
//end
assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits
assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed
wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
(
(first_packet_beat ?
sink_addr :
burst_uncompress_address_offset) + decoded_burstsize
) &
addr_width_burstwrap[ADDR_W-1:0];
wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
always @ (posedge clk) begin
if (source_ready & source_valid) begin
burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
end
end
//always @(posedge clk or posedge reset) begin
// if (reset) begin
// burst_uncompress_address_offset <= '0;
// end
// else begin
// if (source_ready & source_valid) begin
// burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
// // if (first_packet_beat) begin
// // burst_uncompress_address_offset <=
// // (sink_addr + num_symbols) & addr_width_burstwrap;
// // end
// // else begin
// // burst_uncompress_address_offset <=
// // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
// // end
// end
// end
//end
// On the first packet beat, send the input address out unchanged,
// while values are computed/registered for 2nd and subsequent beats.
assign source_addr = first_packet_beat ? sink_addr :
burst_uncompress_address_base | burst_uncompress_address_offset;
assign source_burstwrap = sink_burstwrap;
assign source_burstsize = sink_burstsize;
//-------------------------------------------------------------------
// A single (compressed) read burst will have sop/eop in the same beat.
// A sequence of read sub-bursts emitted by a burst adapter in response to a
// single read burst will have sop on the first sub-burst, eop on the last.
// Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve
// packet conservation.
assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
assign source_endofpacket = sink_endofpacket & last_packet_beat;
assign sink_ready = source_valid & source_ready & last_packet_beat;
// This is correct for the slave agent usage, but won't always be true in the
// width adapter. To do: add an "please uncompress" input, and use it to
// pass-through or modify, and set source_is_compressed accordingly.
assign source_is_compressed = 1'b0;
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZlTuVjbs7t2AvXR8qtB5hlO4OP16VPo84MCPLx2rVhD1zQQWJ7B8d/ZQxcAh23irlYM5PRXVl1hzM1E9XBSwTHX4GiaPXc8KI87MAd2OBRsTVzQ3ploJyDTJ/5iLBZk4lL6RD0/o7jVPAsAA+iYoLIntesrKlzmNSO+ripXoEhypWMwRKSzgZZBPMMElLmdGOVkBpdGTg8XYKHFaxXioKDrffXWH12N3vtI6NzFHQfH/h77pcm8kqSxGEZzefHKCpgRsohq+zmawBPnqIEaklf3w9TR8wCComgJoehSxSSU/SoZucGVczKi/zpxAaV1C3ZvnYRs6KS3lwnftursubOcnVc54fiBCNX0o2tUlOGUN0MZVEhCByjyP7/tDDYHyz9Dyh5CcvlQ1SlPiN2bmCdVaKBDuFQGfnNX4iqkFXbtpf7KyNk9EwAzMRwGegjRDAqiYGeKBW/CfOtS6SxSn5LnfJyo1DRPBwBMYeT9gTB/CrgMTgZ+I0tO5pLPCNfpzFfaADXjL2aK7Oohy9lgFxUbDj3q5P1aPR2PeEeAnnBI1Cr9zvzuR1DljqKvMOVADEKuTYRh0CnptFzPRonyrUW0ISqpzVm4wrGeiVIWDlOU8I0E1VOdTB5G/FOYL7Ebbu+trxrk1HrXg+BTlfLX2HGtuX4biBJX3qBsyXItz0GnbOPIyN3bm3ZPkveSN7/nVnoPqYgXI5x9ilgczDHvSqU9mbmxiKhhU+AFIaVHUSBECnzRd5E6E34UW/Cxs92veqD6Z3nxWZyIP4Xab517bXhz"
`endif
qsys/qsys_top/altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv
+841
View File
@@ -0,0 +1,841 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ns / 1 ns
module qsys_top_altera_merlin_slave_agent_1930_jxauz3i
#(
// Packet parameters
parameter PKT_BEGIN_BURST = 81,
parameter PKT_DATA_H = 31,
parameter PKT_DATA_L = 0,
parameter PKT_SYMBOL_W = 8,
parameter PKT_BYTEEN_H = 71,
parameter PKT_BYTEEN_L = 68,
parameter PKT_ADDR_H = 63,
parameter PKT_ADDR_L = 32,
parameter PKT_TRANS_LOCK = 87,
parameter PKT_TRANS_COMPRESSED_READ = 67,
parameter PKT_TRANS_POSTED = 66,
parameter PKT_TRANS_WRITE = 65,
parameter PKT_TRANS_READ = 64,
parameter PKT_SRC_ID_H = 74,
parameter PKT_SRC_ID_L = 72,
parameter PKT_DEST_ID_H = 77,
parameter PKT_DEST_ID_L = 75,
parameter PKT_BURSTWRAP_H = 85,
parameter PKT_BURSTWRAP_L = 82,
parameter PKT_BYTE_CNT_H = 81,
parameter PKT_BYTE_CNT_L = 78,
parameter PKT_PROTECTION_H = 86,
parameter PKT_PROTECTION_L = 86,
parameter PKT_RESPONSE_STATUS_H = 89,
parameter PKT_RESPONSE_STATUS_L = 88,
parameter PKT_BURST_SIZE_H = 92,
parameter PKT_BURST_SIZE_L = 90,
parameter PKT_ORI_BURST_SIZE_L = 93,
parameter PKT_ORI_BURST_SIZE_H = 95,
parameter PKT_POISON_L = 97,
parameter PKT_POISON_H = 97,
parameter PKT_DATACHK_L = 98,
parameter PKT_DATACHK_H = 98,
parameter PKT_SAI_L = 99,
parameter PKT_SAI_H = 99,
parameter PKT_ADDRCHK_L = 100,
parameter PKT_ADDRCHK_H = 100,
parameter PKT_USER_DATA_L = 101,
parameter PKT_USER_DATA_H = 101,
parameter PKT_ATRACE = 102,
parameter PKT_TRACE = 103,
parameter PKT_AWAKEUP = 104,
//ACE5-Lite signals
parameter PKT_AWATOP_L = 154,
parameter PKT_AWATOP_H = 159,
parameter PKT_AWSTASHNID_L = 160,
parameter PKT_AWSTASHNID_H = 170,
parameter PKT_AWSTASHNIDEN = 171,
parameter PKT_AWSTASHLPID_L = 172,
parameter PKT_AWSTASHLPID_H = 176,
parameter PKT_AWSTASHLPIDEN = 177,
parameter PKT_MMUSECSID = 178,
parameter PKT_MMUSID_L = 179,
parameter PKT_MMUSID_H = 195,
parameter PKT_DATALESS = 196,
parameter ST_DATA_W = 102,
parameter ST_CHANNEL_W = 32,
parameter ROLE_BASED_USER = 0,
parameter ENABLE_AXI5 = 0,
parameter SYNC_RESET = 0,
parameter USE_PKT_DATACHK = 1,
// Slave parameters
parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
parameter AVS_BURSTCOUNT_W = 4,
parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W,
// Slave agent parameters
parameter USE_MEMORY_BLOCKS = 1,
parameter PREVENT_FIFO_OVERFLOW = 0,
parameter SUPPRESS_0_BYTEEN_CMD = 1,
parameter USE_READRESPONSE = 0,
parameter USE_WRITERESPONSE = 0,
// Derived slave parameters
parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
parameter BURST_SIZE_W = 3,
// Derived FIFO width
parameter FIFO_DATA_W = ST_DATA_W + 1,
// ECC parameter
parameter ECC_ENABLE = 0
) (
input clk,
input reset,
// Universal-Avalon anti-slave
output [ADDR_W-1:0] m0_address,
output [AVS_BURSTCOUNT_W-1:0] m0_burstcount,
output [AVS_BE_W-1:0] m0_byteenable,
output m0_read,
input [AVS_DATA_W-1:0] m0_readdata,
input m0_waitrequest,
output m0_write,
output [AVS_DATA_W-1:0] m0_writedata,
input m0_readdatavalid,
output m0_debugaccess,
output m0_lock,
input [1:0] m0_response,
input m0_writeresponsevalid,
// Avalon-ST FIFO interfaces.
// Note: there's no need to include the "data" field here, at least for
// reads, since readdata is filled in from slave info. To keep life
// simple, have a data field, but fill it with 0s.
// Av-st response fifo source interface
output reg [FIFO_DATA_W-1:0] rf_source_data,
output rf_source_valid,
output rf_source_startofpacket,
output rf_source_endofpacket,
input rf_source_ready,
// Av-st response fifo sink interface
input [FIFO_DATA_W-1:0] rf_sink_data,
input rf_sink_valid,
input rf_sink_startofpacket,
input rf_sink_endofpacket,
output reg rf_sink_ready,
// Av-st readdata fifo src interface, data and response
// extra 2 bits for storing RESPONSE STATUS
output [AVS_DATA_W+1:0] rdata_fifo_src_data,
output rdata_fifo_src_valid,
input rdata_fifo_src_ready,
// Av-st readdata fifo sink interface
input [AVS_DATA_W+1:0] rdata_fifo_sink_data,
input rdata_fifo_sink_valid,
output rdata_fifo_sink_ready,
input rdata_fifo_sink_error,
// Av-st sink command packet interface
output cp_ready,
input cp_valid,
input [ST_DATA_W-1:0] cp_data,
input [ST_CHANNEL_W-1:0] cp_channel,
input cp_startofpacket,
input cp_endofpacket,
// Av-st source response packet interface
input rp_ready,
output reg rp_valid,
output reg [ST_DATA_W-1:0] rp_data,
output rp_startofpacket,
output rp_endofpacket
);
// ------------------------------------------------
// Local Parameters
// ------------------------------------------------
localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1;
localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1;
localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1;
localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS);
localparam MAX_BURST = 1 << (AVS_BURSTCOUNT_W - 1);
localparam BURSTING = (MAX_BURST > PKT_SYMBOLS);
localparam PKT_DATACHK_W = DATA_W/8;
// --------------------------------------------------
// Ceil(log2()) function log2ceil of 4 = 2
// --------------------------------------------------
function integer log2ceil;
input reg[63:0] val;
reg [63:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
// --------------------------------------------------
// calcParity: calculates byte-level parity signal
// --------------------------------------------------
function reg [PKT_DATACHK_W-1:0] calcParity (
input [DATA_W-1:0] data
);
for (int i=0; i<PKT_DATACHK_W; i++)
calcParity[i] = ~(^ data[i*8 +:8]);
endfunction
// ------------------------------------------------
// Signals
// ------------------------------------------------
wire [DATA_W-1:0] cmd_data;
wire [BE_W-1:0] cmd_byteen;
wire [ADDR_W-1:0] cmd_addr;
wire [MID_W-1:0] cmd_mid;
wire [SID_W-1:0] cmd_sid;
wire cmd_read;
wire cmd_write;
wire cmd_compressed;
wire cmd_posted;
wire [BYTE_CNT_W-1:0] cmd_byte_cnt;
wire [BURSTWRAP_W-1:0] cmd_burstwrap;
wire [BURSTSIZE_W-1:0] cmd_burstsize;
wire cmd_debugaccess;
wire suppress_cmd;
wire byteen_asserted;
wire suppress_read;
wire suppress_write;
wire needs_response_synthesis;
wire generate_response;
//signals for additional latency due to different memory
wire [AVS_DATA_W-1:0] m0_readdata_q;
wire m0_readdatavalid_q;
wire [1:0] m0_response_q;
wire m0_writeresponsevalid_q;
reg [AVS_DATA_W-1:0] m0_readdata_1;
reg m0_readdatavalid_1;
reg [1:0] m0_response_1;
reg m0_writeresponsevalid_1;
reg [AVS_DATA_W-1:0] m0_readdata_2;
reg m0_readdatavalid_2;
reg [1:0] m0_response_2;
reg m0_writeresponsevalid_2;
// Assign command fields
assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ];
assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L];
assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ];
assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ];
assign cmd_posted = cp_data[PKT_TRANS_POSTED];
assign cmd_write = cp_data[PKT_TRANS_WRITE];
assign cmd_read = cp_data[PKT_TRANS_READ];
assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L];
assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
assign cmd_debugaccess = cp_data[PKT_PROTECTION_L];
// Local "ready_for_command" signal: deasserted when the agent is unable to accept
// another command, e.g. rdv FIFO is full, (local readdata storage is full &&
// ~rp_ready), ...
// Say, this could depend on the type of command, for example, even if the
// rdv FIFO is full, a write request can be accepted. For later.
wire ready_for_command;
wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK];
wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE];
wire local_read = cp_valid & cp_data[PKT_TRANS_READ];
wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ];
wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket;
// num_symbols is PKT_SYMBOLS, appropriately sized.
wire [31:0] int_num_symbols = PKT_SYMBOLS;
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
generate
if (SYNC_RESET ==0 ) begin : async0
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
m0_readdata_2 <= '0;
m0_readdatavalid_2 <= '0;
m0_response_2 <= '0;
m0_writeresponsevalid_2 <= '0;
end
else begin
m0_readdata_2 <= m0_readdata;
m0_readdatavalid_2 <= m0_readdatavalid;
m0_response_2 <= m0_response;
m0_writeresponsevalid_2 <= m0_writeresponsevalid;
end
end //@always_ff
end // async0
else begin :sync0
always_ff @(posedge clk) begin
if (internal_sclr) begin
m0_readdata_2 <= '0;
m0_readdatavalid_2 <= '0;
m0_response_2 <= '0;
m0_writeresponsevalid_2 <= '0;
end
else begin
m0_readdata_2 <= m0_readdata;
m0_readdatavalid_2 <= m0_readdatavalid;
m0_response_2 <= m0_response;
m0_writeresponsevalid_2 <= m0_writeresponsevalid;
end
end //@always_ff
end // sync0
endgenerate
generate
if (SYNC_RESET ==0 ) begin : async1
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
m0_readdata_1 <= '0;
m0_readdatavalid_1 <= '0;
m0_response_1 <= '0;
m0_writeresponsevalid_1 <= '0;
end
else begin
m0_readdata_1 <= m0_readdata_2;
m0_readdatavalid_1 <= m0_readdatavalid_2;
m0_response_1 <= m0_response_2;
m0_writeresponsevalid_1 <= m0_writeresponsevalid_2;
end
end //@always_ff
end // async1
else begin :sync1
always_ff @(posedge clk) begin
if (internal_sclr) begin
m0_readdata_1 <= '0;
m0_readdatavalid_1 <= '0;
m0_response_1 <= '0;
m0_writeresponsevalid_1 <= '0;
end
else begin
m0_readdata_1 <= m0_readdata_2;
m0_readdatavalid_1 <= m0_readdatavalid_2;
m0_response_1 <= m0_response_2;
m0_writeresponsevalid_1 <= m0_writeresponsevalid_2;
end
end //@always_ff
end // sync1
endgenerate
generate
if (USE_MEMORY_BLOCKS) begin : Using_M20k_with_2_clk_latency
assign m0_readdata_q = m0_readdata_1;
assign m0_readdatavalid_q = m0_readdatavalid_1;
assign m0_response_q = m0_response_1;
assign m0_writeresponsevalid_q = m0_writeresponsevalid_1;
end else begin : Using_ALM_memory_with_1_clk_latency
assign m0_readdata_q = m0_readdata;
assign m0_readdatavalid_q = m0_readdatavalid;
assign m0_response_q = m0_response;
assign m0_writeresponsevalid_q = m0_writeresponsevalid;
end
endgenerate
generate
if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow_block
// ---------------------------------------------------
// Backpressure if the slave says to, or if FIFO overflow may occur.
//
// All commands are backpressured once the FIFO is full
// even if they don't need storage. This breaks a long
// combinatorial path from the master read/write through
// this logic and back to the master via the backpressure
// path.
//
// To avoid a loss of throughput the FIFO will be parameterized
// one slot deeper. The extra slot should never be used in normal
// operation, but should a slave misbehave and accept one more
// read than it should then backpressure will kick in.
//
// An example: assume a slave with MPRT = 2. It can accept a
// command sequence RRWW without backpressuring. If the FIFO is
// only 2 deep, we'd backpressure the writes leading to loss of
// throughput. If the FIFO is 3 deep, we'll only backpressure when
// RRR... which is an illegal condition anyway.
// ---------------------------------------------------
assign ready_for_command = rf_source_ready;
assign cp_ready = (~m0_waitrequest | suppress_cmd) && ready_for_command;
end else begin : no_prevent_fifo_overflow_block
// Do not suppress the command or the slave will
// not be able to waitrequest
assign ready_for_command = 1'b1;
// Backpressure only if the slave says to.
assign cp_ready = ~m0_waitrequest | suppress_cmd;
end
endgenerate
generate if (SUPPRESS_0_BYTEEN_CMD && !BURSTING) begin : suppress_0_byteen_cmd_non_bursting
assign byteen_asserted = |cmd_byteen;
assign suppress_read = ~byteen_asserted;
assign suppress_write = ~byteen_asserted;
assign suppress_cmd = ~byteen_asserted;
end else if (SUPPRESS_0_BYTEEN_CMD && BURSTING) begin: suppress_0_byteen_cmd_bursting
assign byteen_asserted = |cmd_byteen;
assign suppress_read = ~byteen_asserted;
assign suppress_write = 1'b0;
assign suppress_cmd = ~byteen_asserted && cmd_read;
end else begin : no_suppress_0_byteen_cmd
assign suppress_read = 1'b0;
assign suppress_write = 1'b0;
assign suppress_cmd = 1'b0;
end
endgenerate
// -------------------------------------------------------------------
// Extract avalon signals from command packet.
// -------------------------------------------------------------------
// Mask off the lower bits of address.
// The burst adapter before this component will break narrow sized packets
// into sub-bursts of length 1. However, the packet addresses are preserved,
// which means this component may see size-aligned addresses.
//
// Masking ensures that the addresses seen by an Avalon slave are aligned to
// the full data width instead of the size.
//
// Example:
// output from burst adapter (datawidth=4, size=2 bytes):
// subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6
// expected output from slave agent:
// subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4
generate
if (BITS_TO_MASK > 0) begin : mask_address
if(ADDR_W == BITS_TO_MASK)
assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK-1], {BITS_TO_MASK-1{1'b0}} };
else
assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} };
end else begin : no_mask_address
assign m0_address = cmd_addr;
end
endgenerate
assign m0_byteenable = cmd_byteen;
assign m0_writedata = cmd_data;
// Note: no Avalon-MM slave in existence accepts uncompressed read bursts -
// this sort of burst exists only in merlin fabric ST packets. What to do
// if we see such a burst? All beats in that burst need to be transmitted
// to the slave so we have enough space-time for byteenable expression.
//
// There can be multiple bursts in a packet, but only one beat per burst
// in <most> cases. The exception is when we've decided not to insert a
// burst adapter for efficiency reasons, in which case this agent is also
// responsible for driving burstcount to 1 on each beat of an uncompressed
// read burst.
assign m0_read = ready_for_command & !suppress_read & (local_compressed_read | local_read);
generate
// AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount
// from a sub-range, or 0-pad, as appropriate.
if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin : m0_burstcount_zero_pad
wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}};
assign m0_burstcount = (local_read & ~local_compressed_read) ?
{zero_pad, num_symbols} :
{zero_pad, cmd_byte_cnt};
end
else begin : m0_burstcount_no_pad
assign m0_burstcount = (local_read & ~local_compressed_read) ?
num_symbols[AVS_BURSTCOUNT_W-1:0] :
cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0];
end
endgenerate
assign m0_write = ready_for_command & local_write & !suppress_write;
assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write);
assign m0_debugaccess = cmd_debugaccess;
// -------------------------------------------------------------------
// Indirection layer for response packet values. Some may always wire
// directly from the slave translator; others will no doubt emerge from
// various FIFOs.
// What to put in resp_data when a write occured? Answer: it does not
// matter, because only response status is needed for non-posted writes,
// and the packet already has a field for that.
//
// We use the rdata_fifo to store write responses as well. This allows us
// to handle backpressure on the response path, and allows write response
// merging.
assign rdata_fifo_src_valid = m0_readdatavalid_q | m0_writeresponsevalid_q;
assign rdata_fifo_src_data = {m0_response_q, m0_readdata_q};
// ------------------------------------------------------------------
// Generate a token when read commands are suppressed. The token
// is stored in the response FIFO, and will be used to synthesize
// a read response. The same token is used for non-posted write
// response synthesis.
//
// Note: this token is not generated for suppressed uncompressed read cycles;
// the burst uncompression logic at the read side of the response FIFO
// generates the correct number of responses.
//
// When the slave can return the response, let it do its job. Don't
// synthesize a response in that case, unless we've suppressed the
// the last transfer in a write sub-burst.
// ------------------------------------------------------------------
wire write_end_of_subburst;
assign needs_response_synthesis = ((local_read | local_compressed_read) & suppress_read) ||
(!USE_WRITERESPONSE && nonposted_write_endofpacket) ||
(USE_WRITERESPONSE && write_end_of_subburst && suppress_write);
// Avalon-ST interfaces to external response FIFO.
//
// For efficiency, when synthesizing a write response we only store a non-posted write
// transaction at its endofpacket, even if it was split into multiple sub-bursts.
//
// When not synthesizing write responses, we store each sub-burst in the FIFO.
// Each sub-burst to the slave will return a response, which corresponds to one
// entry in the FIFO. We merge all the sub-burst responses on the final
// sub-burst and send it on the response channel.
wire internal_cp_endofburst;
wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning
wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount;
assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0];
assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount);
assign write_end_of_subburst = local_write & internal_cp_endofburst;
assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && internal_cp_endofburst && local_write))
& ready_for_command & cp_ready;
assign rf_source_startofpacket = cp_startofpacket;
assign rf_source_endofpacket = cp_endofpacket;
always @* begin
// default: assign every command packet field to the response FIFO...
rf_source_data = {1'b0, cp_data};
// ... and override select fields as needed.
rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis;
rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}};
rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen;
rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr;
rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed;
rf_source_data[PKT_TRANS_POSTED] = cmd_posted;
rf_source_data[PKT_TRANS_WRITE] = cmd_write;
rf_source_data[PKT_TRANS_READ] = cmd_read;
rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid;
rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid;
rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt;
rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap;
rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize;
rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0;
rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess;
end
wire uncompressor_source_valid;
wire [BURSTSIZE_W-1:0] uncompressor_burstsize;
wire last_write_response;
// last_write_response indicates the last response of the broken-up write burst (sub-bursts).
// At this time, the final merged response is sent, and rp_valid is only asserted
// once for the whole burst.
generate
if (USE_WRITERESPONSE) begin
assign last_write_response = rf_sink_data[PKT_TRANS_WRITE] & rf_sink_endofpacket;
always @* begin
if (rf_sink_data[PKT_TRANS_WRITE] == 1)
rp_valid = ((rdata_fifo_sink_valid | generate_response) & last_write_response & !rf_sink_data[PKT_TRANS_POSTED]);
else
rp_valid = (rdata_fifo_sink_valid | uncompressor_source_valid);
end
end else begin
assign last_write_response = 1'b0;
always @* begin
rp_valid = (rdata_fifo_sink_valid | uncompressor_source_valid);
end
end
endgenerate
// ------------------------------------------------------------------
// Response merging
// ------------------------------------------------------------------
reg [1:0] current_response;
reg [1:0] response_merged;
generate
if (USE_WRITERESPONSE) begin : response_merging_all
reg first_write_response;
reg reset_merged_output;
reg [1:0] previous_response_in;
reg [1:0] previous_response;
if (SYNC_RESET ==0 ) begin : async_reg0
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
first_write_response <= 1'b1;
end
else begin // Merging work for write response, for read: previous_response_in = current_response
if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin
first_write_response <= 1'b0;
if (rf_sink_endofpacket)
first_write_response <= 1'b1;
end
end
end //@always_ff
end // async_reg0
else begin :sync_reg0
always_ff @(posedge clk) begin
if (internal_sclr) begin
first_write_response <= 1'b1;
end
else begin // Merging work for write response, for read: previous_response_in = current_response
if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin
first_write_response <= 1'b0;
if (rf_sink_endofpacket)
first_write_response <= 1'b1;
end
end
end //@always_ff
end // sync_reg0
always_comb begin
current_response = generate_response ? 2'b00 : rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | {2{rdata_fifo_sink_error}};
reset_merged_output = first_write_response && (rdata_fifo_sink_valid || generate_response);
previous_response_in = reset_merged_output ? current_response : previous_response;
response_merged = current_response >= previous_response ? current_response: previous_response_in;
end
if (SYNC_RESET == 0) begin : async_reg1
always_ff @(posedge clk or posedge reset) begin
if (reset) begin
previous_response <= 2'b00;
end
else begin
if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin
previous_response <= response_merged;
end
end
end
end // async_reg1
else begin : sync_reg1
always_ff @(posedge clk ) begin
if (internal_sclr) begin
previous_response <= 2'b00;
end
else begin
if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin
previous_response <= response_merged;
end
end
end
end // sync_reg1
end else begin : response_merging_read_only
always @* begin
current_response = generate_response ? 2'b00: rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] |
{2{rdata_fifo_sink_error}};
response_merged = current_response;
end
end
endgenerate
assign generate_response = rf_sink_data[FIFO_DATA_W-1];
wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ];
wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L];
// a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo
wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket;
wire [BYTE_CNT_W-1:0] burst_byte_cnt;
wire [BURSTWRAP_W-1:0] rp_burstwrap;
wire [ADDR_W-1:0] rp_address;
wire rp_is_compressed;
wire ready_for_response;
// ------------------------------------------------------------------
// We're typically ready for a response if the network is ready. There
// is one exception:
//
// If the slave issues write responses, we only issue a merged response on
// the final sub-burst. As a result, we only care about response channel
// availability on the final burst when we send out the merged response.
// ------------------------------------------------------------------
assign ready_for_response = (USE_WRITERESPONSE) ?
rp_ready || (rf_sink_data[PKT_TRANS_WRITE] && !last_write_response) || rf_sink_data[PKT_TRANS_POSTED]:
rp_ready;
// ------------------------------------------------------------------
// Backpressure the readdata fifo if we're supposed to synthesize a response.
// This may be a read response (for suppressed reads) or a write response
// (for non-posted writes).
// ------------------------------------------------------------------
assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & ready_for_response & ~(rf_sink_valid & generate_response);
always @* begin
rp_data[PKT_AWATOP_H:PKT_AWATOP_L] = '0 ;
rp_data[PKT_AWSTASHNID_H:PKT_AWSTASHNID_L] = '0 ;
rp_data[PKT_AWSTASHNIDEN] = '0 ;
rp_data[PKT_AWSTASHLPID_H:PKT_AWSTASHLPID_L] = '0 ;
rp_data[PKT_AWSTASHLPIDEN] = '0 ;
rp_data[PKT_MMUSECSID] = '0 ;
rp_data[PKT_MMUSID_H:PKT_MMUSID_L] = '0 ;
rp_data[PKT_DATALESS] = '0 ;
// By default, return all fields...
rp_data = rf_sink_data[ST_DATA_W - 1 : 0];
// ... and override specific fields.
rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0];
// Assignments directly from the response fifo.
rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED];
rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE];
rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L];
// Burst uncompressor assignments
rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address;
rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap;
rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt;
rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ];
rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed;
rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged;
rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize;
// bounce the original size back to the master untouched
rp_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L] = rf_sink_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L];
if (ROLE_BASED_USER || ENABLE_AXI5) begin
if(USE_PKT_DATACHK == 0)
rp_data[PKT_DATACHK_H:PKT_DATACHK_L] = calcParity(rdata_fifo_sink_data[AVS_DATA_W-1:0]);
else
rp_data[PKT_DATACHK_H:PKT_DATACHK_L] = '0;
rp_data[PKT_POISON_H:PKT_POISON_L] = '0;
rp_data[PKT_SAI_H:PKT_SAI_L] = '0;
end
if (ROLE_BASED_USER) begin
rp_data[PKT_ADDRCHK_H:PKT_ADDRCHK_L] = '0;
rp_data[PKT_USER_DATA_H:PKT_USER_DATA_L] = '0;
end
if(ENABLE_AXI5) begin
rp_data[PKT_TRACE] = '0;
end
end
// ------------------------------------------------------------------
// Note: the burst uncompressor may be asked to generate responses for
// write packets; these are treated the same as single-cycle uncompressed
// reads.
// ------------------------------------------------------------------
altera_merlin_burst_uncompressor #(
.ADDR_W (ADDR_W),
.BURSTWRAP_W (BURSTWRAP_W),
.BYTE_CNT_W (BYTE_CNT_W),
.PKT_SYMBOLS (PKT_SYMBOLS),
.BURST_SIZE_W (BURSTSIZE_W),
.SYNC_RESET (SYNC_RESET)
) uncompressor (
.clk (clk),
.reset (reset),
.sink_startofpacket (rf_sink_startofpacket_wire),
.sink_endofpacket (rf_sink_endofpacket),
.sink_valid ((rf_sink_valid & (rdata_fifo_sink_valid | generate_response))),
.sink_ready (rf_sink_ready),
.sink_addr (rf_sink_addr),
.sink_burstwrap (rf_sink_burstwrap),
.sink_byte_cnt (rf_sink_byte_cnt),
.sink_is_compressed (rf_sink_compressed),
.sink_burstsize (rf_sink_burstsize),
.source_startofpacket (rp_startofpacket),
.source_endofpacket (rp_endofpacket),
.source_valid (uncompressor_source_valid),
.source_ready (ready_for_response),
.source_addr (rp_address),
.source_burstwrap (rp_burstwrap),
.source_byte_cnt (burst_byte_cnt),
.source_is_compressed (rp_is_compressed),
.source_burstsize (uncompressor_burstsize)
);
//--------------------------------------
// Assertion: In case slave support response. The slave needs return response in order
// Ex: non-posted write followed by a read: write response must complete before read data
//--------------------------------------
// synthesis translate_off
ERROR_write_response_and_read_response_cannot_happen_same_time:
assert property ( @(posedge clk)
disable iff (reset) (reset === 0) |-> !(m0_writeresponsevalid_q && m0_readdatavalid_q)
);
// synthesis translate_on
endmodule
qsys/qsys_top/altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv
+383
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@@ -0,0 +1,383 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// ------------------------------------------
// Merlin Burst Uncompressor
//
// Compressed read bursts -> uncompressed
// ------------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_burst_uncompressor
#(
parameter ADDR_W = 16,
parameter BURSTWRAP_W = 3,
parameter BYTE_CNT_W = 4,
parameter PKT_SYMBOLS = 4,
parameter BURST_SIZE_W = 3,
parameter SYNC_RESET = 0,
parameter USED_IN_WIDTH_ADAPTER = 0
)
(
input clk,
input reset,
// sink ST signals
input sink_startofpacket,
input sink_endofpacket,
input sink_valid,
output sink_ready,
// sink ST "data"
input [ADDR_W - 1: 0] sink_addr,
input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
input sink_is_compressed,
input [BURST_SIZE_W-1 : 0] sink_burstsize,
// source ST signals
output source_startofpacket,
output source_endofpacket,
output source_valid,
input source_ready,
// source ST "data"
output [ADDR_W - 1: 0] source_addr,
output [BURSTWRAP_W - 1 : 0] source_burstwrap,
output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
// Note: in the slave agent, the output should always be uncompressed. In
// other applications, it may be required to leave-compressed or not. How to
// control? Seems like a simple mux - pass-through if no uncompression is
// required.
output source_is_compressed,
output [BURST_SIZE_W-1 : 0] source_burstsize
);
//----------------------------------------------------
// AXSIZE decoding
//
// Turns the axsize value into the actual number of bytes
// being transferred.
// ---------------------------------------------------
function reg[63:0] bytes_in_transfer;
input [BURST_SIZE_W-1:0] axsize;
case (axsize)
4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
endcase
endfunction
localparam LG_PKT_SYMBOLS = $clog2(PKT_SYMBOLS);
// num_symbols is PKT_SYMBOLS, appropriately sized.
wire [31:0] int_num_symbols;
if(USED_IN_WIDTH_ADAPTER)
assign int_num_symbols = (|sink_burstsize) ? PKT_SYMBOLS:1;
else
assign int_num_symbols = PKT_SYMBOLS;
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
// def: Burst Compression. In a merlin network, a compressed burst is one
// which is transmitted in a single beat. Example: read burst. In
// constrast, an uncompressed burst (example: write burst) is transmitted in
// one beat per writedata item.
//
// For compressed bursts which require response packets, burst
// uncompression is required. Concrete example: a read burst of size 8
// occupies one response-fifo position. When that fifo position reaches the
// front of the FIFO, the slave starts providing the required 8 readdatavalid
// pulses. The 8 return response beats must be provided in a single packet,
// with incrementing address and decrementing byte_cnt fields. Upon receipt
// of the final readdata item of the burst, the response FIFO item is
// retired.
// Burst uncompression logic provides:
// a) 2-state FSM (idle, busy)
// reset to idle state
// transition to busy state for 2nd and subsequent rdv pulses
// - a single-cycle burst (aka non-burst read) causes no transition to
// busy state.
// b) response startofpacket/endofpacket logic. The response FIFO item
// will have sop asserted, and may have eop asserted. (In the case of
// multiple read bursts transmit in the command fabric in a single packet,
// the eop assertion will come in a later FIFO item.) To support packet
// conservation, and emit a well-formed packet on the response fabric,
// i) response fabric startofpacket is asserted only for the first resp.
// beat;
// ii) response fabric endofpacket is asserted only for the last resp.
// beat.
// c) response address field. The response address field contains an
// incrementing sequence, such that each readdata item is associated with
// its slave-map location. N.b. a) computing the address correctly requires
// knowledge of burstwrap behavior b) there may be no clients of the address
// field, which makes this field a good target for optimization. See
// burst_uncompress_address_counter below.
// d) response byte_cnt field. The response byte_cnt field contains a
// decrementing sequence, such that each beat of the response contains the
// count of bytes to follow. In the case of sub-bursts in a single packet,
// the byte_cnt field may decrement down to num_symbols, then back up to
// some value, multiple times in the packet.
reg burst_uncompress_busy;
reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
wire first_packet_beat;
wire last_packet_beat;
assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
always @ (posedge clk) begin
if (source_valid & source_ready & sink_valid) begin
if(burst_uncompress_busy) begin
burst_uncompress_byte_counter_lint <= burst_uncompress_byte_counter_lint-num_symbols;
end else begin
burst_uncompress_byte_counter_lint <= sink_byte_cnt - num_symbols;
end
end
end
// First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
// the output.
assign source_byte_cnt =
first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
assign source_valid = sink_valid;
// Last packet beat is set throughout receipt of an uncompressed read burst
// from the response FIFO - this forces all the burst uncompression machinery
// idle.
assign last_packet_beat = ~sink_is_compressed |
(
burst_uncompress_busy ?
(sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
sink_valid & (sink_byte_cnt == num_symbols)
);
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
generate
if (SYNC_RESET == 0) begin : async_rst0
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_busy <= '0;
end
else begin
if (source_valid & source_ready & sink_valid) begin
// No matter what the current state, last_packet_beat leads to
// idle.
if (last_packet_beat) begin
burst_uncompress_busy <= '0;
end
else begin
burst_uncompress_busy <= 1'b1;
end
end
end
end
end // async_rst0
else begin // sync_rst0
always @(posedge clk ) begin
if (internal_sclr) begin
burst_uncompress_busy <= '0;
end
else begin
if (source_valid & source_ready & sink_valid) begin
// No matter what the current state, last_packet_beat leads to
// idle.
if (last_packet_beat) begin
burst_uncompress_busy <= '0;
end
else begin
burst_uncompress_busy <= 1'b1;
end
end
end
end
end // sync_rst0
endgenerate
//always @ (posedge clk) begin
// if (source_valid & source_ready & sink_valid) begin
// // No matter what the current state, last_packet_beat leads to
// // idle.
// if (last_packet_beat) begin
// burst_uncompress_byte_counter <= '0;
// end
// else begin
// if (burst_uncompress_busy) begin
// burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ?
// (burst_uncompress_byte_counter_lint[BYTE_CNT_W-1:LG_PKT_SYMBOLS] - num_symbols[BYTE_CNT_W-1:LG_PKT_SYMBOLS]) :
// (sink_byte_cnt[BYTE_CNT_W-1:LG_PKT_SYMBOLS] - num_symbols[BYTE_CNT_W-1:LG_PKT_SYMBOLS]);
// end
// else begin // not busy, at least one more beat to go
// burst_uncompress_byte_counter <= sink_byte_cnt[BYTE_CNT_W-1:LG_PKT_SYMBOLS] - num_symbols[BYTE_CNT_W-1:LG_PKT_SYMBOLS];
// // To do: should busy go true for numsymbols-size compressed
// // bursts?
// end
// end
// end
//end
reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
wire [63:0] decoded_burstsize_wire;
wire [ADDR_W-1:0] decoded_burstsize;
localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
// The input burstwrap value can be used as a mask against address values,
// but with one caveat: the address width may be (probably is) wider than
// the burstwrap width. The spec says: extend the msb of the burstwrap
// value out over the entire address width (but only if the address width
// actually is wider than the burstwrap width; otherwise it's a 0-width or
// negative range and concatenation multiplier).
generate
if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
// Sign-extend, just wires:
assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
{(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
end
else begin
assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
end
endgenerate
always @(posedge clk) begin
if (first_packet_beat & source_ready) begin
burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
end
end
//always @(posedge clk or posedge reset) begin
// if (reset) begin
// burst_uncompress_address_base <= '0;
// end
// else if (first_packet_beat & source_ready) begin
// burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
// end
//end
assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits
assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed
wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
(
(first_packet_beat ?
sink_addr :
burst_uncompress_address_offset) + decoded_burstsize
) &
addr_width_burstwrap[ADDR_W-1:0];
wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
always @ (posedge clk) begin
if (source_ready & source_valid) begin
burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
end
end
//always @(posedge clk or posedge reset) begin
// if (reset) begin
// burst_uncompress_address_offset <= '0;
// end
// else begin
// if (source_ready & source_valid) begin
// burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
// // if (first_packet_beat) begin
// // burst_uncompress_address_offset <=
// // (sink_addr + num_symbols) & addr_width_burstwrap;
// // end
// // else begin
// // burst_uncompress_address_offset <=
// // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
// // end
// end
// end
//end
// On the first packet beat, send the input address out unchanged,
// while values are computed/registered for 2nd and subsequent beats.
assign source_addr = first_packet_beat ? sink_addr :
burst_uncompress_address_base | burst_uncompress_address_offset;
assign source_burstwrap = sink_burstwrap;
assign source_burstsize = sink_burstsize;
//-------------------------------------------------------------------
// A single (compressed) read burst will have sop/eop in the same beat.
// A sequence of read sub-bursts emitted by a burst adapter in response to a
// single read burst will have sop on the first sub-burst, eop on the last.
// Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve
// packet conservation.
assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
assign source_endofpacket = sink_endofpacket & last_packet_beat;
assign sink_ready = source_valid & source_ready & last_packet_beat;
// This is correct for the slave agent usage, but won't always be true in the
// width adapter. To do: add an "please uncompress" input, and use it to
// pass-through or modify, and set source_is_compressed accordingly.
assign source_is_compressed = 1'b0;
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZlTuVjbs7t2AvXR8qtB5hlO4OP16VPo84MCPLx2rVhD1zQQWJ7B8d/ZQxcAh23irlYM5PRXVl1hzM1E9XBSwTHX4GiaPXc8KI87MAd2OBRsTVzQ3ploJyDTJ/5iLBZk4lL6RD0/o7jVPAsAA+iYoLIntesrKlzmNSO+ripXoEhypWMwRKSzgZZBPMMElLmdGOVkBpdGTg8XYKHFaxXioKDrffXWH12N3vtI6NzFHQfH/h77pcm8kqSxGEZzefHKCpgRsohq+zmawBPnqIEaklf3w9TR8wCComgJoehSxSSU/SoZucGVczKi/zpxAaV1C3ZvnYRs6KS3lwnftursubOcnVc54fiBCNX0o2tUlOGUN0MZVEhCByjyP7/tDDYHyz9Dyh5CcvlQ1SlPiN2bmCdVaKBDuFQGfnNX4iqkFXbtpf7KyNk9EwAzMRwGegjRDAqiYGeKBW/CfOtS6SxSn5LnfJyo1DRPBwBMYeT9gTB/CrgMTgZ+I0tO5pLPCNfpzFfaADXjL2aK7Oohy9lgFxUbDj3q5P1aPR2PeEeAnnBI1Cr9zvzuR1DljqKvMOVADEKuTYRh0CnptFzPRonyrUW0ISqpzVm4wrGeiVIWDlOU8I0E1VOdTB5G/FOYL7Ebbu+trxrk1HrXg+BTlfLX2HGtuX4biBJX3qBsyXItz0GnbOPIyN3bm3ZPkveSN7/nVnoPqYgXI5x9ilgczDHvSqU9mbmxiKhhU+AFIaVHUSBECnzRd5E6E34UW/Cxs92veqD6Z3nxWZyIP4Xab517bXhz"
`endif
qsys/qsys_top/altera_merlin_slave_agent_1930/synth/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv
+841
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@@ -0,0 +1,841 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ns / 1 ns
module qsys_top_altera_merlin_slave_agent_1930_jxauz3i
#(
// Packet parameters
parameter PKT_BEGIN_BURST = 81,
parameter PKT_DATA_H = 31,
parameter PKT_DATA_L = 0,
parameter PKT_SYMBOL_W = 8,
parameter PKT_BYTEEN_H = 71,
parameter PKT_BYTEEN_L = 68,
parameter PKT_ADDR_H = 63,
parameter PKT_ADDR_L = 32,
parameter PKT_TRANS_LOCK = 87,
parameter PKT_TRANS_COMPRESSED_READ = 67,
parameter PKT_TRANS_POSTED = 66,
parameter PKT_TRANS_WRITE = 65,
parameter PKT_TRANS_READ = 64,
parameter PKT_SRC_ID_H = 74,
parameter PKT_SRC_ID_L = 72,
parameter PKT_DEST_ID_H = 77,
parameter PKT_DEST_ID_L = 75,
parameter PKT_BURSTWRAP_H = 85,
parameter PKT_BURSTWRAP_L = 82,
parameter PKT_BYTE_CNT_H = 81,
parameter PKT_BYTE_CNT_L = 78,
parameter PKT_PROTECTION_H = 86,
parameter PKT_PROTECTION_L = 86,
parameter PKT_RESPONSE_STATUS_H = 89,
parameter PKT_RESPONSE_STATUS_L = 88,
parameter PKT_BURST_SIZE_H = 92,
parameter PKT_BURST_SIZE_L = 90,
parameter PKT_ORI_BURST_SIZE_L = 93,
parameter PKT_ORI_BURST_SIZE_H = 95,
parameter PKT_POISON_L = 97,
parameter PKT_POISON_H = 97,
parameter PKT_DATACHK_L = 98,
parameter PKT_DATACHK_H = 98,
parameter PKT_SAI_L = 99,
parameter PKT_SAI_H = 99,
parameter PKT_ADDRCHK_L = 100,
parameter PKT_ADDRCHK_H = 100,
parameter PKT_USER_DATA_L = 101,
parameter PKT_USER_DATA_H = 101,
parameter PKT_ATRACE = 102,
parameter PKT_TRACE = 103,
parameter PKT_AWAKEUP = 104,
//ACE5-Lite signals
parameter PKT_AWATOP_L = 154,
parameter PKT_AWATOP_H = 159,
parameter PKT_AWSTASHNID_L = 160,
parameter PKT_AWSTASHNID_H = 170,
parameter PKT_AWSTASHNIDEN = 171,
parameter PKT_AWSTASHLPID_L = 172,
parameter PKT_AWSTASHLPID_H = 176,
parameter PKT_AWSTASHLPIDEN = 177,
parameter PKT_MMUSECSID = 178,
parameter PKT_MMUSID_L = 179,
parameter PKT_MMUSID_H = 195,
parameter PKT_DATALESS = 196,
parameter ST_DATA_W = 102,
parameter ST_CHANNEL_W = 32,
parameter ROLE_BASED_USER = 0,
parameter ENABLE_AXI5 = 0,
parameter SYNC_RESET = 0,
parameter USE_PKT_DATACHK = 1,
// Slave parameters
parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
parameter AVS_BURSTCOUNT_W = 4,
parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W,
// Slave agent parameters
parameter USE_MEMORY_BLOCKS = 1,
parameter PREVENT_FIFO_OVERFLOW = 0,
parameter SUPPRESS_0_BYTEEN_CMD = 1,
parameter USE_READRESPONSE = 0,
parameter USE_WRITERESPONSE = 0,
// Derived slave parameters
parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
parameter BURST_SIZE_W = 3,
// Derived FIFO width
parameter FIFO_DATA_W = ST_DATA_W + 1,
// ECC parameter
parameter ECC_ENABLE = 0
) (
input clk,
input reset,
// Universal-Avalon anti-slave
output [ADDR_W-1:0] m0_address,
output [AVS_BURSTCOUNT_W-1:0] m0_burstcount,
output [AVS_BE_W-1:0] m0_byteenable,
output m0_read,
input [AVS_DATA_W-1:0] m0_readdata,
input m0_waitrequest,
output m0_write,
output [AVS_DATA_W-1:0] m0_writedata,
input m0_readdatavalid,
output m0_debugaccess,
output m0_lock,
input [1:0] m0_response,
input m0_writeresponsevalid,
// Avalon-ST FIFO interfaces.
// Note: there's no need to include the "data" field here, at least for
// reads, since readdata is filled in from slave info. To keep life
// simple, have a data field, but fill it with 0s.
// Av-st response fifo source interface
output reg [FIFO_DATA_W-1:0] rf_source_data,
output rf_source_valid,
output rf_source_startofpacket,
output rf_source_endofpacket,
input rf_source_ready,
// Av-st response fifo sink interface
input [FIFO_DATA_W-1:0] rf_sink_data,
input rf_sink_valid,
input rf_sink_startofpacket,
input rf_sink_endofpacket,
output reg rf_sink_ready,
// Av-st readdata fifo src interface, data and response
// extra 2 bits for storing RESPONSE STATUS
output [AVS_DATA_W+1:0] rdata_fifo_src_data,
output rdata_fifo_src_valid,
input rdata_fifo_src_ready,
// Av-st readdata fifo sink interface
input [AVS_DATA_W+1:0] rdata_fifo_sink_data,
input rdata_fifo_sink_valid,
output rdata_fifo_sink_ready,
input rdata_fifo_sink_error,
// Av-st sink command packet interface
output cp_ready,
input cp_valid,
input [ST_DATA_W-1:0] cp_data,
input [ST_CHANNEL_W-1:0] cp_channel,
input cp_startofpacket,
input cp_endofpacket,
// Av-st source response packet interface
input rp_ready,
output reg rp_valid,
output reg [ST_DATA_W-1:0] rp_data,
output rp_startofpacket,
output rp_endofpacket
);
// ------------------------------------------------
// Local Parameters
// ------------------------------------------------
localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1;
localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1;
localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1;
localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS);
localparam MAX_BURST = 1 << (AVS_BURSTCOUNT_W - 1);
localparam BURSTING = (MAX_BURST > PKT_SYMBOLS);
localparam PKT_DATACHK_W = DATA_W/8;
// --------------------------------------------------
// Ceil(log2()) function log2ceil of 4 = 2
// --------------------------------------------------
function integer log2ceil;
input reg[63:0] val;
reg [63:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
// --------------------------------------------------
// calcParity: calculates byte-level parity signal
// --------------------------------------------------
function reg [PKT_DATACHK_W-1:0] calcParity (
input [DATA_W-1:0] data
);
for (int i=0; i<PKT_DATACHK_W; i++)
calcParity[i] = ~(^ data[i*8 +:8]);
endfunction
// ------------------------------------------------
// Signals
// ------------------------------------------------
wire [DATA_W-1:0] cmd_data;
wire [BE_W-1:0] cmd_byteen;
wire [ADDR_W-1:0] cmd_addr;
wire [MID_W-1:0] cmd_mid;
wire [SID_W-1:0] cmd_sid;
wire cmd_read;
wire cmd_write;
wire cmd_compressed;
wire cmd_posted;
wire [BYTE_CNT_W-1:0] cmd_byte_cnt;
wire [BURSTWRAP_W-1:0] cmd_burstwrap;
wire [BURSTSIZE_W-1:0] cmd_burstsize;
wire cmd_debugaccess;
wire suppress_cmd;
wire byteen_asserted;
wire suppress_read;
wire suppress_write;
wire needs_response_synthesis;
wire generate_response;
//signals for additional latency due to different memory
wire [AVS_DATA_W-1:0] m0_readdata_q;
wire m0_readdatavalid_q;
wire [1:0] m0_response_q;
wire m0_writeresponsevalid_q;
reg [AVS_DATA_W-1:0] m0_readdata_1;
reg m0_readdatavalid_1;
reg [1:0] m0_response_1;
reg m0_writeresponsevalid_1;
reg [AVS_DATA_W-1:0] m0_readdata_2;
reg m0_readdatavalid_2;
reg [1:0] m0_response_2;
reg m0_writeresponsevalid_2;
// Assign command fields
assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ];
assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L];
assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ];
assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ];
assign cmd_posted = cp_data[PKT_TRANS_POSTED];
assign cmd_write = cp_data[PKT_TRANS_WRITE];
assign cmd_read = cp_data[PKT_TRANS_READ];
assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L];
assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
assign cmd_debugaccess = cp_data[PKT_PROTECTION_L];
// Local "ready_for_command" signal: deasserted when the agent is unable to accept
// another command, e.g. rdv FIFO is full, (local readdata storage is full &&
// ~rp_ready), ...
// Say, this could depend on the type of command, for example, even if the
// rdv FIFO is full, a write request can be accepted. For later.
wire ready_for_command;
wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK];
wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE];
wire local_read = cp_valid & cp_data[PKT_TRANS_READ];
wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ];
wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket;
// num_symbols is PKT_SYMBOLS, appropriately sized.
wire [31:0] int_num_symbols = PKT_SYMBOLS;
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
generate
if (SYNC_RESET ==0 ) begin : async0
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
m0_readdata_2 <= '0;
m0_readdatavalid_2 <= '0;
m0_response_2 <= '0;
m0_writeresponsevalid_2 <= '0;
end
else begin
m0_readdata_2 <= m0_readdata;
m0_readdatavalid_2 <= m0_readdatavalid;
m0_response_2 <= m0_response;
m0_writeresponsevalid_2 <= m0_writeresponsevalid;
end
end //@always_ff
end // async0
else begin :sync0
always_ff @(posedge clk) begin
if (internal_sclr) begin
m0_readdata_2 <= '0;
m0_readdatavalid_2 <= '0;
m0_response_2 <= '0;
m0_writeresponsevalid_2 <= '0;
end
else begin
m0_readdata_2 <= m0_readdata;
m0_readdatavalid_2 <= m0_readdatavalid;
m0_response_2 <= m0_response;
m0_writeresponsevalid_2 <= m0_writeresponsevalid;
end
end //@always_ff
end // sync0
endgenerate
generate
if (SYNC_RESET ==0 ) begin : async1
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
m0_readdata_1 <= '0;
m0_readdatavalid_1 <= '0;
m0_response_1 <= '0;
m0_writeresponsevalid_1 <= '0;
end
else begin
m0_readdata_1 <= m0_readdata_2;
m0_readdatavalid_1 <= m0_readdatavalid_2;
m0_response_1 <= m0_response_2;
m0_writeresponsevalid_1 <= m0_writeresponsevalid_2;
end
end //@always_ff
end // async1
else begin :sync1
always_ff @(posedge clk) begin
if (internal_sclr) begin
m0_readdata_1 <= '0;
m0_readdatavalid_1 <= '0;
m0_response_1 <= '0;
m0_writeresponsevalid_1 <= '0;
end
else begin
m0_readdata_1 <= m0_readdata_2;
m0_readdatavalid_1 <= m0_readdatavalid_2;
m0_response_1 <= m0_response_2;
m0_writeresponsevalid_1 <= m0_writeresponsevalid_2;
end
end //@always_ff
end // sync1
endgenerate
generate
if (USE_MEMORY_BLOCKS) begin : Using_M20k_with_2_clk_latency
assign m0_readdata_q = m0_readdata_1;
assign m0_readdatavalid_q = m0_readdatavalid_1;
assign m0_response_q = m0_response_1;
assign m0_writeresponsevalid_q = m0_writeresponsevalid_1;
end else begin : Using_ALM_memory_with_1_clk_latency
assign m0_readdata_q = m0_readdata;
assign m0_readdatavalid_q = m0_readdatavalid;
assign m0_response_q = m0_response;
assign m0_writeresponsevalid_q = m0_writeresponsevalid;
end
endgenerate
generate
if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow_block
// ---------------------------------------------------
// Backpressure if the slave says to, or if FIFO overflow may occur.
//
// All commands are backpressured once the FIFO is full
// even if they don't need storage. This breaks a long
// combinatorial path from the master read/write through
// this logic and back to the master via the backpressure
// path.
//
// To avoid a loss of throughput the FIFO will be parameterized
// one slot deeper. The extra slot should never be used in normal
// operation, but should a slave misbehave and accept one more
// read than it should then backpressure will kick in.
//
// An example: assume a slave with MPRT = 2. It can accept a
// command sequence RRWW without backpressuring. If the FIFO is
// only 2 deep, we'd backpressure the writes leading to loss of
// throughput. If the FIFO is 3 deep, we'll only backpressure when
// RRR... which is an illegal condition anyway.
// ---------------------------------------------------
assign ready_for_command = rf_source_ready;
assign cp_ready = (~m0_waitrequest | suppress_cmd) && ready_for_command;
end else begin : no_prevent_fifo_overflow_block
// Do not suppress the command or the slave will
// not be able to waitrequest
assign ready_for_command = 1'b1;
// Backpressure only if the slave says to.
assign cp_ready = ~m0_waitrequest | suppress_cmd;
end
endgenerate
generate if (SUPPRESS_0_BYTEEN_CMD && !BURSTING) begin : suppress_0_byteen_cmd_non_bursting
assign byteen_asserted = |cmd_byteen;
assign suppress_read = ~byteen_asserted;
assign suppress_write = ~byteen_asserted;
assign suppress_cmd = ~byteen_asserted;
end else if (SUPPRESS_0_BYTEEN_CMD && BURSTING) begin: suppress_0_byteen_cmd_bursting
assign byteen_asserted = |cmd_byteen;
assign suppress_read = ~byteen_asserted;
assign suppress_write = 1'b0;
assign suppress_cmd = ~byteen_asserted && cmd_read;
end else begin : no_suppress_0_byteen_cmd
assign suppress_read = 1'b0;
assign suppress_write = 1'b0;
assign suppress_cmd = 1'b0;
end
endgenerate
// -------------------------------------------------------------------
// Extract avalon signals from command packet.
// -------------------------------------------------------------------
// Mask off the lower bits of address.
// The burst adapter before this component will break narrow sized packets
// into sub-bursts of length 1. However, the packet addresses are preserved,
// which means this component may see size-aligned addresses.
//
// Masking ensures that the addresses seen by an Avalon slave are aligned to
// the full data width instead of the size.
//
// Example:
// output from burst adapter (datawidth=4, size=2 bytes):
// subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6
// expected output from slave agent:
// subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4
generate
if (BITS_TO_MASK > 0) begin : mask_address
if(ADDR_W == BITS_TO_MASK)
assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK-1], {BITS_TO_MASK-1{1'b0}} };
else
assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} };
end else begin : no_mask_address
assign m0_address = cmd_addr;
end
endgenerate
assign m0_byteenable = cmd_byteen;
assign m0_writedata = cmd_data;
// Note: no Avalon-MM slave in existence accepts uncompressed read bursts -
// this sort of burst exists only in merlin fabric ST packets. What to do
// if we see such a burst? All beats in that burst need to be transmitted
// to the slave so we have enough space-time for byteenable expression.
//
// There can be multiple bursts in a packet, but only one beat per burst
// in <most> cases. The exception is when we've decided not to insert a
// burst adapter for efficiency reasons, in which case this agent is also
// responsible for driving burstcount to 1 on each beat of an uncompressed
// read burst.
assign m0_read = ready_for_command & !suppress_read & (local_compressed_read | local_read);
generate
// AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount
// from a sub-range, or 0-pad, as appropriate.
if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin : m0_burstcount_zero_pad
wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}};
assign m0_burstcount = (local_read & ~local_compressed_read) ?
{zero_pad, num_symbols} :
{zero_pad, cmd_byte_cnt};
end
else begin : m0_burstcount_no_pad
assign m0_burstcount = (local_read & ~local_compressed_read) ?
num_symbols[AVS_BURSTCOUNT_W-1:0] :
cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0];
end
endgenerate
assign m0_write = ready_for_command & local_write & !suppress_write;
assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write);
assign m0_debugaccess = cmd_debugaccess;
// -------------------------------------------------------------------
// Indirection layer for response packet values. Some may always wire
// directly from the slave translator; others will no doubt emerge from
// various FIFOs.
// What to put in resp_data when a write occured? Answer: it does not
// matter, because only response status is needed for non-posted writes,
// and the packet already has a field for that.
//
// We use the rdata_fifo to store write responses as well. This allows us
// to handle backpressure on the response path, and allows write response
// merging.
assign rdata_fifo_src_valid = m0_readdatavalid_q | m0_writeresponsevalid_q;
assign rdata_fifo_src_data = {m0_response_q, m0_readdata_q};
// ------------------------------------------------------------------
// Generate a token when read commands are suppressed. The token
// is stored in the response FIFO, and will be used to synthesize
// a read response. The same token is used for non-posted write
// response synthesis.
//
// Note: this token is not generated for suppressed uncompressed read cycles;
// the burst uncompression logic at the read side of the response FIFO
// generates the correct number of responses.
//
// When the slave can return the response, let it do its job. Don't
// synthesize a response in that case, unless we've suppressed the
// the last transfer in a write sub-burst.
// ------------------------------------------------------------------
wire write_end_of_subburst;
assign needs_response_synthesis = ((local_read | local_compressed_read) & suppress_read) ||
(!USE_WRITERESPONSE && nonposted_write_endofpacket) ||
(USE_WRITERESPONSE && write_end_of_subburst && suppress_write);
// Avalon-ST interfaces to external response FIFO.
//
// For efficiency, when synthesizing a write response we only store a non-posted write
// transaction at its endofpacket, even if it was split into multiple sub-bursts.
//
// When not synthesizing write responses, we store each sub-burst in the FIFO.
// Each sub-burst to the slave will return a response, which corresponds to one
// entry in the FIFO. We merge all the sub-burst responses on the final
// sub-burst and send it on the response channel.
wire internal_cp_endofburst;
wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning
wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount;
assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0];
assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount);
assign write_end_of_subburst = local_write & internal_cp_endofburst;
assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && internal_cp_endofburst && local_write))
& ready_for_command & cp_ready;
assign rf_source_startofpacket = cp_startofpacket;
assign rf_source_endofpacket = cp_endofpacket;
always @* begin
// default: assign every command packet field to the response FIFO...
rf_source_data = {1'b0, cp_data};
// ... and override select fields as needed.
rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis;
rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}};
rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen;
rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr;
rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed;
rf_source_data[PKT_TRANS_POSTED] = cmd_posted;
rf_source_data[PKT_TRANS_WRITE] = cmd_write;
rf_source_data[PKT_TRANS_READ] = cmd_read;
rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid;
rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid;
rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt;
rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap;
rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize;
rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0;
rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess;
end
wire uncompressor_source_valid;
wire [BURSTSIZE_W-1:0] uncompressor_burstsize;
wire last_write_response;
// last_write_response indicates the last response of the broken-up write burst (sub-bursts).
// At this time, the final merged response is sent, and rp_valid is only asserted
// once for the whole burst.
generate
if (USE_WRITERESPONSE) begin
assign last_write_response = rf_sink_data[PKT_TRANS_WRITE] & rf_sink_endofpacket;
always @* begin
if (rf_sink_data[PKT_TRANS_WRITE] == 1)
rp_valid = ((rdata_fifo_sink_valid | generate_response) & last_write_response & !rf_sink_data[PKT_TRANS_POSTED]);
else
rp_valid = (rdata_fifo_sink_valid | uncompressor_source_valid);
end
end else begin
assign last_write_response = 1'b0;
always @* begin
rp_valid = (rdata_fifo_sink_valid | uncompressor_source_valid);
end
end
endgenerate
// ------------------------------------------------------------------
// Response merging
// ------------------------------------------------------------------
reg [1:0] current_response;
reg [1:0] response_merged;
generate
if (USE_WRITERESPONSE) begin : response_merging_all
reg first_write_response;
reg reset_merged_output;
reg [1:0] previous_response_in;
reg [1:0] previous_response;
if (SYNC_RESET ==0 ) begin : async_reg0
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
first_write_response <= 1'b1;
end
else begin // Merging work for write response, for read: previous_response_in = current_response
if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin
first_write_response <= 1'b0;
if (rf_sink_endofpacket)
first_write_response <= 1'b1;
end
end
end //@always_ff
end // async_reg0
else begin :sync_reg0
always_ff @(posedge clk) begin
if (internal_sclr) begin
first_write_response <= 1'b1;
end
else begin // Merging work for write response, for read: previous_response_in = current_response
if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin
first_write_response <= 1'b0;
if (rf_sink_endofpacket)
first_write_response <= 1'b1;
end
end
end //@always_ff
end // sync_reg0
always_comb begin
current_response = generate_response ? 2'b00 : rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | {2{rdata_fifo_sink_error}};
reset_merged_output = first_write_response && (rdata_fifo_sink_valid || generate_response);
previous_response_in = reset_merged_output ? current_response : previous_response;
response_merged = current_response >= previous_response ? current_response: previous_response_in;
end
if (SYNC_RESET == 0) begin : async_reg1
always_ff @(posedge clk or posedge reset) begin
if (reset) begin
previous_response <= 2'b00;
end
else begin
if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin
previous_response <= response_merged;
end
end
end
end // async_reg1
else begin : sync_reg1
always_ff @(posedge clk ) begin
if (internal_sclr) begin
previous_response <= 2'b00;
end
else begin
if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin
previous_response <= response_merged;
end
end
end
end // sync_reg1
end else begin : response_merging_read_only
always @* begin
current_response = generate_response ? 2'b00: rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] |
{2{rdata_fifo_sink_error}};
response_merged = current_response;
end
end
endgenerate
assign generate_response = rf_sink_data[FIFO_DATA_W-1];
wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ];
wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L];
// a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo
wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket;
wire [BYTE_CNT_W-1:0] burst_byte_cnt;
wire [BURSTWRAP_W-1:0] rp_burstwrap;
wire [ADDR_W-1:0] rp_address;
wire rp_is_compressed;
wire ready_for_response;
// ------------------------------------------------------------------
// We're typically ready for a response if the network is ready. There
// is one exception:
//
// If the slave issues write responses, we only issue a merged response on
// the final sub-burst. As a result, we only care about response channel
// availability on the final burst when we send out the merged response.
// ------------------------------------------------------------------
assign ready_for_response = (USE_WRITERESPONSE) ?
rp_ready || (rf_sink_data[PKT_TRANS_WRITE] && !last_write_response) || rf_sink_data[PKT_TRANS_POSTED]:
rp_ready;
// ------------------------------------------------------------------
// Backpressure the readdata fifo if we're supposed to synthesize a response.
// This may be a read response (for suppressed reads) or a write response
// (for non-posted writes).
// ------------------------------------------------------------------
assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & ready_for_response & ~(rf_sink_valid & generate_response);
always @* begin
rp_data[PKT_AWATOP_H:PKT_AWATOP_L] = '0 ;
rp_data[PKT_AWSTASHNID_H:PKT_AWSTASHNID_L] = '0 ;
rp_data[PKT_AWSTASHNIDEN] = '0 ;
rp_data[PKT_AWSTASHLPID_H:PKT_AWSTASHLPID_L] = '0 ;
rp_data[PKT_AWSTASHLPIDEN] = '0 ;
rp_data[PKT_MMUSECSID] = '0 ;
rp_data[PKT_MMUSID_H:PKT_MMUSID_L] = '0 ;
rp_data[PKT_DATALESS] = '0 ;
// By default, return all fields...
rp_data = rf_sink_data[ST_DATA_W - 1 : 0];
// ... and override specific fields.
rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0];
// Assignments directly from the response fifo.
rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED];
rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE];
rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L];
// Burst uncompressor assignments
rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address;
rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap;
rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt;
rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ];
rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed;
rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged;
rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize;
// bounce the original size back to the master untouched
rp_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L] = rf_sink_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L];
if (ROLE_BASED_USER || ENABLE_AXI5) begin
if(USE_PKT_DATACHK == 0)
rp_data[PKT_DATACHK_H:PKT_DATACHK_L] = calcParity(rdata_fifo_sink_data[AVS_DATA_W-1:0]);
else
rp_data[PKT_DATACHK_H:PKT_DATACHK_L] = '0;
rp_data[PKT_POISON_H:PKT_POISON_L] = '0;
rp_data[PKT_SAI_H:PKT_SAI_L] = '0;
end
if (ROLE_BASED_USER) begin
rp_data[PKT_ADDRCHK_H:PKT_ADDRCHK_L] = '0;
rp_data[PKT_USER_DATA_H:PKT_USER_DATA_L] = '0;
end
if(ENABLE_AXI5) begin
rp_data[PKT_TRACE] = '0;
end
end
// ------------------------------------------------------------------
// Note: the burst uncompressor may be asked to generate responses for
// write packets; these are treated the same as single-cycle uncompressed
// reads.
// ------------------------------------------------------------------
altera_merlin_burst_uncompressor #(
.ADDR_W (ADDR_W),
.BURSTWRAP_W (BURSTWRAP_W),
.BYTE_CNT_W (BYTE_CNT_W),
.PKT_SYMBOLS (PKT_SYMBOLS),
.BURST_SIZE_W (BURSTSIZE_W),
.SYNC_RESET (SYNC_RESET)
) uncompressor (
.clk (clk),
.reset (reset),
.sink_startofpacket (rf_sink_startofpacket_wire),
.sink_endofpacket (rf_sink_endofpacket),
.sink_valid ((rf_sink_valid & (rdata_fifo_sink_valid | generate_response))),
.sink_ready (rf_sink_ready),
.sink_addr (rf_sink_addr),
.sink_burstwrap (rf_sink_burstwrap),
.sink_byte_cnt (rf_sink_byte_cnt),
.sink_is_compressed (rf_sink_compressed),
.sink_burstsize (rf_sink_burstsize),
.source_startofpacket (rp_startofpacket),
.source_endofpacket (rp_endofpacket),
.source_valid (uncompressor_source_valid),
.source_ready (ready_for_response),
.source_addr (rp_address),
.source_burstwrap (rp_burstwrap),
.source_byte_cnt (burst_byte_cnt),
.source_is_compressed (rp_is_compressed),
.source_burstsize (uncompressor_burstsize)
);
//--------------------------------------
// Assertion: In case slave support response. The slave needs return response in order
// Ex: non-posted write followed by a read: write response must complete before read data
//--------------------------------------
// synthesis translate_off
ERROR_write_response_and_read_response_cannot_happen_same_time:
assert property ( @(posedge clk)
disable iff (reset) (reset === 0) |-> !(m0_writeresponsevalid_q && m0_readdatavalid_q)
);
// synthesis translate_on
endmodule
qsys/qsys_top/altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv
+666
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// -------------------------------------
// Merlin Slave Translator
//
// Translates Universal Avalon MM Slave
// to any Avalon MM Slave
// -------------------------------------
//
//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
//The key feature here is that no same cycle turnaround data is processed through the fabric.
//import avalon_utilities_pkg::*;
`timescale 1 ns / 1 ns
module qsys_top_altera_merlin_slave_translator_191_xg7rzxi #(
parameter
//Widths
AV_ADDRESS_W = 32,
AV_DATA_W = 32,
AV_BURSTCOUNT_W = 4,
AV_BYTEENABLE_W = 4,
UAV_BYTEENABLE_W = 4,
//Read Latency
AV_READLATENCY = 1,
//Timing
AV_READ_WAIT_CYCLES = 0,
AV_WRITE_WAIT_CYCLES = 0,
AV_SETUP_WAIT_CYCLES = 0,
AV_DATA_HOLD_CYCLES = 0,
//Optional Port Declarations
USE_READDATAVALID = 1,
USE_WAITREQUEST = 1,
USE_READRESPONSE = 0,
USE_WRITERESPONSE = 0,
//Variable Addressing
AV_SYMBOLS_PER_WORD = 4,
AV_ADDRESS_SYMBOLS = 0,
AV_BURSTCOUNT_SYMBOLS = 0,
BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
UAV_ADDRESS_W = 38,
UAV_BURSTCOUNT_W = 10,
UAV_DATA_W = 32,
AV_CONSTANT_BURST_BEHAVIOR = 0,
UAV_CONSTANT_BURST_BEHAVIOR = 0,
CHIPSELECT_THROUGH_READLATENCY = 0,
// Tightly-Coupled Options
USE_UAV_CLKEN = 0,
AV_REQUIRE_UNALIGNED_ADDRESSES = 0,
WAITREQUEST_ALLOWANCE = 0,
SYNC_RESET = 0
) (
// -------------------
// Clock & Reset
// -------------------
input wire clk,
input wire reset,
// -------------------
// Universal Avalon Slave
// -------------------
input wire [UAV_ADDRESS_W - 1 : 0] uav_address,
input wire [UAV_DATA_W - 1 : 0] uav_writedata,
input wire uav_write,
input wire uav_read,
input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount,
input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable,
input wire uav_lock,
input wire uav_debugaccess,
input wire uav_clken,
output logic uav_readdatavalid,
output logic uav_waitrequest,
output logic [UAV_DATA_W - 1 : 0] uav_readdata,
output logic [1:0] uav_response,
// input wire uav_writeresponserequest,
output logic uav_writeresponsevalid,
// -------------------
// Customizable Avalon Master
// -------------------
output logic [AV_ADDRESS_W - 1 : 0] av_address,
output logic [AV_DATA_W - 1 : 0] av_writedata,
output logic av_write,
output logic av_read,
output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
output logic av_begintransfer,
output wire av_chipselect,
output logic av_beginbursttransfer,
output logic av_lock,
output wire av_clken,
output wire av_debugaccess,
output wire av_outputenable,
input logic [AV_DATA_W - 1 : 0] av_readdata,
input logic av_readdatavalid,
input logic av_waitrequest,
input logic [1:0] av_response,
// output logic av_writeresponserequest,
input wire av_writeresponsevalid
);
function integer clog2_plusone;
input [31:0] Depth;
integer i;
begin
i = Depth;
for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
i = i >> 1;
end
endfunction
function integer max;
//returns the larger of two passed arguments
input [31:0] one;
input [31:0] two;
if(one > two)
max=one;
else
max=two;
endfunction // int
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
AV_ADDRESS_W :
UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
AV_BURSTCOUNT_W :
UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
// Calculate the symbols per word as the power of 2 extended symbols per word
wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
// +--------------------------------
// |Backwards Compatibility Signals
// +--------------------------------
assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
assign av_debugaccess = uav_debugaccess;
// +-------------------
// |Passthru Signals
// +-------------------
reg [1 : 0] av_response_delayed;
generate
if (SYNC_RESET == 0) begin : async_reg0
always @(posedge clk, posedge reset) begin
if (reset) begin
av_response_delayed <= 2'b0;
end else begin
av_response_delayed <= av_response;
end
end
end // async_reg0
else begin // sync_reg0
always @(posedge clk) begin
if (internal_sclr) begin
av_response_delayed <= 2'b0;
end else begin
av_response_delayed <= av_response;
end
end
end //sync_reg0
endgenerate
always_comb
begin
if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
uav_response = '0;
end else begin
if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
uav_response = av_response;
end else begin
uav_response = av_response_delayed;
end
end
end
// assign av_writeresponserequest = uav_writeresponserequest;
assign uav_writeresponsevalid = av_writeresponsevalid;
//-------------------------
//Writedata and Byteenable
//-------------------------
always@* begin
av_byteenable = '0;
av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
end
always@* begin
av_writedata = '0;
av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
end
// +-------------------
// |Calculated Signals
// +-------------------
logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
if(byteenable[i] == 1) begin
return i;
end
end
return '0;
endfunction
reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
reg [AV_ADDRESS_W - 1 : 0] address_reg;
generate
if (SYNC_RESET == 0) begin : async_reg1
always@(posedge clk, posedge reset) begin
if(reset) begin
burstcount_reg <= '0;
address_reg <= '0;
end else begin
burstcount_reg <= burstcount_reg;
address_reg <= address_reg;
if(av_beginbursttransfer) begin
burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
if (UAV_ADDRESS_W == ADDRESS_SHIFT_SELECTOR && (UAV_ADDRESS_W < AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR))
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR -1];
else
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
end
end
end
end //async_reg1
else begin // sync_reg1
always@(posedge clk) begin
if(internal_sclr) begin
burstcount_reg <= '0;
address_reg <= '0;
end else begin
burstcount_reg <= burstcount_reg;
address_reg <= address_reg;
if(av_beginbursttransfer) begin
burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
if (UAV_ADDRESS_W == ADDRESS_SHIFT_SELECTOR && (UAV_ADDRESS_W < AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR))
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR -1];
else
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
end
end
end
end // sync_reg1
endgenerate
logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
always@* begin
if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
temp_wire = decode_byteenable(uav_byteenable);
real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
end else begin
real_uav_address = uav_address;
end
if (UAV_ADDRESS_W == ADDRESS_SHIFT_SELECTOR && (UAV_ADDRESS_W < AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR))
av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR -1];
else
av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
av_address = address_reg;
end
always@* begin
av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
av_burstcount = burstcount_reg;
end
always@* begin
av_lock = uav_lock;
end
// -------------------
// Writebyteenable Assignment
// -------------------
always@* begin
av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
end
// -------------------
// Waitrequest Assignment
// -------------------
reg av_waitrequest_generated;
reg av_waitrequest_generated_read;
reg av_waitrequest_generated_write;
reg waitrequest_reset_override;
reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
generate
if (SYNC_RESET == 0) begin: async_reg2
always@(posedge reset, posedge clk) begin
if(reset) begin
wait_latency_counter <= '0;
waitrequest_reset_override <= 1'h1;
end else begin
waitrequest_reset_override <= 1'h0;
wait_latency_counter <= '0;
if( ~uav_waitrequest | waitrequest_reset_override )
wait_latency_counter <= '0;
else if( uav_read | uav_write )
wait_latency_counter <= wait_latency_counter + 1'h1;
end
end
end // async_reg2
else begin // sync_reg2
always@(posedge clk) begin
if(internal_sclr) begin
wait_latency_counter <= '0;
waitrequest_reset_override <= 1'h1;
end else begin
waitrequest_reset_override <= 1'h0;
wait_latency_counter <= '0;
if( ~uav_waitrequest | waitrequest_reset_override )
wait_latency_counter <= '0;
else if( uav_read | uav_write )
wait_latency_counter <= wait_latency_counter + 1'h1;
end
end
end // sync_reg2
endgenerate
always @* begin
av_read = uav_read;
av_write = uav_write;
av_waitrequest_generated = 1'h1;
av_waitrequest_generated_read = 1'h1;
av_waitrequest_generated_write = 1'h1;
if(LOG2_OF_LATENCY_SUM == 1)
av_waitrequest_generated = 0;
if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
if(uav_write)
av_waitrequest_generated = av_waitrequest_generated_write;
else
av_waitrequest_generated = av_waitrequest_generated_read;
end
if(USE_WAITREQUEST) begin
uav_waitrequest = av_waitrequest;
end else begin
uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
end
end
// --------------
// Readdata Assignment
// --------------
reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
generate
if (SYNC_RESET == 0) begin:async_reg3
always@(posedge clk, posedge reset) begin
if(reset)
av_readdata_pre <= 'b0;
else
av_readdata_pre <= av_readdata;
end
end // async_reg3
else begin //sync_reg3
always@(posedge clk) begin
if(internal_sclr)
av_readdata_pre <= 'b0;
else
av_readdata_pre <= av_readdata;
end
end //sync_reg3
endgenerate
always@* begin
uav_readdata = {UAV_DATA_W{1'b0}};
if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin
uav_readdata[AV_DATA_W-1:0] = av_readdata;
end else begin
uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
end
end
// -------------------
// Readdatavalid Assigment
// -------------------
reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
reg top_read_latency_shift_reg;
always@* begin
uav_readdatavalid=top_read_latency_shift_reg;
if(USE_READDATAVALID) begin
uav_readdatavalid = av_readdatavalid;
end
end
always@* begin
top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
top_read_latency_shift_reg=read_latency_shift_reg;
end
if (AV_READLATENCY > 1) begin
top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
end
end
generate
if (SYNC_RESET == 0) begin : async_reg4
always@(posedge reset, posedge clk) begin
if (reset) begin
read_latency_shift_reg <= '0;
end else if (av_clken) begin
read_latency_shift_reg[0] <= (WAITREQUEST_ALLOWANCE == 0) ? uav_read && ~uav_waitrequest & ~waitrequest_reset_override
: uav_read;
for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
end
end
end
end // async_reg4
else begin //sync_reg4
always@(posedge clk) begin
if (internal_sclr) begin
read_latency_shift_reg <= '0;
end else if (av_clken) begin
read_latency_shift_reg[0] <= (WAITREQUEST_ALLOWANCE == 0) ? uav_read && ~uav_waitrequest & ~waitrequest_reset_override
: uav_read;
for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
end
end
end
end //sync_reg4
endgenerate
// ------------
// Chipselect and OutputEnable
// ------------
reg av_chipselect_pre;
wire cs_extension;
reg av_outputenable_pre;
assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
generate
if (SYNC_RESET == 0) begin :async_reg5
always@(posedge reset, posedge clk) begin
if(reset)
av_outputenable_pre <= 1'b0;
else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
av_outputenable_pre <= 0;
else
av_outputenable_pre <= cs_extension | uav_read;
end
end //async_reg5
else begin // sync_reg5
always@(posedge clk) begin
if(internal_sclr)
av_outputenable_pre <= 1'b0;
else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
av_outputenable_pre <= 0;
else
av_outputenable_pre <= cs_extension | uav_read;
end
end // sync_reg5
endgenerate
generate
if (SYNC_RESET == 0) begin :async_reg6
always@(posedge reset, posedge clk) begin
if(reset) begin
av_chipselect_pre <= 1'b0;
end else begin
av_chipselect_pre <= 1'b0;
if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
//The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
//There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
if(uav_read) begin
av_chipselect_pre <= 1'b1;
end else if(cs_extension == 1) begin
av_chipselect_pre <= 1'b1;
end
end
end
end
end // async_reg6
else begin // sync_reg6
always@(posedge clk) begin
if(internal_sclr) begin
av_chipselect_pre <= 1'b0;
end else begin
av_chipselect_pre <= 1'b0;
if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
//The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
//There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
if(uav_read) begin
av_chipselect_pre <= 1'b1;
end else if(cs_extension == 1) begin
av_chipselect_pre <= 1'b1;
end
end
end
end
end //sync_reg6
endgenerate
// -------------------
// Begintransfer Assigment
// -------------------
reg end_begintransfer;
always@* begin
if(WAITREQUEST_ALLOWANCE == 0) begin
av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
end
else begin
av_begintransfer = ( uav_write | uav_read );
end
end
generate
if (SYNC_RESET == 0) begin :async_reg7
always@ ( posedge clk or posedge reset ) begin
if(reset) begin
end_begintransfer <= 1'b0;
end else begin
if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
end_begintransfer <= 1'b1;
else if(uav_waitrequest)
end_begintransfer <= end_begintransfer;
else
end_begintransfer <= 1'b0;
end
end
end // async_reg7
else begin // sync_reg7
always@ ( posedge clk ) begin
if(internal_sclr) begin
end_begintransfer <= 1'b0;
end else begin
if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
end_begintransfer <= 1'b1;
else if(uav_waitrequest)
end_begintransfer <= end_begintransfer;
else
end_begintransfer <= 1'b0;
end
end
end //sync_reg7
endgenerate
// -------------------
// Beginbursttransfer Assigment
// -------------------
reg end_beginbursttransfer;
reg in_transfer;
always@* begin
av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
end
generate
if (SYNC_RESET == 0 ) begin : async_reg8
always@ ( posedge clk or posedge reset ) begin
if(reset) begin
end_beginbursttransfer <= 1'b0;
in_transfer <= 1'b0;
end else begin
end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
if(uav_write && uav_burstcount == symbols_per_word)
in_transfer <=1'b0;
else if(uav_write)
in_transfer <=1'b1;
end
end
end // async_reg8
else begin //sync_reg8
always@ ( posedge clk ) begin
if(internal_sclr) begin
end_beginbursttransfer <= 1'b0;
in_transfer <= 1'b0;
end else begin
end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
if(uav_write && uav_burstcount == symbols_per_word)
in_transfer <=1'b0;
else if(uav_write)
in_transfer <=1'b1;
end
end
end //sync_reg8
endgenerate
endmodule
qsys/qsys_top/altera_merlin_slave_translator_191/synth/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv
+666
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// -------------------------------------
// Merlin Slave Translator
//
// Translates Universal Avalon MM Slave
// to any Avalon MM Slave
// -------------------------------------
//
//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
//The key feature here is that no same cycle turnaround data is processed through the fabric.
//import avalon_utilities_pkg::*;
`timescale 1 ns / 1 ns
module qsys_top_altera_merlin_slave_translator_191_xg7rzxi #(
parameter
//Widths
AV_ADDRESS_W = 32,
AV_DATA_W = 32,
AV_BURSTCOUNT_W = 4,
AV_BYTEENABLE_W = 4,
UAV_BYTEENABLE_W = 4,
//Read Latency
AV_READLATENCY = 1,
//Timing
AV_READ_WAIT_CYCLES = 0,
AV_WRITE_WAIT_CYCLES = 0,
AV_SETUP_WAIT_CYCLES = 0,
AV_DATA_HOLD_CYCLES = 0,
//Optional Port Declarations
USE_READDATAVALID = 1,
USE_WAITREQUEST = 1,
USE_READRESPONSE = 0,
USE_WRITERESPONSE = 0,
//Variable Addressing
AV_SYMBOLS_PER_WORD = 4,
AV_ADDRESS_SYMBOLS = 0,
AV_BURSTCOUNT_SYMBOLS = 0,
BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
UAV_ADDRESS_W = 38,
UAV_BURSTCOUNT_W = 10,
UAV_DATA_W = 32,
AV_CONSTANT_BURST_BEHAVIOR = 0,
UAV_CONSTANT_BURST_BEHAVIOR = 0,
CHIPSELECT_THROUGH_READLATENCY = 0,
// Tightly-Coupled Options
USE_UAV_CLKEN = 0,
AV_REQUIRE_UNALIGNED_ADDRESSES = 0,
WAITREQUEST_ALLOWANCE = 0,
SYNC_RESET = 0
) (
// -------------------
// Clock & Reset
// -------------------
input wire clk,
input wire reset,
// -------------------
// Universal Avalon Slave
// -------------------
input wire [UAV_ADDRESS_W - 1 : 0] uav_address,
input wire [UAV_DATA_W - 1 : 0] uav_writedata,
input wire uav_write,
input wire uav_read,
input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount,
input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable,
input wire uav_lock,
input wire uav_debugaccess,
input wire uav_clken,
output logic uav_readdatavalid,
output logic uav_waitrequest,
output logic [UAV_DATA_W - 1 : 0] uav_readdata,
output logic [1:0] uav_response,
// input wire uav_writeresponserequest,
output logic uav_writeresponsevalid,
// -------------------
// Customizable Avalon Master
// -------------------
output logic [AV_ADDRESS_W - 1 : 0] av_address,
output logic [AV_DATA_W - 1 : 0] av_writedata,
output logic av_write,
output logic av_read,
output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
output logic av_begintransfer,
output wire av_chipselect,
output logic av_beginbursttransfer,
output logic av_lock,
output wire av_clken,
output wire av_debugaccess,
output wire av_outputenable,
input logic [AV_DATA_W - 1 : 0] av_readdata,
input logic av_readdatavalid,
input logic av_waitrequest,
input logic [1:0] av_response,
// output logic av_writeresponserequest,
input wire av_writeresponsevalid
);
function integer clog2_plusone;
input [31:0] Depth;
integer i;
begin
i = Depth;
for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
i = i >> 1;
end
endfunction
function integer max;
//returns the larger of two passed arguments
input [31:0] one;
input [31:0] two;
if(one > two)
max=one;
else
max=two;
endfunction // int
// Generation of internal reset synchronization
reg internal_sclr;
generate if (SYNC_RESET == 1) begin : rst_syncronizer
always @ (posedge clk) begin
internal_sclr <= reset;
end
end
endgenerate
localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
AV_ADDRESS_W :
UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
AV_BURSTCOUNT_W :
UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
// Calculate the symbols per word as the power of 2 extended symbols per word
wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
// +--------------------------------
// |Backwards Compatibility Signals
// +--------------------------------
assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
assign av_debugaccess = uav_debugaccess;
// +-------------------
// |Passthru Signals
// +-------------------
reg [1 : 0] av_response_delayed;
generate
if (SYNC_RESET == 0) begin : async_reg0
always @(posedge clk, posedge reset) begin
if (reset) begin
av_response_delayed <= 2'b0;
end else begin
av_response_delayed <= av_response;
end
end
end // async_reg0
else begin // sync_reg0
always @(posedge clk) begin
if (internal_sclr) begin
av_response_delayed <= 2'b0;
end else begin
av_response_delayed <= av_response;
end
end
end //sync_reg0
endgenerate
always_comb
begin
if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
uav_response = '0;
end else begin
if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
uav_response = av_response;
end else begin
uav_response = av_response_delayed;
end
end
end
// assign av_writeresponserequest = uav_writeresponserequest;
assign uav_writeresponsevalid = av_writeresponsevalid;
//-------------------------
//Writedata and Byteenable
//-------------------------
always@* begin
av_byteenable = '0;
av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
end
always@* begin
av_writedata = '0;
av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
end
// +-------------------
// |Calculated Signals
// +-------------------
logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
if(byteenable[i] == 1) begin
return i;
end
end
return '0;
endfunction
reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
reg [AV_ADDRESS_W - 1 : 0] address_reg;
generate
if (SYNC_RESET == 0) begin : async_reg1
always@(posedge clk, posedge reset) begin
if(reset) begin
burstcount_reg <= '0;
address_reg <= '0;
end else begin
burstcount_reg <= burstcount_reg;
address_reg <= address_reg;
if(av_beginbursttransfer) begin
burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
if (UAV_ADDRESS_W == ADDRESS_SHIFT_SELECTOR && (UAV_ADDRESS_W < AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR))
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR -1];
else
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
end
end
end
end //async_reg1
else begin // sync_reg1
always@(posedge clk) begin
if(internal_sclr) begin
burstcount_reg <= '0;
address_reg <= '0;
end else begin
burstcount_reg <= burstcount_reg;
address_reg <= address_reg;
if(av_beginbursttransfer) begin
burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
if (UAV_ADDRESS_W == ADDRESS_SHIFT_SELECTOR && (UAV_ADDRESS_W < AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR))
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR -1];
else
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
end
end
end
end // sync_reg1
endgenerate
logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
always@* begin
if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
temp_wire = decode_byteenable(uav_byteenable);
real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
end else begin
real_uav_address = uav_address;
end
if (UAV_ADDRESS_W == ADDRESS_SHIFT_SELECTOR && (UAV_ADDRESS_W < AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR))
av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR -1];
else
av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
av_address = address_reg;
end
always@* begin
av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
av_burstcount = burstcount_reg;
end
always@* begin
av_lock = uav_lock;
end
// -------------------
// Writebyteenable Assignment
// -------------------
always@* begin
av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
end
// -------------------
// Waitrequest Assignment
// -------------------
reg av_waitrequest_generated;
reg av_waitrequest_generated_read;
reg av_waitrequest_generated_write;
reg waitrequest_reset_override;
reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
generate
if (SYNC_RESET == 0) begin: async_reg2
always@(posedge reset, posedge clk) begin
if(reset) begin
wait_latency_counter <= '0;
waitrequest_reset_override <= 1'h1;
end else begin
waitrequest_reset_override <= 1'h0;
wait_latency_counter <= '0;
if( ~uav_waitrequest | waitrequest_reset_override )
wait_latency_counter <= '0;
else if( uav_read | uav_write )
wait_latency_counter <= wait_latency_counter + 1'h1;
end
end
end // async_reg2
else begin // sync_reg2
always@(posedge clk) begin
if(internal_sclr) begin
wait_latency_counter <= '0;
waitrequest_reset_override <= 1'h1;
end else begin
waitrequest_reset_override <= 1'h0;
wait_latency_counter <= '0;
if( ~uav_waitrequest | waitrequest_reset_override )
wait_latency_counter <= '0;
else if( uav_read | uav_write )
wait_latency_counter <= wait_latency_counter + 1'h1;
end
end
end // sync_reg2
endgenerate
always @* begin
av_read = uav_read;
av_write = uav_write;
av_waitrequest_generated = 1'h1;
av_waitrequest_generated_read = 1'h1;
av_waitrequest_generated_write = 1'h1;
if(LOG2_OF_LATENCY_SUM == 1)
av_waitrequest_generated = 0;
if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
if(uav_write)
av_waitrequest_generated = av_waitrequest_generated_write;
else
av_waitrequest_generated = av_waitrequest_generated_read;
end
if(USE_WAITREQUEST) begin
uav_waitrequest = av_waitrequest;
end else begin
uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
end
end
// --------------
// Readdata Assignment
// --------------
reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
generate
if (SYNC_RESET == 0) begin:async_reg3
always@(posedge clk, posedge reset) begin
if(reset)
av_readdata_pre <= 'b0;
else
av_readdata_pre <= av_readdata;
end
end // async_reg3
else begin //sync_reg3
always@(posedge clk) begin
if(internal_sclr)
av_readdata_pre <= 'b0;
else
av_readdata_pre <= av_readdata;
end
end //sync_reg3
endgenerate
always@* begin
uav_readdata = {UAV_DATA_W{1'b0}};
if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin
uav_readdata[AV_DATA_W-1:0] = av_readdata;
end else begin
uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
end
end
// -------------------
// Readdatavalid Assigment
// -------------------
reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
reg top_read_latency_shift_reg;
always@* begin
uav_readdatavalid=top_read_latency_shift_reg;
if(USE_READDATAVALID) begin
uav_readdatavalid = av_readdatavalid;
end
end
always@* begin
top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
top_read_latency_shift_reg=read_latency_shift_reg;
end
if (AV_READLATENCY > 1) begin
top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
end
end
generate
if (SYNC_RESET == 0) begin : async_reg4
always@(posedge reset, posedge clk) begin
if (reset) begin
read_latency_shift_reg <= '0;
end else if (av_clken) begin
read_latency_shift_reg[0] <= (WAITREQUEST_ALLOWANCE == 0) ? uav_read && ~uav_waitrequest & ~waitrequest_reset_override
: uav_read;
for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
end
end
end
end // async_reg4
else begin //sync_reg4
always@(posedge clk) begin
if (internal_sclr) begin
read_latency_shift_reg <= '0;
end else if (av_clken) begin
read_latency_shift_reg[0] <= (WAITREQUEST_ALLOWANCE == 0) ? uav_read && ~uav_waitrequest & ~waitrequest_reset_override
: uav_read;
for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
end
end
end
end //sync_reg4
endgenerate
// ------------
// Chipselect and OutputEnable
// ------------
reg av_chipselect_pre;
wire cs_extension;
reg av_outputenable_pre;
assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
generate
if (SYNC_RESET == 0) begin :async_reg5
always@(posedge reset, posedge clk) begin
if(reset)
av_outputenable_pre <= 1'b0;
else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
av_outputenable_pre <= 0;
else
av_outputenable_pre <= cs_extension | uav_read;
end
end //async_reg5
else begin // sync_reg5
always@(posedge clk) begin
if(internal_sclr)
av_outputenable_pre <= 1'b0;
else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
av_outputenable_pre <= 0;
else
av_outputenable_pre <= cs_extension | uav_read;
end
end // sync_reg5
endgenerate
generate
if (SYNC_RESET == 0) begin :async_reg6
always@(posedge reset, posedge clk) begin
if(reset) begin
av_chipselect_pre <= 1'b0;
end else begin
av_chipselect_pre <= 1'b0;
if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
//The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
//There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
if(uav_read) begin
av_chipselect_pre <= 1'b1;
end else if(cs_extension == 1) begin
av_chipselect_pre <= 1'b1;
end
end
end
end
end // async_reg6
else begin // sync_reg6
always@(posedge clk) begin
if(internal_sclr) begin
av_chipselect_pre <= 1'b0;
end else begin
av_chipselect_pre <= 1'b0;
if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
//The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
//There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
if(uav_read) begin
av_chipselect_pre <= 1'b1;
end else if(cs_extension == 1) begin
av_chipselect_pre <= 1'b1;
end
end
end
end
end //sync_reg6
endgenerate
// -------------------
// Begintransfer Assigment
// -------------------
reg end_begintransfer;
always@* begin
if(WAITREQUEST_ALLOWANCE == 0) begin
av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
end
else begin
av_begintransfer = ( uav_write | uav_read );
end
end
generate
if (SYNC_RESET == 0) begin :async_reg7
always@ ( posedge clk or posedge reset ) begin
if(reset) begin
end_begintransfer <= 1'b0;
end else begin
if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
end_begintransfer <= 1'b1;
else if(uav_waitrequest)
end_begintransfer <= end_begintransfer;
else
end_begintransfer <= 1'b0;
end
end
end // async_reg7
else begin // sync_reg7
always@ ( posedge clk ) begin
if(internal_sclr) begin
end_begintransfer <= 1'b0;
end else begin
if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
end_begintransfer <= 1'b1;
else if(uav_waitrequest)
end_begintransfer <= end_begintransfer;
else
end_begintransfer <= 1'b0;
end
end
end //sync_reg7
endgenerate
// -------------------
// Beginbursttransfer Assigment
// -------------------
reg end_beginbursttransfer;
reg in_transfer;
always@* begin
av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
end
generate
if (SYNC_RESET == 0 ) begin : async_reg8
always@ ( posedge clk or posedge reset ) begin
if(reset) begin
end_beginbursttransfer <= 1'b0;
in_transfer <= 1'b0;
end else begin
end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
if(uav_write && uav_burstcount == symbols_per_word)
in_transfer <=1'b0;
else if(uav_write)
in_transfer <=1'b1;
end
end
end // async_reg8
else begin //sync_reg8
always@ ( posedge clk ) begin
if(internal_sclr) begin
end_beginbursttransfer <= 1'b0;
in_transfer <= 1'b0;
end else begin
end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
if(uav_write && uav_burstcount == symbols_per_word)
in_transfer <=1'b0;
else if(uav_write)
in_transfer <=1'b1;
end
end
end //sync_reg8
endgenerate
endmodule
qsys/qsys_top/altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v
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qsys/qsys_top/altera_reset_controller_1924/sim/altera_reset_controller.sdc
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# (C) 2001-2026 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any output
# files from any of the foregoing (including device programming or simulation
# files), and any associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License Subscription
# Agreement, Altera IP License Agreement, or other applicable
# license agreement, including, without limitation, that your use is for the
# sole purpose of programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the applicable
# agreement for further details.
# +---------------------------------------------------
# | Cut the async clear paths
# +---------------------------------------------------
set aclr_counter 0
set clrn_counter 0
if { [expr ![info exists show_hpath_of_all_reset_controller_inst]] } {
set show_hpath_of_all_reset_controller_inst 0
}
if {[get_current_instance] == ""} {set hpath ""} else {set hpath "[get_current_instance]|*"}
if {$show_hpath_of_all_reset_controller_inst == 1} {
post_message -type info "Following instance found in the design - $hpath"
}
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
set num_sync_stage [get_registers -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[*]]
set num_sync_count [get_collection_size $num_sync_stage]
set aclr_counter [get_collection_size $aclr_collection]
set clrn_counter [get_collection_size $clrn_collection]
if {$aclr_counter == 0 && $clrn_counter == 0 && $num_sync_count > 0} {
set_max_delay -to [get_registers ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[[expr $num_sync_count-1]]] 100
set_min_delay -to [get_registers ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[[expr $num_sync_count-1]]] -100
}
if {$aclr_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
}
if {$clrn_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
}
qsys/qsys_top/altera_reset_controller_1924/sim/altera_reset_controller.v
+367
View File
@@ -0,0 +1,367 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
reg reset_out_pre_reg;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
//synthesis translate_off
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
//synthesis translate_on
always @(posedge clk or posedge reset_out_pre)
begin
if (reset_out_pre)
reset_out_pre_reg <= 1'h1;
else
reset_out_pre_reg <= reset_out_pre;
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre_reg};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
if (OUTPUT_RESET_SYNC_EDGES != "deassert" ) begin
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
end
else begin
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
end
always @(posedge clk or posedge reset_out_pre )
begin
if(reset_out_pre) begin
r_early_rst <= 1'b1;
end
else begin
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
end
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZnnPJQ9GW+KzJV34fwWUvQ3dkA3L6G1Y5K7Msyidrmy1+Wu1L3OcWjX9FvtOw9qp2N3MEsh8d37Y/XaDWgwPKNC8qRv7AvhMJ8gFYwiLYTkPi1JGF8rlDOciOlSe0OOKsr8Qz81WHxnR038xpX6fIqkZWCweSvngUTKyauUaG3pcY+PLaI1oAcJ9eRym8kGs7+NwWcvmELdBMCucyRm52xLUprKDGjl1P42hAILSXrJXQndIyOW9vmm5Nz2evvj2gB7JvvzIfzZNuCdhnar89ChldW1j3A+Y5m6PjMM9pOU+Kdh26eGwj9fZZaPPrvl+VD5Hayq5zw3hzxXM33wd7ilCEvwS6rEk8Y9ZOslAUf74KejNArjekIHMmeFTx8aBtKMMm9wuP0WfEDxS4D7dDYDACm+FLX34qfxBjV7W/HokgwigFzSriqhaJqGkXLfN5+hTHkfsgDXx2KmN06gp1nCxVedTw83W3GZ0BDKFGGS0SrJDzge4q0Uk/lHtpo0n3W2FLL7TnG2r0QOY3YYnu0XSzCwIGa7WV4lIgGQ2UA+tiJkkVFL8zBqM6qqSx9ti08BQh/ob6g2E6CgPAuslJthgrG6/r1FvrY6mpyjO0c0vIAKswPchm+wB2Dx4+tBsnmX0peJXGJsrHXXjvrk52pzvpmXakJa2qerImbpknUXUBPR32Ek97/2wIEZ2iBp/jGeJDFttVPGoIXLHd4UgEdCmpFbUpZryi8bTJExus/YhIhp284WmXYOU22OgxwRtIPZ4CLG3lWeyiuxybU+R6eL"
`endif
qsys/qsys_top/altera_reset_controller_1924/sim/altera_reset_synchronizer.v
+89
View File
@@ -0,0 +1,89 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZm98qIL7ekOBsgi3Jk6JINlBn1MPss/MY/onstD48jcwiif8Gs4IWdQ2N3ArmvPwztGaa9pFUdrqFC/ySuZse43QXHTSLktppbb5RWP6kUriuoicmo6krAD1dbg/gJD2CPBniH3lvaXSbq4NXuXvaIi5JFjsHvqYH5AYGEBbEYIvX50OtmvM7MmdXWz8yMt/2x5MXTWbyba6bfKDJO6u5VlcHp85j3oXhLyoSx6ddNAgFJy9rjF3Z+u9E7PhkTCkebQtUzC8lIU9rG1+dwJE98atxbf1BPMRyiFcpFny635Ygt4p5jSQaXJnjSr6IUlFMLGpbYxPn1FcSkyMGPl2hZ7QtQENnQ3zejAwBl3Ze7ED8vOSzEBB93wGiKKZGd9hNwx5qeE0sgSNJa00qx6RLsg5tdDdzTo2bNXHlCtfYMIt2/YE75hzYCE//Zmb1mMx8nElfiU7/CpeYigjPvinVN5SqMGjIfMFWJasqdSm9Kw1UAN9s0LK8S6K3T1TGkHThOkJWDfpad7wvhxSkVJ99h9FdBLMlmkBYEwI/u/MKtNrzgKPsLz1FZ5EHB/JZti7aWbfhXQS1FoZYSLodk3NCTCmYgyghebDnmxCjIcHta/kmoyhMwLpM8ogUx6J3QA9oOxI+AvWy9A+id8Pj2XJjjQZxXzlg9JOVaXvn88zi6LVC88csY6kT+ANYw3OMfSjw9C2F6wme2VCibcI+DhqZCNXC41h1m9pqNYMUyyrBy5GMRZpEvb5yXb0+fS85rTPw4BgZkbkOxcmoA92mjOky5L"
`endif
qsys/qsys_top/altera_reset_controller_1924/synth/altera_reset_controller.sdc
+44
View File
@@ -0,0 +1,44 @@
# (C) 2001-2026 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any output
# files from any of the foregoing (including device programming or simulation
# files), and any associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License Subscription
# Agreement, Altera IP License Agreement, or other applicable
# license agreement, including, without limitation, that your use is for the
# sole purpose of programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the applicable
# agreement for further details.
# +---------------------------------------------------
# | Cut the async clear paths
# +---------------------------------------------------
set aclr_counter 0
set clrn_counter 0
if { [expr ![info exists show_hpath_of_all_reset_controller_inst]] } {
set show_hpath_of_all_reset_controller_inst 0
}
if {[get_current_instance] == ""} {set hpath ""} else {set hpath "[get_current_instance]|*"}
if {$show_hpath_of_all_reset_controller_inst == 1} {
post_message -type info "Following instance found in the design - $hpath"
}
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
set num_sync_stage [get_registers -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[*]]
set num_sync_count [get_collection_size $num_sync_stage]
set aclr_counter [get_collection_size $aclr_collection]
set clrn_counter [get_collection_size $clrn_collection]
if {$aclr_counter == 0 && $clrn_counter == 0 && $num_sync_count > 0} {
set_max_delay -to [get_registers ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[[expr $num_sync_count-1]]] 100
set_min_delay -to [get_registers ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[[expr $num_sync_count-1]]] -100
}
if {$aclr_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
}
if {$clrn_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
}
qsys/qsys_top/altera_reset_controller_1924/synth/altera_reset_controller.v
+367
View File
@@ -0,0 +1,367 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
reg reset_out_pre_reg;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
//synthesis translate_off
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
//synthesis translate_on
always @(posedge clk or posedge reset_out_pre)
begin
if (reset_out_pre)
reset_out_pre_reg <= 1'h1;
else
reset_out_pre_reg <= reset_out_pre;
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre_reg};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
if (OUTPUT_RESET_SYNC_EDGES != "deassert" ) begin
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
end
else begin
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
end
always @(posedge clk or posedge reset_out_pre )
begin
if(reset_out_pre) begin
r_early_rst <= 1'b1;
end
else begin
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
end
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZnnPJQ9GW+KzJV34fwWUvQ3dkA3L6G1Y5K7Msyidrmy1+Wu1L3OcWjX9FvtOw9qp2N3MEsh8d37Y/XaDWgwPKNC8qRv7AvhMJ8gFYwiLYTkPi1JGF8rlDOciOlSe0OOKsr8Qz81WHxnR038xpX6fIqkZWCweSvngUTKyauUaG3pcY+PLaI1oAcJ9eRym8kGs7+NwWcvmELdBMCucyRm52xLUprKDGjl1P42hAILSXrJXQndIyOW9vmm5Nz2evvj2gB7JvvzIfzZNuCdhnar89ChldW1j3A+Y5m6PjMM9pOU+Kdh26eGwj9fZZaPPrvl+VD5Hayq5zw3hzxXM33wd7ilCEvwS6rEk8Y9ZOslAUf74KejNArjekIHMmeFTx8aBtKMMm9wuP0WfEDxS4D7dDYDACm+FLX34qfxBjV7W/HokgwigFzSriqhaJqGkXLfN5+hTHkfsgDXx2KmN06gp1nCxVedTw83W3GZ0BDKFGGS0SrJDzge4q0Uk/lHtpo0n3W2FLL7TnG2r0QOY3YYnu0XSzCwIGa7WV4lIgGQ2UA+tiJkkVFL8zBqM6qqSx9ti08BQh/ob6g2E6CgPAuslJthgrG6/r1FvrY6mpyjO0c0vIAKswPchm+wB2Dx4+tBsnmX0peJXGJsrHXXjvrk52pzvpmXakJa2qerImbpknUXUBPR32Ek97/2wIEZ2iBp/jGeJDFttVPGoIXLHd4UgEdCmpFbUpZryi8bTJExus/YhIhp284WmXYOU22OgxwRtIPZ4CLG3lWeyiuxybU+R6eL"
`endif
qsys/qsys_top/altera_reset_controller_1924/synth/altera_reset_synchronizer.v
+89
View File
@@ -0,0 +1,89 @@
// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2026/02/05 $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZm98qIL7ekOBsgi3Jk6JINlBn1MPss/MY/onstD48jcwiif8Gs4IWdQ2N3ArmvPwztGaa9pFUdrqFC/ySuZse43QXHTSLktppbb5RWP6kUriuoicmo6krAD1dbg/gJD2CPBniH3lvaXSbq4NXuXvaIi5JFjsHvqYH5AYGEBbEYIvX50OtmvM7MmdXWz8yMt/2x5MXTWbyba6bfKDJO6u5VlcHp85j3oXhLyoSx6ddNAgFJy9rjF3Z+u9E7PhkTCkebQtUzC8lIU9rG1+dwJE98atxbf1BPMRyiFcpFny635Ygt4p5jSQaXJnjSr6IUlFMLGpbYxPn1FcSkyMGPl2hZ7QtQENnQ3zejAwBl3Ze7ED8vOSzEBB93wGiKKZGd9hNwx5qeE0sgSNJa00qx6RLsg5tdDdzTo2bNXHlCtfYMIt2/YE75hzYCE//Zmb1mMx8nElfiU7/CpeYigjPvinVN5SqMGjIfMFWJasqdSm9Kw1UAN9s0LK8S6K3T1TGkHThOkJWDfpad7wvhxSkVJ99h9FdBLMlmkBYEwI/u/MKtNrzgKPsLz1FZ5EHB/JZti7aWbfhXQS1FoZYSLodk3NCTCmYgyghebDnmxCjIcHta/kmoyhMwLpM8ogUx6J3QA9oOxI+AvWy9A+id8Pj2XJjjQZxXzlg9JOVaXvn88zi6LVC88csY6kT+ANYw3OMfSjw9C2F6wme2VCibcI+DhqZCNXC41h1m9pqNYMUyyrBy5GMRZpEvb5yXb0+fS85rTPw4BgZkbkOxcmoA92mjOky5L"
`endif
qsys/qsys_top/qsys_top.bsf
+1233
View File
File diff suppressed because it is too large Load Diff
qsys/qsys_top/qsys_top.cmp
+148
View File
@@ -0,0 +1,148 @@
component qsys_top is
port (
clk_100_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
ninit_done_ninit_done : out std_logic; -- ninit_done
h2f_reset_reset : out std_logic; -- reset
subsys_hps_hps2fpga_awid : out std_logic_vector(3 downto 0); -- awid
subsys_hps_hps2fpga_awaddr : out std_logic_vector(37 downto 0); -- awaddr
subsys_hps_hps2fpga_awlen : out std_logic_vector(7 downto 0); -- awlen
subsys_hps_hps2fpga_awsize : out std_logic_vector(2 downto 0); -- awsize
subsys_hps_hps2fpga_awburst : out std_logic_vector(1 downto 0); -- awburst
subsys_hps_hps2fpga_awlock : out std_logic; -- awlock
subsys_hps_hps2fpga_awcache : out std_logic_vector(3 downto 0); -- awcache
subsys_hps_hps2fpga_awprot : out std_logic_vector(2 downto 0); -- awprot
subsys_hps_hps2fpga_awvalid : out std_logic; -- awvalid
subsys_hps_hps2fpga_awready : in std_logic := 'X'; -- awready
subsys_hps_hps2fpga_wdata : out std_logic_vector(127 downto 0); -- wdata
subsys_hps_hps2fpga_wstrb : out std_logic_vector(15 downto 0); -- wstrb
subsys_hps_hps2fpga_wlast : out std_logic; -- wlast
subsys_hps_hps2fpga_wvalid : out std_logic; -- wvalid
subsys_hps_hps2fpga_wready : in std_logic := 'X'; -- wready
subsys_hps_hps2fpga_bid : in std_logic_vector(3 downto 0) := (others => 'X'); -- bid
subsys_hps_hps2fpga_bresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp
subsys_hps_hps2fpga_bvalid : in std_logic := 'X'; -- bvalid
subsys_hps_hps2fpga_bready : out std_logic; -- bready
subsys_hps_hps2fpga_arid : out std_logic_vector(3 downto 0); -- arid
subsys_hps_hps2fpga_araddr : out std_logic_vector(37 downto 0); -- araddr
subsys_hps_hps2fpga_arlen : out std_logic_vector(7 downto 0); -- arlen
subsys_hps_hps2fpga_arsize : out std_logic_vector(2 downto 0); -- arsize
subsys_hps_hps2fpga_arburst : out std_logic_vector(1 downto 0); -- arburst
subsys_hps_hps2fpga_arlock : out std_logic; -- arlock
subsys_hps_hps2fpga_arcache : out std_logic_vector(3 downto 0); -- arcache
subsys_hps_hps2fpga_arprot : out std_logic_vector(2 downto 0); -- arprot
subsys_hps_hps2fpga_arvalid : out std_logic; -- arvalid
subsys_hps_hps2fpga_arready : in std_logic := 'X'; -- arready
subsys_hps_hps2fpga_rid : in std_logic_vector(3 downto 0) := (others => 'X'); -- rid
subsys_hps_hps2fpga_rdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- rdata
subsys_hps_hps2fpga_rresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp
subsys_hps_hps2fpga_rlast : in std_logic := 'X'; -- rlast
subsys_hps_hps2fpga_rvalid : in std_logic := 'X'; -- rvalid
subsys_hps_hps2fpga_rready : out std_logic; -- rready
subsys_hps_h2f_warm_reset_handshake_reset_req : out std_logic; -- reset_req
subsys_hps_h2f_warm_reset_handshake_reset_ack : in std_logic := 'X'; -- reset_ack
hps_io_hps_osc_clk : in std_logic := 'X'; -- hps_osc_clk
hps_io_sdmmc_data0 : inout std_logic := 'X'; -- sdmmc_data0
hps_io_sdmmc_data1 : inout std_logic := 'X'; -- sdmmc_data1
hps_io_sdmmc_cclk : out std_logic; -- sdmmc_cclk
hps_io_sdmmc_data2 : inout std_logic := 'X'; -- sdmmc_data2
hps_io_sdmmc_data3 : inout std_logic := 'X'; -- sdmmc_data3
hps_io_sdmmc_cmd : inout std_logic := 'X'; -- sdmmc_cmd
hps_io_usb0_clk : in std_logic := 'X'; -- usb0_clk
hps_io_usb0_stp : out std_logic; -- usb0_stp
hps_io_usb0_dir : in std_logic := 'X'; -- usb0_dir
hps_io_usb0_data0 : inout std_logic := 'X'; -- usb0_data0
hps_io_usb0_data1 : inout std_logic := 'X'; -- usb0_data1
hps_io_usb0_nxt : in std_logic := 'X'; -- usb0_nxt
hps_io_usb0_data2 : inout std_logic := 'X'; -- usb0_data2
hps_io_usb0_data3 : inout std_logic := 'X'; -- usb0_data3
hps_io_usb0_data4 : inout std_logic := 'X'; -- usb0_data4
hps_io_usb0_data5 : inout std_logic := 'X'; -- usb0_data5
hps_io_usb0_data6 : inout std_logic := 'X'; -- usb0_data6
hps_io_usb0_data7 : inout std_logic := 'X'; -- usb0_data7
hps_io_emac0_tx_clk : out std_logic; -- emac0_tx_clk
hps_io_emac0_tx_ctl : out std_logic; -- emac0_tx_ctl
hps_io_emac0_rx_clk : in std_logic := 'X'; -- emac0_rx_clk
hps_io_emac0_rx_ctl : in std_logic := 'X'; -- emac0_rx_ctl
hps_io_emac0_txd0 : out std_logic; -- emac0_txd0
hps_io_emac0_txd1 : out std_logic; -- emac0_txd1
hps_io_emac0_rxd0 : in std_logic := 'X'; -- emac0_rxd0
hps_io_emac0_rxd1 : in std_logic := 'X'; -- emac0_rxd1
hps_io_emac0_txd2 : out std_logic; -- emac0_txd2
hps_io_emac0_txd3 : out std_logic; -- emac0_txd3
hps_io_emac0_rxd2 : in std_logic := 'X'; -- emac0_rxd2
hps_io_emac0_rxd3 : in std_logic := 'X'; -- emac0_rxd3
hps_io_mdio0_mdio : inout std_logic := 'X'; -- mdio0_mdio
hps_io_mdio0_mdc : out std_logic; -- mdio0_mdc
hps_io_uart1_tx : out std_logic; -- uart1_tx
hps_io_uart1_rx : in std_logic := 'X'; -- uart1_rx
hps_io_i2c1_sda : inout std_logic := 'X'; -- i2c1_sda
hps_io_i2c1_scl : inout std_logic := 'X'; -- i2c1_scl
hps_io_gpio28 : inout std_logic := 'X'; -- gpio28
hps_io_gpio34 : inout std_logic := 'X'; -- gpio34
hps_io_gpio40 : inout std_logic := 'X'; -- gpio40
hps_io_gpio41 : inout std_logic := 'X'; -- gpio41
f2h_irq1_in_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
f2sdram_araddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- araddr
f2sdram_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst
f2sdram_arcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- arcache
f2sdram_arid : in std_logic_vector(4 downto 0) := (others => 'X'); -- arid
f2sdram_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- arlen
f2sdram_arlock : in std_logic := 'X'; -- arlock
f2sdram_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
f2sdram_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- arqos
f2sdram_arready : out std_logic; -- arready
f2sdram_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize
f2sdram_arvalid : in std_logic := 'X'; -- arvalid
f2sdram_awaddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- awaddr
f2sdram_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst
f2sdram_awcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- awcache
f2sdram_awid : in std_logic_vector(4 downto 0) := (others => 'X'); -- awid
f2sdram_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- awlen
f2sdram_awlock : in std_logic := 'X'; -- awlock
f2sdram_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
f2sdram_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- awqos
f2sdram_awready : out std_logic; -- awready
f2sdram_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize
f2sdram_awvalid : in std_logic := 'X'; -- awvalid
f2sdram_bid : out std_logic_vector(4 downto 0); -- bid
f2sdram_bready : in std_logic := 'X'; -- bready
f2sdram_bresp : out std_logic_vector(1 downto 0); -- bresp
f2sdram_bvalid : out std_logic; -- bvalid
f2sdram_rdata : out std_logic_vector(255 downto 0); -- rdata
f2sdram_rid : out std_logic_vector(4 downto 0); -- rid
f2sdram_rlast : out std_logic; -- rlast
f2sdram_rready : in std_logic := 'X'; -- rready
f2sdram_rresp : out std_logic_vector(1 downto 0); -- rresp
f2sdram_rvalid : out std_logic; -- rvalid
f2sdram_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- wdata
f2sdram_wlast : in std_logic := 'X'; -- wlast
f2sdram_wready : out std_logic; -- wready
f2sdram_wstrb : in std_logic_vector(31 downto 0) := (others => 'X'); -- wstrb
f2sdram_wvalid : in std_logic := 'X'; -- wvalid
f2sdram_aruser : in std_logic_vector(7 downto 0) := (others => 'X'); -- aruser
f2sdram_awuser : in std_logic_vector(7 downto 0) := (others => 'X'); -- awuser
f2sdram_wuser : in std_logic_vector(7 downto 0) := (others => 'X'); -- wuser
f2sdram_buser : out std_logic_vector(7 downto 0); -- buser
f2sdram_arregion : in std_logic_vector(3 downto 0) := (others => 'X'); -- arregion
f2sdram_ruser : out std_logic_vector(7 downto 0); -- ruser
f2sdram_awregion : in std_logic_vector(3 downto 0) := (others => 'X'); -- awregion
emif_hps_emif_mem_0_mem_cs : out std_logic_vector(0 downto 0); -- mem_cs
emif_hps_emif_mem_0_mem_ca : out std_logic_vector(5 downto 0); -- mem_ca
emif_hps_emif_mem_0_mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
emif_hps_emif_mem_0_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
emif_hps_emif_mem_0_mem_dqs_t : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_t
emif_hps_emif_mem_0_mem_dqs_c : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_c
emif_hps_emif_mem_0_mem_dmi : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dmi
emif_hps_emif_mem_ck_0_mem_ck_t : out std_logic_vector(0 downto 0); -- mem_ck_t
emif_hps_emif_mem_ck_0_mem_ck_c : out std_logic_vector(0 downto 0); -- mem_ck_c
emif_hps_emif_mem_reset_n_mem_reset_n : out std_logic; -- mem_reset_n
emif_hps_emif_oct_0_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
emif_hps_emif_ref_clk_0_clk : in std_logic := 'X'; -- clk
button_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
dipsw_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
led_pio_external_connection_in_port : in std_logic_vector(2 downto 0) := (others => 'X'); -- in_port
led_pio_external_connection_out_port : out std_logic_vector(2 downto 0) -- out_port
);
end component qsys_top;
qsys/qsys_top/qsys_top.csv
+79
View File
@@ -0,0 +1,79 @@
# system info qsys_top on 2026.04.08.10:52:54
system_info:
name,value
DEVICE,A5EB013BB23BE4SCS
DEVICE_FAMILY,Agilex 5
GENERATION_ID,0
#
#
# Files generated for qsys_top on 2026.04.08.10:52:54
files:
filepath,kind,attributes,module,is_top
sim/qsys_top.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top,true
altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top_altera_mm_interconnect_1920_ykfyxdi,false
altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv,SYSTEM_VERILOG,,qsys_top_altera_irq_mapper_2001_lp4cnei,false
altera_reset_controller_1924/sim/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
altera_reset_controller_1924/sim/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
altera_reset_controller_1924/sim/altera_reset_controller.sdc,SDC_ENTITY,NO_SDC_PROMOTION,altera_reset_controller,false
altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_translator_1987_lty7xoq,false
altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_translator_191_xg7rzxi,false
altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_master_ni_19117_qautany,false
altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_master_ni_19117_qautany,false
altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_agent_1930_jxauz3i,false
altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_agent_1930_jxauz3i,false
altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v,VERILOG,,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi,false
altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_router_1921_ox5xuhq,false
altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_router_1921_sxavatq,false
altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q,false
altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_666s25q,false
altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_666s25q,false
altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_demultiplexer_1921_qyizksq,false
altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_yjgptii,false
altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_yjgptii,false
altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di,false
altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv,SYSTEM_VERILOG,,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq,false
altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
qsys_top.clk_100,clk_100
qsys_top.rst_in,rst_in
qsys_top.user_rst_clkgate_0,user_rst_clkgate_0
qsys_top.subsys_hps,hps_subsys
qsys_top.subsys_periph,peripheral_subsys
qsys_top.mm_interconnect_0,qsys_top_altera_mm_interconnect_1920_ykfyxdi
qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_translator,qsys_top_altera_merlin_axi_translator_1987_lty7xoq
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_translator,qsys_top_altera_merlin_slave_translator_191_xg7rzxi
qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_agent,qsys_top_altera_merlin_axi_master_ni_19117_qautany
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent,qsys_top_altera_merlin_slave_agent_1930_jxauz3i
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rdata_fifo,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi
qsys_top.mm_interconnect_0.router,qsys_top_altera_merlin_router_1921_ox5xuhq
qsys_top.mm_interconnect_0.router_001,qsys_top_altera_merlin_router_1921_ox5xuhq
qsys_top.mm_interconnect_0.router_002,qsys_top_altera_merlin_router_1921_sxavatq
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage,qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage.my_altera_avalon_st_pipeline_stage,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.cmd_demux,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
qsys_top.mm_interconnect_0.cmd_demux_001,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
qsys_top.mm_interconnect_0.cmd_mux,qsys_top_altera_merlin_multiplexer_1922_666s25q
qsys_top.mm_interconnect_0.rsp_demux,qsys_top_altera_merlin_demultiplexer_1921_qyizksq
qsys_top.mm_interconnect_0.rsp_mux,qsys_top_altera_merlin_multiplexer_1922_yjgptii
qsys_top.mm_interconnect_0.rsp_mux_001,qsys_top_altera_merlin_multiplexer_1922_yjgptii
qsys_top.mm_interconnect_0.agent_pipeline,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.agent_pipeline_001,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.mux_pipeline,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.mux_pipeline_001,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.mux_pipeline_002,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.mux_pipeline_003,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.irq_mapper,qsys_top_altera_irq_mapper_2001_lp4cnei
qsys_top.rst_controller,altera_reset_controller
1 # system info qsys_top on 2026.04.08.10:52:54
2 system_info:
3 name,value
4 DEVICE,A5EB013BB23BE4SCS
5 DEVICE_FAMILY,Agilex 5
6 GENERATION_ID,0
7 #
8 #
9 # Files generated for qsys_top on 2026.04.08.10:52:54
10 files:
11 filepath,kind,attributes,module,is_top
12 sim/qsys_top.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top,true
13 altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top_altera_mm_interconnect_1920_ykfyxdi,false
14 altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv,SYSTEM_VERILOG,,qsys_top_altera_irq_mapper_2001_lp4cnei,false
15 altera_reset_controller_1924/sim/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
16 altera_reset_controller_1924/sim/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
17 altera_reset_controller_1924/sim/altera_reset_controller.sdc,SDC_ENTITY,NO_SDC_PROMOTION,altera_reset_controller,false
18 altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_translator_1987_lty7xoq,false
19 altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_translator_191_xg7rzxi,false
20 altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_master_ni_19117_qautany,false
21 altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_master_ni_19117_qautany,false
22 altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_agent_1930_jxauz3i,false
23 altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_agent_1930_jxauz3i,false
24 altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v,VERILOG,,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi,false
25 altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_router_1921_ox5xuhq,false
26 altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_router_1921_sxavatq,false
27 altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
28 altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
29 altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
30 altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
31 altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
32 altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
33 altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
34 altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
35 altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q,false
36 altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_666s25q,false
37 altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_666s25q,false
38 altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_demultiplexer_1921_qyizksq,false
39 altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_yjgptii,false
40 altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_yjgptii,false
41 altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di,false
42 altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv,SYSTEM_VERILOG,,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq,false
43 altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq,false
44 #
45 # Map from instance-path to kind of module
46 instances:
47 instancePath,module
48 qsys_top.clk_100,clk_100
49 qsys_top.rst_in,rst_in
50 qsys_top.user_rst_clkgate_0,user_rst_clkgate_0
51 qsys_top.subsys_hps,hps_subsys
52 qsys_top.subsys_periph,peripheral_subsys
53 qsys_top.mm_interconnect_0,qsys_top_altera_mm_interconnect_1920_ykfyxdi
54 qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_translator,qsys_top_altera_merlin_axi_translator_1987_lty7xoq
55 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_translator,qsys_top_altera_merlin_slave_translator_191_xg7rzxi
56 qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_agent,qsys_top_altera_merlin_axi_master_ni_19117_qautany
57 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent,qsys_top_altera_merlin_slave_agent_1930_jxauz3i
58 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi
59 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rdata_fifo,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi
60 qsys_top.mm_interconnect_0.router,qsys_top_altera_merlin_router_1921_ox5xuhq
61 qsys_top.mm_interconnect_0.router_001,qsys_top_altera_merlin_router_1921_ox5xuhq
62 qsys_top.mm_interconnect_0.router_002,qsys_top_altera_merlin_router_1921_sxavatq
63 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy
64 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage,qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di
65 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage.my_altera_avalon_st_pipeline_stage,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
66 qsys_top.mm_interconnect_0.cmd_demux,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
67 qsys_top.mm_interconnect_0.cmd_demux_001,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
68 qsys_top.mm_interconnect_0.cmd_mux,qsys_top_altera_merlin_multiplexer_1922_666s25q
69 qsys_top.mm_interconnect_0.rsp_demux,qsys_top_altera_merlin_demultiplexer_1921_qyizksq
70 qsys_top.mm_interconnect_0.rsp_mux,qsys_top_altera_merlin_multiplexer_1922_yjgptii
71 qsys_top.mm_interconnect_0.rsp_mux_001,qsys_top_altera_merlin_multiplexer_1922_yjgptii
72 qsys_top.mm_interconnect_0.agent_pipeline,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
73 qsys_top.mm_interconnect_0.agent_pipeline_001,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
74 qsys_top.mm_interconnect_0.mux_pipeline,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
75 qsys_top.mm_interconnect_0.mux_pipeline_001,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
76 qsys_top.mm_interconnect_0.mux_pipeline_002,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
77 qsys_top.mm_interconnect_0.mux_pipeline_003,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
78 qsys_top.irq_mapper,qsys_top_altera_irq_mapper_2001_lp4cnei
79 qsys_top.rst_controller,altera_reset_controller
qsys/qsys_top/qsys_top.html
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qsys/qsys_top/qsys_top.qgsimc
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qsys/qsys_top/qsys_top.qgsynthc
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qsys/qsys_top/qsys_top.qip
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set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_TOOL_NAME "QsysPrimePro"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_TOOL_VERSION "26.1"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -library "qsys_top" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_top.sopcinfo"]
set_global_assignment -entity "qsys_top" -library "qsys_top" -name SLD_INFO "QSYS_NAME qsys_top HAS_SOPCINFO 1 GENERATION_ID 0"
set_global_assignment -library "qsys_top" -name MISC_FILE [file join $::quartus(qip_path) "qsys_top.cmp"]
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_TARGETED_PART_TRAIT "BASE_DEVICE::SM4REVB"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_TARGETED_PART_TRAIT "part.DEVICE_IOBANK_REVISION::IO96B_REVB1"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_TARGETED_PART_TRAIT "part.DEVICE_POWER_MODEL::STANDARD_POWER_FIXED"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_TARGETED_PART_TRAIT "part.DEVICE_TEMPERATURE_GRADE::EXTENDED"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_TARGETED_PART_TRAIT "part.SUPPORTS_VID::0"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_QSYS_MODE "SYSTEM"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "qsys_top" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_top.qsys"]
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_NAME "Y2xrXzEwMA=="
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_DISPLAY_NAME "R2VuZXJpYyBDb21wb25lbnQ="
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_DESCRIPTION "QSBkeW5hbWljIGNvbXBvbmVudCB3aGVyZSB5b3UgY2FuIGFkZCwgbW9kaWZ5IG9yIHJlbW92ZSBpbnRlcmZhY2VzIGFuZCBwb3J0cyBvbiB0aGUgZmx5"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_GROUP "R2VuZXJpYyBDb21wb25lbnQ="
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_NAME "cnN0X2lu"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_DISPLAY_NAME "R2VuZXJpYyBDb21wb25lbnQ="
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_DESCRIPTION "QSBkeW5hbWljIGNvbXBvbmVudCB3aGVyZSB5b3UgY2FuIGFkZCwgbW9kaWZ5IG9yIHJlbW92ZSBpbnRlcmZhY2VzIGFuZCBwb3J0cyBvbiB0aGUgZmx5"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_GROUP "R2VuZXJpYyBDb21wb25lbnQ="
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_NAME "dXNlcl9yc3RfY2xrZ2F0ZV8w"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_DISPLAY_NAME "R2VuZXJpYyBDb21wb25lbnQ="
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_DESCRIPTION "QSBkeW5hbWljIGNvbXBvbmVudCB3aGVyZSB5b3UgY2FuIGFkZCwgbW9kaWZ5IG9yIHJlbW92ZSBpbnRlcmZhY2VzIGFuZCBwb3J0cyBvbiB0aGUgZmx5"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_GROUP "R2VuZXJpYyBDb21wb25lbnQ="
set_global_assignment -entity "hps_subsys" -library "qsys_top" -name IP_COMPONENT_NAME "aHBzX3N1YnN5cw=="
set_global_assignment -entity "hps_subsys" -library "qsys_top" -name IP_COMPONENT_DISPLAY_NAME "aHBzX3N1YnN5cw=="
set_global_assignment -entity "hps_subsys" -library "qsys_top" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "hps_subsys" -library "qsys_top" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "hps_subsys" -library "qsys_top" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "peripheral_subsys" -library "qsys_top" -name IP_COMPONENT_NAME "cGVyaXBoZXJhbF9zdWJzeXM="
set_global_assignment -entity "peripheral_subsys" -library "qsys_top" -name IP_COMPONENT_DISPLAY_NAME "cGVyaXBoZXJhbF9zdWJzeXM="
set_global_assignment -entity "peripheral_subsys" -library "qsys_top" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "peripheral_subsys" -library "qsys_top" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "peripheral_subsys" -library "qsys_top" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9heGlfdHJhbnNsYXRvcl8xOTg3X2x0eTd4b3E="
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_COMPONENT_DISPLAY_NAME "QVhJIFRyYW5zbGF0b3IgSVA="
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_COMPONENT_VERSION "MTkuOC43"
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_COMPONENT_DESCRIPTION "Q29udmVydCBpbmNvbXBsZXRlIEFYSTQgaW50ZXJmYWNlIHRvIGNvbXBsZXRlIEFYSTQgaW50ZXJmYWNl"
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_COMPONENT_GROUP "SW50ZXJjb25uZWN0L01lbW9yeS1NYXBwZWQ="
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9zbGF2ZV90cmFuc2xhdG9yXzE5MV94Zzdyenhp"
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1lbW9yeSBNYXBwZWQgU2xhdmUgVHJhbnNsYXRvciBJUA=="
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_COMPONENT_VERSION "MTkuMQ=="
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_COMPONENT_DESCRIPTION "Q29udmVydHMgdGhlIEF2YWxvbiBNZW1vcnkgTWFwcGVkIHNsYXZlIGludGVyZmFjZSB0byBhIHNpbXBsaWZpZWQgcmVwcmVzZW50YXRpb24gdGhhdCB0aGUgUXN5cyBuZXR3b3JrIHVzZXMuIFJlZmVyIHRvIHRoZSBBdmFsb24gSW50ZXJmYWNlIFNwZWNpZmljYXRpb25zIChodHRwOi8vd3d3LmFsdGVyYS5jb20vbGl0ZXJhdHVyZS9tYW51YWwvbW5sX2F2YWxvbl9zcGVjLnBkZikgZm9yIGRlZmluaXRpb25zIG9mIHRoZSBBdmFsb24gTWVtb3J5IE1hcHBlZCBzaWduYWxzIGFuZCBleHBsYW5hdGlvbnMgb2YgdGhlIGJ1cnN0aW5nIHByb3BlcnRpZXMgYW5kIGFkZHJlc3MgYWxpZ25tZW50Lg=="
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_COMPONENT_GROUP "SW50ZWwgRlBHQSBJbnRlcmNvbm5lY3QvTWVtb3J5LU1hcHBlZA=="
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvaGIvcXRzL3FzeXNfaW50ZXJjb25uZWN0LnBkZg=="
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9heGlfbWFzdGVyX25pXzE5MTE3X3FhdXRhbnk="
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_COMPONENT_DISPLAY_NAME "QVhJIE1hc3RlciBOZXR3b3JrIEludGVyZmFjZSBJUA=="
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_COMPONENT_VERSION "MTkuMTEuNw=="
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_COMPONENT_DESCRIPTION "Q29udmVydCBBWEkgdHJhbnNhY3Rpb24gdG8gUXN5cyBwYWNrZXQ="
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_COMPONENT_GROUP "SW50ZXJjb25uZWN0L01lbW9yeS1NYXBwZWQ="
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGYjcGFnZT0zNjA="
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9zbGF2ZV9hZ2VudF8xOTMwX2p4YXV6M2k="
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1lbW9yeSBNYXBwZWQgU2xhdmUgQWdlbnQgSVA="
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_COMPONENT_VERSION "MTkuMy4w"
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjb21tYW5kIHBhY2tldHMgYW5kIGlzc3VlcyB0aGUgcmVzdWx0aW5nIHRyYW5zYWN0aW9ucyB0byB0aGUgQXZhbG9uIGludGVyZmFjZS4gUmVmZXIgdG8gdGhlIEF2YWxvbiBJbnRlcmZhY2UgU3BlY2lmaWNhdGlvbnMgKGh0dHA6Ly93d3cuYWx0ZXJhLmNvbS9saXRlcmF0dXJlL21hbnVhbC9tbmxfYXZhbG9uX3NwZWMucGRmKSBmb3IgZXhwbGFuYXRpb25zIG9mIHRoZSBidXJzdGluZyBwcm9wZXJ0aWVzLg=="
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_COMPONENT_GROUP "SW50ZWwgRlBHQSBJbnRlcmNvbm5lY3QvTWVtb3J5LU1hcHBlZA=="
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvaGIvcXRzL3FzeXNfaW50ZXJjb25uZWN0LnBkZg=="
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX2F2YWxvbl9zY19maWZvXzE5MzJfMjJneHhnaQ=="
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIFN0cmVhbWluZyBTaW5nbGUgQ2xvY2sgRklGTyBJUA=="
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_VERSION "MTkuMy4y"
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_DESCRIPTION "U2luZ2xlIENsb2NrIEZJRk8gd2l0aCBBdmFsb24gU3RyZWFtaW5nIEludGVyZmFjZXM="
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL09uIENoaXAgTWVtb3J5"
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL3NmbzE0MDA3ODc5NTI5MzIvaWdhMTQwMTM5NTU2Mzc3OQ=="
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MjE2OTgwNDIwODcvaGNvMTQyMTY5NzY4OTMwMA=="
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9yb3V0ZXJfMTkyMV9veDV4dWhx"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5LU1hcHBlZCBSb3V0ZXIgSVA="
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_COMPONENT_VERSION "MTkuMi4x"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_COMPONENT_GROUP "SW50ZXJjb25uZWN0L01lbW9yeS1NYXBwZWQ="
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3pjbjE1MTM5ODcyODI5MzUuaHRtbCNtd2gxNDA5OTU4ODI4NzMy"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9yb3V0ZXJfMTkyMV9zeGF2YXRx"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5LU1hcHBlZCBSb3V0ZXIgSVA="
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_COMPONENT_VERSION "MTkuMi4x"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_COMPONENT_GROUP "SW50ZXJjb25uZWN0L01lbW9yeS1NYXBwZWQ="
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3pjbjE1MTM5ODcyODI5MzUuaHRtbCNtd2gxNDA5OTU4ODI4NzMy"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX2F2YWxvbl9zdF9waXBlbGluZV9zdGFnZV8xOTMwX29pdXBlaXE="
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIFN0cmVhbWluZyBQaXBlbGluZSBTdGFnZSBJUA=="
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_COMPONENT_VERSION "MTkuMy4w"
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_COMPONENT_DESCRIPTION "SW5zZXJ0cyBhIHNpbmdsZSBwaXBlbGluZSAocmVnaXN0ZXIpIHN0YWdlIGluIHRoZSBBdmFsb24gU3RyZWFtaW5nIGNvbW1hbmQgYW5kIHJlc3BvbnNlIGRhdGFwYXRocy4gUmVjZWl2ZXMgZGF0YSBvbiBpdHMgQXZhbG9uIFN0cmVhbWluZyBzaW5rIGludGVyZmFjZXMgYW5kIGRyaXZlcyBpdCB1bmNoYW5nZWQgb24gaXRzIEF2YWxvbiBTdHJlYW1pbmcgc291cmNlIGludGVyZmFjZS4="
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0JyaWRnZXMgYW5kIEFkYXB0b3JzL0F2YWxvbiBTdHJlYW1pbmc="
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL213aDE0MDk5NjAxODE2NDEvbXdoMTQwOTk1OTQ0MDg2Nw=="
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MTY4MzYxNDU1NTUvaGNvMTQxNjgzNjY1MzIyMQ=="
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9idXJzdF9hZGFwdGVyX2FsdGVyYV9hdmFsb25fc3RfcGlwZWxpbmVfc3RhZ2VfMTk0MF95a2R3NmRp"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_DISPLAY_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9idXJzdF9hZGFwdGVyX2FsdGVyYV9hdmFsb25fc3RfcGlwZWxpbmVfc3RhZ2VfMTk0MF95a2R3NmRp"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_VERSION "MTkuNC4w"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9idXJzdF9hZGFwdGVyXzE5NDBfNnp2d2RmeQ=="
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5LU1hcHBlZCBCdXJzdCBBZGFwdGVyIElQ"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_VERSION "MTkuNC4w"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_DESCRIPTION "QWNjb21tb2RhdGVzIHRoZSBidXJzdCBjYXBhYmlsaXRpZXMgb2YgZWFjaCBpbnRlcmZhY2UgaW4gdGhlIHN5c3RlbSwgaW5jbHVkaW5nIGludGVyZmFjZXMgdGhhdCBkbyBub3Qgc3VwcG9ydCBidXJzdCB0cmFuc2ZlcnMsIHRyYW5zbGF0aW5nIGJ1cnN0IHNpemVzIGFzIHJlcXVpcmVkLg=="
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_GROUP "SW50ZXJjb25uZWN0L01lbW9yeS1NYXBwZWQ="
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3pjbjE1MTM5ODcyODI5MzUuaHRtbCNtd2gxNDA5OTU4ODI4NzMy"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9kZW11bHRpcGxleGVyXzE5MjFfMnYybHc2cQ=="
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5LU1hcHBlZCBEZW11bHRpcGxleGVyIElQ"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_VERSION "MTkuMi4x"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_GROUP "SW50ZXJjb25uZWN0L01lbW9yeS1NYXBwZWQ="
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3pjbjE1MTM5ODcyODI5MzUuaHRtbCNtd2gxNDA5OTU4ODI4NzMy"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9tdWx0aXBsZXhlcl8xOTIyXzY2NnMyNXE="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5LU1hcHBlZCBNdWx0aXBsZXhlciBJUA=="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_VERSION "MTkuMi4y"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_GROUP "SW50ZXJjb25uZWN0L01lbW9yeS1NYXBwZWQ="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3pjbjE1MTM5ODcyODI5MzUuaHRtbCNtd2gxNDA5OTU4ODI4NzMy"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9kZW11bHRpcGxleGVyXzE5MjFfcXlpemtzcQ=="
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5LU1hcHBlZCBEZW11bHRpcGxleGVyIElQ"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_VERSION "MTkuMi4x"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_GROUP "SW50ZXJjb25uZWN0L01lbW9yeS1NYXBwZWQ="
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3pjbjE1MTM5ODcyODI5MzUuaHRtbCNtd2gxNDA5OTU4ODI4NzMy"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21lcmxpbl9tdWx0aXBsZXhlcl8xOTIyX3lqZ3B0aWk="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5LU1hcHBlZCBNdWx0aXBsZXhlciBJUA=="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_VERSION "MTkuMi4y"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_GROUP "SW50ZXJjb25uZWN0L01lbW9yeS1NYXBwZWQ="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3pjbjE1MTM5ODcyODI5MzUuaHRtbCNtd2gxNDA5OTU4ODI4NzMy"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top_altera_mm_interconnect_1920_ykfyxdi" -library "altera_mm_interconnect_1920" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX21tX2ludGVyY29ubmVjdF8xOTIwX3lrZnl4ZGk="
set_global_assignment -entity "qsys_top_altera_mm_interconnect_1920_ykfyxdi" -library "altera_mm_interconnect_1920" -name IP_COMPONENT_DISPLAY_NAME "TU0gSW50ZXJjb25uZWN0"
set_global_assignment -entity "qsys_top_altera_mm_interconnect_1920_ykfyxdi" -library "altera_mm_interconnect_1920" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_mm_interconnect_1920_ykfyxdi" -library "altera_mm_interconnect_1920" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "qsys_top_altera_mm_interconnect_1920_ykfyxdi" -library "altera_mm_interconnect_1920" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_mm_interconnect_1920_ykfyxdi" -library "altera_mm_interconnect_1920" -name IP_COMPONENT_VERSION "MTkuMi4w"
set_global_assignment -entity "qsys_top_altera_mm_interconnect_1920_ykfyxdi" -library "altera_mm_interconnect_1920" -name IP_COMPONENT_DESCRIPTION "TU0gSW50ZXJjb25uZWN0"
set_global_assignment -entity "qsys_top_altera_mm_interconnect_1920_ykfyxdi" -library "altera_mm_interconnect_1920" -name IP_COMPONENT_GROUP "TWVybGluIENvbXBvbmVudHM="
set_global_assignment -entity "qsys_top_altera_irq_mapper_2001_lp4cnei" -library "altera_irq_mapper_2001" -name IP_COMPONENT_NAME "cXN5c190b3BfYWx0ZXJhX2lycV9tYXBwZXJfMjAwMV9scDRjbmVp"
set_global_assignment -entity "qsys_top_altera_irq_mapper_2001_lp4cnei" -library "altera_irq_mapper_2001" -name IP_COMPONENT_DISPLAY_NAME "TWVybGluIElSUSBNYXBwZXIgSVA="
set_global_assignment -entity "qsys_top_altera_irq_mapper_2001_lp4cnei" -library "altera_irq_mapper_2001" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "qsys_top_altera_irq_mapper_2001_lp4cnei" -library "altera_irq_mapper_2001" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "qsys_top_altera_irq_mapper_2001_lp4cnei" -library "altera_irq_mapper_2001" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "qsys_top_altera_irq_mapper_2001_lp4cnei" -library "altera_irq_mapper_2001" -name IP_COMPONENT_VERSION "MjAuMC4x"
set_global_assignment -entity "qsys_top_altera_irq_mapper_2001_lp4cnei" -library "altera_irq_mapper_2001" -name IP_COMPONENT_DESCRIPTION "Q29udmVydHMgaW5kaXZpZHVhbCBpbnRlcnJ1cHQgd2lyZXMgdG8gYSBidXMuIEJ5IGRlZmF1bHQsIHRoZSBpbnRlcnJ1cHQgc2VuZGVyIGNvbm5lY3RlZCB0byB0aGUgcmVjZWl2ZXIwIGludGVyZmFjZSBvZiB0aGUgSVJRIG1hcHBlciBpcyB0aGUgaGlnaGVzdCBwcmlvcml0eSB3aXRoIHNlcXVlbnRpYWwgcmVjZWl2ZXJzIGJlaWluZyBzdWNjZXNzaXZlbHkgbG93ZXIgcHJpb3JpdHku"
set_global_assignment -entity "qsys_top_altera_irq_mapper_2001_lp4cnei" -library "altera_irq_mapper_2001" -name IP_COMPONENT_GROUP "SW50ZXJjb25uZWN0L0ludGVycnVwdA=="
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_NAME "YWx0ZXJhX3Jlc2V0X2NvbnRyb2xsZXI="
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_DISPLAY_NAME "TWVybGluIFJlc2V0IENvbnRyb2xsZXIgSVA="
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_VERSION "MTkuMi40"
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_DESCRIPTION "Rm9yIHN5c3RlbXMgd2l0aCBtdWx0aXBsZSByZXNldCBpbnB1dHMsIHRoZSBNZXJsaW4gUmVzZXQgQ29udHJvbGxlciBPUnMgYWxsIHJlc2V0IGlucHV0cyBhbmQgZ2VuZXJhdGVzIGEgc2luZ2xlIHJlc2V0IG91dHB1dC4="
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0Nsb2NrczsgUExMcyBhbmQgUmVzZXRz"
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3pjbjE1MTM5ODcyODI5MzUuaHRtbCNtd2gxNDA5OTU4ODI4NzMy"
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_COMPONENT_NAME "cXN5c190b3A="
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_COMPONENT_DISPLAY_NAME "cXN5c190b3A="
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "qsys_top" -library "qsys_top" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -library "altera_merlin_axi_translator_1987" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_axi_translator_1987/synth/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv"]
set_global_assignment -library "altera_merlin_slave_translator_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_slave_translator_191/synth/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv"]
set_global_assignment -library "altera_merlin_axi_master_ni_19117" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_axi_master_ni_19117/synth/altera_merlin_address_alignment.sv"]
set_global_assignment -library "altera_merlin_axi_master_ni_19117" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_axi_master_ni_19117/synth/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv"]
set_global_assignment -library "altera_merlin_slave_agent_1930" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_slave_agent_1930/synth/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv"]
set_global_assignment -library "altera_merlin_slave_agent_1930" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv"]
set_global_assignment -library "altera_avalon_sc_fifo_1932" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_sc_fifo_1932/synth/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v"]
set_global_assignment -library "altera_merlin_router_1921" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_router_1921/synth/qsys_top_altera_merlin_router_1921_ox5xuhq.sv"]
set_global_assignment -library "altera_merlin_router_1921" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_router_1921/synth/qsys_top_altera_merlin_router_1921_sxavatq.sv"]
set_global_assignment -library "altera_avalon_st_pipeline_stage_1930" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_st_pipeline_stage_1930/synth/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv"]
set_global_assignment -library "altera_avalon_st_pipeline_stage_1930" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_st_pipeline_stage_1930/synth/altera_avalon_st_pipeline_base.v"]
set_global_assignment -library "altera_merlin_burst_adapter_1940" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_burst_adapter_1940/synth/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v"]
set_global_assignment -library "altera_merlin_burst_adapter_1940" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_burst_adapter_1940/synth/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv"]
set_global_assignment -library "altera_merlin_burst_adapter_1940" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_uncmpr.sv"]
set_global_assignment -library "altera_merlin_burst_adapter_1940" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_13_1.sv"]
set_global_assignment -library "altera_merlin_burst_adapter_1940" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_new.sv"]
set_global_assignment -library "altera_merlin_burst_adapter_1940" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_burst_adapter_1940/synth/altera_incr_burst_converter.sv"]
set_global_assignment -library "altera_merlin_burst_adapter_1940" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_burst_adapter_1940/synth/altera_wrap_burst_converter.sv"]
set_global_assignment -library "altera_merlin_burst_adapter_1940" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_burst_adapter_1940/synth/altera_default_burst_converter.sv"]
set_global_assignment -library "altera_merlin_burst_adapter_1940" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_burst_adapter_1940/synth/altera_merlin_address_alignment.sv"]
set_global_assignment -library "altera_merlin_demultiplexer_1921" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv"]
set_global_assignment -library "altera_merlin_multiplexer_1922" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv"]
set_global_assignment -library "altera_merlin_multiplexer_1922" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv"]
set_global_assignment -library "altera_merlin_demultiplexer_1921" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv"]
set_global_assignment -library "altera_merlin_multiplexer_1922" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv"]
set_global_assignment -library "altera_mm_interconnect_1920" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_mm_interconnect_1920/synth/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v"]
set_global_assignment -library "altera_irq_mapper_2001" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_irq_mapper_2001/synth/qsys_top_altera_irq_mapper_2001_lp4cnei.sv"]
set_global_assignment -library "altera_reset_controller_1924" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_reset_controller_1924/synth/altera_reset_controller.v"]
set_global_assignment -library "altera_reset_controller_1924" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_reset_controller_1924/synth/altera_reset_synchronizer.v"]
set_instance_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name SDC_ENTITY_FILE [file join $::quartus(qip_path) "altera_reset_controller_1924/synth/altera_reset_controller.sdc"] -no_sdc_promotion
set_global_assignment -library "qsys_top" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/qsys_top.v"]
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_TOOL_NAME "altera_reset_controller"
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_TOOL_VERSION "19.2.4"
set_global_assignment -entity "altera_reset_controller" -library "altera_reset_controller_1924" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_irq_mapper_2001_lp4cnei" -library "altera_irq_mapper_2001" -name IP_TOOL_NAME "altera_irq_mapper"
set_global_assignment -entity "qsys_top_altera_irq_mapper_2001_lp4cnei" -library "altera_irq_mapper_2001" -name IP_TOOL_VERSION "20.0.1"
set_global_assignment -entity "qsys_top_altera_irq_mapper_2001_lp4cnei" -library "altera_irq_mapper_2001" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_mm_interconnect_1920_ykfyxdi" -library "altera_mm_interconnect_1920" -name IP_TOOL_NAME "altera_mm_interconnect"
set_global_assignment -entity "qsys_top_altera_mm_interconnect_1920_ykfyxdi" -library "altera_mm_interconnect_1920" -name IP_TOOL_VERSION "19.2.0"
set_global_assignment -entity "qsys_top_altera_mm_interconnect_1920_ykfyxdi" -library "altera_mm_interconnect_1920" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_TOOL_NAME "altera_merlin_multiplexer"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_TOOL_VERSION "19.2.2"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_yjgptii" -library "altera_merlin_multiplexer_1922" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_TOOL_VERSION "19.2.1"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_qyizksq" -library "altera_merlin_demultiplexer_1921" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_TOOL_NAME "altera_merlin_multiplexer"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_TOOL_VERSION "19.2.2"
set_global_assignment -entity "qsys_top_altera_merlin_multiplexer_1922_666s25q" -library "altera_merlin_multiplexer_1922" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_TOOL_VERSION "19.2.1"
set_global_assignment -entity "qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q" -library "altera_merlin_demultiplexer_1921" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_TOOL_NAME "altera_merlin_burst_adapter"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_TOOL_VERSION "19.4.0"
set_global_assignment -entity "qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy" -library "altera_merlin_burst_adapter_1940" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_TOOL_NAME "altera_avalon_st_pipeline_stage"
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_TOOL_VERSION "19.3.0"
set_global_assignment -entity "qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq" -library "altera_avalon_st_pipeline_stage_1930" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_TOOL_VERSION "19.2.1"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_sxavatq" -library "altera_merlin_router_1921" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_TOOL_VERSION "19.2.1"
set_global_assignment -entity "qsys_top_altera_merlin_router_1921_ox5xuhq" -library "altera_merlin_router_1921" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_TOOL_NAME "altera_avalon_sc_fifo"
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_TOOL_VERSION "19.3.2"
set_global_assignment -entity "qsys_top_altera_avalon_sc_fifo_1932_22gxxgi" -library "altera_avalon_sc_fifo_1932" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_TOOL_NAME "altera_merlin_slave_agent"
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_TOOL_VERSION "19.3.0"
set_global_assignment -entity "qsys_top_altera_merlin_slave_agent_1930_jxauz3i" -library "altera_merlin_slave_agent_1930" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_TOOL_NAME "altera_merlin_axi_master_ni"
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_TOOL_VERSION "19.11.7"
set_global_assignment -entity "qsys_top_altera_merlin_axi_master_ni_19117_qautany" -library "altera_merlin_axi_master_ni_19117" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_TOOL_NAME "altera_merlin_slave_translator"
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_TOOL_VERSION "19.1"
set_global_assignment -entity "qsys_top_altera_merlin_slave_translator_191_xg7rzxi" -library "altera_merlin_slave_translator_191" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_TOOL_NAME "altera_merlin_axi_translator"
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_TOOL_VERSION "19.8.7"
set_global_assignment -entity "qsys_top_altera_merlin_axi_translator_1987_lty7xoq" -library "altera_merlin_axi_translator_1987" -name IP_TOOL_ENV "QsysPrimePro"
qsys/qsys_top/qsys_top.sopcinfo
+31175
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qsys/qsys_top/qsys_top.spd
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<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_axi_translator_1987" />
<file
path="altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_slave_translator_191" />
<file
path="altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_axi_master_ni_19117" />
<file
path="altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_axi_master_ni_19117" />
<file
path="altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_slave_agent_1930" />
<file
path="altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_slave_agent_1930" />
<file
path="altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v"
type="VERILOG"
library="altera_avalon_sc_fifo_1932" />
<file
path="altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_router_1921" />
<file
path="altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_router_1921" />
<file
path="altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv"
type="SYSTEM_VERILOG"
library="altera_avalon_st_pipeline_stage_1930" />
<file
path="altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v"
type="SYSTEM_VERILOG"
library="altera_avalon_st_pipeline_stage_1930" />
<file
path="altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v"
type="VERILOG"
library="altera_merlin_burst_adapter_1940"
hasInlineConfiguration="true" />
<file
path="altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_burst_adapter_1940" />
<file
path="altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_burst_adapter_1940" />
<file
path="altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_burst_adapter_1940" />
<file
path="altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_burst_adapter_1940" />
<file
path="altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_burst_adapter_1940" />
<file
path="altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_burst_adapter_1940" />
<file
path="altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_burst_adapter_1940" />
<file
path="altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_burst_adapter_1940" />
<file
path="altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_demultiplexer_1921" />
<file
path="altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_multiplexer_1922" />
<file
path="altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_multiplexer_1922" />
<file
path="altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_demultiplexer_1921" />
<file
path="altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_multiplexer_1922" />
<file
path="altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="altera_merlin_multiplexer_1922" />
<file
path="altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v"
type="VERILOG"
library="altera_mm_interconnect_1920"
hasInlineConfiguration="true" />
<file
path="altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv"
type="SYSTEM_VERILOG"
library="altera_irq_mapper_2001" />
<file
path="altera_reset_controller_1924/sim/altera_reset_controller.v"
type="VERILOG"
library="altera_reset_controller_1924" />
<file
path="altera_reset_controller_1924/sim/altera_reset_synchronizer.v"
type="VERILOG"
library="altera_reset_controller_1924" />
<file
path="altera_reset_controller_1924/sim/altera_reset_controller.sdc"
type="SDC_ENTITY"
library="altera_reset_controller_1924" />
<file
path="sim/qsys_top.v"
type="VERILOG"
library="qsys_top"
hasInlineConfiguration="true" />
<topLevel name="qsys_top.qsys_top" />
<deviceFamily name="agilex5" />
<device name="A5EB013BB23BE4SCS" />
</simPackage>
qsys/qsys_top/qsys_top.xml
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qsys/qsys_top/qsys_top_bb.v
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module qsys_top (
input wire clk_100_clk, // clk_100.clk
input wire reset_reset_n, // reset.reset_n
output wire ninit_done_ninit_done, // ninit_done.ninit_done
output wire h2f_reset_reset, // h2f_reset.reset
output wire [3:0] subsys_hps_hps2fpga_awid, // subsys_hps_hps2fpga.awid
output wire [37:0] subsys_hps_hps2fpga_awaddr, // .awaddr
output wire [7:0] subsys_hps_hps2fpga_awlen, // .awlen
output wire [2:0] subsys_hps_hps2fpga_awsize, // .awsize
output wire [1:0] subsys_hps_hps2fpga_awburst, // .awburst
output wire subsys_hps_hps2fpga_awlock, // .awlock
output wire [3:0] subsys_hps_hps2fpga_awcache, // .awcache
output wire [2:0] subsys_hps_hps2fpga_awprot, // .awprot
output wire subsys_hps_hps2fpga_awvalid, // .awvalid
input wire subsys_hps_hps2fpga_awready, // .awready
output wire [127:0] subsys_hps_hps2fpga_wdata, // .wdata
output wire [15:0] subsys_hps_hps2fpga_wstrb, // .wstrb
output wire subsys_hps_hps2fpga_wlast, // .wlast
output wire subsys_hps_hps2fpga_wvalid, // .wvalid
input wire subsys_hps_hps2fpga_wready, // .wready
input wire [3:0] subsys_hps_hps2fpga_bid, // .bid
input wire [1:0] subsys_hps_hps2fpga_bresp, // .bresp
input wire subsys_hps_hps2fpga_bvalid, // .bvalid
output wire subsys_hps_hps2fpga_bready, // .bready
output wire [3:0] subsys_hps_hps2fpga_arid, // .arid
output wire [37:0] subsys_hps_hps2fpga_araddr, // .araddr
output wire [7:0] subsys_hps_hps2fpga_arlen, // .arlen
output wire [2:0] subsys_hps_hps2fpga_arsize, // .arsize
output wire [1:0] subsys_hps_hps2fpga_arburst, // .arburst
output wire subsys_hps_hps2fpga_arlock, // .arlock
output wire [3:0] subsys_hps_hps2fpga_arcache, // .arcache
output wire [2:0] subsys_hps_hps2fpga_arprot, // .arprot
output wire subsys_hps_hps2fpga_arvalid, // .arvalid
input wire subsys_hps_hps2fpga_arready, // .arready
input wire [3:0] subsys_hps_hps2fpga_rid, // .rid
input wire [127:0] subsys_hps_hps2fpga_rdata, // .rdata
input wire [1:0] subsys_hps_hps2fpga_rresp, // .rresp
input wire subsys_hps_hps2fpga_rlast, // .rlast
input wire subsys_hps_hps2fpga_rvalid, // .rvalid
output wire subsys_hps_hps2fpga_rready, // .rready
output wire subsys_hps_h2f_warm_reset_handshake_reset_req, // subsys_hps_h2f_warm_reset_handshake.reset_req
input wire subsys_hps_h2f_warm_reset_handshake_reset_ack, // .reset_ack
input wire hps_io_hps_osc_clk, // hps_io.hps_osc_clk
inout wire hps_io_sdmmc_data0, // .sdmmc_data0
inout wire hps_io_sdmmc_data1, // .sdmmc_data1
output wire hps_io_sdmmc_cclk, // .sdmmc_cclk
inout wire hps_io_sdmmc_data2, // .sdmmc_data2
inout wire hps_io_sdmmc_data3, // .sdmmc_data3
inout wire hps_io_sdmmc_cmd, // .sdmmc_cmd
input wire hps_io_usb0_clk, // .usb0_clk
output wire hps_io_usb0_stp, // .usb0_stp
input wire hps_io_usb0_dir, // .usb0_dir
inout wire hps_io_usb0_data0, // .usb0_data0
inout wire hps_io_usb0_data1, // .usb0_data1
input wire hps_io_usb0_nxt, // .usb0_nxt
inout wire hps_io_usb0_data2, // .usb0_data2
inout wire hps_io_usb0_data3, // .usb0_data3
inout wire hps_io_usb0_data4, // .usb0_data4
inout wire hps_io_usb0_data5, // .usb0_data5
inout wire hps_io_usb0_data6, // .usb0_data6
inout wire hps_io_usb0_data7, // .usb0_data7
output wire hps_io_emac0_tx_clk, // .emac0_tx_clk
output wire hps_io_emac0_tx_ctl, // .emac0_tx_ctl
input wire hps_io_emac0_rx_clk, // .emac0_rx_clk
input wire hps_io_emac0_rx_ctl, // .emac0_rx_ctl
output wire hps_io_emac0_txd0, // .emac0_txd0
output wire hps_io_emac0_txd1, // .emac0_txd1
input wire hps_io_emac0_rxd0, // .emac0_rxd0
input wire hps_io_emac0_rxd1, // .emac0_rxd1
output wire hps_io_emac0_txd2, // .emac0_txd2
output wire hps_io_emac0_txd3, // .emac0_txd3
input wire hps_io_emac0_rxd2, // .emac0_rxd2
input wire hps_io_emac0_rxd3, // .emac0_rxd3
inout wire hps_io_mdio0_mdio, // .mdio0_mdio
output wire hps_io_mdio0_mdc, // .mdio0_mdc
output wire hps_io_uart1_tx, // .uart1_tx
input wire hps_io_uart1_rx, // .uart1_rx
inout wire hps_io_i2c1_sda, // .i2c1_sda
inout wire hps_io_i2c1_scl, // .i2c1_scl
inout wire hps_io_gpio28, // .gpio28
inout wire hps_io_gpio34, // .gpio34
inout wire hps_io_gpio40, // .gpio40
inout wire hps_io_gpio41, // .gpio41
input wire [31:0] f2h_irq1_in_irq, // f2h_irq1_in.irq
input wire [31:0] f2sdram_araddr, // f2sdram.araddr
input wire [1:0] f2sdram_arburst, // .arburst
input wire [3:0] f2sdram_arcache, // .arcache
input wire [4:0] f2sdram_arid, // .arid
input wire [7:0] f2sdram_arlen, // .arlen
input wire f2sdram_arlock, // .arlock
input wire [2:0] f2sdram_arprot, // .arprot
input wire [3:0] f2sdram_arqos, // .arqos
output wire f2sdram_arready, // .arready
input wire [2:0] f2sdram_arsize, // .arsize
input wire f2sdram_arvalid, // .arvalid
input wire [31:0] f2sdram_awaddr, // .awaddr
input wire [1:0] f2sdram_awburst, // .awburst
input wire [3:0] f2sdram_awcache, // .awcache
input wire [4:0] f2sdram_awid, // .awid
input wire [7:0] f2sdram_awlen, // .awlen
input wire f2sdram_awlock, // .awlock
input wire [2:0] f2sdram_awprot, // .awprot
input wire [3:0] f2sdram_awqos, // .awqos
output wire f2sdram_awready, // .awready
input wire [2:0] f2sdram_awsize, // .awsize
input wire f2sdram_awvalid, // .awvalid
output wire [4:0] f2sdram_bid, // .bid
input wire f2sdram_bready, // .bready
output wire [1:0] f2sdram_bresp, // .bresp
output wire f2sdram_bvalid, // .bvalid
output wire [255:0] f2sdram_rdata, // .rdata
output wire [4:0] f2sdram_rid, // .rid
output wire f2sdram_rlast, // .rlast
input wire f2sdram_rready, // .rready
output wire [1:0] f2sdram_rresp, // .rresp
output wire f2sdram_rvalid, // .rvalid
input wire [255:0] f2sdram_wdata, // .wdata
input wire f2sdram_wlast, // .wlast
output wire f2sdram_wready, // .wready
input wire [31:0] f2sdram_wstrb, // .wstrb
input wire f2sdram_wvalid, // .wvalid
input wire [7:0] f2sdram_aruser, // .aruser
input wire [7:0] f2sdram_awuser, // .awuser
input wire [7:0] f2sdram_wuser, // .wuser
output wire [7:0] f2sdram_buser, // .buser
input wire [3:0] f2sdram_arregion, // .arregion
output wire [7:0] f2sdram_ruser, // .ruser
input wire [3:0] f2sdram_awregion, // .awregion
output wire [0:0] emif_hps_emif_mem_0_mem_cs, // emif_hps_emif_mem_0.mem_cs
output wire [5:0] emif_hps_emif_mem_0_mem_ca, // .mem_ca
output wire [0:0] emif_hps_emif_mem_0_mem_cke, // .mem_cke
inout wire [31:0] emif_hps_emif_mem_0_mem_dq, // .mem_dq
inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_t, // .mem_dqs_t
inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_c, // .mem_dqs_c
inout wire [3:0] emif_hps_emif_mem_0_mem_dmi, // .mem_dmi
output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_t, // emif_hps_emif_mem_ck_0.mem_ck_t
output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_c, // .mem_ck_c
output wire emif_hps_emif_mem_reset_n_mem_reset_n, // emif_hps_emif_mem_reset_n.mem_reset_n
input wire emif_hps_emif_oct_0_oct_rzqin, // emif_hps_emif_oct_0.oct_rzqin
input wire emif_hps_emif_ref_clk_0_clk, // emif_hps_emif_ref_clk_0.clk
input wire [3:0] button_pio_external_connection_export, // button_pio_external_connection.export
input wire [3:0] dipsw_pio_external_connection_export, // dipsw_pio_external_connection.export
input wire [2:0] led_pio_external_connection_in_port, // led_pio_external_connection.in_port
output wire [2:0] led_pio_external_connection_out_port // .out_port
);
endmodule
qsys/qsys_top/qsys_top_generation.rpt
+44
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Info: Generated by version: 26.1 build 110
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top.qsys --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top --family="Agilex 5" --part=A5EB013BB23BE4SCS
Progress: Loading qsys/qsys_top.qsys
Progress: Reading input file
Progress: Parameterizing module clk_100
Progress: Parameterizing module rst_in
Progress: Parameterizing module subsys_hps
Progress: Parameterizing module subsys_periph
Progress: Parameterizing module user_rst_clkgate_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: qsys_top: "Transforming system: qsys_top"
Info: Interconnect is inserted between master subsys_hps.lwhps2fpga and slave subsys_periph.pb_cpu_0_s0 because the master is of type axi4 and the slave is of type avalon.
Warning: subsys_hps.f2h_irq0_in: Cannot connect clock for irq_mapper.sender
Warning: subsys_hps.f2h_irq0_in: Cannot connect reset for irq_mapper.sender
Info: qsys_top: "Naming system components in system: qsys_top"
Info: qsys_top: "Processing generation queue"
Info: qsys_top: "Generating: qsys_top"
Info: qsys_top: "Generating: clk_100"
Info: qsys_top: "Generating: rst_in"
Info: qsys_top: "Generating: user_rst_clkgate_0"
Info: qsys_top: "Generating: qsys_top_altera_mm_interconnect_1920_ykfyxdi"
Info: qsys_top: "Generating: qsys_top_altera_irq_mapper_2001_lp4cnei"
Info: qsys_top: "Generating: altera_reset_controller"
Info: qsys_top: "Generating: qsys_top_altera_merlin_axi_translator_1987_lty7xoq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_slave_translator_191_xg7rzxi"
Info: qsys_top: "Generating: qsys_top_altera_merlin_axi_master_ni_19117_qautany"
Info: qsys_top: "Generating: qsys_top_altera_merlin_slave_agent_1930_jxauz3i"
Info: qsys_top: "Generating: qsys_top_altera_avalon_sc_fifo_1932_22gxxgi"
Info: qsys_top: "Generating: qsys_top_altera_merlin_router_1921_ox5xuhq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_router_1921_sxavatq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy"
Info: my_altera_avalon_st_pipeline_stage: "Generating: my_altera_avalon_st_pipeline_stage"
Info: qsys_top: "Generating: qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q"
Info: qsys_top: "Generating: qsys_top_altera_merlin_multiplexer_1922_666s25q"
Info: qsys_top: "Generating: qsys_top_altera_merlin_demultiplexer_1921_qyizksq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_multiplexer_1922_yjgptii"
Info: qsys_top: "Generating: qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di"
Info: qsys_top: Done "qsys_top" with 23 modules, 32 files
Info: Finished: Create HDL design files for synthesis
qsys/qsys_top/qsys_top_generation_previous.rpt
+44
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@@ -0,0 +1,44 @@
Info: Generated by version: 25.3.1 build 100
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top.qsys --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top --family="Agilex 5" --part=A5EB013BB23BE4SCS
Progress: Loading qsys/qsys_top.qsys
Progress: Reading input file
Progress: Parameterizing module clk_100
Progress: Parameterizing module rst_in
Progress: Parameterizing module subsys_hps
Progress: Parameterizing module subsys_periph
Progress: Parameterizing module user_rst_clkgate_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: qsys_top: "Transforming system: qsys_top"
Info: Interconnect is inserted between master subsys_hps.lwhps2fpga and slave subsys_periph.pb_cpu_0_s0 because the master is of type axi4 and the slave is of type avalon.
Warning: subsys_hps.f2h_irq0_in: Cannot connect clock for irq_mapper.sender
Warning: subsys_hps.f2h_irq0_in: Cannot connect reset for irq_mapper.sender
Info: qsys_top: "Naming system components in system: qsys_top"
Info: qsys_top: "Processing generation queue"
Info: qsys_top: "Generating: qsys_top"
Info: qsys_top: "Generating: clk_100"
Info: qsys_top: "Generating: rst_in"
Info: qsys_top: "Generating: user_rst_clkgate_0"
Info: qsys_top: "Generating: qsys_top_altera_mm_interconnect_1920_6wkpj2i"
Info: qsys_top: "Generating: qsys_top_altera_irq_mapper_2001_lp4cnei"
Info: qsys_top: "Generating: altera_reset_controller"
Info: qsys_top: "Generating: qsys_top_altera_merlin_axi_translator_1986_4khp5ei"
Info: qsys_top: "Generating: qsys_top_altera_merlin_slave_translator_191_xg7rzxi"
Info: qsys_top: "Generating: qsys_top_altera_merlin_axi_master_ni_19116_f5viiry"
Info: qsys_top: "Generating: qsys_top_altera_merlin_slave_agent_1930_jxauz3i"
Info: qsys_top: "Generating: qsys_top_altera_avalon_sc_fifo_1932_22gxxgi"
Info: qsys_top: "Generating: qsys_top_altera_merlin_router_1921_ox5xuhq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_router_1921_sxavatq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy"
Info: my_altera_avalon_st_pipeline_stage: "Generating: my_altera_avalon_st_pipeline_stage"
Info: qsys_top: "Generating: qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q"
Info: qsys_top: "Generating: qsys_top_altera_merlin_multiplexer_1922_666s25q"
Info: qsys_top: "Generating: qsys_top_altera_merlin_demultiplexer_1921_qyizksq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_multiplexer_1922_yjgptii"
Info: qsys_top: "Generating: qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di"
Info: qsys_top: Done "qsys_top" with 23 modules, 32 files
Info: Finished: Create HDL design files for synthesis
qsys/qsys_top/qsys_top_inst.v
+146
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qsys_top u0 (
.clk_100_clk (_connected_to_clk_100_clk_), // input, width = 1, clk_100.clk
.reset_reset_n (_connected_to_reset_reset_n_), // input, width = 1, reset.reset_n
.ninit_done_ninit_done (_connected_to_ninit_done_ninit_done_), // output, width = 1, ninit_done.ninit_done
.h2f_reset_reset (_connected_to_h2f_reset_reset_), // output, width = 1, h2f_reset.reset
.subsys_hps_hps2fpga_awid (_connected_to_subsys_hps_hps2fpga_awid_), // output, width = 4, subsys_hps_hps2fpga.awid
.subsys_hps_hps2fpga_awaddr (_connected_to_subsys_hps_hps2fpga_awaddr_), // output, width = 38, .awaddr
.subsys_hps_hps2fpga_awlen (_connected_to_subsys_hps_hps2fpga_awlen_), // output, width = 8, .awlen
.subsys_hps_hps2fpga_awsize (_connected_to_subsys_hps_hps2fpga_awsize_), // output, width = 3, .awsize
.subsys_hps_hps2fpga_awburst (_connected_to_subsys_hps_hps2fpga_awburst_), // output, width = 2, .awburst
.subsys_hps_hps2fpga_awlock (_connected_to_subsys_hps_hps2fpga_awlock_), // output, width = 1, .awlock
.subsys_hps_hps2fpga_awcache (_connected_to_subsys_hps_hps2fpga_awcache_), // output, width = 4, .awcache
.subsys_hps_hps2fpga_awprot (_connected_to_subsys_hps_hps2fpga_awprot_), // output, width = 3, .awprot
.subsys_hps_hps2fpga_awvalid (_connected_to_subsys_hps_hps2fpga_awvalid_), // output, width = 1, .awvalid
.subsys_hps_hps2fpga_awready (_connected_to_subsys_hps_hps2fpga_awready_), // input, width = 1, .awready
.subsys_hps_hps2fpga_wdata (_connected_to_subsys_hps_hps2fpga_wdata_), // output, width = 128, .wdata
.subsys_hps_hps2fpga_wstrb (_connected_to_subsys_hps_hps2fpga_wstrb_), // output, width = 16, .wstrb
.subsys_hps_hps2fpga_wlast (_connected_to_subsys_hps_hps2fpga_wlast_), // output, width = 1, .wlast
.subsys_hps_hps2fpga_wvalid (_connected_to_subsys_hps_hps2fpga_wvalid_), // output, width = 1, .wvalid
.subsys_hps_hps2fpga_wready (_connected_to_subsys_hps_hps2fpga_wready_), // input, width = 1, .wready
.subsys_hps_hps2fpga_bid (_connected_to_subsys_hps_hps2fpga_bid_), // input, width = 4, .bid
.subsys_hps_hps2fpga_bresp (_connected_to_subsys_hps_hps2fpga_bresp_), // input, width = 2, .bresp
.subsys_hps_hps2fpga_bvalid (_connected_to_subsys_hps_hps2fpga_bvalid_), // input, width = 1, .bvalid
.subsys_hps_hps2fpga_bready (_connected_to_subsys_hps_hps2fpga_bready_), // output, width = 1, .bready
.subsys_hps_hps2fpga_arid (_connected_to_subsys_hps_hps2fpga_arid_), // output, width = 4, .arid
.subsys_hps_hps2fpga_araddr (_connected_to_subsys_hps_hps2fpga_araddr_), // output, width = 38, .araddr
.subsys_hps_hps2fpga_arlen (_connected_to_subsys_hps_hps2fpga_arlen_), // output, width = 8, .arlen
.subsys_hps_hps2fpga_arsize (_connected_to_subsys_hps_hps2fpga_arsize_), // output, width = 3, .arsize
.subsys_hps_hps2fpga_arburst (_connected_to_subsys_hps_hps2fpga_arburst_), // output, width = 2, .arburst
.subsys_hps_hps2fpga_arlock (_connected_to_subsys_hps_hps2fpga_arlock_), // output, width = 1, .arlock
.subsys_hps_hps2fpga_arcache (_connected_to_subsys_hps_hps2fpga_arcache_), // output, width = 4, .arcache
.subsys_hps_hps2fpga_arprot (_connected_to_subsys_hps_hps2fpga_arprot_), // output, width = 3, .arprot
.subsys_hps_hps2fpga_arvalid (_connected_to_subsys_hps_hps2fpga_arvalid_), // output, width = 1, .arvalid
.subsys_hps_hps2fpga_arready (_connected_to_subsys_hps_hps2fpga_arready_), // input, width = 1, .arready
.subsys_hps_hps2fpga_rid (_connected_to_subsys_hps_hps2fpga_rid_), // input, width = 4, .rid
.subsys_hps_hps2fpga_rdata (_connected_to_subsys_hps_hps2fpga_rdata_), // input, width = 128, .rdata
.subsys_hps_hps2fpga_rresp (_connected_to_subsys_hps_hps2fpga_rresp_), // input, width = 2, .rresp
.subsys_hps_hps2fpga_rlast (_connected_to_subsys_hps_hps2fpga_rlast_), // input, width = 1, .rlast
.subsys_hps_hps2fpga_rvalid (_connected_to_subsys_hps_hps2fpga_rvalid_), // input, width = 1, .rvalid
.subsys_hps_hps2fpga_rready (_connected_to_subsys_hps_hps2fpga_rready_), // output, width = 1, .rready
.subsys_hps_h2f_warm_reset_handshake_reset_req (_connected_to_subsys_hps_h2f_warm_reset_handshake_reset_req_), // output, width = 1, subsys_hps_h2f_warm_reset_handshake.reset_req
.subsys_hps_h2f_warm_reset_handshake_reset_ack (_connected_to_subsys_hps_h2f_warm_reset_handshake_reset_ack_), // input, width = 1, .reset_ack
.hps_io_hps_osc_clk (_connected_to_hps_io_hps_osc_clk_), // input, width = 1, hps_io.hps_osc_clk
.hps_io_sdmmc_data0 (_connected_to_hps_io_sdmmc_data0_), // inout, width = 1, .sdmmc_data0
.hps_io_sdmmc_data1 (_connected_to_hps_io_sdmmc_data1_), // inout, width = 1, .sdmmc_data1
.hps_io_sdmmc_cclk (_connected_to_hps_io_sdmmc_cclk_), // output, width = 1, .sdmmc_cclk
.hps_io_sdmmc_data2 (_connected_to_hps_io_sdmmc_data2_), // inout, width = 1, .sdmmc_data2
.hps_io_sdmmc_data3 (_connected_to_hps_io_sdmmc_data3_), // inout, width = 1, .sdmmc_data3
.hps_io_sdmmc_cmd (_connected_to_hps_io_sdmmc_cmd_), // inout, width = 1, .sdmmc_cmd
.hps_io_usb0_clk (_connected_to_hps_io_usb0_clk_), // input, width = 1, .usb0_clk
.hps_io_usb0_stp (_connected_to_hps_io_usb0_stp_), // output, width = 1, .usb0_stp
.hps_io_usb0_dir (_connected_to_hps_io_usb0_dir_), // input, width = 1, .usb0_dir
.hps_io_usb0_data0 (_connected_to_hps_io_usb0_data0_), // inout, width = 1, .usb0_data0
.hps_io_usb0_data1 (_connected_to_hps_io_usb0_data1_), // inout, width = 1, .usb0_data1
.hps_io_usb0_nxt (_connected_to_hps_io_usb0_nxt_), // input, width = 1, .usb0_nxt
.hps_io_usb0_data2 (_connected_to_hps_io_usb0_data2_), // inout, width = 1, .usb0_data2
.hps_io_usb0_data3 (_connected_to_hps_io_usb0_data3_), // inout, width = 1, .usb0_data3
.hps_io_usb0_data4 (_connected_to_hps_io_usb0_data4_), // inout, width = 1, .usb0_data4
.hps_io_usb0_data5 (_connected_to_hps_io_usb0_data5_), // inout, width = 1, .usb0_data5
.hps_io_usb0_data6 (_connected_to_hps_io_usb0_data6_), // inout, width = 1, .usb0_data6
.hps_io_usb0_data7 (_connected_to_hps_io_usb0_data7_), // inout, width = 1, .usb0_data7
.hps_io_emac0_tx_clk (_connected_to_hps_io_emac0_tx_clk_), // output, width = 1, .emac0_tx_clk
.hps_io_emac0_tx_ctl (_connected_to_hps_io_emac0_tx_ctl_), // output, width = 1, .emac0_tx_ctl
.hps_io_emac0_rx_clk (_connected_to_hps_io_emac0_rx_clk_), // input, width = 1, .emac0_rx_clk
.hps_io_emac0_rx_ctl (_connected_to_hps_io_emac0_rx_ctl_), // input, width = 1, .emac0_rx_ctl
.hps_io_emac0_txd0 (_connected_to_hps_io_emac0_txd0_), // output, width = 1, .emac0_txd0
.hps_io_emac0_txd1 (_connected_to_hps_io_emac0_txd1_), // output, width = 1, .emac0_txd1
.hps_io_emac0_rxd0 (_connected_to_hps_io_emac0_rxd0_), // input, width = 1, .emac0_rxd0
.hps_io_emac0_rxd1 (_connected_to_hps_io_emac0_rxd1_), // input, width = 1, .emac0_rxd1
.hps_io_emac0_txd2 (_connected_to_hps_io_emac0_txd2_), // output, width = 1, .emac0_txd2
.hps_io_emac0_txd3 (_connected_to_hps_io_emac0_txd3_), // output, width = 1, .emac0_txd3
.hps_io_emac0_rxd2 (_connected_to_hps_io_emac0_rxd2_), // input, width = 1, .emac0_rxd2
.hps_io_emac0_rxd3 (_connected_to_hps_io_emac0_rxd3_), // input, width = 1, .emac0_rxd3
.hps_io_mdio0_mdio (_connected_to_hps_io_mdio0_mdio_), // inout, width = 1, .mdio0_mdio
.hps_io_mdio0_mdc (_connected_to_hps_io_mdio0_mdc_), // output, width = 1, .mdio0_mdc
.hps_io_uart1_tx (_connected_to_hps_io_uart1_tx_), // output, width = 1, .uart1_tx
.hps_io_uart1_rx (_connected_to_hps_io_uart1_rx_), // input, width = 1, .uart1_rx
.hps_io_i2c1_sda (_connected_to_hps_io_i2c1_sda_), // inout, width = 1, .i2c1_sda
.hps_io_i2c1_scl (_connected_to_hps_io_i2c1_scl_), // inout, width = 1, .i2c1_scl
.hps_io_gpio28 (_connected_to_hps_io_gpio28_), // inout, width = 1, .gpio28
.hps_io_gpio34 (_connected_to_hps_io_gpio34_), // inout, width = 1, .gpio34
.hps_io_gpio40 (_connected_to_hps_io_gpio40_), // inout, width = 1, .gpio40
.hps_io_gpio41 (_connected_to_hps_io_gpio41_), // inout, width = 1, .gpio41
.f2h_irq1_in_irq (_connected_to_f2h_irq1_in_irq_), // input, width = 32, f2h_irq1_in.irq
.f2sdram_araddr (_connected_to_f2sdram_araddr_), // input, width = 32, f2sdram.araddr
.f2sdram_arburst (_connected_to_f2sdram_arburst_), // input, width = 2, .arburst
.f2sdram_arcache (_connected_to_f2sdram_arcache_), // input, width = 4, .arcache
.f2sdram_arid (_connected_to_f2sdram_arid_), // input, width = 5, .arid
.f2sdram_arlen (_connected_to_f2sdram_arlen_), // input, width = 8, .arlen
.f2sdram_arlock (_connected_to_f2sdram_arlock_), // input, width = 1, .arlock
.f2sdram_arprot (_connected_to_f2sdram_arprot_), // input, width = 3, .arprot
.f2sdram_arqos (_connected_to_f2sdram_arqos_), // input, width = 4, .arqos
.f2sdram_arready (_connected_to_f2sdram_arready_), // output, width = 1, .arready
.f2sdram_arsize (_connected_to_f2sdram_arsize_), // input, width = 3, .arsize
.f2sdram_arvalid (_connected_to_f2sdram_arvalid_), // input, width = 1, .arvalid
.f2sdram_awaddr (_connected_to_f2sdram_awaddr_), // input, width = 32, .awaddr
.f2sdram_awburst (_connected_to_f2sdram_awburst_), // input, width = 2, .awburst
.f2sdram_awcache (_connected_to_f2sdram_awcache_), // input, width = 4, .awcache
.f2sdram_awid (_connected_to_f2sdram_awid_), // input, width = 5, .awid
.f2sdram_awlen (_connected_to_f2sdram_awlen_), // input, width = 8, .awlen
.f2sdram_awlock (_connected_to_f2sdram_awlock_), // input, width = 1, .awlock
.f2sdram_awprot (_connected_to_f2sdram_awprot_), // input, width = 3, .awprot
.f2sdram_awqos (_connected_to_f2sdram_awqos_), // input, width = 4, .awqos
.f2sdram_awready (_connected_to_f2sdram_awready_), // output, width = 1, .awready
.f2sdram_awsize (_connected_to_f2sdram_awsize_), // input, width = 3, .awsize
.f2sdram_awvalid (_connected_to_f2sdram_awvalid_), // input, width = 1, .awvalid
.f2sdram_bid (_connected_to_f2sdram_bid_), // output, width = 5, .bid
.f2sdram_bready (_connected_to_f2sdram_bready_), // input, width = 1, .bready
.f2sdram_bresp (_connected_to_f2sdram_bresp_), // output, width = 2, .bresp
.f2sdram_bvalid (_connected_to_f2sdram_bvalid_), // output, width = 1, .bvalid
.f2sdram_rdata (_connected_to_f2sdram_rdata_), // output, width = 256, .rdata
.f2sdram_rid (_connected_to_f2sdram_rid_), // output, width = 5, .rid
.f2sdram_rlast (_connected_to_f2sdram_rlast_), // output, width = 1, .rlast
.f2sdram_rready (_connected_to_f2sdram_rready_), // input, width = 1, .rready
.f2sdram_rresp (_connected_to_f2sdram_rresp_), // output, width = 2, .rresp
.f2sdram_rvalid (_connected_to_f2sdram_rvalid_), // output, width = 1, .rvalid
.f2sdram_wdata (_connected_to_f2sdram_wdata_), // input, width = 256, .wdata
.f2sdram_wlast (_connected_to_f2sdram_wlast_), // input, width = 1, .wlast
.f2sdram_wready (_connected_to_f2sdram_wready_), // output, width = 1, .wready
.f2sdram_wstrb (_connected_to_f2sdram_wstrb_), // input, width = 32, .wstrb
.f2sdram_wvalid (_connected_to_f2sdram_wvalid_), // input, width = 1, .wvalid
.f2sdram_aruser (_connected_to_f2sdram_aruser_), // input, width = 8, .aruser
.f2sdram_awuser (_connected_to_f2sdram_awuser_), // input, width = 8, .awuser
.f2sdram_wuser (_connected_to_f2sdram_wuser_), // input, width = 8, .wuser
.f2sdram_buser (_connected_to_f2sdram_buser_), // output, width = 8, .buser
.f2sdram_arregion (_connected_to_f2sdram_arregion_), // input, width = 4, .arregion
.f2sdram_ruser (_connected_to_f2sdram_ruser_), // output, width = 8, .ruser
.f2sdram_awregion (_connected_to_f2sdram_awregion_), // input, width = 4, .awregion
.emif_hps_emif_mem_0_mem_cs (_connected_to_emif_hps_emif_mem_0_mem_cs_), // output, width = 1, emif_hps_emif_mem_0.mem_cs
.emif_hps_emif_mem_0_mem_ca (_connected_to_emif_hps_emif_mem_0_mem_ca_), // output, width = 6, .mem_ca
.emif_hps_emif_mem_0_mem_cke (_connected_to_emif_hps_emif_mem_0_mem_cke_), // output, width = 1, .mem_cke
.emif_hps_emif_mem_0_mem_dq (_connected_to_emif_hps_emif_mem_0_mem_dq_), // inout, width = 32, .mem_dq
.emif_hps_emif_mem_0_mem_dqs_t (_connected_to_emif_hps_emif_mem_0_mem_dqs_t_), // inout, width = 4, .mem_dqs_t
.emif_hps_emif_mem_0_mem_dqs_c (_connected_to_emif_hps_emif_mem_0_mem_dqs_c_), // inout, width = 4, .mem_dqs_c
.emif_hps_emif_mem_0_mem_dmi (_connected_to_emif_hps_emif_mem_0_mem_dmi_), // inout, width = 4, .mem_dmi
.emif_hps_emif_mem_ck_0_mem_ck_t (_connected_to_emif_hps_emif_mem_ck_0_mem_ck_t_), // output, width = 1, emif_hps_emif_mem_ck_0.mem_ck_t
.emif_hps_emif_mem_ck_0_mem_ck_c (_connected_to_emif_hps_emif_mem_ck_0_mem_ck_c_), // output, width = 1, .mem_ck_c
.emif_hps_emif_mem_reset_n_mem_reset_n (_connected_to_emif_hps_emif_mem_reset_n_mem_reset_n_), // output, width = 1, emif_hps_emif_mem_reset_n.mem_reset_n
.emif_hps_emif_oct_0_oct_rzqin (_connected_to_emif_hps_emif_oct_0_oct_rzqin_), // input, width = 1, emif_hps_emif_oct_0.oct_rzqin
.emif_hps_emif_ref_clk_0_clk (_connected_to_emif_hps_emif_ref_clk_0_clk_), // input, width = 1, emif_hps_emif_ref_clk_0.clk
.button_pio_external_connection_export (_connected_to_button_pio_external_connection_export_), // input, width = 4, button_pio_external_connection.export
.dipsw_pio_external_connection_export (_connected_to_dipsw_pio_external_connection_export_), // input, width = 4, dipsw_pio_external_connection.export
.led_pio_external_connection_in_port (_connected_to_led_pio_external_connection_in_port_), // input, width = 3, led_pio_external_connection.in_port
.led_pio_external_connection_out_port (_connected_to_led_pio_external_connection_out_port_) // output, width = 3, .out_port
);
qsys/qsys_top/qsys_top_inst.vhd
+295
View File
@@ -0,0 +1,295 @@
component qsys_top is
port (
clk_100_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
ninit_done_ninit_done : out std_logic; -- ninit_done
h2f_reset_reset : out std_logic; -- reset
subsys_hps_hps2fpga_awid : out std_logic_vector(3 downto 0); -- awid
subsys_hps_hps2fpga_awaddr : out std_logic_vector(37 downto 0); -- awaddr
subsys_hps_hps2fpga_awlen : out std_logic_vector(7 downto 0); -- awlen
subsys_hps_hps2fpga_awsize : out std_logic_vector(2 downto 0); -- awsize
subsys_hps_hps2fpga_awburst : out std_logic_vector(1 downto 0); -- awburst
subsys_hps_hps2fpga_awlock : out std_logic; -- awlock
subsys_hps_hps2fpga_awcache : out std_logic_vector(3 downto 0); -- awcache
subsys_hps_hps2fpga_awprot : out std_logic_vector(2 downto 0); -- awprot
subsys_hps_hps2fpga_awvalid : out std_logic; -- awvalid
subsys_hps_hps2fpga_awready : in std_logic := 'X'; -- awready
subsys_hps_hps2fpga_wdata : out std_logic_vector(127 downto 0); -- wdata
subsys_hps_hps2fpga_wstrb : out std_logic_vector(15 downto 0); -- wstrb
subsys_hps_hps2fpga_wlast : out std_logic; -- wlast
subsys_hps_hps2fpga_wvalid : out std_logic; -- wvalid
subsys_hps_hps2fpga_wready : in std_logic := 'X'; -- wready
subsys_hps_hps2fpga_bid : in std_logic_vector(3 downto 0) := (others => 'X'); -- bid
subsys_hps_hps2fpga_bresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp
subsys_hps_hps2fpga_bvalid : in std_logic := 'X'; -- bvalid
subsys_hps_hps2fpga_bready : out std_logic; -- bready
subsys_hps_hps2fpga_arid : out std_logic_vector(3 downto 0); -- arid
subsys_hps_hps2fpga_araddr : out std_logic_vector(37 downto 0); -- araddr
subsys_hps_hps2fpga_arlen : out std_logic_vector(7 downto 0); -- arlen
subsys_hps_hps2fpga_arsize : out std_logic_vector(2 downto 0); -- arsize
subsys_hps_hps2fpga_arburst : out std_logic_vector(1 downto 0); -- arburst
subsys_hps_hps2fpga_arlock : out std_logic; -- arlock
subsys_hps_hps2fpga_arcache : out std_logic_vector(3 downto 0); -- arcache
subsys_hps_hps2fpga_arprot : out std_logic_vector(2 downto 0); -- arprot
subsys_hps_hps2fpga_arvalid : out std_logic; -- arvalid
subsys_hps_hps2fpga_arready : in std_logic := 'X'; -- arready
subsys_hps_hps2fpga_rid : in std_logic_vector(3 downto 0) := (others => 'X'); -- rid
subsys_hps_hps2fpga_rdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- rdata
subsys_hps_hps2fpga_rresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp
subsys_hps_hps2fpga_rlast : in std_logic := 'X'; -- rlast
subsys_hps_hps2fpga_rvalid : in std_logic := 'X'; -- rvalid
subsys_hps_hps2fpga_rready : out std_logic; -- rready
subsys_hps_h2f_warm_reset_handshake_reset_req : out std_logic; -- reset_req
subsys_hps_h2f_warm_reset_handshake_reset_ack : in std_logic := 'X'; -- reset_ack
hps_io_hps_osc_clk : in std_logic := 'X'; -- hps_osc_clk
hps_io_sdmmc_data0 : inout std_logic := 'X'; -- sdmmc_data0
hps_io_sdmmc_data1 : inout std_logic := 'X'; -- sdmmc_data1
hps_io_sdmmc_cclk : out std_logic; -- sdmmc_cclk
hps_io_sdmmc_data2 : inout std_logic := 'X'; -- sdmmc_data2
hps_io_sdmmc_data3 : inout std_logic := 'X'; -- sdmmc_data3
hps_io_sdmmc_cmd : inout std_logic := 'X'; -- sdmmc_cmd
hps_io_usb0_clk : in std_logic := 'X'; -- usb0_clk
hps_io_usb0_stp : out std_logic; -- usb0_stp
hps_io_usb0_dir : in std_logic := 'X'; -- usb0_dir
hps_io_usb0_data0 : inout std_logic := 'X'; -- usb0_data0
hps_io_usb0_data1 : inout std_logic := 'X'; -- usb0_data1
hps_io_usb0_nxt : in std_logic := 'X'; -- usb0_nxt
hps_io_usb0_data2 : inout std_logic := 'X'; -- usb0_data2
hps_io_usb0_data3 : inout std_logic := 'X'; -- usb0_data3
hps_io_usb0_data4 : inout std_logic := 'X'; -- usb0_data4
hps_io_usb0_data5 : inout std_logic := 'X'; -- usb0_data5
hps_io_usb0_data6 : inout std_logic := 'X'; -- usb0_data6
hps_io_usb0_data7 : inout std_logic := 'X'; -- usb0_data7
hps_io_emac0_tx_clk : out std_logic; -- emac0_tx_clk
hps_io_emac0_tx_ctl : out std_logic; -- emac0_tx_ctl
hps_io_emac0_rx_clk : in std_logic := 'X'; -- emac0_rx_clk
hps_io_emac0_rx_ctl : in std_logic := 'X'; -- emac0_rx_ctl
hps_io_emac0_txd0 : out std_logic; -- emac0_txd0
hps_io_emac0_txd1 : out std_logic; -- emac0_txd1
hps_io_emac0_rxd0 : in std_logic := 'X'; -- emac0_rxd0
hps_io_emac0_rxd1 : in std_logic := 'X'; -- emac0_rxd1
hps_io_emac0_txd2 : out std_logic; -- emac0_txd2
hps_io_emac0_txd3 : out std_logic; -- emac0_txd3
hps_io_emac0_rxd2 : in std_logic := 'X'; -- emac0_rxd2
hps_io_emac0_rxd3 : in std_logic := 'X'; -- emac0_rxd3
hps_io_mdio0_mdio : inout std_logic := 'X'; -- mdio0_mdio
hps_io_mdio0_mdc : out std_logic; -- mdio0_mdc
hps_io_uart1_tx : out std_logic; -- uart1_tx
hps_io_uart1_rx : in std_logic := 'X'; -- uart1_rx
hps_io_i2c1_sda : inout std_logic := 'X'; -- i2c1_sda
hps_io_i2c1_scl : inout std_logic := 'X'; -- i2c1_scl
hps_io_gpio28 : inout std_logic := 'X'; -- gpio28
hps_io_gpio34 : inout std_logic := 'X'; -- gpio34
hps_io_gpio40 : inout std_logic := 'X'; -- gpio40
hps_io_gpio41 : inout std_logic := 'X'; -- gpio41
f2h_irq1_in_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
f2sdram_araddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- araddr
f2sdram_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst
f2sdram_arcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- arcache
f2sdram_arid : in std_logic_vector(4 downto 0) := (others => 'X'); -- arid
f2sdram_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- arlen
f2sdram_arlock : in std_logic := 'X'; -- arlock
f2sdram_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
f2sdram_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- arqos
f2sdram_arready : out std_logic; -- arready
f2sdram_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize
f2sdram_arvalid : in std_logic := 'X'; -- arvalid
f2sdram_awaddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- awaddr
f2sdram_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst
f2sdram_awcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- awcache
f2sdram_awid : in std_logic_vector(4 downto 0) := (others => 'X'); -- awid
f2sdram_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- awlen
f2sdram_awlock : in std_logic := 'X'; -- awlock
f2sdram_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
f2sdram_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- awqos
f2sdram_awready : out std_logic; -- awready
f2sdram_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize
f2sdram_awvalid : in std_logic := 'X'; -- awvalid
f2sdram_bid : out std_logic_vector(4 downto 0); -- bid
f2sdram_bready : in std_logic := 'X'; -- bready
f2sdram_bresp : out std_logic_vector(1 downto 0); -- bresp
f2sdram_bvalid : out std_logic; -- bvalid
f2sdram_rdata : out std_logic_vector(255 downto 0); -- rdata
f2sdram_rid : out std_logic_vector(4 downto 0); -- rid
f2sdram_rlast : out std_logic; -- rlast
f2sdram_rready : in std_logic := 'X'; -- rready
f2sdram_rresp : out std_logic_vector(1 downto 0); -- rresp
f2sdram_rvalid : out std_logic; -- rvalid
f2sdram_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- wdata
f2sdram_wlast : in std_logic := 'X'; -- wlast
f2sdram_wready : out std_logic; -- wready
f2sdram_wstrb : in std_logic_vector(31 downto 0) := (others => 'X'); -- wstrb
f2sdram_wvalid : in std_logic := 'X'; -- wvalid
f2sdram_aruser : in std_logic_vector(7 downto 0) := (others => 'X'); -- aruser
f2sdram_awuser : in std_logic_vector(7 downto 0) := (others => 'X'); -- awuser
f2sdram_wuser : in std_logic_vector(7 downto 0) := (others => 'X'); -- wuser
f2sdram_buser : out std_logic_vector(7 downto 0); -- buser
f2sdram_arregion : in std_logic_vector(3 downto 0) := (others => 'X'); -- arregion
f2sdram_ruser : out std_logic_vector(7 downto 0); -- ruser
f2sdram_awregion : in std_logic_vector(3 downto 0) := (others => 'X'); -- awregion
emif_hps_emif_mem_0_mem_cs : out std_logic_vector(0 downto 0); -- mem_cs
emif_hps_emif_mem_0_mem_ca : out std_logic_vector(5 downto 0); -- mem_ca
emif_hps_emif_mem_0_mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
emif_hps_emif_mem_0_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
emif_hps_emif_mem_0_mem_dqs_t : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_t
emif_hps_emif_mem_0_mem_dqs_c : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_c
emif_hps_emif_mem_0_mem_dmi : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dmi
emif_hps_emif_mem_ck_0_mem_ck_t : out std_logic_vector(0 downto 0); -- mem_ck_t
emif_hps_emif_mem_ck_0_mem_ck_c : out std_logic_vector(0 downto 0); -- mem_ck_c
emif_hps_emif_mem_reset_n_mem_reset_n : out std_logic; -- mem_reset_n
emif_hps_emif_oct_0_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
emif_hps_emif_ref_clk_0_clk : in std_logic := 'X'; -- clk
button_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
dipsw_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
led_pio_external_connection_in_port : in std_logic_vector(2 downto 0) := (others => 'X'); -- in_port
led_pio_external_connection_out_port : out std_logic_vector(2 downto 0) -- out_port
);
end component qsys_top;
u0 : component qsys_top
port map (
clk_100_clk => CONNECTED_TO_clk_100_clk, -- clk_100.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
ninit_done_ninit_done => CONNECTED_TO_ninit_done_ninit_done, -- ninit_done.ninit_done
h2f_reset_reset => CONNECTED_TO_h2f_reset_reset, -- h2f_reset.reset
subsys_hps_hps2fpga_awid => CONNECTED_TO_subsys_hps_hps2fpga_awid, -- subsys_hps_hps2fpga.awid
subsys_hps_hps2fpga_awaddr => CONNECTED_TO_subsys_hps_hps2fpga_awaddr, -- .awaddr
subsys_hps_hps2fpga_awlen => CONNECTED_TO_subsys_hps_hps2fpga_awlen, -- .awlen
subsys_hps_hps2fpga_awsize => CONNECTED_TO_subsys_hps_hps2fpga_awsize, -- .awsize
subsys_hps_hps2fpga_awburst => CONNECTED_TO_subsys_hps_hps2fpga_awburst, -- .awburst
subsys_hps_hps2fpga_awlock => CONNECTED_TO_subsys_hps_hps2fpga_awlock, -- .awlock
subsys_hps_hps2fpga_awcache => CONNECTED_TO_subsys_hps_hps2fpga_awcache, -- .awcache
subsys_hps_hps2fpga_awprot => CONNECTED_TO_subsys_hps_hps2fpga_awprot, -- .awprot
subsys_hps_hps2fpga_awvalid => CONNECTED_TO_subsys_hps_hps2fpga_awvalid, -- .awvalid
subsys_hps_hps2fpga_awready => CONNECTED_TO_subsys_hps_hps2fpga_awready, -- .awready
subsys_hps_hps2fpga_wdata => CONNECTED_TO_subsys_hps_hps2fpga_wdata, -- .wdata
subsys_hps_hps2fpga_wstrb => CONNECTED_TO_subsys_hps_hps2fpga_wstrb, -- .wstrb
subsys_hps_hps2fpga_wlast => CONNECTED_TO_subsys_hps_hps2fpga_wlast, -- .wlast
subsys_hps_hps2fpga_wvalid => CONNECTED_TO_subsys_hps_hps2fpga_wvalid, -- .wvalid
subsys_hps_hps2fpga_wready => CONNECTED_TO_subsys_hps_hps2fpga_wready, -- .wready
subsys_hps_hps2fpga_bid => CONNECTED_TO_subsys_hps_hps2fpga_bid, -- .bid
subsys_hps_hps2fpga_bresp => CONNECTED_TO_subsys_hps_hps2fpga_bresp, -- .bresp
subsys_hps_hps2fpga_bvalid => CONNECTED_TO_subsys_hps_hps2fpga_bvalid, -- .bvalid
subsys_hps_hps2fpga_bready => CONNECTED_TO_subsys_hps_hps2fpga_bready, -- .bready
subsys_hps_hps2fpga_arid => CONNECTED_TO_subsys_hps_hps2fpga_arid, -- .arid
subsys_hps_hps2fpga_araddr => CONNECTED_TO_subsys_hps_hps2fpga_araddr, -- .araddr
subsys_hps_hps2fpga_arlen => CONNECTED_TO_subsys_hps_hps2fpga_arlen, -- .arlen
subsys_hps_hps2fpga_arsize => CONNECTED_TO_subsys_hps_hps2fpga_arsize, -- .arsize
subsys_hps_hps2fpga_arburst => CONNECTED_TO_subsys_hps_hps2fpga_arburst, -- .arburst
subsys_hps_hps2fpga_arlock => CONNECTED_TO_subsys_hps_hps2fpga_arlock, -- .arlock
subsys_hps_hps2fpga_arcache => CONNECTED_TO_subsys_hps_hps2fpga_arcache, -- .arcache
subsys_hps_hps2fpga_arprot => CONNECTED_TO_subsys_hps_hps2fpga_arprot, -- .arprot
subsys_hps_hps2fpga_arvalid => CONNECTED_TO_subsys_hps_hps2fpga_arvalid, -- .arvalid
subsys_hps_hps2fpga_arready => CONNECTED_TO_subsys_hps_hps2fpga_arready, -- .arready
subsys_hps_hps2fpga_rid => CONNECTED_TO_subsys_hps_hps2fpga_rid, -- .rid
subsys_hps_hps2fpga_rdata => CONNECTED_TO_subsys_hps_hps2fpga_rdata, -- .rdata
subsys_hps_hps2fpga_rresp => CONNECTED_TO_subsys_hps_hps2fpga_rresp, -- .rresp
subsys_hps_hps2fpga_rlast => CONNECTED_TO_subsys_hps_hps2fpga_rlast, -- .rlast
subsys_hps_hps2fpga_rvalid => CONNECTED_TO_subsys_hps_hps2fpga_rvalid, -- .rvalid
subsys_hps_hps2fpga_rready => CONNECTED_TO_subsys_hps_hps2fpga_rready, -- .rready
subsys_hps_h2f_warm_reset_handshake_reset_req => CONNECTED_TO_subsys_hps_h2f_warm_reset_handshake_reset_req, -- subsys_hps_h2f_warm_reset_handshake.reset_req
subsys_hps_h2f_warm_reset_handshake_reset_ack => CONNECTED_TO_subsys_hps_h2f_warm_reset_handshake_reset_ack, -- .reset_ack
hps_io_hps_osc_clk => CONNECTED_TO_hps_io_hps_osc_clk, -- hps_io.hps_osc_clk
hps_io_sdmmc_data0 => CONNECTED_TO_hps_io_sdmmc_data0, -- .sdmmc_data0
hps_io_sdmmc_data1 => CONNECTED_TO_hps_io_sdmmc_data1, -- .sdmmc_data1
hps_io_sdmmc_cclk => CONNECTED_TO_hps_io_sdmmc_cclk, -- .sdmmc_cclk
hps_io_sdmmc_data2 => CONNECTED_TO_hps_io_sdmmc_data2, -- .sdmmc_data2
hps_io_sdmmc_data3 => CONNECTED_TO_hps_io_sdmmc_data3, -- .sdmmc_data3
hps_io_sdmmc_cmd => CONNECTED_TO_hps_io_sdmmc_cmd, -- .sdmmc_cmd
hps_io_usb0_clk => CONNECTED_TO_hps_io_usb0_clk, -- .usb0_clk
hps_io_usb0_stp => CONNECTED_TO_hps_io_usb0_stp, -- .usb0_stp
hps_io_usb0_dir => CONNECTED_TO_hps_io_usb0_dir, -- .usb0_dir
hps_io_usb0_data0 => CONNECTED_TO_hps_io_usb0_data0, -- .usb0_data0
hps_io_usb0_data1 => CONNECTED_TO_hps_io_usb0_data1, -- .usb0_data1
hps_io_usb0_nxt => CONNECTED_TO_hps_io_usb0_nxt, -- .usb0_nxt
hps_io_usb0_data2 => CONNECTED_TO_hps_io_usb0_data2, -- .usb0_data2
hps_io_usb0_data3 => CONNECTED_TO_hps_io_usb0_data3, -- .usb0_data3
hps_io_usb0_data4 => CONNECTED_TO_hps_io_usb0_data4, -- .usb0_data4
hps_io_usb0_data5 => CONNECTED_TO_hps_io_usb0_data5, -- .usb0_data5
hps_io_usb0_data6 => CONNECTED_TO_hps_io_usb0_data6, -- .usb0_data6
hps_io_usb0_data7 => CONNECTED_TO_hps_io_usb0_data7, -- .usb0_data7
hps_io_emac0_tx_clk => CONNECTED_TO_hps_io_emac0_tx_clk, -- .emac0_tx_clk
hps_io_emac0_tx_ctl => CONNECTED_TO_hps_io_emac0_tx_ctl, -- .emac0_tx_ctl
hps_io_emac0_rx_clk => CONNECTED_TO_hps_io_emac0_rx_clk, -- .emac0_rx_clk
hps_io_emac0_rx_ctl => CONNECTED_TO_hps_io_emac0_rx_ctl, -- .emac0_rx_ctl
hps_io_emac0_txd0 => CONNECTED_TO_hps_io_emac0_txd0, -- .emac0_txd0
hps_io_emac0_txd1 => CONNECTED_TO_hps_io_emac0_txd1, -- .emac0_txd1
hps_io_emac0_rxd0 => CONNECTED_TO_hps_io_emac0_rxd0, -- .emac0_rxd0
hps_io_emac0_rxd1 => CONNECTED_TO_hps_io_emac0_rxd1, -- .emac0_rxd1
hps_io_emac0_txd2 => CONNECTED_TO_hps_io_emac0_txd2, -- .emac0_txd2
hps_io_emac0_txd3 => CONNECTED_TO_hps_io_emac0_txd3, -- .emac0_txd3
hps_io_emac0_rxd2 => CONNECTED_TO_hps_io_emac0_rxd2, -- .emac0_rxd2
hps_io_emac0_rxd3 => CONNECTED_TO_hps_io_emac0_rxd3, -- .emac0_rxd3
hps_io_mdio0_mdio => CONNECTED_TO_hps_io_mdio0_mdio, -- .mdio0_mdio
hps_io_mdio0_mdc => CONNECTED_TO_hps_io_mdio0_mdc, -- .mdio0_mdc
hps_io_uart1_tx => CONNECTED_TO_hps_io_uart1_tx, -- .uart1_tx
hps_io_uart1_rx => CONNECTED_TO_hps_io_uart1_rx, -- .uart1_rx
hps_io_i2c1_sda => CONNECTED_TO_hps_io_i2c1_sda, -- .i2c1_sda
hps_io_i2c1_scl => CONNECTED_TO_hps_io_i2c1_scl, -- .i2c1_scl
hps_io_gpio28 => CONNECTED_TO_hps_io_gpio28, -- .gpio28
hps_io_gpio34 => CONNECTED_TO_hps_io_gpio34, -- .gpio34
hps_io_gpio40 => CONNECTED_TO_hps_io_gpio40, -- .gpio40
hps_io_gpio41 => CONNECTED_TO_hps_io_gpio41, -- .gpio41
f2h_irq1_in_irq => CONNECTED_TO_f2h_irq1_in_irq, -- f2h_irq1_in.irq
f2sdram_araddr => CONNECTED_TO_f2sdram_araddr, -- f2sdram.araddr
f2sdram_arburst => CONNECTED_TO_f2sdram_arburst, -- .arburst
f2sdram_arcache => CONNECTED_TO_f2sdram_arcache, -- .arcache
f2sdram_arid => CONNECTED_TO_f2sdram_arid, -- .arid
f2sdram_arlen => CONNECTED_TO_f2sdram_arlen, -- .arlen
f2sdram_arlock => CONNECTED_TO_f2sdram_arlock, -- .arlock
f2sdram_arprot => CONNECTED_TO_f2sdram_arprot, -- .arprot
f2sdram_arqos => CONNECTED_TO_f2sdram_arqos, -- .arqos
f2sdram_arready => CONNECTED_TO_f2sdram_arready, -- .arready
f2sdram_arsize => CONNECTED_TO_f2sdram_arsize, -- .arsize
f2sdram_arvalid => CONNECTED_TO_f2sdram_arvalid, -- .arvalid
f2sdram_awaddr => CONNECTED_TO_f2sdram_awaddr, -- .awaddr
f2sdram_awburst => CONNECTED_TO_f2sdram_awburst, -- .awburst
f2sdram_awcache => CONNECTED_TO_f2sdram_awcache, -- .awcache
f2sdram_awid => CONNECTED_TO_f2sdram_awid, -- .awid
f2sdram_awlen => CONNECTED_TO_f2sdram_awlen, -- .awlen
f2sdram_awlock => CONNECTED_TO_f2sdram_awlock, -- .awlock
f2sdram_awprot => CONNECTED_TO_f2sdram_awprot, -- .awprot
f2sdram_awqos => CONNECTED_TO_f2sdram_awqos, -- .awqos
f2sdram_awready => CONNECTED_TO_f2sdram_awready, -- .awready
f2sdram_awsize => CONNECTED_TO_f2sdram_awsize, -- .awsize
f2sdram_awvalid => CONNECTED_TO_f2sdram_awvalid, -- .awvalid
f2sdram_bid => CONNECTED_TO_f2sdram_bid, -- .bid
f2sdram_bready => CONNECTED_TO_f2sdram_bready, -- .bready
f2sdram_bresp => CONNECTED_TO_f2sdram_bresp, -- .bresp
f2sdram_bvalid => CONNECTED_TO_f2sdram_bvalid, -- .bvalid
f2sdram_rdata => CONNECTED_TO_f2sdram_rdata, -- .rdata
f2sdram_rid => CONNECTED_TO_f2sdram_rid, -- .rid
f2sdram_rlast => CONNECTED_TO_f2sdram_rlast, -- .rlast
f2sdram_rready => CONNECTED_TO_f2sdram_rready, -- .rready
f2sdram_rresp => CONNECTED_TO_f2sdram_rresp, -- .rresp
f2sdram_rvalid => CONNECTED_TO_f2sdram_rvalid, -- .rvalid
f2sdram_wdata => CONNECTED_TO_f2sdram_wdata, -- .wdata
f2sdram_wlast => CONNECTED_TO_f2sdram_wlast, -- .wlast
f2sdram_wready => CONNECTED_TO_f2sdram_wready, -- .wready
f2sdram_wstrb => CONNECTED_TO_f2sdram_wstrb, -- .wstrb
f2sdram_wvalid => CONNECTED_TO_f2sdram_wvalid, -- .wvalid
f2sdram_aruser => CONNECTED_TO_f2sdram_aruser, -- .aruser
f2sdram_awuser => CONNECTED_TO_f2sdram_awuser, -- .awuser
f2sdram_wuser => CONNECTED_TO_f2sdram_wuser, -- .wuser
f2sdram_buser => CONNECTED_TO_f2sdram_buser, -- .buser
f2sdram_arregion => CONNECTED_TO_f2sdram_arregion, -- .arregion
f2sdram_ruser => CONNECTED_TO_f2sdram_ruser, -- .ruser
f2sdram_awregion => CONNECTED_TO_f2sdram_awregion, -- .awregion
emif_hps_emif_mem_0_mem_cs => CONNECTED_TO_emif_hps_emif_mem_0_mem_cs, -- emif_hps_emif_mem_0.mem_cs
emif_hps_emif_mem_0_mem_ca => CONNECTED_TO_emif_hps_emif_mem_0_mem_ca, -- .mem_ca
emif_hps_emif_mem_0_mem_cke => CONNECTED_TO_emif_hps_emif_mem_0_mem_cke, -- .mem_cke
emif_hps_emif_mem_0_mem_dq => CONNECTED_TO_emif_hps_emif_mem_0_mem_dq, -- .mem_dq
emif_hps_emif_mem_0_mem_dqs_t => CONNECTED_TO_emif_hps_emif_mem_0_mem_dqs_t, -- .mem_dqs_t
emif_hps_emif_mem_0_mem_dqs_c => CONNECTED_TO_emif_hps_emif_mem_0_mem_dqs_c, -- .mem_dqs_c
emif_hps_emif_mem_0_mem_dmi => CONNECTED_TO_emif_hps_emif_mem_0_mem_dmi, -- .mem_dmi
emif_hps_emif_mem_ck_0_mem_ck_t => CONNECTED_TO_emif_hps_emif_mem_ck_0_mem_ck_t, -- emif_hps_emif_mem_ck_0.mem_ck_t
emif_hps_emif_mem_ck_0_mem_ck_c => CONNECTED_TO_emif_hps_emif_mem_ck_0_mem_ck_c, -- .mem_ck_c
emif_hps_emif_mem_reset_n_mem_reset_n => CONNECTED_TO_emif_hps_emif_mem_reset_n_mem_reset_n, -- emif_hps_emif_mem_reset_n.mem_reset_n
emif_hps_emif_oct_0_oct_rzqin => CONNECTED_TO_emif_hps_emif_oct_0_oct_rzqin, -- emif_hps_emif_oct_0.oct_rzqin
emif_hps_emif_ref_clk_0_clk => CONNECTED_TO_emif_hps_emif_ref_clk_0_clk, -- emif_hps_emif_ref_clk_0.clk
button_pio_external_connection_export => CONNECTED_TO_button_pio_external_connection_export, -- button_pio_external_connection.export
dipsw_pio_external_connection_export => CONNECTED_TO_dipsw_pio_external_connection_export, -- dipsw_pio_external_connection.export
led_pio_external_connection_in_port => CONNECTED_TO_led_pio_external_connection_in_port, -- led_pio_external_connection.in_port
led_pio_external_connection_out_port => CONNECTED_TO_led_pio_external_connection_out_port -- .out_port
);
qsys/qsys_top/sim/aldec/rivierapro_setup.tcl
+475
View File
@@ -0,0 +1,475 @@
# (C) 2001-2026 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Intel
# Program License Subscription Agreement, Intel MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Intel and sold by Intel
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 26.1 110 linux 2026.04.08.10:52:56
# ----------------------------------------
# Auto-generated simulation script rivierapro_setup.tcl
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# qsys_top
#
# Intel recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Intel simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "aldec.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog -sv2k5 <your compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If qsys_top is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Intel IP
# within the Quartus project, and generate a unified
# script which supports all the Intel IP within the design.
# ----------------------------------------
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "qsys_top.qsys_top"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "/opt/altera_pro/26.1/quartus/"
}
if ![info exists QUARTUS_SIM_LIB_DIR] {
set QUARTUS_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/eda/sim_lib/"
}
if ![info exists DEVICES_SIM_LIB_DIR] {
set DEVICES_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS ""
}
if ![info exists SILENCE] {
set SILENCE "false"
}
if ![info exists PRECOMP_DEVICE_LIB_FILE] {
set PRECOMP_DEVICE_LIB_FILE ""
}
#-------------------------------------------
# read .tcl file to override initialized variables
if { [info exists ::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)] && [file exist $::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)] } {
echo "Sourcing $::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)"
source $::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)
}
# ----------------------------------------
# Source Common Tcl File
source $QSYS_SIMDIR/common/riviera_files.tcl
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
set LD_LIBRARY_PATH [dict create]
if { ![ string match "*-64 vsim*" [ vsim -version ] ] } {
set SIMULATOR_TOOL_BITNESS "bit_32"
} else {
set SIMULATOR_TOOL_BITNESS "bit_64"
}
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [qsys_top::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
if {[dict size $LD_LIBRARY_PATH] !=0 } {
set LD_LIBRARY_PATH [subst [join [dict keys $LD_LIBRARY_PATH] ":"]]
setenv LD_LIBRARY_PATH "$LD_LIBRARY_PATH"
}
append ELAB_OPTIONS [subst [qsys_top::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append SIM_OPTIONS [subst [qsys_top::get_sim_options $SIMULATOR_TOOL_BITNESS]]
#-------------------------------------------
# Check if $PRECOMP_DEVICE_LIB_FILE is set and points to correct file
if { $PRECOMP_DEVICE_LIB_FILE ne "" } {
set PRECOMP_DEVICE_LIB_FILE [string trim $PRECOMP_DEVICE_LIB_FILE]
if { [file exists $PRECOMP_DEVICE_LIB_FILE] && [string match [file tail $PRECOMP_DEVICE_LIB_FILE] "library.cfg" ] } {
echo "Using $PRECOMP_DEVICE_LIB_FILE for device library mapping"
} else {
echo "Unable to use $PRECOMP_DEVICE_LIB_FILE for device library mapping. Switching back to local library compilation"
set PRECOMP_DEVICE_LIB_FILE ""
}
}
set Aldec "Riviera"
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
set Aldec "Active"
}
if { [ string match "Active" $Aldec ] } {
scripterconf -tcl
createdesign "$TOP_LEVEL_NAME" "."
opendesign "$TOP_LEVEL_NAME"
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
if [string is false -strict $SILENCE] {
echo "\[exec\] file_copy"
}
set memory_files [list]
set memory_files [concat $memory_files [qsys_top::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
foreach file $memory_files {
set itercount 0
while {$itercount < 10 && [file type $file] eq "link"} {
set nf [file readlink $file]
if {[string index $nf 0] ne "/"} {
set nf [file dirname $file]/$nf
}
set file $nf
}
set dest_file [file join ./ [file tail $file]]
set normalized_src [qsys_top::normalize_path "$file"]
set normalized_dest [qsys_top::normalize_path "$dest_file"]
if { $normalized_src ne $normalized_dest } {
file copy -force $file ./
}
}
}
# ----------------------------------------
# Create compilation libraries
set logical_libraries [list "work" "work_lib" "lpm_ver" "sgate_ver" "altera_ver" "altera_mf_ver" "altera_lnsim_ver" "tennm_ver" "tennm_sm_hps_ver" "tennm_sm4_hssi_ver" "tennm_revb_hvio_ver" "tennm_revb_io96_ver" "lpm" "sgate" "altera" "altera_mf" "altera_lnsim" "tennm" "tennm_sm_hps" "tennm_sm4_hssi" "tennm_revb_hvio" "tennm_revb_io96"]
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
# ----------------------------------------
# get DPI libraries
set libraries [dict create]
set libraries [dict merge $libraries [qsys_top::get_dpi_libraries "$QSYS_SIMDIR"]]
set dpi_libraries [dict values $libraries]
# ----------------------------------------
# setup shared libraries
set DPI_LIBRARIES_ELAB ""
if { [llength $dpi_libraries] != 0 } {
echo "Using DPI Library settings"
foreach library $dpi_libraries {
append DPI_LIBRARIES_ELAB "-sv_lib $library "
}
}
ensure_lib ./libraries/
ensure_lib ./libraries/work
vmap work ./libraries/work
if { $PRECOMP_DEVICE_LIB_FILE eq "" } {
ensure_lib ./libraries/lpm_ver
vmap lpm_ver ./libraries/lpm_ver
ensure_lib ./libraries/sgate_ver
vmap sgate_ver ./libraries/sgate_ver
ensure_lib ./libraries/altera_ver
vmap altera_ver ./libraries/altera_ver
ensure_lib ./libraries/altera_mf_ver
vmap altera_mf_ver ./libraries/altera_mf_ver
ensure_lib ./libraries/altera_lnsim_ver
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
ensure_lib ./libraries/tennm_ver
vmap tennm_ver ./libraries/tennm_ver
ensure_lib ./libraries/tennm_sm_hps_ver
vmap tennm_sm_hps_ver ./libraries/tennm_sm_hps_ver
ensure_lib ./libraries/tennm_sm4_hssi_ver
vmap tennm_sm4_hssi_ver ./libraries/tennm_sm4_hssi_ver
ensure_lib ./libraries/tennm_revb_hvio_ver
vmap tennm_revb_hvio_ver ./libraries/tennm_revb_hvio_ver
ensure_lib ./libraries/tennm_revb_io96_ver
vmap tennm_revb_io96_ver ./libraries/tennm_revb_io96_ver
ensure_lib ./libraries/lpm
vmap lpm ./libraries/lpm
ensure_lib ./libraries/sgate
vmap sgate ./libraries/sgate
ensure_lib ./libraries/altera
vmap altera ./libraries/altera
ensure_lib ./libraries/altera_mf
vmap altera_mf ./libraries/altera_mf
ensure_lib ./libraries/altera_lnsim
vmap altera_lnsim ./libraries/altera_lnsim
ensure_lib ./libraries/tennm
vmap tennm ./libraries/tennm
ensure_lib ./libraries/tennm_sm_hps
vmap tennm_sm_hps ./libraries/tennm_sm_hps
ensure_lib ./libraries/tennm_sm4_hssi
vmap tennm_sm4_hssi ./libraries/tennm_sm4_hssi
ensure_lib ./libraries/tennm_revb_hvio
vmap tennm_revb_hvio ./libraries/tennm_revb_hvio
ensure_lib ./libraries/tennm_revb_io96
vmap tennm_revb_io96 ./libraries/tennm_revb_io96
} else {
vmap -link $PRECOMP_DEVICE_LIB_FILE
}
set design_libraries [dict create]
set design_libraries [dict merge $design_libraries [qsys_top::get_design_libraries]]
set libraries [dict keys $design_libraries]
foreach library $libraries {
ensure_lib ./libraries/$library/
vmap $library ./libraries/$library/
lappend logical_libraries $library
}
# ----------------------------------------
# Compile device library files
alias dev_com {
if [string is false -strict $SILENCE] {
echo "\[exec\] dev_com"
}
if { $PRECOMP_DEVICE_LIB_FILE eq "" } {
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/aldec/tennm_atoms_ncrypt.sv" -work tennm_ver
eval vlog -dpilib +define+fm7_fmica_SVA_OFF $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps_ver
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps_ver
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi_ver
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96_ver
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -work lpm
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.vhd" -work lpm
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -work sgate
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -work sgate
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -work altera_mf
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -work altera_mf
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -work altera_lnsim
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/aldec/tennm_atoms_ncrypt.sv" -work tennm
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -work tennm
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -work tennm
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96
}
ccomp -dpi -sc -o work "$QUARTUS_SIM_LIB_DIR/simsf_dpi.cpp"
}
# ----------------------------------------
# add device library elaboration and simulation properties
append ELAB_OPTIONS " -sv_lib work"
# ----------------------------------------
# Compile the design files in correct order
alias com {
if [string is false -strict $SILENCE] {
echo "\[exec\] com"
}
set design_files [dict create]
set design_files [dict merge [qsys_top::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
set common_design_files [dict values $design_files]
foreach file $common_design_files {
eval $file
}
set design_files [list]
set design_files [concat $design_files [qsys_top::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
foreach file $design_files {
eval $file
}
}
# ----------------------------------------
# Elaborate top level design
alias elab {
if [string is false -strict $SILENCE] {
echo "\[exec\] elab"
}
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
foreach library $logical_libraries { append elabcommand " -L $library" }
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
eval vsim +access +r $elabcommand
}
# ----------------------------------------
# Elaborate the top level design with -dbg -O2 option
alias elab_debug {
if [string is false -strict $SILENCE] {
echo "\[exec\] elab_debug"
}
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
foreach library $logical_libraries { append elabcommand " -L $library" }
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
eval vsim -dbg -O2 +access +r $elabcommand
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -dbg -O2
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo " For most designs, this should be overridden"
echo " to enable the elab/elab_debug aliases."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Qsys base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
echo
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
echo
echo "SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. "
echo
echo "PRECOMP_DEVICE_LIB_FILE -- Precompiled device library file."
echo " Use this variable to provide library.cfg containing device library mapping and dev_com will be skipped"
echo " If value is empty, device libraries will be compiled local"
}
file_copy
h
qsys/qsys_top/sim/aldec/run_rivierapro_setup.tcl
+34
View File
@@ -0,0 +1,34 @@
# (C) 2001-2026 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Intel
# Program License Subscription Agreement, Intel MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Intel and sold by Intel
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 26.1 110 linux 2026.04.08.10:52:56
# ----------------------------------------
# Auto-generated simulation script run_rivierapro_setup.tcl
# ----------------------------------------
# This script provides commands to run the rivierapro_setup.tcl script for the following IP detected in
# your Quartus project:
# qsys_top
#
#
# Intel recommends that you source this Quartus-generated IP simulation
# script to compile, elab and run the design without any customization.
# For customization, please follow the steps mentioned in rivierapro_setup.tcl.
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
ld
run -all
quit
qsys/qsys_top/sim/common/modelsim_files.tcl
+168
View File
@@ -0,0 +1,168 @@
source [file join [file dirname [info script]] ./../../../ip/qsys_top/rst_in/sim/common/modelsim_files.tcl]
source [file join [file dirname [info script]] ./../../../hps_subsys/hps_subsys/sim/common/modelsim_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/qsys_top/clk_100/sim/common/modelsim_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/qsys_top/user_rst_clkgate_0/sim/common/modelsim_files.tcl]
source [file join [file dirname [info script]] ./../../../peripheral_subsys/peripheral_subsys/sim/common/modelsim_files.tcl]
namespace eval qsys_top {
proc get_design_libraries {} {
set libraries [dict create]
set libraries [dict merge $libraries [rst_in::get_design_libraries]]
set libraries [dict merge $libraries [hps_subsys::get_design_libraries]]
set libraries [dict merge $libraries [clk_100::get_design_libraries]]
set libraries [dict merge $libraries [user_rst_clkgate_0::get_design_libraries]]
set libraries [dict merge $libraries [peripheral_subsys::get_design_libraries]]
dict set libraries altera_merlin_axi_translator_1987 1
dict set libraries altera_merlin_slave_translator_191 1
dict set libraries altera_merlin_axi_master_ni_19117 1
dict set libraries altera_merlin_slave_agent_1930 1
dict set libraries altera_avalon_sc_fifo_1932 1
dict set libraries altera_merlin_router_1921 1
dict set libraries altera_avalon_st_pipeline_stage_1930 1
dict set libraries altera_merlin_burst_adapter_1940 1
dict set libraries altera_merlin_demultiplexer_1921 1
dict set libraries altera_merlin_multiplexer_1922 1
dict set libraries altera_mm_interconnect_1920 1
dict set libraries altera_irq_mapper_2001 1
dict set libraries altera_reset_controller_1924 1
dict set libraries qsys_top 1
return $libraries
}
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
set memory_files [list]
set memory_files [concat $memory_files [rst_in::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [hps_subsys::get_memory_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [clk_100::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [user_rst_clkgate_0::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [peripheral_subsys::get_memory_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
return $memory_files
}
proc get_common_design_files {QSYS_SIMDIR} {
set design_files [dict create]
set design_files [dict merge $design_files [rst_in::get_common_design_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
set design_files [dict merge $design_files [hps_subsys::get_common_design_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
set design_files [dict merge $design_files [clk_100::get_common_design_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
set design_files [dict merge $design_files [user_rst_clkgate_0::get_common_design_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
set design_files [dict merge $design_files [peripheral_subsys::get_common_design_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
return $design_files
}
proc get_design_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
set design_files [list]
set design_files [concat $design_files [rst_in::get_design_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [hps_subsys::get_design_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [clk_100::get_design_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [user_rst_clkgate_0::get_design_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [peripheral_subsys::get_design_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
lappend design_files "-makelib altera_merlin_axi_translator_1987 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv"]\" -end"
lappend design_files "-makelib altera_merlin_slave_translator_191 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv"]\" -end"
lappend design_files "-makelib altera_merlin_axi_master_ni_19117 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv"]\" -end"
lappend design_files "-makelib altera_merlin_axi_master_ni_19117 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv"]\" -end"
lappend design_files "-makelib altera_merlin_slave_agent_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv"]\" -end"
lappend design_files "-makelib altera_merlin_slave_agent_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv"]\" -end"
lappend design_files "-makelib altera_avalon_sc_fifo_1932 \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v"]\" -end"
lappend design_files "-makelib altera_merlin_router_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv"]\" -end"
lappend design_files "-makelib altera_merlin_router_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv"]\" -end"
lappend design_files "-makelib altera_avalon_st_pipeline_stage_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv"]\" -end"
lappend design_files "-makelib altera_avalon_st_pipeline_stage_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v"]\" -end"
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v"]\" -end"
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv"]\" -end"
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv"]\" -end"
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv"]\" -end"
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv"]\" -end"
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv"]\" -end"
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv"]\" -end"
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv"]\" -end"
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv"]\" -end"
lappend design_files "-makelib altera_merlin_demultiplexer_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv"]\" -end"
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv"]\" -end"
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\" -end"
lappend design_files "-makelib altera_merlin_demultiplexer_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv"]\" -end"
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv"]\" -end"
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\" -end"
lappend design_files "-makelib altera_mm_interconnect_1920 \"[normalize_path "$QSYS_SIMDIR/../altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v"]\" -end"
lappend design_files "-makelib altera_irq_mapper_2001 \"[normalize_path "$QSYS_SIMDIR/../altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv"]\" -end"
lappend design_files "-makelib altera_reset_controller_1924 \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_controller.v"]\" -end"
lappend design_files "-makelib altera_reset_controller_1924 \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_synchronizer.v"]\" -end"
lappend design_files "-makelib qsys_top \"[normalize_path "$QSYS_SIMDIR/qsys_top.v"]\" -end"
return $design_files
}
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
if {$IS_DUPLICATE == -1} {
return $NEW_ELAB_OPTION
} else {
return ""
}
}
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
set ELAB_OPTIONS ""
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [rst_in::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [hps_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [clk_100::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [user_rst_clkgate_0::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [peripheral_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $ELAB_OPTIONS
}
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
set SIM_OPTIONS ""
append SIM_OPTIONS [rst_in::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [hps_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [clk_100::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [user_rst_clkgate_0::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [peripheral_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $SIM_OPTIONS
}
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
set ENV_VARIABLES [dict create]
set LD_LIBRARY_PATH [dict create]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [rst_in::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [hps_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [clk_100::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [user_rst_clkgate_0::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [peripheral_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $ENV_VARIABLES
}
proc normalize_path {FILEPATH} {
if {[catch { package require fileutil } err]} {
return $FILEPATH
}
set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]
if {[file pathtype $FILEPATH] eq "relative"} {
set path [fileutil::relative [pwd] $path]
}
return $path
}
proc get_dpi_libraries {QSYS_SIMDIR} {
set libraries [dict create]
set libraries [dict merge $libraries [rst_in::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
set libraries [dict merge $libraries [hps_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
set libraries [dict merge $libraries [clk_100::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
set libraries [dict merge $libraries [user_rst_clkgate_0::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
set libraries [dict merge $libraries [peripheral_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
return $libraries
}
}
qsys/qsys_top/sim/common/riviera_files.tcl
+168
View File
@@ -0,0 +1,168 @@
source [file join [file dirname [info script]] ./../../../ip/qsys_top/rst_in/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../hps_subsys/hps_subsys/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/qsys_top/clk_100/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/qsys_top/user_rst_clkgate_0/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../peripheral_subsys/peripheral_subsys/sim/common/riviera_files.tcl]
namespace eval qsys_top {
proc get_design_libraries {} {
set libraries [dict create]
set libraries [dict merge $libraries [rst_in::get_design_libraries]]
set libraries [dict merge $libraries [hps_subsys::get_design_libraries]]
set libraries [dict merge $libraries [clk_100::get_design_libraries]]
set libraries [dict merge $libraries [user_rst_clkgate_0::get_design_libraries]]
set libraries [dict merge $libraries [peripheral_subsys::get_design_libraries]]
dict set libraries altera_merlin_axi_translator_1987 1
dict set libraries altera_merlin_slave_translator_191 1
dict set libraries altera_merlin_axi_master_ni_19117 1
dict set libraries altera_merlin_slave_agent_1930 1
dict set libraries altera_avalon_sc_fifo_1932 1
dict set libraries altera_merlin_router_1921 1
dict set libraries altera_avalon_st_pipeline_stage_1930 1
dict set libraries altera_merlin_burst_adapter_1940 1
dict set libraries altera_merlin_demultiplexer_1921 1
dict set libraries altera_merlin_multiplexer_1922 1
dict set libraries altera_mm_interconnect_1920 1
dict set libraries altera_irq_mapper_2001 1
dict set libraries altera_reset_controller_1924 1
dict set libraries qsys_top 1
return $libraries
}
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
set memory_files [list]
set memory_files [concat $memory_files [rst_in::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [hps_subsys::get_memory_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [clk_100::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [user_rst_clkgate_0::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [peripheral_subsys::get_memory_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
return $memory_files
}
proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
set design_files [dict create]
set design_files [dict merge $design_files [rst_in::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
set design_files [dict merge $design_files [hps_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
set design_files [dict merge $design_files [clk_100::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
set design_files [dict merge $design_files [user_rst_clkgate_0::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
set design_files [dict merge $design_files [peripheral_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
return $design_files
}
proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
set design_files [list]
set design_files [concat $design_files [rst_in::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [hps_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [clk_100::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [user_rst_clkgate_0::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [peripheral_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv"]\" -work altera_merlin_axi_translator_1987"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv"]\" -work altera_merlin_slave_translator_191"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv"]\" -work altera_merlin_axi_master_ni_19117"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv"]\" -work altera_merlin_axi_master_ni_19117"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv"]\" -work altera_merlin_slave_agent_1930"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv"]\" -work altera_merlin_slave_agent_1930"
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v"]\" -work altera_avalon_sc_fifo_1932"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv"]\" -work altera_merlin_router_1921"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv"]\" -work altera_merlin_router_1921"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv"]\" -work altera_avalon_st_pipeline_stage_1930"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v"]\" -work altera_avalon_st_pipeline_stage_1930"
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v"]\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv"]\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv"]\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv"]\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv"]\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv"]\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv"]\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv"]\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv"]\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv"]\" -work altera_merlin_demultiplexer_1921"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv"]\" -work altera_merlin_multiplexer_1922"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\" -work altera_merlin_multiplexer_1922"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv"]\" -work altera_merlin_demultiplexer_1921"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv"]\" -work altera_merlin_multiplexer_1922"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\" -work altera_merlin_multiplexer_1922"
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v"]\" -work altera_mm_interconnect_1920"
lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv"]\" -work altera_irq_mapper_2001"
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_controller.v"]\" -work altera_reset_controller_1924"
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_synchronizer.v"]\" -work altera_reset_controller_1924"
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/qsys_top.v"]\" -work qsys_top"
return $design_files
}
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
if {$IS_DUPLICATE == -1} {
return $NEW_ELAB_OPTION
} else {
return ""
}
}
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
set ELAB_OPTIONS ""
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [rst_in::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [hps_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [clk_100::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [user_rst_clkgate_0::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [peripheral_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $ELAB_OPTIONS
}
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
set SIM_OPTIONS ""
append SIM_OPTIONS [rst_in::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [hps_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [clk_100::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [user_rst_clkgate_0::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [peripheral_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $SIM_OPTIONS
}
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
set ENV_VARIABLES [dict create]
set LD_LIBRARY_PATH [dict create]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [rst_in::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [hps_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [clk_100::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [user_rst_clkgate_0::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [peripheral_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $ENV_VARIABLES
}
proc normalize_path {FILEPATH} {
if {[catch { package require fileutil } err]} {
return $FILEPATH
}
set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]
if {[file pathtype $FILEPATH] eq "relative"} {
set path [fileutil::relative [pwd] $path]
}
return $path
}
proc get_dpi_libraries {QSYS_SIMDIR} {
set libraries [dict create]
set libraries [dict merge $libraries [rst_in::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
set libraries [dict merge $libraries [hps_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
set libraries [dict merge $libraries [clk_100::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
set libraries [dict merge $libraries [user_rst_clkgate_0::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
set libraries [dict merge $libraries [peripheral_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
return $libraries
}
}
qsys/qsys_top/sim/common/vcsmx_files.tcl
+158
View File
@@ -0,0 +1,158 @@
source [file join [file dirname [info script]] ./../../../ip/qsys_top/rst_in/sim/common/vcsmx_files.tcl]
source [file join [file dirname [info script]] ./../../../hps_subsys/hps_subsys/sim/common/vcsmx_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/qsys_top/clk_100/sim/common/vcsmx_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/qsys_top/user_rst_clkgate_0/sim/common/vcsmx_files.tcl]
source [file join [file dirname [info script]] ./../../../peripheral_subsys/peripheral_subsys/sim/common/vcsmx_files.tcl]
namespace eval qsys_top {
proc get_design_libraries {} {
set libraries [dict create]
set libraries [dict merge $libraries [rst_in::get_design_libraries]]
set libraries [dict merge $libraries [hps_subsys::get_design_libraries]]
set libraries [dict merge $libraries [clk_100::get_design_libraries]]
set libraries [dict merge $libraries [user_rst_clkgate_0::get_design_libraries]]
set libraries [dict merge $libraries [peripheral_subsys::get_design_libraries]]
dict set libraries altera_merlin_axi_translator_1987 1
dict set libraries altera_merlin_slave_translator_191 1
dict set libraries altera_merlin_axi_master_ni_19117 1
dict set libraries altera_merlin_slave_agent_1930 1
dict set libraries altera_avalon_sc_fifo_1932 1
dict set libraries altera_merlin_router_1921 1
dict set libraries altera_avalon_st_pipeline_stage_1930 1
dict set libraries altera_merlin_burst_adapter_1940 1
dict set libraries altera_merlin_demultiplexer_1921 1
dict set libraries altera_merlin_multiplexer_1922 1
dict set libraries altera_mm_interconnect_1920 1
dict set libraries altera_irq_mapper_2001 1
dict set libraries altera_reset_controller_1924 1
dict set libraries qsys_top 1
return $libraries
}
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
set memory_files [list]
set memory_files [concat $memory_files [rst_in::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [hps_subsys::get_memory_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [clk_100::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [user_rst_clkgate_0::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [peripheral_subsys::get_memory_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
return $memory_files
}
proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
set design_files [dict create]
set design_files [dict merge $design_files [rst_in::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
set design_files [dict merge $design_files [hps_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
set design_files [dict merge $design_files [clk_100::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
set design_files [dict merge $design_files [user_rst_clkgate_0::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
set design_files [dict merge $design_files [peripheral_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
return $design_files
}
proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
set design_files [list]
set design_files [concat $design_files [rst_in::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [hps_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [clk_100::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [user_rst_clkgate_0::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [peripheral_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv\" -work altera_merlin_axi_translator_1987"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv\" -work altera_merlin_slave_translator_191"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv\" -work altera_merlin_axi_master_ni_19117"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv\" -work altera_merlin_axi_master_ni_19117"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv\" -work altera_merlin_slave_agent_1930"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv\" -work altera_merlin_slave_agent_1930"
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v\" -work altera_avalon_sc_fifo_1932"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv\" -work altera_merlin_router_1921"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv\" -work altera_merlin_router_1921"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv\" -work altera_avalon_st_pipeline_stage_1930"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v\" -work altera_avalon_st_pipeline_stage_1930"
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv\" -work altera_merlin_burst_adapter_1940"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv\" -work altera_merlin_demultiplexer_1921"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv\" -work altera_merlin_multiplexer_1922"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv\" -work altera_merlin_multiplexer_1922"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv\" -work altera_merlin_demultiplexer_1921"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv\" -work altera_merlin_multiplexer_1922"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv\" -work altera_merlin_multiplexer_1922"
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v\" -work altera_mm_interconnect_1920"
lappend design_files "vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv\" -work altera_irq_mapper_2001"
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_controller.v\" -work altera_reset_controller_1924"
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_synchronizer.v\" -work altera_reset_controller_1924"
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/qsys_top.v\" -work qsys_top"
return $design_files
}
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
if {$IS_DUPLICATE == -1} {
return $NEW_ELAB_OPTION
} else {
return ""
}
}
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
set ELAB_OPTIONS ""
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [rst_in::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [hps_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [clk_100::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [user_rst_clkgate_0::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [peripheral_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $ELAB_OPTIONS
}
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
set SIM_OPTIONS ""
append SIM_OPTIONS [rst_in::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [hps_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [clk_100::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [user_rst_clkgate_0::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [peripheral_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $SIM_OPTIONS
}
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
set ENV_VARIABLES [dict create]
set LD_LIBRARY_PATH [dict create]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [rst_in::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [hps_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [clk_100::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [user_rst_clkgate_0::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [peripheral_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $ENV_VARIABLES
}
proc get_dpi_libraries {QSYS_SIMDIR} {
set libraries [dict create]
set libraries [dict merge $libraries [rst_in::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
set libraries [dict merge $libraries [hps_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
set libraries [dict merge $libraries [clk_100::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
set libraries [dict merge $libraries [user_rst_clkgate_0::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
set libraries [dict merge $libraries [peripheral_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
return $libraries
}
}
qsys/qsys_top/sim/common/xcelium_files.tcl
+158
View File
@@ -0,0 +1,158 @@
source [file join [file dirname [info script]] ./../../../ip/qsys_top/rst_in/sim/common/xcelium_files.tcl]
source [file join [file dirname [info script]] ./../../../hps_subsys/hps_subsys/sim/common/xcelium_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/qsys_top/clk_100/sim/common/xcelium_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/qsys_top/user_rst_clkgate_0/sim/common/xcelium_files.tcl]
source [file join [file dirname [info script]] ./../../../peripheral_subsys/peripheral_subsys/sim/common/xcelium_files.tcl]
namespace eval qsys_top {
proc get_design_libraries {} {
set libraries [dict create]
set libraries [dict merge $libraries [rst_in::get_design_libraries]]
set libraries [dict merge $libraries [hps_subsys::get_design_libraries]]
set libraries [dict merge $libraries [clk_100::get_design_libraries]]
set libraries [dict merge $libraries [user_rst_clkgate_0::get_design_libraries]]
set libraries [dict merge $libraries [peripheral_subsys::get_design_libraries]]
dict set libraries altera_merlin_axi_translator_1987 1
dict set libraries altera_merlin_slave_translator_191 1
dict set libraries altera_merlin_axi_master_ni_19117 1
dict set libraries altera_merlin_slave_agent_1930 1
dict set libraries altera_avalon_sc_fifo_1932 1
dict set libraries altera_merlin_router_1921 1
dict set libraries altera_avalon_st_pipeline_stage_1930 1
dict set libraries altera_merlin_burst_adapter_1940 1
dict set libraries altera_merlin_demultiplexer_1921 1
dict set libraries altera_merlin_multiplexer_1922 1
dict set libraries altera_mm_interconnect_1920 1
dict set libraries altera_irq_mapper_2001 1
dict set libraries altera_reset_controller_1924 1
dict set libraries qsys_top 1
return $libraries
}
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
set memory_files [list]
set memory_files [concat $memory_files [rst_in::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [hps_subsys::get_memory_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [clk_100::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [user_rst_clkgate_0::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
set memory_files [concat $memory_files [peripheral_subsys::get_memory_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
return $memory_files
}
proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
set design_files [dict create]
set design_files [dict merge $design_files [rst_in::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
set design_files [dict merge $design_files [hps_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
set design_files [dict merge $design_files [clk_100::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
set design_files [dict merge $design_files [user_rst_clkgate_0::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
set design_files [dict merge $design_files [peripheral_subsys::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
return $design_files
}
proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
set design_files [list]
set design_files [concat $design_files [rst_in::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [hps_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [clk_100::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [user_rst_clkgate_0::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
set design_files [concat $design_files [peripheral_subsys::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv\" -work altera_merlin_axi_translator_1987 -cdslib ./cds_libs/altera_merlin_axi_translator_1987.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv\" -work altera_merlin_slave_translator_191 -cdslib ./cds_libs/altera_merlin_slave_translator_191.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv\" -work altera_merlin_axi_master_ni_19117 -cdslib ./cds_libs/altera_merlin_axi_master_ni_19117.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv\" -work altera_merlin_axi_master_ni_19117 -cdslib ./cds_libs/altera_merlin_axi_master_ni_19117.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv\" -work altera_merlin_slave_agent_1930 -cdslib ./cds_libs/altera_merlin_slave_agent_1930.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv\" -work altera_merlin_slave_agent_1930 -cdslib ./cds_libs/altera_merlin_slave_agent_1930.cds.lib"
lappend design_files "xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v\" -work altera_avalon_sc_fifo_1932 -cdslib ./cds_libs/altera_avalon_sc_fifo_1932.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv\" -work altera_merlin_router_1921 -cdslib ./cds_libs/altera_merlin_router_1921.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv\" -work altera_merlin_router_1921 -cdslib ./cds_libs/altera_merlin_router_1921.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv\" -work altera_avalon_st_pipeline_stage_1930 -cdslib ./cds_libs/altera_avalon_st_pipeline_stage_1930.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v\" -work altera_avalon_st_pipeline_stage_1930 -cdslib ./cds_libs/altera_avalon_st_pipeline_stage_1930.cds.lib"
lappend design_files "xmvlog -zlib 1 -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v\" -work altera_merlin_burst_adapter_1940"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv\" -work altera_merlin_burst_adapter_1940 -cdslib ./cds_libs/altera_merlin_burst_adapter_1940.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv\" -work altera_merlin_demultiplexer_1921 -cdslib ./cds_libs/altera_merlin_demultiplexer_1921.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv\" -work altera_merlin_multiplexer_1922 -cdslib ./cds_libs/altera_merlin_multiplexer_1922.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv\" -work altera_merlin_multiplexer_1922 -cdslib ./cds_libs/altera_merlin_multiplexer_1922.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv\" -work altera_merlin_demultiplexer_1921 -cdslib ./cds_libs/altera_merlin_demultiplexer_1921.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv\" -work altera_merlin_multiplexer_1922 -cdslib ./cds_libs/altera_merlin_multiplexer_1922.cds.lib"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv\" -work altera_merlin_multiplexer_1922 -cdslib ./cds_libs/altera_merlin_multiplexer_1922.cds.lib"
lappend design_files "xmvlog -zlib 1 -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v\" -work altera_mm_interconnect_1920"
lappend design_files "xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv\" -work altera_irq_mapper_2001 -cdslib ./cds_libs/altera_irq_mapper_2001.cds.lib"
lappend design_files "xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_controller.v\" -work altera_reset_controller_1924 -cdslib ./cds_libs/altera_reset_controller_1924.cds.lib"
lappend design_files "xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_synchronizer.v\" -work altera_reset_controller_1924 -cdslib ./cds_libs/altera_reset_controller_1924.cds.lib"
lappend design_files "xmvlog -zlib 1 -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/qsys_top.v\" -work qsys_top"
return $design_files
}
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
if {$IS_DUPLICATE == -1} {
return $NEW_ELAB_OPTION
} else {
return ""
}
}
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
set ELAB_OPTIONS ""
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [rst_in::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [hps_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [clk_100::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [user_rst_clkgate_0::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [peripheral_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $ELAB_OPTIONS
}
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
set SIM_OPTIONS ""
append SIM_OPTIONS [rst_in::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [hps_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [clk_100::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [user_rst_clkgate_0::get_sim_options $SIMULATOR_TOOL_BITNESS]
append SIM_OPTIONS [peripheral_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $SIM_OPTIONS
}
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
set ENV_VARIABLES [dict create]
set LD_LIBRARY_PATH [dict create]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [rst_in::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [hps_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [clk_100::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [user_rst_clkgate_0::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [peripheral_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
} else {
}
return $ENV_VARIABLES
}
proc get_dpi_libraries {QSYS_SIMDIR} {
set libraries [dict create]
set libraries [dict merge $libraries [rst_in::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
set libraries [dict merge $libraries [hps_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
set libraries [dict merge $libraries [clk_100::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
set libraries [dict merge $libraries [user_rst_clkgate_0::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
set libraries [dict merge $libraries [peripheral_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
return $libraries
}
}
qsys/qsys_top/sim/mentor/msim_setup.tcl
+505
View File
@@ -0,0 +1,505 @@
# (C) 2001-2026 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Intel
# Program License Subscription Agreement, Intel MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Intel and sold by Intel
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ----------------------------------------
# Auto-generated simulation script msim_setup.tcl
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# qsys_top
#
# Intel recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Intel simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "mentor.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog <compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run -a
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If qsys_top is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Intel IP
# within the Quartus project, and generate a unified
# script which supports all the Intel IP within the design.
# ----------------------------------------
# ACDS 26.1 110 linux 2026.04.08.10:52:56
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "qsys_top.qsys_top"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "/opt/altera_pro/26.1/quartus/"
}
if ![info exists QUARTUS_SIM_LIB_DIR] {
set QUARTUS_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/eda/sim_lib/"
}
if ![info exists DEVICES_SIM_LIB_DIR] {
set DEVICES_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS ""
}
if ![info exists SILENCE] {
set SILENCE "false"
}
if ![info exists PRECOMP_DEVICE_LIB_FILE] {
set PRECOMP_DEVICE_LIB_FILE ""
}
if ![info exists FORCE_MODELSIM_AE_SELECTION] {
set FORCE_MODELSIM_AE_SELECTION "false"
}
if ![info exists ENABLE_QE_LIBRARY_COMPILATION] {
set ENABLE_QE_LIBRARY_COMPILATION "false"
}
#-------------------------------------------
# read .tcl file to override initialized variables
if { [info exists ::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)] && [file exist $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)] } {
echo "Sourcing $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)"
source $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)
}
# ----------------------------------------
# Source Common Tcl File
source $QSYS_SIMDIR/common/modelsim_files.tcl
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
set LD_LIBRARY_PATH [dict create]
if { ![ string match "*-64 vsim*" [ vsimVersionString ] ] } {
set SIMULATOR_TOOL_BITNESS "bit_32"
} else {
set SIMULATOR_TOOL_BITNESS "bit_64"
}
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [qsys_top::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
if {[dict size $LD_LIBRARY_PATH] !=0 } {
set LD_LIBRARY_PATH [subst [join [dict keys $LD_LIBRARY_PATH] ":"]]
setenv LD_LIBRARY_PATH "$LD_LIBRARY_PATH"
}
append ELAB_OPTIONS [subst [qsys_top::get_elab_options $SIMULATOR_TOOL_BITNESS]]
append SIM_OPTIONS [subst [qsys_top::get_sim_options $SIMULATOR_TOOL_BITNESS]]
proc check_precomp_device {precomp_device_lib_path force_select_modelsim_ae enable_qe_library_compilation} {
set len [string length $precomp_device_lib_path]
if {($len == 0) && ([string is false -strict [modelsim_ae_select $force_select_modelsim_ae]] || [string is true -strict $enable_qe_library_compilation])} {
return 1
}
return 0
}
proc modelsim_ae_select {force_select_modelsim_ae} {
if [string is true -strict $force_select_modelsim_ae] {
return 1
}
return [string match -nocase "*Altera*FPGA*" [ vsimVersionString ]]
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
if [string is false -strict $SILENCE] {
echo "\[exec\] file_copy"
}
set memory_files [list]
set memory_files [concat $memory_files [qsys_top::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
foreach file $memory_files {
set itercount 0
while {$itercount < 10 && [file type $file] eq "link"} {
set nf [file readlink $file]
if {[string index $nf 0] ne "/"} {
set nf [file dirname $file]/$nf
}
set file $nf
}
set dest_file [file join ./ [file tail $file]]
set normalized_src [qsys_top::normalize_path "$file"]
set normalized_dest [qsys_top::normalize_path "$dest_file"]
if { $normalized_src ne $normalized_dest } {
file copy -force $file ./
}
}
}
# ----------------------------------------
# Modify modelsim.ini if precompiled device libraries are in use
if { $PRECOMP_DEVICE_LIB_FILE ne "" } {
echo "Modifying modelsim.ini according to $PRECOMP_DEVICE_LIB_FILE"
set PRECOMP_DEVICE_LIB_FILE [string trim $PRECOMP_DEVICE_LIB_FILE]
if { [file exists $PRECOMP_DEVICE_LIB_FILE] && [string match [file tail $PRECOMP_DEVICE_LIB_FILE] "modelsim.ini" ] } {
if { [file exists "modelsim.ini"] } {
echo "modelsim.ini already exists, making backup modelsim.ini.bak"
file copy -force "modelsim.ini" "modelsim.ini.bak"
}
echo "Copying modelsim.ini from $PRECOMP_DEVICE_LIB_FILE"
file copy -force $PRECOMP_DEVICE_LIB_FILE ./
} elseif { [file exists $PRECOMP_DEVICE_LIB_FILE] && [string match "*tcl" [file tail $PRECOMP_DEVICE_LIB_FILE] ] } {
echo "Running $PRECOMP_DEVICE_LIB_FILE to generate device library mapping"
source $PRECOMP_DEVICE_LIB_FILE
} else {
echo "Unable to use $PRECOMP_DEVICE_LIB_FILE for device library mapping. Switching back to local library compilation"
set PRECOMP_DEVICE_LIB_FILE ""
}
}
# ----------------------------------------
# Create compilation libraries
set logical_libraries [list "work" "work_lib" "lpm_ver" "sgate_ver" "altera_ver" "altera_mf_ver" "altera_lnsim_ver" "tennm_ver" "tennm_sm_hps_ver" "tennm_sm4_hssi_ver" "tennm_revb_hvio_ver" "tennm_revb_io96_ver" "lpm" "sgate" "altera" "altera_mf" "altera_lnsim" "tennm" "tennm_sm_hps" "tennm_sm4_hssi" "tennm_revb_hvio" "tennm_revb_io96"]
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries/
ensure_lib ./libraries/work/
vmap work ./libraries/work/
vmap work_lib ./libraries/work/
# ----------------------------------------
# get DPI libraries
set libraries [dict create]
set libraries [dict merge $libraries [qsys_top::get_dpi_libraries "$QSYS_SIMDIR"]]
set dpi_libraries [dict values $libraries]
# ----------------------------------------
# setup shared libraries
set DPI_LIBRARIES_ELAB ""
if { [llength $dpi_libraries] != 0 } {
echo "Using DPI Library settings"
foreach library $dpi_libraries {
append DPI_LIBRARIES_ELAB "-sv_lib $library "
}
}
if [ check_precomp_device $PRECOMP_DEVICE_LIB_FILE $FORCE_MODELSIM_AE_SELECTION $ENABLE_QE_LIBRARY_COMPILATION ] {
ensure_lib ./libraries/lpm_ver/
vmap lpm_ver ./libraries/lpm_ver/
ensure_lib ./libraries/sgate_ver/
vmap sgate_ver ./libraries/sgate_ver/
ensure_lib ./libraries/altera_ver/
vmap altera_ver ./libraries/altera_ver/
ensure_lib ./libraries/altera_mf_ver/
vmap altera_mf_ver ./libraries/altera_mf_ver/
ensure_lib ./libraries/altera_lnsim_ver/
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
ensure_lib ./libraries/tennm_ver/
vmap tennm_ver ./libraries/tennm_ver/
ensure_lib ./libraries/tennm_sm_hps_ver/
vmap tennm_sm_hps_ver ./libraries/tennm_sm_hps_ver/
ensure_lib ./libraries/tennm_sm4_hssi_ver/
vmap tennm_sm4_hssi_ver ./libraries/tennm_sm4_hssi_ver/
ensure_lib ./libraries/tennm_revb_hvio_ver/
vmap tennm_revb_hvio_ver ./libraries/tennm_revb_hvio_ver/
ensure_lib ./libraries/tennm_revb_io96_ver/
vmap tennm_revb_io96_ver ./libraries/tennm_revb_io96_ver/
ensure_lib ./libraries/lpm/
vmap lpm ./libraries/lpm/
ensure_lib ./libraries/sgate/
vmap sgate ./libraries/sgate/
ensure_lib ./libraries/altera/
vmap altera ./libraries/altera/
ensure_lib ./libraries/altera_mf/
vmap altera_mf ./libraries/altera_mf/
ensure_lib ./libraries/altera_lnsim/
vmap altera_lnsim ./libraries/altera_lnsim/
ensure_lib ./libraries/tennm/
vmap tennm ./libraries/tennm/
ensure_lib ./libraries/tennm_sm_hps/
vmap tennm_sm_hps ./libraries/tennm_sm_hps/
ensure_lib ./libraries/tennm_sm4_hssi/
vmap tennm_sm4_hssi ./libraries/tennm_sm4_hssi/
ensure_lib ./libraries/tennm_revb_hvio/
vmap tennm_revb_hvio ./libraries/tennm_revb_hvio/
ensure_lib ./libraries/tennm_revb_io96/
vmap tennm_revb_io96 ./libraries/tennm_revb_io96/
}
set design_libraries [dict create]
set design_libraries [dict merge $design_libraries [qsys_top::get_design_libraries]]
set libraries [dict keys $design_libraries]
foreach library $libraries {
ensure_lib ./libraries/$library/
vmap $library ./libraries/$library/
lappend logical_libraries $library
}
# ----------------------------------------
# Compile device library files
alias dev_com {
if [string is false -strict $SILENCE] {
echo "\[exec\] dev_com"
}
if [ check_precomp_device $PRECOMP_DEVICE_LIB_FILE $FORCE_MODELSIM_AE_SELECTION $ENABLE_QE_LIBRARY_COMPILATION ] {
eval qrun -compile -noautoorder -parallel -outdir ./libraries -vlog.options $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS -end \
-vcom.options $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS -end \
-vlog.ext=+.vo -vlog.ext=+.vt -vcom.ext=+.vho -sv -suppress 13338 \
-makelib lpm_ver "$QUARTUS_SIM_LIB_DIR/220model.v" -end \
-makelib sgate_ver "$QUARTUS_SIM_LIB_DIR/sgate.v" -end \
-makelib altera_ver "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -end \
-makelib altera_mf_ver "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -end \
-makelib altera_lnsim_ver "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -end \
-makelib tennm_ver "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -end \
-makelib tennm_ver "$QUARTUS_SIM_LIB_DIR/mentor/tennm_atoms_ncrypt.sv" -end \
-makelib tennm_ver "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -end \
-makelib tennm_sm_hps_ver "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -end \
-makelib tennm_sm_hps_ver "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -end \
-makelib tennm_sm4_hssi_ver "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -end \
-makelib tennm_sm4_hssi_ver "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -suppress 7061,2583,13314,2244,2283,2600,3691 -end \
-makelib tennm_revb_hvio_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -end \
-makelib tennm_revb_hvio_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -suppress 2583 -end \
-makelib tennm_revb_io96_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -end \
-makelib tennm_revb_io96_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -end \
-makelib lpm "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -end \
-makelib lpm "$QUARTUS_SIM_LIB_DIR/220model.vhd" -end \
-makelib sgate "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -end \
-makelib sgate "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -end \
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -end \
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -end \
-makelib altera "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -end \
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -end \
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -end \
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -end \
-makelib altera_mf "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -end \
-makelib altera_mf "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -end \
-makelib altera_lnsim "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -end \
-makelib altera_lnsim "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -end \
-makelib tennm "$QUARTUS_SIM_LIB_DIR/mentor/tennm_atoms_ncrypt.sv" -end \
-makelib tennm "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -end \
-makelib tennm "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -end \
-makelib tennm_sm_hps "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -end \
-makelib tennm_sm_hps "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -end \
-makelib tennm_sm4_hssi "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -end \
-makelib tennm_sm4_hssi "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -suppress 7061,2583,13314,2244,2283,2600,3691 -end \
-makelib tennm_revb_hvio "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -end \
-makelib tennm_revb_hvio "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -suppress 2583 -end \
-makelib tennm_revb_io96 "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -end \
-makelib tennm_revb_io96 "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -end \
}
eval qrun -compile -noautoorder -parallel -outdir ./libraries -vlog.options $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS -end \
-vcom.options $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS -end \
-vlog.ext=+.vo -vlog.ext=+.vt -vcom.ext=+.vho -sv -suppress 13338 \
-makelib work "$QUARTUS_SIM_LIB_DIR/simsf_dpi.cpp" -end \
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
if [string is false -strict $SILENCE] {
echo "\[exec\] com"
}
set common_design_files [dict values [qsys_top::get_common_design_files "$QSYS_SIMDIR"]]
set design_files [list]
set design_files [concat $design_files [qsys_top::get_design_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
set files [concat $common_design_files $design_files ]
set files [join $files " \\\n"]
set com_file [open "modelsim_com.f" w+]
puts $com_file $files
close $com_file
eval qrun -compile -noautoorder -parallel -outdir ./libraries -vlog.options $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS -end \
-vcom.options $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS -end \
-vlog.ext=+.vo -vlog.ext=+.vt -vcom.ext=+.vho -sv -suppress 13338 \
-f modelsim_com.f
}
# ----------------------------------------
# Elaborate top level design
alias elab {
if [string is false -strict $SILENCE] {
echo "\[exec\] elab"
}
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
foreach library $logical_libraries { append elabcommand " -L $library" }
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
eval vsim $elabcommand
}
# ----------------------------------------
# Elaborate the top level design with -voptargs=+acc option
alias elab_debug {
if [string is false -strict $SILENCE] {
echo "\[exec\] elab_debug"
}
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
foreach library $logical_libraries { append elabcommand " -L $library" }
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
eval vsim -voptargs=+acc $elabcommand
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -voptargs=+acc
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo " For most designs, this should be overridden"
echo " to enable the elab/elab_debug aliases."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Qsys base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
echo
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
echo
echo "SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. "
echo
echo "PRECOMP_DEVICE_LIB_FILE -- Precompiled device library file."
echo " Use this variable to provide modelsim.ini or tcl containing device library mapping and dev_com will be skipped"
echo " If value is empty, device libraries will be compiled local"
echo
echo "FORCE_MODELSIM_AE_SELECTION -- Set to true to force to select Modelsim AE always."
echo
echo "ENABLE_QE_LIBRARY_COMPILATION -- Set to true to enable device library compilation for Questa FE."
}
file_copy
h
qsys/qsys_top/sim/mentor/run_msim_setup.tcl
+34
View File
@@ -0,0 +1,34 @@
# (C) 2001-2026 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Intel
# Program License Subscription Agreement, Intel MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Intel and sold by Intel
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 26.1 110 linux 2026.04.08.10:52:56
# ----------------------------------------
# Auto-generated simulation script run_msim_setup.tcl
# ----------------------------------------
# This script provides commands to run the msim_setup.tcl script for the following IP detected in
# your Quartus project:
# qsys_top
#
#
# Intel recommends that you source this Quartus-generated IP simulation
# script to compile, elab and run the design without any customization.
# For customization, please follow the steps mentioned in msim_setup.tcl.
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
source $QSYS_SIMDIR/mentor/msim_setup.tcl
ld
run -all
quit
qsys/qsys_top/sim/qsys_top.v
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// qsys_top.v
// Generated using ACDS version 26.1 110
`timescale 1 ps / 1 ps
module qsys_top (
input wire clk_100_clk, // clk_100.clk
input wire reset_reset_n, // reset.reset_n
output wire ninit_done_ninit_done, // ninit_done.ninit_done
output wire h2f_reset_reset, // h2f_reset.reset
output wire [3:0] subsys_hps_hps2fpga_awid, // subsys_hps_hps2fpga.awid
output wire [37:0] subsys_hps_hps2fpga_awaddr, // .awaddr
output wire [7:0] subsys_hps_hps2fpga_awlen, // .awlen
output wire [2:0] subsys_hps_hps2fpga_awsize, // .awsize
output wire [1:0] subsys_hps_hps2fpga_awburst, // .awburst
output wire subsys_hps_hps2fpga_awlock, // .awlock
output wire [3:0] subsys_hps_hps2fpga_awcache, // .awcache
output wire [2:0] subsys_hps_hps2fpga_awprot, // .awprot
output wire subsys_hps_hps2fpga_awvalid, // .awvalid
input wire subsys_hps_hps2fpga_awready, // .awready
output wire [127:0] subsys_hps_hps2fpga_wdata, // .wdata
output wire [15:0] subsys_hps_hps2fpga_wstrb, // .wstrb
output wire subsys_hps_hps2fpga_wlast, // .wlast
output wire subsys_hps_hps2fpga_wvalid, // .wvalid
input wire subsys_hps_hps2fpga_wready, // .wready
input wire [3:0] subsys_hps_hps2fpga_bid, // .bid
input wire [1:0] subsys_hps_hps2fpga_bresp, // .bresp
input wire subsys_hps_hps2fpga_bvalid, // .bvalid
output wire subsys_hps_hps2fpga_bready, // .bready
output wire [3:0] subsys_hps_hps2fpga_arid, // .arid
output wire [37:0] subsys_hps_hps2fpga_araddr, // .araddr
output wire [7:0] subsys_hps_hps2fpga_arlen, // .arlen
output wire [2:0] subsys_hps_hps2fpga_arsize, // .arsize
output wire [1:0] subsys_hps_hps2fpga_arburst, // .arburst
output wire subsys_hps_hps2fpga_arlock, // .arlock
output wire [3:0] subsys_hps_hps2fpga_arcache, // .arcache
output wire [2:0] subsys_hps_hps2fpga_arprot, // .arprot
output wire subsys_hps_hps2fpga_arvalid, // .arvalid
input wire subsys_hps_hps2fpga_arready, // .arready
input wire [3:0] subsys_hps_hps2fpga_rid, // .rid
input wire [127:0] subsys_hps_hps2fpga_rdata, // .rdata
input wire [1:0] subsys_hps_hps2fpga_rresp, // .rresp
input wire subsys_hps_hps2fpga_rlast, // .rlast
input wire subsys_hps_hps2fpga_rvalid, // .rvalid
output wire subsys_hps_hps2fpga_rready, // .rready
output wire subsys_hps_h2f_warm_reset_handshake_reset_req, // subsys_hps_h2f_warm_reset_handshake.reset_req
input wire subsys_hps_h2f_warm_reset_handshake_reset_ack, // .reset_ack
input wire hps_io_hps_osc_clk, // hps_io.hps_osc_clk
inout wire hps_io_sdmmc_data0, // .sdmmc_data0
inout wire hps_io_sdmmc_data1, // .sdmmc_data1
output wire hps_io_sdmmc_cclk, // .sdmmc_cclk
inout wire hps_io_sdmmc_data2, // .sdmmc_data2
inout wire hps_io_sdmmc_data3, // .sdmmc_data3
inout wire hps_io_sdmmc_cmd, // .sdmmc_cmd
input wire hps_io_usb0_clk, // .usb0_clk
output wire hps_io_usb0_stp, // .usb0_stp
input wire hps_io_usb0_dir, // .usb0_dir
inout wire hps_io_usb0_data0, // .usb0_data0
inout wire hps_io_usb0_data1, // .usb0_data1
input wire hps_io_usb0_nxt, // .usb0_nxt
inout wire hps_io_usb0_data2, // .usb0_data2
inout wire hps_io_usb0_data3, // .usb0_data3
inout wire hps_io_usb0_data4, // .usb0_data4
inout wire hps_io_usb0_data5, // .usb0_data5
inout wire hps_io_usb0_data6, // .usb0_data6
inout wire hps_io_usb0_data7, // .usb0_data7
output wire hps_io_emac0_tx_clk, // .emac0_tx_clk
output wire hps_io_emac0_tx_ctl, // .emac0_tx_ctl
input wire hps_io_emac0_rx_clk, // .emac0_rx_clk
input wire hps_io_emac0_rx_ctl, // .emac0_rx_ctl
output wire hps_io_emac0_txd0, // .emac0_txd0
output wire hps_io_emac0_txd1, // .emac0_txd1
input wire hps_io_emac0_rxd0, // .emac0_rxd0
input wire hps_io_emac0_rxd1, // .emac0_rxd1
output wire hps_io_emac0_txd2, // .emac0_txd2
output wire hps_io_emac0_txd3, // .emac0_txd3
input wire hps_io_emac0_rxd2, // .emac0_rxd2
input wire hps_io_emac0_rxd3, // .emac0_rxd3
inout wire hps_io_mdio0_mdio, // .mdio0_mdio
output wire hps_io_mdio0_mdc, // .mdio0_mdc
output wire hps_io_uart1_tx, // .uart1_tx
input wire hps_io_uart1_rx, // .uart1_rx
inout wire hps_io_i2c1_sda, // .i2c1_sda
inout wire hps_io_i2c1_scl, // .i2c1_scl
inout wire hps_io_gpio28, // .gpio28
inout wire hps_io_gpio34, // .gpio34
inout wire hps_io_gpio40, // .gpio40
inout wire hps_io_gpio41, // .gpio41
input wire [31:0] f2h_irq1_in_irq, // f2h_irq1_in.irq
input wire [31:0] f2sdram_araddr, // f2sdram.araddr
input wire [1:0] f2sdram_arburst, // .arburst
input wire [3:0] f2sdram_arcache, // .arcache
input wire [4:0] f2sdram_arid, // .arid
input wire [7:0] f2sdram_arlen, // .arlen
input wire f2sdram_arlock, // .arlock
input wire [2:0] f2sdram_arprot, // .arprot
input wire [3:0] f2sdram_arqos, // .arqos
output wire f2sdram_arready, // .arready
input wire [2:0] f2sdram_arsize, // .arsize
input wire f2sdram_arvalid, // .arvalid
input wire [31:0] f2sdram_awaddr, // .awaddr
input wire [1:0] f2sdram_awburst, // .awburst
input wire [3:0] f2sdram_awcache, // .awcache
input wire [4:0] f2sdram_awid, // .awid
input wire [7:0] f2sdram_awlen, // .awlen
input wire f2sdram_awlock, // .awlock
input wire [2:0] f2sdram_awprot, // .awprot
input wire [3:0] f2sdram_awqos, // .awqos
output wire f2sdram_awready, // .awready
input wire [2:0] f2sdram_awsize, // .awsize
input wire f2sdram_awvalid, // .awvalid
output wire [4:0] f2sdram_bid, // .bid
input wire f2sdram_bready, // .bready
output wire [1:0] f2sdram_bresp, // .bresp
output wire f2sdram_bvalid, // .bvalid
output wire [255:0] f2sdram_rdata, // .rdata
output wire [4:0] f2sdram_rid, // .rid
output wire f2sdram_rlast, // .rlast
input wire f2sdram_rready, // .rready
output wire [1:0] f2sdram_rresp, // .rresp
output wire f2sdram_rvalid, // .rvalid
input wire [255:0] f2sdram_wdata, // .wdata
input wire f2sdram_wlast, // .wlast
output wire f2sdram_wready, // .wready
input wire [31:0] f2sdram_wstrb, // .wstrb
input wire f2sdram_wvalid, // .wvalid
input wire [7:0] f2sdram_aruser, // .aruser
input wire [7:0] f2sdram_awuser, // .awuser
input wire [7:0] f2sdram_wuser, // .wuser
output wire [7:0] f2sdram_buser, // .buser
input wire [3:0] f2sdram_arregion, // .arregion
output wire [7:0] f2sdram_ruser, // .ruser
input wire [3:0] f2sdram_awregion, // .awregion
output wire [0:0] emif_hps_emif_mem_0_mem_cs, // emif_hps_emif_mem_0.mem_cs
output wire [5:0] emif_hps_emif_mem_0_mem_ca, // .mem_ca
output wire [0:0] emif_hps_emif_mem_0_mem_cke, // .mem_cke
inout wire [31:0] emif_hps_emif_mem_0_mem_dq, // .mem_dq
inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_t, // .mem_dqs_t
inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_c, // .mem_dqs_c
inout wire [3:0] emif_hps_emif_mem_0_mem_dmi, // .mem_dmi
output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_t, // emif_hps_emif_mem_ck_0.mem_ck_t
output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_c, // .mem_ck_c
output wire emif_hps_emif_mem_reset_n_mem_reset_n, // emif_hps_emif_mem_reset_n.mem_reset_n
input wire emif_hps_emif_oct_0_oct_rzqin, // emif_hps_emif_oct_0.oct_rzqin
input wire emif_hps_emif_ref_clk_0_clk, // emif_hps_emif_ref_clk_0.clk
input wire [3:0] button_pio_external_connection_export, // button_pio_external_connection.export
input wire [3:0] dipsw_pio_external_connection_export, // dipsw_pio_external_connection.export
input wire [2:0] led_pio_external_connection_in_port, // led_pio_external_connection.in_port
output wire [2:0] led_pio_external_connection_out_port // .out_port
);
wire clk_100_out_clk_clk; // clk_100:out_clk -> [mm_interconnect_0:clk_100_out_clk_clk, rst_controller:clk, subsys_hps:f2sdram_clk_clk, subsys_hps:hps2fpga_clk_clk, subsys_hps:lwhps2fpga_clk_clk, subsys_periph:clk_clk]
wire rst_in_out_reset_reset; // rst_in:out_reset_n -> [rst_controller:reset_in0, subsys_hps:f2sdram_rst_reset, subsys_hps:hps2fpga_rst_reset, subsys_hps:lwhps2fpga_rst_reset, subsys_periph:reset_reset_n]
wire [1:0] subsys_hps_lwhps2fpga_awburst; // subsys_hps:lwhps2fpga_awburst -> mm_interconnect_0:subsys_hps_lwhps2fpga_awburst
wire [7:0] subsys_hps_lwhps2fpga_arlen; // subsys_hps:lwhps2fpga_arlen -> mm_interconnect_0:subsys_hps_lwhps2fpga_arlen
wire [3:0] subsys_hps_lwhps2fpga_wstrb; // subsys_hps:lwhps2fpga_wstrb -> mm_interconnect_0:subsys_hps_lwhps2fpga_wstrb
wire subsys_hps_lwhps2fpga_wready; // mm_interconnect_0:subsys_hps_lwhps2fpga_wready -> subsys_hps:lwhps2fpga_wready
wire [3:0] subsys_hps_lwhps2fpga_rid; // mm_interconnect_0:subsys_hps_lwhps2fpga_rid -> subsys_hps:lwhps2fpga_rid
wire subsys_hps_lwhps2fpga_rready; // subsys_hps:lwhps2fpga_rready -> mm_interconnect_0:subsys_hps_lwhps2fpga_rready
wire [7:0] subsys_hps_lwhps2fpga_awlen; // subsys_hps:lwhps2fpga_awlen -> mm_interconnect_0:subsys_hps_lwhps2fpga_awlen
wire [3:0] subsys_hps_lwhps2fpga_arcache; // subsys_hps:lwhps2fpga_arcache -> mm_interconnect_0:subsys_hps_lwhps2fpga_arcache
wire subsys_hps_lwhps2fpga_wvalid; // subsys_hps:lwhps2fpga_wvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_wvalid
wire [28:0] subsys_hps_lwhps2fpga_araddr; // subsys_hps:lwhps2fpga_araddr -> mm_interconnect_0:subsys_hps_lwhps2fpga_araddr
wire [2:0] subsys_hps_lwhps2fpga_arprot; // subsys_hps:lwhps2fpga_arprot -> mm_interconnect_0:subsys_hps_lwhps2fpga_arprot
wire [2:0] subsys_hps_lwhps2fpga_awprot; // subsys_hps:lwhps2fpga_awprot -> mm_interconnect_0:subsys_hps_lwhps2fpga_awprot
wire [31:0] subsys_hps_lwhps2fpga_wdata; // subsys_hps:lwhps2fpga_wdata -> mm_interconnect_0:subsys_hps_lwhps2fpga_wdata
wire subsys_hps_lwhps2fpga_arvalid; // subsys_hps:lwhps2fpga_arvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_arvalid
wire [3:0] subsys_hps_lwhps2fpga_awcache; // subsys_hps:lwhps2fpga_awcache -> mm_interconnect_0:subsys_hps_lwhps2fpga_awcache
wire [3:0] subsys_hps_lwhps2fpga_arid; // subsys_hps:lwhps2fpga_arid -> mm_interconnect_0:subsys_hps_lwhps2fpga_arid
wire subsys_hps_lwhps2fpga_arlock; // subsys_hps:lwhps2fpga_arlock -> mm_interconnect_0:subsys_hps_lwhps2fpga_arlock
wire subsys_hps_lwhps2fpga_awlock; // subsys_hps:lwhps2fpga_awlock -> mm_interconnect_0:subsys_hps_lwhps2fpga_awlock
wire [28:0] subsys_hps_lwhps2fpga_awaddr; // subsys_hps:lwhps2fpga_awaddr -> mm_interconnect_0:subsys_hps_lwhps2fpga_awaddr
wire [1:0] subsys_hps_lwhps2fpga_bresp; // mm_interconnect_0:subsys_hps_lwhps2fpga_bresp -> subsys_hps:lwhps2fpga_bresp
wire subsys_hps_lwhps2fpga_arready; // mm_interconnect_0:subsys_hps_lwhps2fpga_arready -> subsys_hps:lwhps2fpga_arready
wire [31:0] subsys_hps_lwhps2fpga_rdata; // mm_interconnect_0:subsys_hps_lwhps2fpga_rdata -> subsys_hps:lwhps2fpga_rdata
wire subsys_hps_lwhps2fpga_awready; // mm_interconnect_0:subsys_hps_lwhps2fpga_awready -> subsys_hps:lwhps2fpga_awready
wire [1:0] subsys_hps_lwhps2fpga_arburst; // subsys_hps:lwhps2fpga_arburst -> mm_interconnect_0:subsys_hps_lwhps2fpga_arburst
wire [2:0] subsys_hps_lwhps2fpga_arsize; // subsys_hps:lwhps2fpga_arsize -> mm_interconnect_0:subsys_hps_lwhps2fpga_arsize
wire subsys_hps_lwhps2fpga_bready; // subsys_hps:lwhps2fpga_bready -> mm_interconnect_0:subsys_hps_lwhps2fpga_bready
wire subsys_hps_lwhps2fpga_rlast; // mm_interconnect_0:subsys_hps_lwhps2fpga_rlast -> subsys_hps:lwhps2fpga_rlast
wire subsys_hps_lwhps2fpga_wlast; // subsys_hps:lwhps2fpga_wlast -> mm_interconnect_0:subsys_hps_lwhps2fpga_wlast
wire [1:0] subsys_hps_lwhps2fpga_rresp; // mm_interconnect_0:subsys_hps_lwhps2fpga_rresp -> subsys_hps:lwhps2fpga_rresp
wire [3:0] subsys_hps_lwhps2fpga_awid; // subsys_hps:lwhps2fpga_awid -> mm_interconnect_0:subsys_hps_lwhps2fpga_awid
wire [3:0] subsys_hps_lwhps2fpga_bid; // mm_interconnect_0:subsys_hps_lwhps2fpga_bid -> subsys_hps:lwhps2fpga_bid
wire subsys_hps_lwhps2fpga_bvalid; // mm_interconnect_0:subsys_hps_lwhps2fpga_bvalid -> subsys_hps:lwhps2fpga_bvalid
wire [2:0] subsys_hps_lwhps2fpga_awsize; // subsys_hps:lwhps2fpga_awsize -> mm_interconnect_0:subsys_hps_lwhps2fpga_awsize
wire subsys_hps_lwhps2fpga_awvalid; // subsys_hps:lwhps2fpga_awvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_awvalid
wire subsys_hps_lwhps2fpga_rvalid; // mm_interconnect_0:subsys_hps_lwhps2fpga_rvalid -> subsys_hps:lwhps2fpga_rvalid
wire [31:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata; // subsys_periph:pb_cpu_0_s0_readdata -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_readdata
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest; // subsys_periph:pb_cpu_0_s0_waitrequest -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_waitrequest
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_debugaccess -> subsys_periph:pb_cpu_0_s0_debugaccess
wire [16:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_address -> subsys_periph:pb_cpu_0_s0_address
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_read -> subsys_periph:pb_cpu_0_s0_read
wire [3:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_byteenable -> subsys_periph:pb_cpu_0_s0_byteenable
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid; // subsys_periph:pb_cpu_0_s0_readdatavalid -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_readdatavalid
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_write -> subsys_periph:pb_cpu_0_s0_write
wire [31:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_writedata -> subsys_periph:pb_cpu_0_s0_writedata
wire [0:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_burstcount -> subsys_periph:pb_cpu_0_s0_burstcount
wire irq_mapper_receiver0_irq; // subsys_periph:button_pio_irq_irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // subsys_periph:dipsw_pio_irq_irq -> irq_mapper:receiver1_irq
wire [31:0] subsys_hps_f2h_irq0_in_irq; // irq_mapper:sender_irq -> subsys_hps:f2h_irq0_in_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_0:subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset]
clk_100 clk_100 (
.in_clk (clk_100_clk), // input, width = 1, in_clk.clk
.out_clk (clk_100_out_clk_clk) // output, width = 1, out_clk.clk
);
rst_in rst_in (
.in_reset_n (reset_reset_n), // input, width = 1, in_reset.reset_n
.out_reset_n (rst_in_out_reset_reset) // output, width = 1, out_reset.reset_n
);
user_rst_clkgate_0 user_rst_clkgate_0 (
.ninit_done (ninit_done_ninit_done) // output, width = 1, ninit_done.ninit_done
);
hps_subsys subsys_hps (
.h2f_reset_reset (h2f_reset_reset), // output, width = 1, h2f_reset.reset
.hps2fpga_clk_clk (clk_100_out_clk_clk), // input, width = 1, hps2fpga_clk.clk
.hps2fpga_rst_reset (~rst_in_out_reset_reset), // input, width = 1, hps2fpga_rst.reset
.hps2fpga_awid (subsys_hps_hps2fpga_awid), // output, width = 4, hps2fpga.awid
.hps2fpga_awaddr (subsys_hps_hps2fpga_awaddr), // output, width = 38, .awaddr
.hps2fpga_awlen (subsys_hps_hps2fpga_awlen), // output, width = 8, .awlen
.hps2fpga_awsize (subsys_hps_hps2fpga_awsize), // output, width = 3, .awsize
.hps2fpga_awburst (subsys_hps_hps2fpga_awburst), // output, width = 2, .awburst
.hps2fpga_awlock (subsys_hps_hps2fpga_awlock), // output, width = 1, .awlock
.hps2fpga_awcache (subsys_hps_hps2fpga_awcache), // output, width = 4, .awcache
.hps2fpga_awprot (subsys_hps_hps2fpga_awprot), // output, width = 3, .awprot
.hps2fpga_awvalid (subsys_hps_hps2fpga_awvalid), // output, width = 1, .awvalid
.hps2fpga_awready (subsys_hps_hps2fpga_awready), // input, width = 1, .awready
.hps2fpga_wdata (subsys_hps_hps2fpga_wdata), // output, width = 128, .wdata
.hps2fpga_wstrb (subsys_hps_hps2fpga_wstrb), // output, width = 16, .wstrb
.hps2fpga_wlast (subsys_hps_hps2fpga_wlast), // output, width = 1, .wlast
.hps2fpga_wvalid (subsys_hps_hps2fpga_wvalid), // output, width = 1, .wvalid
.hps2fpga_wready (subsys_hps_hps2fpga_wready), // input, width = 1, .wready
.hps2fpga_bid (subsys_hps_hps2fpga_bid), // input, width = 4, .bid
.hps2fpga_bresp (subsys_hps_hps2fpga_bresp), // input, width = 2, .bresp
.hps2fpga_bvalid (subsys_hps_hps2fpga_bvalid), // input, width = 1, .bvalid
.hps2fpga_bready (subsys_hps_hps2fpga_bready), // output, width = 1, .bready
.hps2fpga_arid (subsys_hps_hps2fpga_arid), // output, width = 4, .arid
.hps2fpga_araddr (subsys_hps_hps2fpga_araddr), // output, width = 38, .araddr
.hps2fpga_arlen (subsys_hps_hps2fpga_arlen), // output, width = 8, .arlen
.hps2fpga_arsize (subsys_hps_hps2fpga_arsize), // output, width = 3, .arsize
.hps2fpga_arburst (subsys_hps_hps2fpga_arburst), // output, width = 2, .arburst
.hps2fpga_arlock (subsys_hps_hps2fpga_arlock), // output, width = 1, .arlock
.hps2fpga_arcache (subsys_hps_hps2fpga_arcache), // output, width = 4, .arcache
.hps2fpga_arprot (subsys_hps_hps2fpga_arprot), // output, width = 3, .arprot
.hps2fpga_arvalid (subsys_hps_hps2fpga_arvalid), // output, width = 1, .arvalid
.hps2fpga_arready (subsys_hps_hps2fpga_arready), // input, width = 1, .arready
.hps2fpga_rid (subsys_hps_hps2fpga_rid), // input, width = 4, .rid
.hps2fpga_rdata (subsys_hps_hps2fpga_rdata), // input, width = 128, .rdata
.hps2fpga_rresp (subsys_hps_hps2fpga_rresp), // input, width = 2, .rresp
.hps2fpga_rlast (subsys_hps_hps2fpga_rlast), // input, width = 1, .rlast
.hps2fpga_rvalid (subsys_hps_hps2fpga_rvalid), // input, width = 1, .rvalid
.hps2fpga_rready (subsys_hps_hps2fpga_rready), // output, width = 1, .rready
.lwhps2fpga_clk_clk (clk_100_out_clk_clk), // input, width = 1, lwhps2fpga_clk.clk
.lwhps2fpga_rst_reset (~rst_in_out_reset_reset), // input, width = 1, lwhps2fpga_rst.reset
.lwhps2fpga_awid (subsys_hps_lwhps2fpga_awid), // output, width = 4, lwhps2fpga.awid
.lwhps2fpga_awaddr (subsys_hps_lwhps2fpga_awaddr), // output, width = 29, .awaddr
.lwhps2fpga_awlen (subsys_hps_lwhps2fpga_awlen), // output, width = 8, .awlen
.lwhps2fpga_awsize (subsys_hps_lwhps2fpga_awsize), // output, width = 3, .awsize
.lwhps2fpga_awburst (subsys_hps_lwhps2fpga_awburst), // output, width = 2, .awburst
.lwhps2fpga_awlock (subsys_hps_lwhps2fpga_awlock), // output, width = 1, .awlock
.lwhps2fpga_awcache (subsys_hps_lwhps2fpga_awcache), // output, width = 4, .awcache
.lwhps2fpga_awprot (subsys_hps_lwhps2fpga_awprot), // output, width = 3, .awprot
.lwhps2fpga_awvalid (subsys_hps_lwhps2fpga_awvalid), // output, width = 1, .awvalid
.lwhps2fpga_awready (subsys_hps_lwhps2fpga_awready), // input, width = 1, .awready
.lwhps2fpga_wdata (subsys_hps_lwhps2fpga_wdata), // output, width = 32, .wdata
.lwhps2fpga_wstrb (subsys_hps_lwhps2fpga_wstrb), // output, width = 4, .wstrb
.lwhps2fpga_wlast (subsys_hps_lwhps2fpga_wlast), // output, width = 1, .wlast
.lwhps2fpga_wvalid (subsys_hps_lwhps2fpga_wvalid), // output, width = 1, .wvalid
.lwhps2fpga_wready (subsys_hps_lwhps2fpga_wready), // input, width = 1, .wready
.lwhps2fpga_bid (subsys_hps_lwhps2fpga_bid), // input, width = 4, .bid
.lwhps2fpga_bresp (subsys_hps_lwhps2fpga_bresp), // input, width = 2, .bresp
.lwhps2fpga_bvalid (subsys_hps_lwhps2fpga_bvalid), // input, width = 1, .bvalid
.lwhps2fpga_bready (subsys_hps_lwhps2fpga_bready), // output, width = 1, .bready
.lwhps2fpga_arid (subsys_hps_lwhps2fpga_arid), // output, width = 4, .arid
.lwhps2fpga_araddr (subsys_hps_lwhps2fpga_araddr), // output, width = 29, .araddr
.lwhps2fpga_arlen (subsys_hps_lwhps2fpga_arlen), // output, width = 8, .arlen
.lwhps2fpga_arsize (subsys_hps_lwhps2fpga_arsize), // output, width = 3, .arsize
.lwhps2fpga_arburst (subsys_hps_lwhps2fpga_arburst), // output, width = 2, .arburst
.lwhps2fpga_arlock (subsys_hps_lwhps2fpga_arlock), // output, width = 1, .arlock
.lwhps2fpga_arcache (subsys_hps_lwhps2fpga_arcache), // output, width = 4, .arcache
.lwhps2fpga_arprot (subsys_hps_lwhps2fpga_arprot), // output, width = 3, .arprot
.lwhps2fpga_arvalid (subsys_hps_lwhps2fpga_arvalid), // output, width = 1, .arvalid
.lwhps2fpga_arready (subsys_hps_lwhps2fpga_arready), // input, width = 1, .arready
.lwhps2fpga_rid (subsys_hps_lwhps2fpga_rid), // input, width = 4, .rid
.lwhps2fpga_rdata (subsys_hps_lwhps2fpga_rdata), // input, width = 32, .rdata
.lwhps2fpga_rresp (subsys_hps_lwhps2fpga_rresp), // input, width = 2, .rresp
.lwhps2fpga_rlast (subsys_hps_lwhps2fpga_rlast), // input, width = 1, .rlast
.lwhps2fpga_rvalid (subsys_hps_lwhps2fpga_rvalid), // input, width = 1, .rvalid
.lwhps2fpga_rready (subsys_hps_lwhps2fpga_rready), // output, width = 1, .rready
.h2f_warm_reset_handshake_reset_req (subsys_hps_h2f_warm_reset_handshake_reset_req), // output, width = 1, h2f_warm_reset_handshake.reset_req
.h2f_warm_reset_handshake_reset_ack (subsys_hps_h2f_warm_reset_handshake_reset_ack), // input, width = 1, .reset_ack
.hps_io_hps_osc_clk (hps_io_hps_osc_clk), // input, width = 1, hps_io.hps_osc_clk
.hps_io_sdmmc_data0 (hps_io_sdmmc_data0), // inout, width = 1, .sdmmc_data0
.hps_io_sdmmc_data1 (hps_io_sdmmc_data1), // inout, width = 1, .sdmmc_data1
.hps_io_sdmmc_cclk (hps_io_sdmmc_cclk), // output, width = 1, .sdmmc_cclk
.hps_io_sdmmc_data2 (hps_io_sdmmc_data2), // inout, width = 1, .sdmmc_data2
.hps_io_sdmmc_data3 (hps_io_sdmmc_data3), // inout, width = 1, .sdmmc_data3
.hps_io_sdmmc_cmd (hps_io_sdmmc_cmd), // inout, width = 1, .sdmmc_cmd
.hps_io_usb0_clk (hps_io_usb0_clk), // input, width = 1, .usb0_clk
.hps_io_usb0_stp (hps_io_usb0_stp), // output, width = 1, .usb0_stp
.hps_io_usb0_dir (hps_io_usb0_dir), // input, width = 1, .usb0_dir
.hps_io_usb0_data0 (hps_io_usb0_data0), // inout, width = 1, .usb0_data0
.hps_io_usb0_data1 (hps_io_usb0_data1), // inout, width = 1, .usb0_data1
.hps_io_usb0_nxt (hps_io_usb0_nxt), // input, width = 1, .usb0_nxt
.hps_io_usb0_data2 (hps_io_usb0_data2), // inout, width = 1, .usb0_data2
.hps_io_usb0_data3 (hps_io_usb0_data3), // inout, width = 1, .usb0_data3
.hps_io_usb0_data4 (hps_io_usb0_data4), // inout, width = 1, .usb0_data4
.hps_io_usb0_data5 (hps_io_usb0_data5), // inout, width = 1, .usb0_data5
.hps_io_usb0_data6 (hps_io_usb0_data6), // inout, width = 1, .usb0_data6
.hps_io_usb0_data7 (hps_io_usb0_data7), // inout, width = 1, .usb0_data7
.hps_io_emac0_tx_clk (hps_io_emac0_tx_clk), // output, width = 1, .emac0_tx_clk
.hps_io_emac0_tx_ctl (hps_io_emac0_tx_ctl), // output, width = 1, .emac0_tx_ctl
.hps_io_emac0_rx_clk (hps_io_emac0_rx_clk), // input, width = 1, .emac0_rx_clk
.hps_io_emac0_rx_ctl (hps_io_emac0_rx_ctl), // input, width = 1, .emac0_rx_ctl
.hps_io_emac0_txd0 (hps_io_emac0_txd0), // output, width = 1, .emac0_txd0
.hps_io_emac0_txd1 (hps_io_emac0_txd1), // output, width = 1, .emac0_txd1
.hps_io_emac0_rxd0 (hps_io_emac0_rxd0), // input, width = 1, .emac0_rxd0
.hps_io_emac0_rxd1 (hps_io_emac0_rxd1), // input, width = 1, .emac0_rxd1
.hps_io_emac0_txd2 (hps_io_emac0_txd2), // output, width = 1, .emac0_txd2
.hps_io_emac0_txd3 (hps_io_emac0_txd3), // output, width = 1, .emac0_txd3
.hps_io_emac0_rxd2 (hps_io_emac0_rxd2), // input, width = 1, .emac0_rxd2
.hps_io_emac0_rxd3 (hps_io_emac0_rxd3), // input, width = 1, .emac0_rxd3
.hps_io_mdio0_mdio (hps_io_mdio0_mdio), // inout, width = 1, .mdio0_mdio
.hps_io_mdio0_mdc (hps_io_mdio0_mdc), // output, width = 1, .mdio0_mdc
.hps_io_uart1_tx (hps_io_uart1_tx), // output, width = 1, .uart1_tx
.hps_io_uart1_rx (hps_io_uart1_rx), // input, width = 1, .uart1_rx
.hps_io_i2c1_sda (hps_io_i2c1_sda), // inout, width = 1, .i2c1_sda
.hps_io_i2c1_scl (hps_io_i2c1_scl), // inout, width = 1, .i2c1_scl
.hps_io_gpio28 (hps_io_gpio28), // inout, width = 1, .gpio28
.hps_io_gpio34 (hps_io_gpio34), // inout, width = 1, .gpio34
.hps_io_gpio40 (hps_io_gpio40), // inout, width = 1, .gpio40
.hps_io_gpio41 (hps_io_gpio41), // inout, width = 1, .gpio41
.f2h_irq1_in_irq (f2h_irq1_in_irq), // input, width = 32, f2h_irq1_in.irq
.f2h_irq0_in_irq (subsys_hps_f2h_irq0_in_irq), // input, width = 32, f2h_irq0_in.irq
.f2sdram_clk_clk (clk_100_out_clk_clk), // input, width = 1, f2sdram_clk.clk
.f2sdram_rst_reset (~rst_in_out_reset_reset), // input, width = 1, f2sdram_rst.reset
.f2sdram_araddr (f2sdram_araddr), // input, width = 32, f2sdram.araddr
.f2sdram_arburst (f2sdram_arburst), // input, width = 2, .arburst
.f2sdram_arcache (f2sdram_arcache), // input, width = 4, .arcache
.f2sdram_arid (f2sdram_arid), // input, width = 5, .arid
.f2sdram_arlen (f2sdram_arlen), // input, width = 8, .arlen
.f2sdram_arlock (f2sdram_arlock), // input, width = 1, .arlock
.f2sdram_arprot (f2sdram_arprot), // input, width = 3, .arprot
.f2sdram_arqos (f2sdram_arqos), // input, width = 4, .arqos
.f2sdram_arready (f2sdram_arready), // output, width = 1, .arready
.f2sdram_arsize (f2sdram_arsize), // input, width = 3, .arsize
.f2sdram_arvalid (f2sdram_arvalid), // input, width = 1, .arvalid
.f2sdram_awaddr (f2sdram_awaddr), // input, width = 32, .awaddr
.f2sdram_awburst (f2sdram_awburst), // input, width = 2, .awburst
.f2sdram_awcache (f2sdram_awcache), // input, width = 4, .awcache
.f2sdram_awid (f2sdram_awid), // input, width = 5, .awid
.f2sdram_awlen (f2sdram_awlen), // input, width = 8, .awlen
.f2sdram_awlock (f2sdram_awlock), // input, width = 1, .awlock
.f2sdram_awprot (f2sdram_awprot), // input, width = 3, .awprot
.f2sdram_awqos (f2sdram_awqos), // input, width = 4, .awqos
.f2sdram_awready (f2sdram_awready), // output, width = 1, .awready
.f2sdram_awsize (f2sdram_awsize), // input, width = 3, .awsize
.f2sdram_awvalid (f2sdram_awvalid), // input, width = 1, .awvalid
.f2sdram_bid (f2sdram_bid), // output, width = 5, .bid
.f2sdram_bready (f2sdram_bready), // input, width = 1, .bready
.f2sdram_bresp (f2sdram_bresp), // output, width = 2, .bresp
.f2sdram_bvalid (f2sdram_bvalid), // output, width = 1, .bvalid
.f2sdram_rdata (f2sdram_rdata), // output, width = 256, .rdata
.f2sdram_rid (f2sdram_rid), // output, width = 5, .rid
.f2sdram_rlast (f2sdram_rlast), // output, width = 1, .rlast
.f2sdram_rready (f2sdram_rready), // input, width = 1, .rready
.f2sdram_rresp (f2sdram_rresp), // output, width = 2, .rresp
.f2sdram_rvalid (f2sdram_rvalid), // output, width = 1, .rvalid
.f2sdram_wdata (f2sdram_wdata), // input, width = 256, .wdata
.f2sdram_wlast (f2sdram_wlast), // input, width = 1, .wlast
.f2sdram_wready (f2sdram_wready), // output, width = 1, .wready
.f2sdram_wstrb (f2sdram_wstrb), // input, width = 32, .wstrb
.f2sdram_wvalid (f2sdram_wvalid), // input, width = 1, .wvalid
.f2sdram_aruser (f2sdram_aruser), // input, width = 8, .aruser
.f2sdram_awuser (f2sdram_awuser), // input, width = 8, .awuser
.f2sdram_wuser (f2sdram_wuser), // input, width = 8, .wuser
.f2sdram_buser (f2sdram_buser), // output, width = 8, .buser
.f2sdram_arregion (f2sdram_arregion), // input, width = 4, .arregion
.f2sdram_ruser (f2sdram_ruser), // output, width = 8, .ruser
.f2sdram_awregion (f2sdram_awregion), // input, width = 4, .awregion
.emif_hps_emif_mem_0_mem_cs (emif_hps_emif_mem_0_mem_cs), // output, width = 1, emif_hps_emif_mem_0.mem_cs
.emif_hps_emif_mem_0_mem_ca (emif_hps_emif_mem_0_mem_ca), // output, width = 6, .mem_ca
.emif_hps_emif_mem_0_mem_cke (emif_hps_emif_mem_0_mem_cke), // output, width = 1, .mem_cke
.emif_hps_emif_mem_0_mem_dq (emif_hps_emif_mem_0_mem_dq), // inout, width = 32, .mem_dq
.emif_hps_emif_mem_0_mem_dqs_t (emif_hps_emif_mem_0_mem_dqs_t), // inout, width = 4, .mem_dqs_t
.emif_hps_emif_mem_0_mem_dqs_c (emif_hps_emif_mem_0_mem_dqs_c), // inout, width = 4, .mem_dqs_c
.emif_hps_emif_mem_0_mem_dmi (emif_hps_emif_mem_0_mem_dmi), // inout, width = 4, .mem_dmi
.emif_hps_emif_mem_ck_0_mem_ck_t (emif_hps_emif_mem_ck_0_mem_ck_t), // output, width = 1, emif_hps_emif_mem_ck_0.mem_ck_t
.emif_hps_emif_mem_ck_0_mem_ck_c (emif_hps_emif_mem_ck_0_mem_ck_c), // output, width = 1, .mem_ck_c
.emif_hps_emif_mem_reset_n_mem_reset_n (emif_hps_emif_mem_reset_n_mem_reset_n), // output, width = 1, emif_hps_emif_mem_reset_n.mem_reset_n
.emif_hps_emif_oct_0_oct_rzqin (emif_hps_emif_oct_0_oct_rzqin), // input, width = 1, emif_hps_emif_oct_0.oct_rzqin
.emif_hps_emif_ref_clk_clk (emif_hps_emif_ref_clk_0_clk) // input, width = 1, emif_hps_emif_ref_clk.clk
);
peripheral_subsys subsys_periph (
.button_pio_external_connection_export (button_pio_external_connection_export), // input, width = 4, button_pio_external_connection.export
.button_pio_irq_irq (irq_mapper_receiver0_irq), // output, width = 1, button_pio_irq.irq
.dipsw_pio_external_connection_export (dipsw_pio_external_connection_export), // input, width = 4, dipsw_pio_external_connection.export
.dipsw_pio_irq_irq (irq_mapper_receiver1_irq), // output, width = 1, dipsw_pio_irq.irq
.led_pio_external_connection_in_port (led_pio_external_connection_in_port), // input, width = 3, led_pio_external_connection.in_port
.led_pio_external_connection_out_port (led_pio_external_connection_out_port), // output, width = 3, .out_port
.pb_cpu_0_s0_waitrequest (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest), // output, width = 1, pb_cpu_0_s0.waitrequest
.pb_cpu_0_s0_readdata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata), // output, width = 32, .readdata
.pb_cpu_0_s0_readdatavalid (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid), // output, width = 1, .readdatavalid
.pb_cpu_0_s0_burstcount (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount), // input, width = 1, .burstcount
.pb_cpu_0_s0_writedata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata), // input, width = 32, .writedata
.pb_cpu_0_s0_address (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address), // input, width = 17, .address
.pb_cpu_0_s0_write (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write), // input, width = 1, .write
.pb_cpu_0_s0_read (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read), // input, width = 1, .read
.pb_cpu_0_s0_byteenable (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable), // input, width = 4, .byteenable
.pb_cpu_0_s0_debugaccess (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess), // input, width = 1, .debugaccess
.clk_clk (clk_100_out_clk_clk), // input, width = 1, clk.clk
.reset_reset_n (rst_in_out_reset_reset) // input, width = 1, reset.reset_n
);
qsys_top_altera_mm_interconnect_1920_ykfyxdi mm_interconnect_0 (
.subsys_hps_lwhps2fpga_awid (subsys_hps_lwhps2fpga_awid), // input, width = 4, subsys_hps_lwhps2fpga.awid
.subsys_hps_lwhps2fpga_awaddr (subsys_hps_lwhps2fpga_awaddr), // input, width = 29, .awaddr
.subsys_hps_lwhps2fpga_awlen (subsys_hps_lwhps2fpga_awlen), // input, width = 8, .awlen
.subsys_hps_lwhps2fpga_awsize (subsys_hps_lwhps2fpga_awsize), // input, width = 3, .awsize
.subsys_hps_lwhps2fpga_awburst (subsys_hps_lwhps2fpga_awburst), // input, width = 2, .awburst
.subsys_hps_lwhps2fpga_awlock (subsys_hps_lwhps2fpga_awlock), // input, width = 1, .awlock
.subsys_hps_lwhps2fpga_awcache (subsys_hps_lwhps2fpga_awcache), // input, width = 4, .awcache
.subsys_hps_lwhps2fpga_awprot (subsys_hps_lwhps2fpga_awprot), // input, width = 3, .awprot
.subsys_hps_lwhps2fpga_awvalid (subsys_hps_lwhps2fpga_awvalid), // input, width = 1, .awvalid
.subsys_hps_lwhps2fpga_awready (subsys_hps_lwhps2fpga_awready), // output, width = 1, .awready
.subsys_hps_lwhps2fpga_wdata (subsys_hps_lwhps2fpga_wdata), // input, width = 32, .wdata
.subsys_hps_lwhps2fpga_wstrb (subsys_hps_lwhps2fpga_wstrb), // input, width = 4, .wstrb
.subsys_hps_lwhps2fpga_wlast (subsys_hps_lwhps2fpga_wlast), // input, width = 1, .wlast
.subsys_hps_lwhps2fpga_wvalid (subsys_hps_lwhps2fpga_wvalid), // input, width = 1, .wvalid
.subsys_hps_lwhps2fpga_wready (subsys_hps_lwhps2fpga_wready), // output, width = 1, .wready
.subsys_hps_lwhps2fpga_bid (subsys_hps_lwhps2fpga_bid), // output, width = 4, .bid
.subsys_hps_lwhps2fpga_bresp (subsys_hps_lwhps2fpga_bresp), // output, width = 2, .bresp
.subsys_hps_lwhps2fpga_bvalid (subsys_hps_lwhps2fpga_bvalid), // output, width = 1, .bvalid
.subsys_hps_lwhps2fpga_bready (subsys_hps_lwhps2fpga_bready), // input, width = 1, .bready
.subsys_hps_lwhps2fpga_arid (subsys_hps_lwhps2fpga_arid), // input, width = 4, .arid
.subsys_hps_lwhps2fpga_araddr (subsys_hps_lwhps2fpga_araddr), // input, width = 29, .araddr
.subsys_hps_lwhps2fpga_arlen (subsys_hps_lwhps2fpga_arlen), // input, width = 8, .arlen
.subsys_hps_lwhps2fpga_arsize (subsys_hps_lwhps2fpga_arsize), // input, width = 3, .arsize
.subsys_hps_lwhps2fpga_arburst (subsys_hps_lwhps2fpga_arburst), // input, width = 2, .arburst
.subsys_hps_lwhps2fpga_arlock (subsys_hps_lwhps2fpga_arlock), // input, width = 1, .arlock
.subsys_hps_lwhps2fpga_arcache (subsys_hps_lwhps2fpga_arcache), // input, width = 4, .arcache
.subsys_hps_lwhps2fpga_arprot (subsys_hps_lwhps2fpga_arprot), // input, width = 3, .arprot
.subsys_hps_lwhps2fpga_arvalid (subsys_hps_lwhps2fpga_arvalid), // input, width = 1, .arvalid
.subsys_hps_lwhps2fpga_arready (subsys_hps_lwhps2fpga_arready), // output, width = 1, .arready
.subsys_hps_lwhps2fpga_rid (subsys_hps_lwhps2fpga_rid), // output, width = 4, .rid
.subsys_hps_lwhps2fpga_rdata (subsys_hps_lwhps2fpga_rdata), // output, width = 32, .rdata
.subsys_hps_lwhps2fpga_rresp (subsys_hps_lwhps2fpga_rresp), // output, width = 2, .rresp
.subsys_hps_lwhps2fpga_rlast (subsys_hps_lwhps2fpga_rlast), // output, width = 1, .rlast
.subsys_hps_lwhps2fpga_rvalid (subsys_hps_lwhps2fpga_rvalid), // output, width = 1, .rvalid
.subsys_hps_lwhps2fpga_rready (subsys_hps_lwhps2fpga_rready), // input, width = 1, .rready
.subsys_periph_pb_cpu_0_s0_address (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address), // output, width = 17, subsys_periph_pb_cpu_0_s0.address
.subsys_periph_pb_cpu_0_s0_write (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write), // output, width = 1, .write
.subsys_periph_pb_cpu_0_s0_read (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read), // output, width = 1, .read
.subsys_periph_pb_cpu_0_s0_readdata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata), // input, width = 32, .readdata
.subsys_periph_pb_cpu_0_s0_writedata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata), // output, width = 32, .writedata
.subsys_periph_pb_cpu_0_s0_burstcount (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount), // output, width = 1, .burstcount
.subsys_periph_pb_cpu_0_s0_byteenable (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable), // output, width = 4, .byteenable
.subsys_periph_pb_cpu_0_s0_readdatavalid (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid), // input, width = 1, .readdatavalid
.subsys_periph_pb_cpu_0_s0_waitrequest (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest), // input, width = 1, .waitrequest
.subsys_periph_pb_cpu_0_s0_debugaccess (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess), // output, width = 1, .debugaccess
.subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // input, width = 1, subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset.reset
.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // input, width = 1, subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset.reset
.clk_100_out_clk_clk (clk_100_out_clk_clk) // input, width = 1, clk_100_out_clk.clk
);
qsys_top_altera_irq_mapper_2001_lp4cnei irq_mapper (
.clk (), // input, width = 1, clk.clk
.reset (), // input, width = 1, clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // input, width = 1, receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // input, width = 1, receiver1.irq
.sender_irq (subsys_hps_f2h_irq0_in_irq) // output, width = 32, sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("both"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~rst_in_out_reset_reset), // input, width = 1, reset_in0.reset
.clk (clk_100_out_clk_clk), // input, width = 1, clk.clk
.reset_out (rst_controller_reset_out_reset), // output, width = 1, reset_out.reset
.reset_req (), // (terminated),
.reset_req_in0 (1'b0), // (terminated),
.reset_in1 (1'b0), // (terminated),
.reset_req_in1 (1'b0), // (terminated),
.reset_in2 (1'b0), // (terminated),
.reset_req_in2 (1'b0), // (terminated),
.reset_in3 (1'b0), // (terminated),
.reset_req_in3 (1'b0), // (terminated),
.reset_in4 (1'b0), // (terminated),
.reset_req_in4 (1'b0), // (terminated),
.reset_in5 (1'b0), // (terminated),
.reset_req_in5 (1'b0), // (terminated),
.reset_in6 (1'b0), // (terminated),
.reset_req_in6 (1'b0), // (terminated),
.reset_in7 (1'b0), // (terminated),
.reset_req_in7 (1'b0), // (terminated),
.reset_in8 (1'b0), // (terminated),
.reset_req_in8 (1'b0), // (terminated),
.reset_in9 (1'b0), // (terminated),
.reset_req_in9 (1'b0), // (terminated),
.reset_in10 (1'b0), // (terminated),
.reset_req_in10 (1'b0), // (terminated),
.reset_in11 (1'b0), // (terminated),
.reset_req_in11 (1'b0), // (terminated),
.reset_in12 (1'b0), // (terminated),
.reset_req_in12 (1'b0), // (terminated),
.reset_in13 (1'b0), // (terminated),
.reset_req_in13 (1'b0), // (terminated),
.reset_in14 (1'b0), // (terminated),
.reset_req_in14 (1'b0), // (terminated),
.reset_in15 (1'b0), // (terminated),
.reset_req_in15 (1'b0) // (terminated),
);
endmodule
qsys/qsys_top/sim/synopsys/vcsmx/_device_synopsys_sim.setup
+2
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-- DONOT MODIFY
-- Contains device library mapping
qsys/qsys_top/sim/synopsys/vcsmx/synopsys_sim.setup
+21
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WORK > DEFAULT
DEFAULT: ./libraries/work/
work: ./libraries/work/
altera_merlin_axi_translator_1987: ./libraries/altera_merlin_axi_translator_1987/
altera_merlin_slave_translator_191: ./libraries/altera_merlin_slave_translator_191/
altera_merlin_axi_master_ni_19117: ./libraries/altera_merlin_axi_master_ni_19117/
altera_merlin_slave_agent_1930: ./libraries/altera_merlin_slave_agent_1930/
altera_avalon_sc_fifo_1932: ./libraries/altera_avalon_sc_fifo_1932/
altera_merlin_router_1921: ./libraries/altera_merlin_router_1921/
altera_avalon_st_pipeline_stage_1930: ./libraries/altera_avalon_st_pipeline_stage_1930/
altera_merlin_burst_adapter_1940: ./libraries/altera_merlin_burst_adapter_1940/
altera_merlin_demultiplexer_1921: ./libraries/altera_merlin_demultiplexer_1921/
altera_merlin_multiplexer_1922: ./libraries/altera_merlin_multiplexer_1922/
altera_mm_interconnect_1920: ./libraries/altera_mm_interconnect_1920/
altera_irq_mapper_2001: ./libraries/altera_irq_mapper_2001/
altera_reset_controller_1924: ./libraries/altera_reset_controller_1924/
qsys_top: ./libraries/qsys_top/
OTHERS=_device_synopsys_sim.setup
OTHERS=_default_synopsys_sim.setup
LIBRARY_SCAN = TRUE
qsys/qsys_top/sim/synopsys/vcsmx/vcsmx_setup.sh
Executable
+429
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@@ -0,0 +1,429 @@
# (C) 2001-2026 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Intel
# Program License Subscription Agreement, Intel MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Intel and sold by Intel
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 26.1 110 linux 2026.04.08.10:52:56
# ----------------------------------------
# vcsmx - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# qsys_top
#
# Intel recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level shell script that compiles Intel simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
#
# You can also modify the simulation flow to suit your needs. Set the
# following variables to 1 to disable their corresponding processes:
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator. In this case, you must also copy the generated library
# # setup "synopsys_sim.setup" into the location from which you launch the
# # simulator, or incorporate into any existing library setup.
# #
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
# # simulation libraries and Quartus-generated IP simulation files, and copy
# # any ROM/RAM initialization files to the simulation directory.
# #
# # - If necessary, specify any compilation options:
# # USER_DEFINED_COMPILE_OPTIONS
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_ELAB=1 \
# SKIP_SIM=1 \
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
# QSYS_SIMDIR=<script generation output directory>
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the IP script)
# #
# vlogan <compilation options> <design and testbench files>
# #
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
# # testbench module/entity name.
# #
# # Run the IP script again to elaborate and simulate the top level:
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_FILE_COPY=1 \
# SKIP_DEV_COM=1 \
# SKIP_COM=1 \
# TOP_LEVEL_NAME="'-top <simulation top>'" \
# QSYS_SIMDIR=<script generation output directory> \
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
# DEFAULT_ELAB_OPTIONS=<default elaboration options for your design> \
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If qsys_top is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Intel IP
# within the Quartus project, and generate a unified
# script which supports all the Intel IP within the design.
# ----------------------------------------
# ACDS 26.1 110 linux 2026.04.08.10:52:56
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="qsys_top.qsys_top"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="/opt/altera_pro/26.1/quartus/"
QUARTUS_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/eda/sim_lib/"
DEVICES_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
DEFAULT_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
PRECOMP_DEVICE_LIB_FILE=""
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
#-------------------------------------------
# check tclsh version no earlier than 8.5
version=$(echo "puts [package vcompare [info tclversion] 8.5]; exit" | tclsh)
if [ $version -eq -1 ]; then
echo "Error: Minimum required tcl package version is 8.5." >&2
exit 1
fi
#-------------------------------------------
# read .sh file to override initialized variables
if [ -n "${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}" ] && [ -f ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE} ]; then
echo "Sourcing ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}"
source ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}
if [ $? -ne 0 ]; then
echo "Error:: This file ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE} has invalid expression/s" >&2
exit $?
fi
fi
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* && `vcs -platform` != *"suse64"* && `vcs -platform` != *"linux64"* ]]; then
SIMULATOR_TOOL_BITNESS="bit_32"
else
SIMULATOR_TOOL_BITNESS="bit_64"
fi
TCLSCRIPT='
set QSYS_SIMDIR [lindex $argv 1]
set SIMULATOR_TOOL_BITNESS [lindex $argv 2]
source $QSYS_SIMDIR/common/vcsmx_files.tcl
set LD_LIBRARY_PATH [dict create]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [qsys_top::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
if {[dict size $LD_LIBRARY_PATH] !=0 } {
set LD_LIBRARY_PATH [join [dict keys $LD_LIBRARY_PATH] ":"]
puts "LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\""
}
set ELAB_OPTIONS ""
append ELAB_OPTIONS [qsys_top::get_elab_options $SIMULATOR_TOOL_BITNESS]
puts "ELAB_OPTIONS+=\"$ELAB_OPTIONS\""
set SIM_OPTIONS ""
append SIM_OPTIONS [qsys_top::get_sim_options $SIMULATOR_TOOL_BITNESS]
puts "SIM_OPTIONS+=\"$SIM_OPTIONS\""
exit 0
'
cmd_output=$(
tclsh -args "$QSYS_SIMDIR" "$SIMULATOR_TOOL_BITNESS" << SCRIPT
$TCLSCRIPT
SCRIPT
)
eval $cmd_output
#-------------------------------------------
# Decision to skip device compilation,
# based on value of PRECOMP_DEVICE_LIB_FILE.
# if PRECOMP_DEVICE_LIB_FILE is set, SKIP_DEV_COM will become true
if [ ! -z "$PRECOMP_DEVICE_LIB_FILE" ] && [ -e $PRECOMP_DEVICE_LIB_FILE ]; then
echo "Using $PRECOMP_DEVICE_LIB_FILE for device library mapping"
SKIP_DEV_COM=1
else
PRECOMP_DEVICE_LIB_FILE=""
fi
TCLSCRIPT='
set QSYS_SIMDIR [lindex $argv 1]
set libraries [dict create]
source $QSYS_SIMDIR/common/vcsmx_files.tcl
set libraries [dict merge $libraries [qsys_top::get_design_libraries]]
set design_libraries [dict keys $libraries]
foreach file $design_libraries { puts "$file" }
exit 0
'
cmd_output=$(
tclsh -args "$QSYS_SIMDIR" << SCRIPT
$TCLSCRIPT
SCRIPT
)
design_libraries=$cmd_output
# ----------------------------------------
# create compilation libraries
device_libraries='lpm_ver sgate_ver altera_ver altera_mf_ver altera_lnsim_ver tennm_ver tennm_sm_hps_ver tennm_sm4_hssi_ver tennm_revb_hvio_ver tennm_revb_io96_ver lpm sgate altera altera_mf altera_lnsim tennm tennm_sm_hps tennm_sm4_hssi tennm_revb_hvio tennm_revb_io96 '
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
for library in $device_libraries
do
mkdir -p ./libraries/$library
done
fi
for library in $design_libraries
do
mkdir -p ./libraries/$library
done
mkdir -p ./libraries/work
#-------------------------------------------
# write out _device_synopsys_sim.setup including all device libraries
echo "--DONOT MODIFY" > _device_synopsys_sim.setup
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
for library in $device_libraries
do
echo "$library: ./libraries/$library" >> _device_synopsys_sim.setup
done
else
echo "OTHERS=$PRECOMP_DEVICE_LIB_FILE" >> _device_synopsys_sim.setup
fi
#-------------------------------------------
# write out _default_synopsys_sim.setup including all design libraries
echo "-- DO NOT MODIFY " > _default_synopsys_sim.setup
for library in $design_libraries
do
echo "$library: ./libraries/$library" >> _default_synopsys_sim.setup
done
# ----------------------------------------
# copy RAM/ROM files to simulation directory
TCLSCRIPT='
set QSYS_SIMDIR [lindex $argv 1]
set QUARTUS_INSTALL_DIR [lindex $argv 2]
set memory_files [list]
source $QSYS_SIMDIR/common/vcsmx_files.tcl
set memory_files [concat $memory_files [qsys_top::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
foreach file $memory_files { puts "$file" }
exit 0
'
cmd_output=$(
tclsh -args "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
$TCLSCRIPT
SCRIPT
)
memory_files=$cmd_output
if [ $SKIP_FILE_COPY -eq 0 ]; then
for file in $memory_files
do
cp -f $file ./
done
fi
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/synopsys/tennm_atoms_ncrypt.sv" -work tennm_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96_ver
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -work lpm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.vhd" -work lpm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -work sgate
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -work sgate
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -work altera_mf
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -work altera_mf
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -work altera_lnsim
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/synopsys/tennm_atoms_ncrypt.sv" -work tennm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -work tennm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -work tennm
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96
fi
# ----------------------------------------
# add device library elaboration and simulation properties
ELAB_OPTIONS="$ELAB_OPTIONS $QUARTUS_INSTALL_DIR/eda/sim_lib/simsf_dpi.cpp"
# ----------------------------------------
# get common system verilog package design files
TCLSCRIPT='
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
set QSYS_SIMDIR [lindex $argv 4]
set design_files [dict create]
source $QSYS_SIMDIR/common/vcsmx_files.tcl
set design_files [dict merge $design_files [qsys_top::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
set common_design_files [dict values $design_files]
foreach file $common_design_files { puts "$file" }
exit 0
'
cmd_output=$(
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
$TCLSCRIPT
SCRIPT
)
common_design_files=$cmd_output
# ----------------------------------------
# get design files
TCLSCRIPT='
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
set QSYS_SIMDIR [lindex $argv 4]
set QUARTUS_INSTALL_DIR [lindex $argv 5]
set files [list]
source $QSYS_SIMDIR/common/vcsmx_files.tcl
set files [concat $files [qsys_top::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
set design_files $files
foreach file $design_files { puts "$file" }
exit 0
'
cmd_output=$(
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
$TCLSCRIPT
SCRIPT
)
design_files=$cmd_output
# ----------------------------------------
# get DPI libraries
TCLSCRIPT='
set QSYS_SIMDIR [lindex $argv 1]
set libraries [dict create]
source $QSYS_SIMDIR/common/vcsmx_files.tcl
set libraries [dict merge $libraries [qsys_top::get_dpi_libraries "$QSYS_SIMDIR"]]
set dpi_libraries [dict values $libraries]
foreach library $dpi_libraries { puts -nonewline "$library " }
exit 0
'
cmd_output=$(
tclsh -args "$QSYS_SIMDIR" << SCRIPT
$TCLSCRIPT
SCRIPT
)
dpi_libraries=$cmd_output
if [ -n "$dpi_libraries" ]; then
echo "Using DPI Library settings"
LDFLAGS_LOCAL=""
for library in $dpi_libraries; do
library=$(readlink -m $library)
FILENAME=${library##*/}
LDFLAGS_LOCAL+=" -Wl,-rpath ${library%/*} -L ${library%/*} -l${FILENAME:3}"
done
export LDFLAGS="$LDFLAGS_LOCAL $LDFLAGS"
ELAB_OPTIONS="$ELAB_OPTIONS -debug_access+r+w+nomemcbk"
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
eval "$common_design_files"
eval "$design_files"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
vcs -lca -t ps -liblist_work $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $DEFAULT_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi
qsys/qsys_top/sim/xcelium/cds.lib
+27
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@@ -0,0 +1,27 @@
DEFINE std $CDS_ROOT/tools/inca/files/STD/
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
DEFINE work ./libraries/work/
DEFINE altera_merlin_axi_translator_1987 ./libraries/altera_merlin_axi_translator_1987/
DEFINE altera_merlin_slave_translator_191 ./libraries/altera_merlin_slave_translator_191/
DEFINE altera_merlin_axi_master_ni_19117 ./libraries/altera_merlin_axi_master_ni_19117/
DEFINE altera_merlin_slave_agent_1930 ./libraries/altera_merlin_slave_agent_1930/
DEFINE altera_avalon_sc_fifo_1932 ./libraries/altera_avalon_sc_fifo_1932/
DEFINE altera_merlin_router_1921 ./libraries/altera_merlin_router_1921/
DEFINE altera_avalon_st_pipeline_stage_1930 ./libraries/altera_avalon_st_pipeline_stage_1930/
DEFINE altera_merlin_burst_adapter_1940 ./libraries/altera_merlin_burst_adapter_1940/
DEFINE altera_merlin_demultiplexer_1921 ./libraries/altera_merlin_demultiplexer_1921/
DEFINE altera_merlin_multiplexer_1922 ./libraries/altera_merlin_multiplexer_1922/
DEFINE altera_mm_interconnect_1920 ./libraries/altera_mm_interconnect_1920/
DEFINE altera_irq_mapper_2001 ./libraries/altera_irq_mapper_2001/
DEFINE altera_reset_controller_1924 ./libraries/altera_reset_controller_1924/
DEFINE qsys_top ./libraries/qsys_top/
SOFTINCLUDE _device.cds.lib
INCLUDE _default.cds.lib
qsys/qsys_top/sim/xcelium/cds_libs/simulator.cds.lib
+10
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@@ -0,0 +1,10 @@
DEFINE std $CDS_ROOT/tools/inca/files/STD/
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
qsys/qsys_top/sim/xcelium/hdl.var
+2
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@@ -0,0 +1,2 @@
DEFINE WORK work
qsys/qsys_top/sim/xcelium/xcelium_setup.sh
Executable
+440
View File
@@ -0,0 +1,440 @@
# (C) 2001-2026 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Intel
# Program License Subscription Agreement, Intel MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Intel and sold by Intel
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 26.1 110 linux 2026.04.08.10:52:56
# ----------------------------------------
# xcelium - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# qsys_top
#
# Intel recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# Xcelium Simulation Script.
# To write a top-level shell script that compiles Intel simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "xcelium_sim.sh", and modify text as directed.
#
# You can also modify the simulation flow to suit your needs. Set the
# following variables to 1 to disable their corresponding processes:
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator. In this case, you must also copy the generated files
# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
# # into the location from which you launch the simulator, or incorporate
# # into any existing library setup.
# #
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
# # simulation libraries and Quartus-generated IP simulation files, and copy
# # any ROM/RAM initialization files to the simulation directory.
# # - If necessary, specify any compilation options:
# # USER_DEFINED_COMPILE_OPTIONS
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
# #
# source <script generation output directory>/xcelium/xcelium_setup.sh \
# SKIP_ELAB=1 \
# SKIP_SIM=1 \
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
# QSYS_SIMDIR=<script generation output directory>
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the IP script)
# #
# xmvlog <compilation options> <design and testbench files>
# #
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
# # testbench module/entity name.
# #
# # Run the IP script again to elaborate and simulate the top level:
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# #
# source <script generation output directory>/xcelium/xcelium_setup.sh \
# SKIP_FILE_COPY=1 \
# SKIP_DEV_COM=1 \
# SKIP_COM=1 \
# TOP_LEVEL_NAME=<simulation top> \
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
# DEFAULT_ELAB_OPTIONS=<default elaboration options for your design> \
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If qsys_top is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Intel IP
# within the Quartus project, and generate a unified
# script which supports all the Intel IP within the design.
# ----------------------------------------
# ACDS 26.1 110 linux 2026.04.08.10:52:56
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="qsys_top.qsys_top"
QSYS_SIMDIR="./../"
QUARTUS_INSTALL_DIR="/opt/altera_pro/26.1/quartus/"
QUARTUS_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/eda/sim_lib/"
DEVICES_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
DEFAULT_ELAB_OPTIONS=" -access +w+r+c -update -namemap_mixgen +DISABLEGENCHK -relax"
USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
PRECOMP_DEVICE_LIB_FILE=""
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
#-------------------------------------------
# check tclsh version no earlier than 8.5
version=$(echo "puts [package vcompare [info tclversion] 8.5]; exit" | tclsh)
if [ $version -eq -1 ]; then
echo "Error: Minimum required tcl package version is 8.5." >&2
exit 1
fi
#-------------------------------------------
# read .sh file to override initialized variables
if [ -n "${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}" ] && [ -f ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE} ]; then
echo "Sourcing ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}"
source ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}
if [ $? -ne 0 ]; then
echo "Error:: This file ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE} has invalid expression/s" >&2
exit $?
fi
fi
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `xmsim -version` != *"xmsim(64)"* ]]; then
SIMULATOR_TOOL_BITNESS="bit_32"
else
SIMULATOR_TOOL_BITNESS="bit_64"
fi
TCLSCRIPT='
set QSYS_SIMDIR [lindex $argv 1]
set SIMULATOR_TOOL_BITNESS [lindex $argv 2]
source $QSYS_SIMDIR/common/xcelium_files.tcl
set LD_LIBRARY_PATH [dict create]
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [qsys_top::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
if {[dict size $LD_LIBRARY_PATH] !=0 } {
set LD_LIBRARY_PATH [join [dict keys $LD_LIBRARY_PATH] ":"]
puts "LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\""
}
set ELAB_OPTIONS ""
append ELAB_OPTIONS [qsys_top::get_elab_options $SIMULATOR_TOOL_BITNESS]
puts "ELAB_OPTIONS+=\"$ELAB_OPTIONS\""
set SIM_OPTIONS ""
append SIM_OPTIONS [qsys_top::get_sim_options $SIMULATOR_TOOL_BITNESS]
puts "SIM_OPTIONS+=\"$SIM_OPTIONS\""
exit 0
'
cmd_output=$(
tclsh -args "$QSYS_SIMDIR" "$SIMULATOR_TOOL_BITNESS" << SCRIPT
$TCLSCRIPT
SCRIPT
)
eval $cmd_output
#-------------------------------------------
# Decision to skip device compilation,
# based on value of PRECOMP_DEVICE_LIB_FILE.
# if PRECOMP_DEVICE_LIB_FILE is set, SKIP_DEV_COM will become true
if [ ! -z "$PRECOMP_DEVICE_LIB_FILE" ] && [ -e $PRECOMP_DEVICE_LIB_FILE ]; then
echo "Using $PRECOMP_DEVICE_LIB_FILE for device library mapping"
SKIP_DEV_COM=1
else
PRECOMP_DEVICE_LIB_FILE=""
fi
TCLSCRIPT='
set QSYS_SIMDIR [lindex $argv 1]
set libraries [dict create]
source $QSYS_SIMDIR/common/xcelium_files.tcl
set libraries [dict merge $libraries [qsys_top::get_design_libraries]]
set design_libraries [dict keys $libraries]
foreach file $design_libraries { puts "$file" }
exit 0
'
cmd_output=$(
tclsh -args "$QSYS_SIMDIR" << SCRIPT
$TCLSCRIPT
SCRIPT
)
design_libraries=$cmd_output
# ----------------------------------------
# create compilation libraries
device_libraries='lpm_ver sgate_ver altera_ver altera_mf_ver tennm_ver lpm sgate altera altera_mf altera_lnsim tennm tennm_sm_hps tennm_sm4_hssi tennm_revb_hvio tennm_revb_io96 '
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
for library in $device_libraries
do
mkdir -p ./libraries/$library
done
fi
for library in $design_libraries
do
mkdir -p ./libraries/$library
done
mkdir -p ./libraries/work
#-------------------------------------------
# write out _device.cds.lib including all design libraries
echo "# DO NOT MODIFY " > _device.cds.lib
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
for library in $device_libraries
do
echo "DEFINE $library ./libraries/$library" >> _device.cds.lib
done
else
echo "INCLUDE $PRECOMP_DEVICE_LIB_FILE" >> _device.cds.lib
fi
#-------------------------------------------
# write out device.cds.lib including all design libraries
echo "# DO NOT MODIFY " > ./cds_libs/device.cds.lib
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
for library in $device_libraries
do
echo "DEFINE $library ./../libraries/$library" >> ./cds_libs/device.cds.lib
done
else
echo "INCLUDE $PRECOMP_DEVICE_LIB_FILE" >> ./cds_libs/device.cds.lib
fi
#-------------------------------------------
# write out _default.cds.lib including all design libraries
echo "# DO NOT MODIFY " > _default.cds.lib
for library in $design_libraries
do
echo "DEFINE $library ./libraries/$library" >> _default.cds.lib
done
#-------------------------------------------
# create cds_libs for each design library
for library in $design_libraries
do
echo "INCLUDE simulator.cds.lib" > cds_libs/$library.cds.lib
echo "INCLUDE device.cds.lib" >> cds_libs/$library.cds.lib
if [[ $design_libraries =~ "altera_common_sv_packages" ]] && [[ $library != "altera_common_sv_packages" ]]; then
echo "DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/" >> cds_libs/$library.cds.lib
fi
echo "DEFINE $library ./../libraries/$library" >> cds_libs/$library.cds.lib
done
# ----------------------------------------
# copy RAM/ROM files to simulation directory
TCLSCRIPT='
set QSYS_SIMDIR [lindex $argv 1]
set QUARTUS_INSTALL_DIR [lindex $argv 2]
set memory_files [list]
source $QSYS_SIMDIR/common/xcelium_files.tcl
set memory_files [concat $memory_files [qsys_top::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
foreach file $memory_files { puts "$file" }
exit 0
'
cmd_output=$(
tclsh -args "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
$TCLSCRIPT
SCRIPT
)
memory_files=$cmd_output
if [ $SKIP_FILE_COPY -eq 0 ]; then
for file in $memory_files
do
cp -f $file ./
done
fi
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -work lpm
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.vhd" -work lpm
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -work sgate
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -work sgate
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -work altera
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -work altera
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -work altera
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -work altera
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -work altera
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -work altera
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -work altera_mf
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -work altera_mf
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -work altera_lnsim
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/cadence/tennm_atoms_ncrypt.sv" -work tennm
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -work tennm
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -work tennm
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96
fi
gcc -fPIC -g -shared -o libdpi.so -I/`ncroot`/tools/inca/include "$QUARTUS_SIM_LIB_DIR/simsf_dpi.cpp"
# ----------------------------------------
# add device library elaboration and simulation properties
# ----------------------------------------
# get common system verilog package design files
TCLSCRIPT='
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
set QSYS_SIMDIR [lindex $argv 4]
set design_files [dict create]
source $QSYS_SIMDIR/common/xcelium_files.tcl
set design_files [dict merge $design_files [qsys_top::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
set common_design_files [dict values $design_files]
foreach file $common_design_files { puts "$file" }
exit 0
'
cmd_output=$(
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
$TCLSCRIPT
SCRIPT
)
common_design_files=$cmd_output
# ----------------------------------------
# get design files
TCLSCRIPT='
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
set QSYS_SIMDIR [lindex $argv 4]
set QUARTUS_INSTALL_DIR [lindex $argv 5]
set files [list]
source $QSYS_SIMDIR/common/xcelium_files.tcl
set files [concat $files [qsys_top::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
set design_files $files
foreach file $design_files { puts "$file" }
exit 0
'
cmd_output=$(
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
$TCLSCRIPT
SCRIPT
)
design_files=$cmd_output
# ----------------------------------------
# get DPI libraries
TCLSCRIPT='
set QSYS_SIMDIR [lindex $argv 1]
set libraries [dict create]
source $QSYS_SIMDIR/common/xcelium_files.tcl
set libraries [dict merge $libraries [qsys_top::get_dpi_libraries "$QSYS_SIMDIR"]]
set dpi_libraries [dict values $libraries]
foreach library $dpi_libraries { puts -nonewline "$library " }
exit 0
'
cmd_output=$(
tclsh -args "$QSYS_SIMDIR" << SCRIPT
$TCLSCRIPT
SCRIPT
)
dpi_libraries=$cmd_output
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
eval "$common_design_files"
eval "$design_files"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
xmelab $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $DEFAULT_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
if [ -n "$dpi_libraries" ]; then
echo "Using DPI Library settings"
FILES=""
for library in $dpi_libraries; do
FILES+="-sv_lib $library"
done
eval xmsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME $FILES
else
eval xmsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
fi
fi
qsys/qsys_top/synth/qsys_top.v
+542
View File
@@ -0,0 +1,542 @@
// qsys_top.v
// Generated using ACDS version 26.1 110
`timescale 1 ps / 1 ps
module qsys_top (
input wire clk_100_clk, // clk_100.clk
input wire reset_reset_n, // reset.reset_n
output wire ninit_done_ninit_done, // ninit_done.ninit_done
output wire h2f_reset_reset, // h2f_reset.reset
output wire [3:0] subsys_hps_hps2fpga_awid, // subsys_hps_hps2fpga.awid
output wire [37:0] subsys_hps_hps2fpga_awaddr, // .awaddr
output wire [7:0] subsys_hps_hps2fpga_awlen, // .awlen
output wire [2:0] subsys_hps_hps2fpga_awsize, // .awsize
output wire [1:0] subsys_hps_hps2fpga_awburst, // .awburst
output wire subsys_hps_hps2fpga_awlock, // .awlock
output wire [3:0] subsys_hps_hps2fpga_awcache, // .awcache
output wire [2:0] subsys_hps_hps2fpga_awprot, // .awprot
output wire subsys_hps_hps2fpga_awvalid, // .awvalid
input wire subsys_hps_hps2fpga_awready, // .awready
output wire [127:0] subsys_hps_hps2fpga_wdata, // .wdata
output wire [15:0] subsys_hps_hps2fpga_wstrb, // .wstrb
output wire subsys_hps_hps2fpga_wlast, // .wlast
output wire subsys_hps_hps2fpga_wvalid, // .wvalid
input wire subsys_hps_hps2fpga_wready, // .wready
input wire [3:0] subsys_hps_hps2fpga_bid, // .bid
input wire [1:0] subsys_hps_hps2fpga_bresp, // .bresp
input wire subsys_hps_hps2fpga_bvalid, // .bvalid
output wire subsys_hps_hps2fpga_bready, // .bready
output wire [3:0] subsys_hps_hps2fpga_arid, // .arid
output wire [37:0] subsys_hps_hps2fpga_araddr, // .araddr
output wire [7:0] subsys_hps_hps2fpga_arlen, // .arlen
output wire [2:0] subsys_hps_hps2fpga_arsize, // .arsize
output wire [1:0] subsys_hps_hps2fpga_arburst, // .arburst
output wire subsys_hps_hps2fpga_arlock, // .arlock
output wire [3:0] subsys_hps_hps2fpga_arcache, // .arcache
output wire [2:0] subsys_hps_hps2fpga_arprot, // .arprot
output wire subsys_hps_hps2fpga_arvalid, // .arvalid
input wire subsys_hps_hps2fpga_arready, // .arready
input wire [3:0] subsys_hps_hps2fpga_rid, // .rid
input wire [127:0] subsys_hps_hps2fpga_rdata, // .rdata
input wire [1:0] subsys_hps_hps2fpga_rresp, // .rresp
input wire subsys_hps_hps2fpga_rlast, // .rlast
input wire subsys_hps_hps2fpga_rvalid, // .rvalid
output wire subsys_hps_hps2fpga_rready, // .rready
output wire subsys_hps_h2f_warm_reset_handshake_reset_req, // subsys_hps_h2f_warm_reset_handshake.reset_req
input wire subsys_hps_h2f_warm_reset_handshake_reset_ack, // .reset_ack
input wire hps_io_hps_osc_clk, // hps_io.hps_osc_clk
inout wire hps_io_sdmmc_data0, // .sdmmc_data0
inout wire hps_io_sdmmc_data1, // .sdmmc_data1
output wire hps_io_sdmmc_cclk, // .sdmmc_cclk
inout wire hps_io_sdmmc_data2, // .sdmmc_data2
inout wire hps_io_sdmmc_data3, // .sdmmc_data3
inout wire hps_io_sdmmc_cmd, // .sdmmc_cmd
input wire hps_io_usb0_clk, // .usb0_clk
output wire hps_io_usb0_stp, // .usb0_stp
input wire hps_io_usb0_dir, // .usb0_dir
inout wire hps_io_usb0_data0, // .usb0_data0
inout wire hps_io_usb0_data1, // .usb0_data1
input wire hps_io_usb0_nxt, // .usb0_nxt
inout wire hps_io_usb0_data2, // .usb0_data2
inout wire hps_io_usb0_data3, // .usb0_data3
inout wire hps_io_usb0_data4, // .usb0_data4
inout wire hps_io_usb0_data5, // .usb0_data5
inout wire hps_io_usb0_data6, // .usb0_data6
inout wire hps_io_usb0_data7, // .usb0_data7
output wire hps_io_emac0_tx_clk, // .emac0_tx_clk
output wire hps_io_emac0_tx_ctl, // .emac0_tx_ctl
input wire hps_io_emac0_rx_clk, // .emac0_rx_clk
input wire hps_io_emac0_rx_ctl, // .emac0_rx_ctl
output wire hps_io_emac0_txd0, // .emac0_txd0
output wire hps_io_emac0_txd1, // .emac0_txd1
input wire hps_io_emac0_rxd0, // .emac0_rxd0
input wire hps_io_emac0_rxd1, // .emac0_rxd1
output wire hps_io_emac0_txd2, // .emac0_txd2
output wire hps_io_emac0_txd3, // .emac0_txd3
input wire hps_io_emac0_rxd2, // .emac0_rxd2
input wire hps_io_emac0_rxd3, // .emac0_rxd3
inout wire hps_io_mdio0_mdio, // .mdio0_mdio
output wire hps_io_mdio0_mdc, // .mdio0_mdc
output wire hps_io_uart1_tx, // .uart1_tx
input wire hps_io_uart1_rx, // .uart1_rx
inout wire hps_io_i2c1_sda, // .i2c1_sda
inout wire hps_io_i2c1_scl, // .i2c1_scl
inout wire hps_io_gpio28, // .gpio28
inout wire hps_io_gpio34, // .gpio34
inout wire hps_io_gpio40, // .gpio40
inout wire hps_io_gpio41, // .gpio41
input wire [31:0] f2h_irq1_in_irq, // f2h_irq1_in.irq
input wire [31:0] f2sdram_araddr, // f2sdram.araddr
input wire [1:0] f2sdram_arburst, // .arburst
input wire [3:0] f2sdram_arcache, // .arcache
input wire [4:0] f2sdram_arid, // .arid
input wire [7:0] f2sdram_arlen, // .arlen
input wire f2sdram_arlock, // .arlock
input wire [2:0] f2sdram_arprot, // .arprot
input wire [3:0] f2sdram_arqos, // .arqos
output wire f2sdram_arready, // .arready
input wire [2:0] f2sdram_arsize, // .arsize
input wire f2sdram_arvalid, // .arvalid
input wire [31:0] f2sdram_awaddr, // .awaddr
input wire [1:0] f2sdram_awburst, // .awburst
input wire [3:0] f2sdram_awcache, // .awcache
input wire [4:0] f2sdram_awid, // .awid
input wire [7:0] f2sdram_awlen, // .awlen
input wire f2sdram_awlock, // .awlock
input wire [2:0] f2sdram_awprot, // .awprot
input wire [3:0] f2sdram_awqos, // .awqos
output wire f2sdram_awready, // .awready
input wire [2:0] f2sdram_awsize, // .awsize
input wire f2sdram_awvalid, // .awvalid
output wire [4:0] f2sdram_bid, // .bid
input wire f2sdram_bready, // .bready
output wire [1:0] f2sdram_bresp, // .bresp
output wire f2sdram_bvalid, // .bvalid
output wire [255:0] f2sdram_rdata, // .rdata
output wire [4:0] f2sdram_rid, // .rid
output wire f2sdram_rlast, // .rlast
input wire f2sdram_rready, // .rready
output wire [1:0] f2sdram_rresp, // .rresp
output wire f2sdram_rvalid, // .rvalid
input wire [255:0] f2sdram_wdata, // .wdata
input wire f2sdram_wlast, // .wlast
output wire f2sdram_wready, // .wready
input wire [31:0] f2sdram_wstrb, // .wstrb
input wire f2sdram_wvalid, // .wvalid
input wire [7:0] f2sdram_aruser, // .aruser
input wire [7:0] f2sdram_awuser, // .awuser
input wire [7:0] f2sdram_wuser, // .wuser
output wire [7:0] f2sdram_buser, // .buser
input wire [3:0] f2sdram_arregion, // .arregion
output wire [7:0] f2sdram_ruser, // .ruser
input wire [3:0] f2sdram_awregion, // .awregion
output wire [0:0] emif_hps_emif_mem_0_mem_cs, // emif_hps_emif_mem_0.mem_cs
output wire [5:0] emif_hps_emif_mem_0_mem_ca, // .mem_ca
output wire [0:0] emif_hps_emif_mem_0_mem_cke, // .mem_cke
inout wire [31:0] emif_hps_emif_mem_0_mem_dq, // .mem_dq
inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_t, // .mem_dqs_t
inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_c, // .mem_dqs_c
inout wire [3:0] emif_hps_emif_mem_0_mem_dmi, // .mem_dmi
output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_t, // emif_hps_emif_mem_ck_0.mem_ck_t
output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_c, // .mem_ck_c
output wire emif_hps_emif_mem_reset_n_mem_reset_n, // emif_hps_emif_mem_reset_n.mem_reset_n
input wire emif_hps_emif_oct_0_oct_rzqin, // emif_hps_emif_oct_0.oct_rzqin
input wire emif_hps_emif_ref_clk_0_clk, // emif_hps_emif_ref_clk_0.clk
input wire [3:0] button_pio_external_connection_export, // button_pio_external_connection.export
input wire [3:0] dipsw_pio_external_connection_export, // dipsw_pio_external_connection.export
input wire [2:0] led_pio_external_connection_in_port, // led_pio_external_connection.in_port
output wire [2:0] led_pio_external_connection_out_port // .out_port
);
wire clk_100_out_clk_clk; // clk_100:out_clk -> [mm_interconnect_0:clk_100_out_clk_clk, rst_controller:clk, subsys_hps:f2sdram_clk_clk, subsys_hps:hps2fpga_clk_clk, subsys_hps:lwhps2fpga_clk_clk, subsys_periph:clk_clk]
wire rst_in_out_reset_reset; // rst_in:out_reset_n -> [rst_controller:reset_in0, subsys_hps:f2sdram_rst_reset, subsys_hps:hps2fpga_rst_reset, subsys_hps:lwhps2fpga_rst_reset, subsys_periph:reset_reset_n]
wire [1:0] subsys_hps_lwhps2fpga_awburst; // subsys_hps:lwhps2fpga_awburst -> mm_interconnect_0:subsys_hps_lwhps2fpga_awburst
wire [7:0] subsys_hps_lwhps2fpga_arlen; // subsys_hps:lwhps2fpga_arlen -> mm_interconnect_0:subsys_hps_lwhps2fpga_arlen
wire [3:0] subsys_hps_lwhps2fpga_wstrb; // subsys_hps:lwhps2fpga_wstrb -> mm_interconnect_0:subsys_hps_lwhps2fpga_wstrb
wire subsys_hps_lwhps2fpga_wready; // mm_interconnect_0:subsys_hps_lwhps2fpga_wready -> subsys_hps:lwhps2fpga_wready
wire [3:0] subsys_hps_lwhps2fpga_rid; // mm_interconnect_0:subsys_hps_lwhps2fpga_rid -> subsys_hps:lwhps2fpga_rid
wire subsys_hps_lwhps2fpga_rready; // subsys_hps:lwhps2fpga_rready -> mm_interconnect_0:subsys_hps_lwhps2fpga_rready
wire [7:0] subsys_hps_lwhps2fpga_awlen; // subsys_hps:lwhps2fpga_awlen -> mm_interconnect_0:subsys_hps_lwhps2fpga_awlen
wire [3:0] subsys_hps_lwhps2fpga_arcache; // subsys_hps:lwhps2fpga_arcache -> mm_interconnect_0:subsys_hps_lwhps2fpga_arcache
wire subsys_hps_lwhps2fpga_wvalid; // subsys_hps:lwhps2fpga_wvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_wvalid
wire [28:0] subsys_hps_lwhps2fpga_araddr; // subsys_hps:lwhps2fpga_araddr -> mm_interconnect_0:subsys_hps_lwhps2fpga_araddr
wire [2:0] subsys_hps_lwhps2fpga_arprot; // subsys_hps:lwhps2fpga_arprot -> mm_interconnect_0:subsys_hps_lwhps2fpga_arprot
wire [2:0] subsys_hps_lwhps2fpga_awprot; // subsys_hps:lwhps2fpga_awprot -> mm_interconnect_0:subsys_hps_lwhps2fpga_awprot
wire [31:0] subsys_hps_lwhps2fpga_wdata; // subsys_hps:lwhps2fpga_wdata -> mm_interconnect_0:subsys_hps_lwhps2fpga_wdata
wire subsys_hps_lwhps2fpga_arvalid; // subsys_hps:lwhps2fpga_arvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_arvalid
wire [3:0] subsys_hps_lwhps2fpga_awcache; // subsys_hps:lwhps2fpga_awcache -> mm_interconnect_0:subsys_hps_lwhps2fpga_awcache
wire [3:0] subsys_hps_lwhps2fpga_arid; // subsys_hps:lwhps2fpga_arid -> mm_interconnect_0:subsys_hps_lwhps2fpga_arid
wire subsys_hps_lwhps2fpga_arlock; // subsys_hps:lwhps2fpga_arlock -> mm_interconnect_0:subsys_hps_lwhps2fpga_arlock
wire subsys_hps_lwhps2fpga_awlock; // subsys_hps:lwhps2fpga_awlock -> mm_interconnect_0:subsys_hps_lwhps2fpga_awlock
wire [28:0] subsys_hps_lwhps2fpga_awaddr; // subsys_hps:lwhps2fpga_awaddr -> mm_interconnect_0:subsys_hps_lwhps2fpga_awaddr
wire [1:0] subsys_hps_lwhps2fpga_bresp; // mm_interconnect_0:subsys_hps_lwhps2fpga_bresp -> subsys_hps:lwhps2fpga_bresp
wire subsys_hps_lwhps2fpga_arready; // mm_interconnect_0:subsys_hps_lwhps2fpga_arready -> subsys_hps:lwhps2fpga_arready
wire [31:0] subsys_hps_lwhps2fpga_rdata; // mm_interconnect_0:subsys_hps_lwhps2fpga_rdata -> subsys_hps:lwhps2fpga_rdata
wire subsys_hps_lwhps2fpga_awready; // mm_interconnect_0:subsys_hps_lwhps2fpga_awready -> subsys_hps:lwhps2fpga_awready
wire [1:0] subsys_hps_lwhps2fpga_arburst; // subsys_hps:lwhps2fpga_arburst -> mm_interconnect_0:subsys_hps_lwhps2fpga_arburst
wire [2:0] subsys_hps_lwhps2fpga_arsize; // subsys_hps:lwhps2fpga_arsize -> mm_interconnect_0:subsys_hps_lwhps2fpga_arsize
wire subsys_hps_lwhps2fpga_bready; // subsys_hps:lwhps2fpga_bready -> mm_interconnect_0:subsys_hps_lwhps2fpga_bready
wire subsys_hps_lwhps2fpga_rlast; // mm_interconnect_0:subsys_hps_lwhps2fpga_rlast -> subsys_hps:lwhps2fpga_rlast
wire subsys_hps_lwhps2fpga_wlast; // subsys_hps:lwhps2fpga_wlast -> mm_interconnect_0:subsys_hps_lwhps2fpga_wlast
wire [1:0] subsys_hps_lwhps2fpga_rresp; // mm_interconnect_0:subsys_hps_lwhps2fpga_rresp -> subsys_hps:lwhps2fpga_rresp
wire [3:0] subsys_hps_lwhps2fpga_awid; // subsys_hps:lwhps2fpga_awid -> mm_interconnect_0:subsys_hps_lwhps2fpga_awid
wire [3:0] subsys_hps_lwhps2fpga_bid; // mm_interconnect_0:subsys_hps_lwhps2fpga_bid -> subsys_hps:lwhps2fpga_bid
wire subsys_hps_lwhps2fpga_bvalid; // mm_interconnect_0:subsys_hps_lwhps2fpga_bvalid -> subsys_hps:lwhps2fpga_bvalid
wire [2:0] subsys_hps_lwhps2fpga_awsize; // subsys_hps:lwhps2fpga_awsize -> mm_interconnect_0:subsys_hps_lwhps2fpga_awsize
wire subsys_hps_lwhps2fpga_awvalid; // subsys_hps:lwhps2fpga_awvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_awvalid
wire subsys_hps_lwhps2fpga_rvalid; // mm_interconnect_0:subsys_hps_lwhps2fpga_rvalid -> subsys_hps:lwhps2fpga_rvalid
wire [31:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata; // subsys_periph:pb_cpu_0_s0_readdata -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_readdata
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest; // subsys_periph:pb_cpu_0_s0_waitrequest -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_waitrequest
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_debugaccess -> subsys_periph:pb_cpu_0_s0_debugaccess
wire [16:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_address -> subsys_periph:pb_cpu_0_s0_address
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_read -> subsys_periph:pb_cpu_0_s0_read
wire [3:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_byteenable -> subsys_periph:pb_cpu_0_s0_byteenable
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid; // subsys_periph:pb_cpu_0_s0_readdatavalid -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_readdatavalid
wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_write -> subsys_periph:pb_cpu_0_s0_write
wire [31:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_writedata -> subsys_periph:pb_cpu_0_s0_writedata
wire [0:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_burstcount -> subsys_periph:pb_cpu_0_s0_burstcount
wire irq_mapper_receiver0_irq; // subsys_periph:button_pio_irq_irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // subsys_periph:dipsw_pio_irq_irq -> irq_mapper:receiver1_irq
wire [31:0] subsys_hps_f2h_irq0_in_irq; // irq_mapper:sender_irq -> subsys_hps:f2h_irq0_in_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_0:subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset]
clk_100 clk_100 (
.in_clk (clk_100_clk), // input, width = 1, in_clk.clk
.out_clk (clk_100_out_clk_clk) // output, width = 1, out_clk.clk
);
rst_in rst_in (
.in_reset_n (reset_reset_n), // input, width = 1, in_reset.reset_n
.out_reset_n (rst_in_out_reset_reset) // output, width = 1, out_reset.reset_n
);
user_rst_clkgate_0 user_rst_clkgate_0 (
.ninit_done (ninit_done_ninit_done) // output, width = 1, ninit_done.ninit_done
);
hps_subsys subsys_hps (
.h2f_reset_reset (h2f_reset_reset), // output, width = 1, h2f_reset.reset
.hps2fpga_clk_clk (clk_100_out_clk_clk), // input, width = 1, hps2fpga_clk.clk
.hps2fpga_rst_reset (~rst_in_out_reset_reset), // input, width = 1, hps2fpga_rst.reset
.hps2fpga_awid (subsys_hps_hps2fpga_awid), // output, width = 4, hps2fpga.awid
.hps2fpga_awaddr (subsys_hps_hps2fpga_awaddr), // output, width = 38, .awaddr
.hps2fpga_awlen (subsys_hps_hps2fpga_awlen), // output, width = 8, .awlen
.hps2fpga_awsize (subsys_hps_hps2fpga_awsize), // output, width = 3, .awsize
.hps2fpga_awburst (subsys_hps_hps2fpga_awburst), // output, width = 2, .awburst
.hps2fpga_awlock (subsys_hps_hps2fpga_awlock), // output, width = 1, .awlock
.hps2fpga_awcache (subsys_hps_hps2fpga_awcache), // output, width = 4, .awcache
.hps2fpga_awprot (subsys_hps_hps2fpga_awprot), // output, width = 3, .awprot
.hps2fpga_awvalid (subsys_hps_hps2fpga_awvalid), // output, width = 1, .awvalid
.hps2fpga_awready (subsys_hps_hps2fpga_awready), // input, width = 1, .awready
.hps2fpga_wdata (subsys_hps_hps2fpga_wdata), // output, width = 128, .wdata
.hps2fpga_wstrb (subsys_hps_hps2fpga_wstrb), // output, width = 16, .wstrb
.hps2fpga_wlast (subsys_hps_hps2fpga_wlast), // output, width = 1, .wlast
.hps2fpga_wvalid (subsys_hps_hps2fpga_wvalid), // output, width = 1, .wvalid
.hps2fpga_wready (subsys_hps_hps2fpga_wready), // input, width = 1, .wready
.hps2fpga_bid (subsys_hps_hps2fpga_bid), // input, width = 4, .bid
.hps2fpga_bresp (subsys_hps_hps2fpga_bresp), // input, width = 2, .bresp
.hps2fpga_bvalid (subsys_hps_hps2fpga_bvalid), // input, width = 1, .bvalid
.hps2fpga_bready (subsys_hps_hps2fpga_bready), // output, width = 1, .bready
.hps2fpga_arid (subsys_hps_hps2fpga_arid), // output, width = 4, .arid
.hps2fpga_araddr (subsys_hps_hps2fpga_araddr), // output, width = 38, .araddr
.hps2fpga_arlen (subsys_hps_hps2fpga_arlen), // output, width = 8, .arlen
.hps2fpga_arsize (subsys_hps_hps2fpga_arsize), // output, width = 3, .arsize
.hps2fpga_arburst (subsys_hps_hps2fpga_arburst), // output, width = 2, .arburst
.hps2fpga_arlock (subsys_hps_hps2fpga_arlock), // output, width = 1, .arlock
.hps2fpga_arcache (subsys_hps_hps2fpga_arcache), // output, width = 4, .arcache
.hps2fpga_arprot (subsys_hps_hps2fpga_arprot), // output, width = 3, .arprot
.hps2fpga_arvalid (subsys_hps_hps2fpga_arvalid), // output, width = 1, .arvalid
.hps2fpga_arready (subsys_hps_hps2fpga_arready), // input, width = 1, .arready
.hps2fpga_rid (subsys_hps_hps2fpga_rid), // input, width = 4, .rid
.hps2fpga_rdata (subsys_hps_hps2fpga_rdata), // input, width = 128, .rdata
.hps2fpga_rresp (subsys_hps_hps2fpga_rresp), // input, width = 2, .rresp
.hps2fpga_rlast (subsys_hps_hps2fpga_rlast), // input, width = 1, .rlast
.hps2fpga_rvalid (subsys_hps_hps2fpga_rvalid), // input, width = 1, .rvalid
.hps2fpga_rready (subsys_hps_hps2fpga_rready), // output, width = 1, .rready
.lwhps2fpga_clk_clk (clk_100_out_clk_clk), // input, width = 1, lwhps2fpga_clk.clk
.lwhps2fpga_rst_reset (~rst_in_out_reset_reset), // input, width = 1, lwhps2fpga_rst.reset
.lwhps2fpga_awid (subsys_hps_lwhps2fpga_awid), // output, width = 4, lwhps2fpga.awid
.lwhps2fpga_awaddr (subsys_hps_lwhps2fpga_awaddr), // output, width = 29, .awaddr
.lwhps2fpga_awlen (subsys_hps_lwhps2fpga_awlen), // output, width = 8, .awlen
.lwhps2fpga_awsize (subsys_hps_lwhps2fpga_awsize), // output, width = 3, .awsize
.lwhps2fpga_awburst (subsys_hps_lwhps2fpga_awburst), // output, width = 2, .awburst
.lwhps2fpga_awlock (subsys_hps_lwhps2fpga_awlock), // output, width = 1, .awlock
.lwhps2fpga_awcache (subsys_hps_lwhps2fpga_awcache), // output, width = 4, .awcache
.lwhps2fpga_awprot (subsys_hps_lwhps2fpga_awprot), // output, width = 3, .awprot
.lwhps2fpga_awvalid (subsys_hps_lwhps2fpga_awvalid), // output, width = 1, .awvalid
.lwhps2fpga_awready (subsys_hps_lwhps2fpga_awready), // input, width = 1, .awready
.lwhps2fpga_wdata (subsys_hps_lwhps2fpga_wdata), // output, width = 32, .wdata
.lwhps2fpga_wstrb (subsys_hps_lwhps2fpga_wstrb), // output, width = 4, .wstrb
.lwhps2fpga_wlast (subsys_hps_lwhps2fpga_wlast), // output, width = 1, .wlast
.lwhps2fpga_wvalid (subsys_hps_lwhps2fpga_wvalid), // output, width = 1, .wvalid
.lwhps2fpga_wready (subsys_hps_lwhps2fpga_wready), // input, width = 1, .wready
.lwhps2fpga_bid (subsys_hps_lwhps2fpga_bid), // input, width = 4, .bid
.lwhps2fpga_bresp (subsys_hps_lwhps2fpga_bresp), // input, width = 2, .bresp
.lwhps2fpga_bvalid (subsys_hps_lwhps2fpga_bvalid), // input, width = 1, .bvalid
.lwhps2fpga_bready (subsys_hps_lwhps2fpga_bready), // output, width = 1, .bready
.lwhps2fpga_arid (subsys_hps_lwhps2fpga_arid), // output, width = 4, .arid
.lwhps2fpga_araddr (subsys_hps_lwhps2fpga_araddr), // output, width = 29, .araddr
.lwhps2fpga_arlen (subsys_hps_lwhps2fpga_arlen), // output, width = 8, .arlen
.lwhps2fpga_arsize (subsys_hps_lwhps2fpga_arsize), // output, width = 3, .arsize
.lwhps2fpga_arburst (subsys_hps_lwhps2fpga_arburst), // output, width = 2, .arburst
.lwhps2fpga_arlock (subsys_hps_lwhps2fpga_arlock), // output, width = 1, .arlock
.lwhps2fpga_arcache (subsys_hps_lwhps2fpga_arcache), // output, width = 4, .arcache
.lwhps2fpga_arprot (subsys_hps_lwhps2fpga_arprot), // output, width = 3, .arprot
.lwhps2fpga_arvalid (subsys_hps_lwhps2fpga_arvalid), // output, width = 1, .arvalid
.lwhps2fpga_arready (subsys_hps_lwhps2fpga_arready), // input, width = 1, .arready
.lwhps2fpga_rid (subsys_hps_lwhps2fpga_rid), // input, width = 4, .rid
.lwhps2fpga_rdata (subsys_hps_lwhps2fpga_rdata), // input, width = 32, .rdata
.lwhps2fpga_rresp (subsys_hps_lwhps2fpga_rresp), // input, width = 2, .rresp
.lwhps2fpga_rlast (subsys_hps_lwhps2fpga_rlast), // input, width = 1, .rlast
.lwhps2fpga_rvalid (subsys_hps_lwhps2fpga_rvalid), // input, width = 1, .rvalid
.lwhps2fpga_rready (subsys_hps_lwhps2fpga_rready), // output, width = 1, .rready
.h2f_warm_reset_handshake_reset_req (subsys_hps_h2f_warm_reset_handshake_reset_req), // output, width = 1, h2f_warm_reset_handshake.reset_req
.h2f_warm_reset_handshake_reset_ack (subsys_hps_h2f_warm_reset_handshake_reset_ack), // input, width = 1, .reset_ack
.hps_io_hps_osc_clk (hps_io_hps_osc_clk), // input, width = 1, hps_io.hps_osc_clk
.hps_io_sdmmc_data0 (hps_io_sdmmc_data0), // inout, width = 1, .sdmmc_data0
.hps_io_sdmmc_data1 (hps_io_sdmmc_data1), // inout, width = 1, .sdmmc_data1
.hps_io_sdmmc_cclk (hps_io_sdmmc_cclk), // output, width = 1, .sdmmc_cclk
.hps_io_sdmmc_data2 (hps_io_sdmmc_data2), // inout, width = 1, .sdmmc_data2
.hps_io_sdmmc_data3 (hps_io_sdmmc_data3), // inout, width = 1, .sdmmc_data3
.hps_io_sdmmc_cmd (hps_io_sdmmc_cmd), // inout, width = 1, .sdmmc_cmd
.hps_io_usb0_clk (hps_io_usb0_clk), // input, width = 1, .usb0_clk
.hps_io_usb0_stp (hps_io_usb0_stp), // output, width = 1, .usb0_stp
.hps_io_usb0_dir (hps_io_usb0_dir), // input, width = 1, .usb0_dir
.hps_io_usb0_data0 (hps_io_usb0_data0), // inout, width = 1, .usb0_data0
.hps_io_usb0_data1 (hps_io_usb0_data1), // inout, width = 1, .usb0_data1
.hps_io_usb0_nxt (hps_io_usb0_nxt), // input, width = 1, .usb0_nxt
.hps_io_usb0_data2 (hps_io_usb0_data2), // inout, width = 1, .usb0_data2
.hps_io_usb0_data3 (hps_io_usb0_data3), // inout, width = 1, .usb0_data3
.hps_io_usb0_data4 (hps_io_usb0_data4), // inout, width = 1, .usb0_data4
.hps_io_usb0_data5 (hps_io_usb0_data5), // inout, width = 1, .usb0_data5
.hps_io_usb0_data6 (hps_io_usb0_data6), // inout, width = 1, .usb0_data6
.hps_io_usb0_data7 (hps_io_usb0_data7), // inout, width = 1, .usb0_data7
.hps_io_emac0_tx_clk (hps_io_emac0_tx_clk), // output, width = 1, .emac0_tx_clk
.hps_io_emac0_tx_ctl (hps_io_emac0_tx_ctl), // output, width = 1, .emac0_tx_ctl
.hps_io_emac0_rx_clk (hps_io_emac0_rx_clk), // input, width = 1, .emac0_rx_clk
.hps_io_emac0_rx_ctl (hps_io_emac0_rx_ctl), // input, width = 1, .emac0_rx_ctl
.hps_io_emac0_txd0 (hps_io_emac0_txd0), // output, width = 1, .emac0_txd0
.hps_io_emac0_txd1 (hps_io_emac0_txd1), // output, width = 1, .emac0_txd1
.hps_io_emac0_rxd0 (hps_io_emac0_rxd0), // input, width = 1, .emac0_rxd0
.hps_io_emac0_rxd1 (hps_io_emac0_rxd1), // input, width = 1, .emac0_rxd1
.hps_io_emac0_txd2 (hps_io_emac0_txd2), // output, width = 1, .emac0_txd2
.hps_io_emac0_txd3 (hps_io_emac0_txd3), // output, width = 1, .emac0_txd3
.hps_io_emac0_rxd2 (hps_io_emac0_rxd2), // input, width = 1, .emac0_rxd2
.hps_io_emac0_rxd3 (hps_io_emac0_rxd3), // input, width = 1, .emac0_rxd3
.hps_io_mdio0_mdio (hps_io_mdio0_mdio), // inout, width = 1, .mdio0_mdio
.hps_io_mdio0_mdc (hps_io_mdio0_mdc), // output, width = 1, .mdio0_mdc
.hps_io_uart1_tx (hps_io_uart1_tx), // output, width = 1, .uart1_tx
.hps_io_uart1_rx (hps_io_uart1_rx), // input, width = 1, .uart1_rx
.hps_io_i2c1_sda (hps_io_i2c1_sda), // inout, width = 1, .i2c1_sda
.hps_io_i2c1_scl (hps_io_i2c1_scl), // inout, width = 1, .i2c1_scl
.hps_io_gpio28 (hps_io_gpio28), // inout, width = 1, .gpio28
.hps_io_gpio34 (hps_io_gpio34), // inout, width = 1, .gpio34
.hps_io_gpio40 (hps_io_gpio40), // inout, width = 1, .gpio40
.hps_io_gpio41 (hps_io_gpio41), // inout, width = 1, .gpio41
.f2h_irq1_in_irq (f2h_irq1_in_irq), // input, width = 32, f2h_irq1_in.irq
.f2h_irq0_in_irq (subsys_hps_f2h_irq0_in_irq), // input, width = 32, f2h_irq0_in.irq
.f2sdram_clk_clk (clk_100_out_clk_clk), // input, width = 1, f2sdram_clk.clk
.f2sdram_rst_reset (~rst_in_out_reset_reset), // input, width = 1, f2sdram_rst.reset
.f2sdram_araddr (f2sdram_araddr), // input, width = 32, f2sdram.araddr
.f2sdram_arburst (f2sdram_arburst), // input, width = 2, .arburst
.f2sdram_arcache (f2sdram_arcache), // input, width = 4, .arcache
.f2sdram_arid (f2sdram_arid), // input, width = 5, .arid
.f2sdram_arlen (f2sdram_arlen), // input, width = 8, .arlen
.f2sdram_arlock (f2sdram_arlock), // input, width = 1, .arlock
.f2sdram_arprot (f2sdram_arprot), // input, width = 3, .arprot
.f2sdram_arqos (f2sdram_arqos), // input, width = 4, .arqos
.f2sdram_arready (f2sdram_arready), // output, width = 1, .arready
.f2sdram_arsize (f2sdram_arsize), // input, width = 3, .arsize
.f2sdram_arvalid (f2sdram_arvalid), // input, width = 1, .arvalid
.f2sdram_awaddr (f2sdram_awaddr), // input, width = 32, .awaddr
.f2sdram_awburst (f2sdram_awburst), // input, width = 2, .awburst
.f2sdram_awcache (f2sdram_awcache), // input, width = 4, .awcache
.f2sdram_awid (f2sdram_awid), // input, width = 5, .awid
.f2sdram_awlen (f2sdram_awlen), // input, width = 8, .awlen
.f2sdram_awlock (f2sdram_awlock), // input, width = 1, .awlock
.f2sdram_awprot (f2sdram_awprot), // input, width = 3, .awprot
.f2sdram_awqos (f2sdram_awqos), // input, width = 4, .awqos
.f2sdram_awready (f2sdram_awready), // output, width = 1, .awready
.f2sdram_awsize (f2sdram_awsize), // input, width = 3, .awsize
.f2sdram_awvalid (f2sdram_awvalid), // input, width = 1, .awvalid
.f2sdram_bid (f2sdram_bid), // output, width = 5, .bid
.f2sdram_bready (f2sdram_bready), // input, width = 1, .bready
.f2sdram_bresp (f2sdram_bresp), // output, width = 2, .bresp
.f2sdram_bvalid (f2sdram_bvalid), // output, width = 1, .bvalid
.f2sdram_rdata (f2sdram_rdata), // output, width = 256, .rdata
.f2sdram_rid (f2sdram_rid), // output, width = 5, .rid
.f2sdram_rlast (f2sdram_rlast), // output, width = 1, .rlast
.f2sdram_rready (f2sdram_rready), // input, width = 1, .rready
.f2sdram_rresp (f2sdram_rresp), // output, width = 2, .rresp
.f2sdram_rvalid (f2sdram_rvalid), // output, width = 1, .rvalid
.f2sdram_wdata (f2sdram_wdata), // input, width = 256, .wdata
.f2sdram_wlast (f2sdram_wlast), // input, width = 1, .wlast
.f2sdram_wready (f2sdram_wready), // output, width = 1, .wready
.f2sdram_wstrb (f2sdram_wstrb), // input, width = 32, .wstrb
.f2sdram_wvalid (f2sdram_wvalid), // input, width = 1, .wvalid
.f2sdram_aruser (f2sdram_aruser), // input, width = 8, .aruser
.f2sdram_awuser (f2sdram_awuser), // input, width = 8, .awuser
.f2sdram_wuser (f2sdram_wuser), // input, width = 8, .wuser
.f2sdram_buser (f2sdram_buser), // output, width = 8, .buser
.f2sdram_arregion (f2sdram_arregion), // input, width = 4, .arregion
.f2sdram_ruser (f2sdram_ruser), // output, width = 8, .ruser
.f2sdram_awregion (f2sdram_awregion), // input, width = 4, .awregion
.emif_hps_emif_mem_0_mem_cs (emif_hps_emif_mem_0_mem_cs), // output, width = 1, emif_hps_emif_mem_0.mem_cs
.emif_hps_emif_mem_0_mem_ca (emif_hps_emif_mem_0_mem_ca), // output, width = 6, .mem_ca
.emif_hps_emif_mem_0_mem_cke (emif_hps_emif_mem_0_mem_cke), // output, width = 1, .mem_cke
.emif_hps_emif_mem_0_mem_dq (emif_hps_emif_mem_0_mem_dq), // inout, width = 32, .mem_dq
.emif_hps_emif_mem_0_mem_dqs_t (emif_hps_emif_mem_0_mem_dqs_t), // inout, width = 4, .mem_dqs_t
.emif_hps_emif_mem_0_mem_dqs_c (emif_hps_emif_mem_0_mem_dqs_c), // inout, width = 4, .mem_dqs_c
.emif_hps_emif_mem_0_mem_dmi (emif_hps_emif_mem_0_mem_dmi), // inout, width = 4, .mem_dmi
.emif_hps_emif_mem_ck_0_mem_ck_t (emif_hps_emif_mem_ck_0_mem_ck_t), // output, width = 1, emif_hps_emif_mem_ck_0.mem_ck_t
.emif_hps_emif_mem_ck_0_mem_ck_c (emif_hps_emif_mem_ck_0_mem_ck_c), // output, width = 1, .mem_ck_c
.emif_hps_emif_mem_reset_n_mem_reset_n (emif_hps_emif_mem_reset_n_mem_reset_n), // output, width = 1, emif_hps_emif_mem_reset_n.mem_reset_n
.emif_hps_emif_oct_0_oct_rzqin (emif_hps_emif_oct_0_oct_rzqin), // input, width = 1, emif_hps_emif_oct_0.oct_rzqin
.emif_hps_emif_ref_clk_clk (emif_hps_emif_ref_clk_0_clk) // input, width = 1, emif_hps_emif_ref_clk.clk
);
peripheral_subsys subsys_periph (
.button_pio_external_connection_export (button_pio_external_connection_export), // input, width = 4, button_pio_external_connection.export
.button_pio_irq_irq (irq_mapper_receiver0_irq), // output, width = 1, button_pio_irq.irq
.dipsw_pio_external_connection_export (dipsw_pio_external_connection_export), // input, width = 4, dipsw_pio_external_connection.export
.dipsw_pio_irq_irq (irq_mapper_receiver1_irq), // output, width = 1, dipsw_pio_irq.irq
.led_pio_external_connection_in_port (led_pio_external_connection_in_port), // input, width = 3, led_pio_external_connection.in_port
.led_pio_external_connection_out_port (led_pio_external_connection_out_port), // output, width = 3, .out_port
.pb_cpu_0_s0_waitrequest (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest), // output, width = 1, pb_cpu_0_s0.waitrequest
.pb_cpu_0_s0_readdata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata), // output, width = 32, .readdata
.pb_cpu_0_s0_readdatavalid (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid), // output, width = 1, .readdatavalid
.pb_cpu_0_s0_burstcount (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount), // input, width = 1, .burstcount
.pb_cpu_0_s0_writedata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata), // input, width = 32, .writedata
.pb_cpu_0_s0_address (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address), // input, width = 17, .address
.pb_cpu_0_s0_write (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write), // input, width = 1, .write
.pb_cpu_0_s0_read (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read), // input, width = 1, .read
.pb_cpu_0_s0_byteenable (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable), // input, width = 4, .byteenable
.pb_cpu_0_s0_debugaccess (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess), // input, width = 1, .debugaccess
.clk_clk (clk_100_out_clk_clk), // input, width = 1, clk.clk
.reset_reset_n (rst_in_out_reset_reset) // input, width = 1, reset.reset_n
);
qsys_top_altera_mm_interconnect_1920_ykfyxdi mm_interconnect_0 (
.subsys_hps_lwhps2fpga_awid (subsys_hps_lwhps2fpga_awid), // input, width = 4, subsys_hps_lwhps2fpga.awid
.subsys_hps_lwhps2fpga_awaddr (subsys_hps_lwhps2fpga_awaddr), // input, width = 29, .awaddr
.subsys_hps_lwhps2fpga_awlen (subsys_hps_lwhps2fpga_awlen), // input, width = 8, .awlen
.subsys_hps_lwhps2fpga_awsize (subsys_hps_lwhps2fpga_awsize), // input, width = 3, .awsize
.subsys_hps_lwhps2fpga_awburst (subsys_hps_lwhps2fpga_awburst), // input, width = 2, .awburst
.subsys_hps_lwhps2fpga_awlock (subsys_hps_lwhps2fpga_awlock), // input, width = 1, .awlock
.subsys_hps_lwhps2fpga_awcache (subsys_hps_lwhps2fpga_awcache), // input, width = 4, .awcache
.subsys_hps_lwhps2fpga_awprot (subsys_hps_lwhps2fpga_awprot), // input, width = 3, .awprot
.subsys_hps_lwhps2fpga_awvalid (subsys_hps_lwhps2fpga_awvalid), // input, width = 1, .awvalid
.subsys_hps_lwhps2fpga_awready (subsys_hps_lwhps2fpga_awready), // output, width = 1, .awready
.subsys_hps_lwhps2fpga_wdata (subsys_hps_lwhps2fpga_wdata), // input, width = 32, .wdata
.subsys_hps_lwhps2fpga_wstrb (subsys_hps_lwhps2fpga_wstrb), // input, width = 4, .wstrb
.subsys_hps_lwhps2fpga_wlast (subsys_hps_lwhps2fpga_wlast), // input, width = 1, .wlast
.subsys_hps_lwhps2fpga_wvalid (subsys_hps_lwhps2fpga_wvalid), // input, width = 1, .wvalid
.subsys_hps_lwhps2fpga_wready (subsys_hps_lwhps2fpga_wready), // output, width = 1, .wready
.subsys_hps_lwhps2fpga_bid (subsys_hps_lwhps2fpga_bid), // output, width = 4, .bid
.subsys_hps_lwhps2fpga_bresp (subsys_hps_lwhps2fpga_bresp), // output, width = 2, .bresp
.subsys_hps_lwhps2fpga_bvalid (subsys_hps_lwhps2fpga_bvalid), // output, width = 1, .bvalid
.subsys_hps_lwhps2fpga_bready (subsys_hps_lwhps2fpga_bready), // input, width = 1, .bready
.subsys_hps_lwhps2fpga_arid (subsys_hps_lwhps2fpga_arid), // input, width = 4, .arid
.subsys_hps_lwhps2fpga_araddr (subsys_hps_lwhps2fpga_araddr), // input, width = 29, .araddr
.subsys_hps_lwhps2fpga_arlen (subsys_hps_lwhps2fpga_arlen), // input, width = 8, .arlen
.subsys_hps_lwhps2fpga_arsize (subsys_hps_lwhps2fpga_arsize), // input, width = 3, .arsize
.subsys_hps_lwhps2fpga_arburst (subsys_hps_lwhps2fpga_arburst), // input, width = 2, .arburst
.subsys_hps_lwhps2fpga_arlock (subsys_hps_lwhps2fpga_arlock), // input, width = 1, .arlock
.subsys_hps_lwhps2fpga_arcache (subsys_hps_lwhps2fpga_arcache), // input, width = 4, .arcache
.subsys_hps_lwhps2fpga_arprot (subsys_hps_lwhps2fpga_arprot), // input, width = 3, .arprot
.subsys_hps_lwhps2fpga_arvalid (subsys_hps_lwhps2fpga_arvalid), // input, width = 1, .arvalid
.subsys_hps_lwhps2fpga_arready (subsys_hps_lwhps2fpga_arready), // output, width = 1, .arready
.subsys_hps_lwhps2fpga_rid (subsys_hps_lwhps2fpga_rid), // output, width = 4, .rid
.subsys_hps_lwhps2fpga_rdata (subsys_hps_lwhps2fpga_rdata), // output, width = 32, .rdata
.subsys_hps_lwhps2fpga_rresp (subsys_hps_lwhps2fpga_rresp), // output, width = 2, .rresp
.subsys_hps_lwhps2fpga_rlast (subsys_hps_lwhps2fpga_rlast), // output, width = 1, .rlast
.subsys_hps_lwhps2fpga_rvalid (subsys_hps_lwhps2fpga_rvalid), // output, width = 1, .rvalid
.subsys_hps_lwhps2fpga_rready (subsys_hps_lwhps2fpga_rready), // input, width = 1, .rready
.subsys_periph_pb_cpu_0_s0_address (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address), // output, width = 17, subsys_periph_pb_cpu_0_s0.address
.subsys_periph_pb_cpu_0_s0_write (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write), // output, width = 1, .write
.subsys_periph_pb_cpu_0_s0_read (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read), // output, width = 1, .read
.subsys_periph_pb_cpu_0_s0_readdata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata), // input, width = 32, .readdata
.subsys_periph_pb_cpu_0_s0_writedata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata), // output, width = 32, .writedata
.subsys_periph_pb_cpu_0_s0_burstcount (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount), // output, width = 1, .burstcount
.subsys_periph_pb_cpu_0_s0_byteenable (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable), // output, width = 4, .byteenable
.subsys_periph_pb_cpu_0_s0_readdatavalid (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid), // input, width = 1, .readdatavalid
.subsys_periph_pb_cpu_0_s0_waitrequest (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest), // input, width = 1, .waitrequest
.subsys_periph_pb_cpu_0_s0_debugaccess (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess), // output, width = 1, .debugaccess
.subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // input, width = 1, subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset.reset
.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // input, width = 1, subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset.reset
.clk_100_out_clk_clk (clk_100_out_clk_clk) // input, width = 1, clk_100_out_clk.clk
);
qsys_top_altera_irq_mapper_2001_lp4cnei irq_mapper (
.clk (), // input, width = 1, clk.clk
.reset (), // input, width = 1, clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // input, width = 1, receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // input, width = 1, receiver1.irq
.sender_irq (subsys_hps_f2h_irq0_in_irq) // output, width = 32, sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("both"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~rst_in_out_reset_reset), // input, width = 1, reset_in0.reset
.clk (clk_100_out_clk_clk), // input, width = 1, clk.clk
.reset_out (rst_controller_reset_out_reset), // output, width = 1, reset_out.reset
.reset_req (), // (terminated),
.reset_req_in0 (1'b0), // (terminated),
.reset_in1 (1'b0), // (terminated),
.reset_req_in1 (1'b0), // (terminated),
.reset_in2 (1'b0), // (terminated),
.reset_req_in2 (1'b0), // (terminated),
.reset_in3 (1'b0), // (terminated),
.reset_req_in3 (1'b0), // (terminated),
.reset_in4 (1'b0), // (terminated),
.reset_req_in4 (1'b0), // (terminated),
.reset_in5 (1'b0), // (terminated),
.reset_req_in5 (1'b0), // (terminated),
.reset_in6 (1'b0), // (terminated),
.reset_req_in6 (1'b0), // (terminated),
.reset_in7 (1'b0), // (terminated),
.reset_req_in7 (1'b0), // (terminated),
.reset_in8 (1'b0), // (terminated),
.reset_req_in8 (1'b0), // (terminated),
.reset_in9 (1'b0), // (terminated),
.reset_req_in9 (1'b0), // (terminated),
.reset_in10 (1'b0), // (terminated),
.reset_req_in10 (1'b0), // (terminated),
.reset_in11 (1'b0), // (terminated),
.reset_req_in11 (1'b0), // (terminated),
.reset_in12 (1'b0), // (terminated),
.reset_req_in12 (1'b0), // (terminated),
.reset_in13 (1'b0), // (terminated),
.reset_req_in13 (1'b0), // (terminated),
.reset_in14 (1'b0), // (terminated),
.reset_req_in14 (1'b0), // (terminated),
.reset_in15 (1'b0), // (terminated),
.reset_req_in15 (1'b0) // (terminated),
);
endmodule