Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
@@ -0,0 +1,7 @@
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component clk_100 is
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port (
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in_clk : in std_logic := 'X'; -- clk
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out_clk : out std_logic -- clk
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);
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end component clk_100;
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@@ -0,0 +1,145 @@
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<html xmlns="http://www.w3.org/1999/xhtml">
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<head>
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<title>datasheet for clk_100</title>
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<style type="text/css">
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body { font-family:arial ;}
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a { text-decoration:underline ; color:#003000 ;}
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a:hover { text-decoration:underline ; color:0030f0 ;}
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td { padding : 5px ;}
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table.topTitle { width:100% ;}
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table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
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table.blueBar td.l { text-align : left ;}
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div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
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table.grid { border-collapse:collapse ;}
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table.grid td { border:1px solid #bbb ; font-size:12px ;}
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body { font-family:arial ;}
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table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
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table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
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table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
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table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
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table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
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table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
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.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
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.flowbox { display:inline-block ;}
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.parametersbox table { font-size:10px ;}
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td.parametername { font-style:italic ;}
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td.parametervalue { font-weight:bold ;}
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div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
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</head>
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<body>
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<table class="topTitle">
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<tr>
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<td class="l">clk_100</td>
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<td class="r">
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<br/>
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<br/>
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</td>
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</tr>
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</table>
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<table class="blueBar">
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<tr>
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<td class="l">2026.05.11.21:03:48</td>
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<td class="r">Datasheet</td>
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</tr>
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</table>
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<div style="width:100% ; height:10px"> </div>
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<div class="label">Overview</div>
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<div class="greydiv">
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<div style="display:inline-block ; text-align:left">
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<table class="connectionboxes">
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<tr style="height:6px">
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<td></td>
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</tr>
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</table>
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</div><span style="display:inline-block ; width:28px"> </span>
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<div style="display:inline-block ; text-align:left"><span>
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<br/></span>
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</div>
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</div>
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<div style="width:100% ; height:10px"> </div>
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<div class="label">Memory Map</div>
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<table class="mmap">
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<tr>
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<td class="empty" rowspan="2"></td>
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</tr>
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</table>
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<a name="module_altera_clock_bridge_inst"> </a>
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<div>
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<hr/>
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<h2>altera_clock_bridge_inst</h2>altera_clock_bridge v19.2.0
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<br/>
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<br/>
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<br/>
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<table class="flowbox">
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<tr>
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<td class="parametersbox">
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<h2>Parameters</h2>
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<table>
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<tr>
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<td class="parametername">DERIVED_CLOCK_RATE</td>
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<td class="parametervalue">0</td>
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</tr>
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<tr>
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<td class="parametername">EXPLICIT_CLOCK_RATE</td>
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<td class="parametervalue">100000000</td>
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</tr>
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<tr>
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<td class="parametername">NUM_CLOCK_OUTPUTS</td>
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<td class="parametervalue">1</td>
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</tr>
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<tr>
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<td class="parametername">deviceFamily</td>
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<td class="parametervalue">UNKNOWN</td>
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</tr>
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<tr>
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<td class="parametername">generateLegacySim</td>
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<td class="parametervalue">false</td>
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||||
</tr>
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</table>
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||||
</td>
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</tr>
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</table>  
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<table class="flowbox">
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<tr>
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<td class="parametersbox">
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<h2>Software Assignments</h2>(none)</td>
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</tr>
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</table>
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</div>
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<table class="blueBar">
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<tr>
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<td class="l">generation took 0.00 seconds</td>
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<td class="r">rendering took 0.02 seconds</td>
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</tr>
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</table>
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</body>
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</html>
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@@ -0,0 +1,44 @@
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<?xml version="1.0" ?>
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<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
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<instanceKey xsi:type="xs:string">clk_100</instanceKey>
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<instanceData xsi:type="data">
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<parameters></parameters>
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<interconnectAssignments></interconnectAssignments>
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<className>clk_100</className>
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<version>1.0</version>
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<name>clk_100</name>
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<uniqueName>clk_100</uniqueName>
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<nonce>0</nonce>
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<incidentConnections></incidentConnections>
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</instanceData>
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<children>
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<node>
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<instanceKey xsi:type="xs:string">altera_clock_bridge_inst</instanceKey>
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<instanceData xsi:type="data">
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<parameters>
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<parameter>
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<name>DERIVED_CLOCK_RATE</name>
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<value>0</value>
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</parameter>
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<parameter>
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<name>EXPLICIT_CLOCK_RATE</name>
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<value>100000000</value>
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</parameter>
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<parameter>
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<name>NUM_CLOCK_OUTPUTS</name>
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<value>1</value>
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</parameter>
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</parameters>
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<interconnectAssignments></interconnectAssignments>
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<className>altera_clock_bridge</className>
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<version>19.2.0</version>
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<name>altera_clock_bridge_inst</name>
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<uniqueName>clk_100_altera_clock_bridge_1920_njakcna</uniqueName>
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<nonce>0</nonce>
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<incidentConnections></incidentConnections>
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<path>clk_100.altera_clock_bridge_inst</path>
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||||
</instanceData>
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||||
<children></children>
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</node>
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</children>
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</node>
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@@ -0,0 +1,29 @@
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_NAME "QsysPrimePro"
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_VERSION "26.1"
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_ENV "QsysPrimePro"
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_clock_bridge"
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set_global_assignment -entity "clk_100" -library "clk_100" -name PRE_COMPILED_MODULE "ON"
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set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_FILE [file join $::quartus(qip_path) "../clk_100.ip"]
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set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_TYPE "altera_clock_bridge"
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set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_VERSION "19.2.0"
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set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_HASH "njakcna"
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set_global_assignment -library "clk_100" -name SOPCINFO_FILE [file join $::quartus(qip_path) "clk_100.sopcinfo"]
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set_global_assignment -entity "clk_100" -library "clk_100" -name SLD_INFO "QSYS_NAME clk_100 HAS_SOPCINFO 1 GENERATION_ID 0"
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set_global_assignment -library "clk_100" -name MISC_FILE [file join $::quartus(qip_path) "clk_100.cmp"]
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_QSYS_MODE "STANDALONE"
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set_global_assignment -name SYNTHESIS_ONLY_QIP ON
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set_global_assignment -library "clk_100" -name MISC_FILE [file join $::quartus(qip_path) "../clk_100.ip"]
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_NAME "Y2xrXzEwMA=="
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_REPORT_HIERARCHY "On"
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_VERSION "MS4w"
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set_global_assignment -library "clk_100" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/clk_100.v"]
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@@ -0,0 +1,316 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="clk_100" kind="clk_100" version="1.0" fabric="QSYS">
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<!-- Format version 26.1 110 (Future versions may contain additional information.) -->
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<!-- 2026.05.11.21:03:48 -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<value>0</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>GENERATION_ID</sysinfo_type>
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</parameter>
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<parameter name="AUTO_UNIQUE_ID">
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<type>java.lang.String</type>
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<value></value>
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<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
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<valid>true</valid>
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<sysinfo_type>UNIQUE_ID</sysinfo_type>
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</parameter>
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<parameter name="AUTO_DEVICE_FAMILY">
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<type>java.lang.String</type>
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<value>Agilex 5</value>
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<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
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||||
<valid>true</valid>
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<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
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||||
</parameter>
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||||
<parameter name="AUTO_DEVICE">
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||||
<type>java.lang.String</type>
|
||||
<value>A5EB013BB23BE4SCS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
||||
<type>java.lang.String</type>
|
||||
<value>4</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_BOARD">
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||||
<type>java.lang.String</type>
|
||||
<value>default</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>BOARD</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_RATE">
|
||||
<type>java.lang.Long</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_DOMAIN">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_RESET_DOMAIN">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="altera_clock_bridge_inst"
|
||||
kind="altera_clock_bridge"
|
||||
version="19.2.0"
|
||||
path="altera_clock_bridge_inst"
|
||||
className="altera_clock_bridge">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="DERIVED_CLOCK_RATE">
|
||||
<type>long</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="EXPLICIT_CLOCK_RATE">
|
||||
<type>long</type>
|
||||
<value>100000000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="NUM_CLOCK_OUTPUTS">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="in_clk" kind="clock_sink" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRateKnown">
|
||||
<type>java.lang.Boolean</type>
|
||||
<value>false</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRate">
|
||||
<type>java.lang.Long</type>
|
||||
<value>0</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<span>0</span>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>in_clk</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="out_clk" kind="clock_source" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedDirectClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>in_clk</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRate">
|
||||
<type>long</type>
|
||||
<value>100000000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRateKnown">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<span>0</span>
|
||||
<isStart>true</isStart>
|
||||
<port>
|
||||
<name>out_clk</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altera_clock_bridge</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>Clock Bridge IP</displayName>
|
||||
<version>19.2.0</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Clock Input</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_source</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Clock Output</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<reportVersion>26.1 110</reportVersion>
|
||||
<uniqueIdentifier></uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
@@ -0,0 +1,104 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.05.11.21:03:48"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5EB013BB23BE4SCS"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="6"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_CLOCK_RATE"
|
||||
type="Long"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_CLOCK_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_RESET_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="in_clk" kind="clock" start="0">
|
||||
<property name="clockRate" value="0" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="in_clk" direction="input" role="clk" width="1" />
|
||||
</interface>
|
||||
<interface name="out_clk" kind="clock" start="1">
|
||||
<property name="associatedDirectClock" value="in_clk" />
|
||||
<property name="clockRate" value="100000000" />
|
||||
<property name="clockRateKnown" value="true" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="out_clk" direction="output" role="clk" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity kind="clk_100" version="1.0" name="clk_100">
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_IN_CLK_RESET_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_DOMAIN" value="-1" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100/synth/clk_100.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100/synth/clk_100.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<messages>
|
||||
<message level="Info" culprit="clk_100">"Generating: clk_100"</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
@@ -0,0 +1,6 @@
|
||||
module clk_100 (
|
||||
input wire in_clk, // in_clk.clk, Clock Input
|
||||
output wire out_clk // out_clk.clk, Clock Output
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: clk_100: "Transforming system: clk_100"
|
||||
Info: clk_100: "Naming system components in system: clk_100"
|
||||
Info: clk_100: "Processing generation queue"
|
||||
Info: clk_100: "Generating: clk_100"
|
||||
Info: clk_100: Done "clk_100" with 1 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,9 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: clk_100: "Transforming system: clk_100"
|
||||
Info: clk_100: "Naming system components in system: clk_100"
|
||||
Info: clk_100: "Processing generation queue"
|
||||
Info: clk_100: "Generating: clk_100"
|
||||
Info: clk_100: Done "clk_100" with 1 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,5 @@
|
||||
clk_100 u0 (
|
||||
.in_clk (_connected_to_in_clk_), // input, width = 1, in_clk.clk
|
||||
.out_clk (_connected_to_out_clk_) // output, width = 1, out_clk.clk
|
||||
);
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
component clk_100 is
|
||||
port (
|
||||
in_clk : in std_logic := 'X'; -- clk
|
||||
out_clk : out std_logic -- clk
|
||||
);
|
||||
end component clk_100;
|
||||
|
||||
u0 : component clk_100
|
||||
port map (
|
||||
in_clk => CONNECTED_TO_in_clk, -- in_clk.clk
|
||||
out_clk => CONNECTED_TO_out_clk -- out_clk.clk
|
||||
);
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
// clk_100.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module clk_100 (
|
||||
input wire in_clk, // in_clk.clk, Clock Input
|
||||
output wire out_clk // out_clk.clk, Clock Output
|
||||
);
|
||||
|
||||
assign out_clk = in_clk;
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user