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retroDE_ps2/qsys/ip/qsys_top/clk_100/clk_100.cmp
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thejayman77 ec82764bef Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-06-29 20:10:50 -04:00

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component clk_100 is
port (
in_clk : in std_logic := 'X'; -- clk
out_clk : out std_logic -- clk
);
end component clk_100;