Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
Executable
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<?xml version="1.0" ?>
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||||
<!--Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.-->
|
||||
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
|
||||
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
||||
<ipxact:library>clk_100</ipxact:library>
|
||||
<ipxact:name>altera_clock_bridge_inst</ipxact:name>
|
||||
<ipxact:version>19.2.0</ipxact:version>
|
||||
<ipxact:busInterfaces>
|
||||
<ipxact:busInterface>
|
||||
<ipxact:name>in_clk</ipxact:name>
|
||||
<ipxact:busType vendor="intel" library="intel" name="clock" version="25.3"></ipxact:busType>
|
||||
<ipxact:abstractionTypes>
|
||||
<ipxact:abstractionType>
|
||||
<ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="25.3"></ipxact:abstractionRef>
|
||||
<ipxact:portMaps>
|
||||
<ipxact:portMap>
|
||||
<ipxact:logicalPort>
|
||||
<ipxact:name>clk</ipxact:name>
|
||||
</ipxact:logicalPort>
|
||||
<ipxact:physicalPort>
|
||||
<ipxact:name>in_clk</ipxact:name>
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||||
</ipxact:physicalPort>
|
||||
</ipxact:portMap>
|
||||
</ipxact:portMaps>
|
||||
</ipxact:abstractionType>
|
||||
</ipxact:abstractionTypes>
|
||||
<ipxact:slave></ipxact:slave>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="clockRate" type="longint">
|
||||
<ipxact:name>clockRate</ipxact:name>
|
||||
<ipxact:displayName>Clock rate</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="externallyDriven" type="bit">
|
||||
<ipxact:name>externallyDriven</ipxact:name>
|
||||
<ipxact:displayName>Externally driven</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="ptfSchematicName" type="string">
|
||||
<ipxact:name>ptfSchematicName</ipxact:name>
|
||||
<ipxact:displayName>PTF schematic name</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</ipxact:busInterface>
|
||||
<ipxact:busInterface>
|
||||
<ipxact:name>out_clk</ipxact:name>
|
||||
<ipxact:busType vendor="intel" library="intel" name="clock" version="25.3"></ipxact:busType>
|
||||
<ipxact:abstractionTypes>
|
||||
<ipxact:abstractionType>
|
||||
<ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="25.3"></ipxact:abstractionRef>
|
||||
<ipxact:portMaps>
|
||||
<ipxact:portMap>
|
||||
<ipxact:logicalPort>
|
||||
<ipxact:name>clk</ipxact:name>
|
||||
</ipxact:logicalPort>
|
||||
<ipxact:physicalPort>
|
||||
<ipxact:name>out_clk</ipxact:name>
|
||||
</ipxact:physicalPort>
|
||||
</ipxact:portMap>
|
||||
</ipxact:portMaps>
|
||||
</ipxact:abstractionType>
|
||||
</ipxact:abstractionTypes>
|
||||
<ipxact:master></ipxact:master>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="associatedDirectClock" type="string">
|
||||
<ipxact:name>associatedDirectClock</ipxact:name>
|
||||
<ipxact:displayName>Associated direct clock</ipxact:displayName>
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||||
<ipxact:value>in_clk</ipxact:value>
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||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="clockRate" type="longint">
|
||||
<ipxact:name>clockRate</ipxact:name>
|
||||
<ipxact:displayName>Clock rate</ipxact:displayName>
|
||||
<ipxact:value>100000000</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="clockRateKnown" type="bit">
|
||||
<ipxact:name>clockRateKnown</ipxact:name>
|
||||
<ipxact:displayName>Clock rate known</ipxact:displayName>
|
||||
<ipxact:value>true</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="externallyDriven" type="bit">
|
||||
<ipxact:name>externallyDriven</ipxact:name>
|
||||
<ipxact:displayName>Externally driven</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="ptfSchematicName" type="string">
|
||||
<ipxact:name>ptfSchematicName</ipxact:name>
|
||||
<ipxact:displayName>PTF schematic name</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</ipxact:busInterface>
|
||||
</ipxact:busInterfaces>
|
||||
<ipxact:model>
|
||||
<ipxact:views>
|
||||
<ipxact:view>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
|
||||
<ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
|
||||
</ipxact:view>
|
||||
</ipxact:views>
|
||||
<ipxact:instantiations>
|
||||
<ipxact:componentInstantiation>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:moduleName>altera_clock_bridge</ipxact:moduleName>
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||||
<ipxact:fileSetRef>
|
||||
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
|
||||
</ipxact:fileSetRef>
|
||||
<ipxact:parameters></ipxact:parameters>
|
||||
</ipxact:componentInstantiation>
|
||||
</ipxact:instantiations>
|
||||
<ipxact:ports>
|
||||
<ipxact:port>
|
||||
<ipxact:name>in_clk</ipxact:name>
|
||||
<ipxact:wire>
|
||||
<ipxact:direction>in</ipxact:direction>
|
||||
<ipxact:vectors></ipxact:vectors>
|
||||
<ipxact:wireTypeDefs>
|
||||
<ipxact:wireTypeDef>
|
||||
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
|
||||
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
|
||||
</ipxact:wireTypeDef>
|
||||
</ipxact:wireTypeDefs>
|
||||
</ipxact:wire>
|
||||
</ipxact:port>
|
||||
<ipxact:port>
|
||||
<ipxact:name>out_clk</ipxact:name>
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||||
<ipxact:wire>
|
||||
<ipxact:direction>out</ipxact:direction>
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||||
<ipxact:vectors></ipxact:vectors>
|
||||
<ipxact:wireTypeDefs>
|
||||
<ipxact:wireTypeDef>
|
||||
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
|
||||
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
|
||||
</ipxact:wireTypeDef>
|
||||
</ipxact:wireTypeDefs>
|
||||
</ipxact:wire>
|
||||
</ipxact:port>
|
||||
</ipxact:ports>
|
||||
</ipxact:model>
|
||||
<ipxact:vendorExtensions>
|
||||
<altera:entity_info>
|
||||
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
||||
<ipxact:library>clk_100</ipxact:library>
|
||||
<ipxact:name>altera_clock_bridge</ipxact:name>
|
||||
<ipxact:version>19.2.0</ipxact:version>
|
||||
</altera:entity_info>
|
||||
<altera:altera_module_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="DERIVED_CLOCK_RATE" type="longint">
|
||||
<ipxact:name>DERIVED_CLOCK_RATE</ipxact:name>
|
||||
<ipxact:displayName>Derived clock rate</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="EXPLICIT_CLOCK_RATE" type="longint">
|
||||
<ipxact:name>EXPLICIT_CLOCK_RATE</ipxact:name>
|
||||
<ipxact:displayName>Explicit clock rate</ipxact:displayName>
|
||||
<ipxact:value>100000000</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="NUM_CLOCK_OUTPUTS" type="int">
|
||||
<ipxact:name>NUM_CLOCK_OUTPUTS</ipxact:name>
|
||||
<ipxact:displayName>Number of Clock Outputs</ipxact:displayName>
|
||||
<ipxact:value>1</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_module_parameters>
|
||||
<altera:altera_system_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="board" type="string">
|
||||
<ipxact:name>board</ipxact:name>
|
||||
<ipxact:displayName>Board</ipxact:displayName>
|
||||
<ipxact:value>default</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="device" type="string">
|
||||
<ipxact:name>device</ipxact:name>
|
||||
<ipxact:displayName>Device</ipxact:displayName>
|
||||
<ipxact:value>A5EB013BB23BE4SCS</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceFamily" type="string">
|
||||
<ipxact:name>deviceFamily</ipxact:name>
|
||||
<ipxact:displayName>Device family</ipxact:displayName>
|
||||
<ipxact:value>Agilex 5</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
|
||||
<ipxact:name>deviceSpeedGrade</ipxact:name>
|
||||
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
|
||||
<ipxact:value>6</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="generationId" type="int">
|
||||
<ipxact:name>generationId</ipxact:name>
|
||||
<ipxact:displayName>Generation Id</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="bonusData" type="string">
|
||||
<ipxact:name>bonusData</ipxact:name>
|
||||
<ipxact:displayName>bonusData</ipxact:displayName>
|
||||
<ipxact:value>bonusData
|
||||
{
|
||||
element $system
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Agilex 5";
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||||
type = "String";
|
||||
}
|
||||
}
|
||||
element altera_clock_bridge_inst
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||||
{
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||||
datum _sortIndex
|
||||
{
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||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
|
||||
<ipxact:name>hideFromIPCatalog</ipxact:name>
|
||||
<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
|
||||
<ipxact:name>lockedInterfaceDefinition</ipxact:name>
|
||||
<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
|
||||
<ipxact:value><boundaryDefinition>
|
||||
<interfaces>
|
||||
<interface>
|
||||
<name>in_clk</name>
|
||||
<type>clock</type>
|
||||
<isStart>false</isStart>
|
||||
<ports>
|
||||
<port>
|
||||
<name>in_clk</name>
|
||||
<role>clk</role>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<lowerBound>0</lowerBound>
|
||||
<vhdlType>STD_LOGIC</vhdlType>
|
||||
<terminationValue>0</terminationValue>
|
||||
</port>
|
||||
</ports>
|
||||
<assignments>
|
||||
<assignmentValueMap/>
|
||||
</assignments>
|
||||
<parameters>
|
||||
<parameterValueMap>
|
||||
<entry>
|
||||
<key>clockRate</key>
|
||||
<value>0</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>externallyDriven</key>
|
||||
<value>false</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>ptfSchematicName</key>
|
||||
</entry>
|
||||
</parameterValueMap>
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface>
|
||||
<name>out_clk</name>
|
||||
<type>clock</type>
|
||||
<isStart>true</isStart>
|
||||
<ports>
|
||||
<port>
|
||||
<name>out_clk</name>
|
||||
<role>clk</role>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<lowerBound>0</lowerBound>
|
||||
<vhdlType>STD_LOGIC</vhdlType>
|
||||
<terminationValue>0</terminationValue>
|
||||
</port>
|
||||
</ports>
|
||||
<assignments>
|
||||
<assignmentValueMap/>
|
||||
</assignments>
|
||||
<parameters>
|
||||
<parameterValueMap>
|
||||
<entry>
|
||||
<key>associatedDirectClock</key>
|
||||
<value>in_clk</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>clockRate</key>
|
||||
<value>100000000</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>clockRateKnown</key>
|
||||
<value>true</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>externallyDriven</key>
|
||||
<value>false</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>ptfSchematicName</key>
|
||||
</entry>
|
||||
</parameterValueMap>
|
||||
</parameters>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</boundaryDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="systemInfos" type="string">
|
||||
<ipxact:name>systemInfos</ipxact:name>
|
||||
<ipxact:displayName>systemInfos</ipxact:displayName>
|
||||
<ipxact:value><systemInfosDefinition>
|
||||
<connPtSystemInfos>
|
||||
<entry>
|
||||
<key>in_clk</key>
|
||||
<value>
|
||||
<connectionPointName>in_clk</connectionPointName>
|
||||
<suppliedSystemInfos>
|
||||
<entry>
|
||||
<key>CLOCK_RATE</key>
|
||||
<value>0</value>
|
||||
</entry>
|
||||
</suppliedSystemInfos>
|
||||
<consumedSystemInfos/>
|
||||
</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>out_clk</key>
|
||||
<value>
|
||||
<connectionPointName>out_clk</connectionPointName>
|
||||
<suppliedSystemInfos/>
|
||||
<consumedSystemInfos>
|
||||
<entry>
|
||||
<key>CLOCK_RATE</key>
|
||||
<value>100000000</value>
|
||||
</entry>
|
||||
</consumedSystemInfos>
|
||||
</value>
|
||||
</entry>
|
||||
</connPtSystemInfos>
|
||||
</systemInfosDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="dflBitArray" type="string">
|
||||
<ipxact:name>dflBitArray</ipxact:name>
|
||||
<ipxact:displayName>dflBitArray</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="cpuInfo" type="string">
|
||||
<ipxact:name>cpuInfo</ipxact:name>
|
||||
<ipxact:displayName>cpuInfo</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_system_parameters>
|
||||
<altera:altera_interface_boundary>
|
||||
<altera:interface_mapping altera:name="in_clk" altera:internal="altera_clock_bridge_inst.in_clk" altera:type="clock" altera:dir="end">
|
||||
<altera:port_mapping altera:name="in_clk" altera:internal="in_clk"></altera:port_mapping>
|
||||
</altera:interface_mapping>
|
||||
<altera:interface_mapping altera:name="out_clk" altera:internal="altera_clock_bridge_inst.out_clk" altera:type="clock" altera:dir="start">
|
||||
<altera:port_mapping altera:name="out_clk" altera:internal="out_clk"></altera:port_mapping>
|
||||
</altera:interface_mapping>
|
||||
</altera:altera_interface_boundary>
|
||||
<altera:altera_has_warnings>false</altera:altera_has_warnings>
|
||||
<altera:altera_has_errors>false</altera:altera_has_errors>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:component>
|
||||
@@ -0,0 +1,7 @@
|
||||
component clk_100 is
|
||||
port (
|
||||
in_clk : in std_logic := 'X'; -- clk
|
||||
out_clk : out std_logic -- clk
|
||||
);
|
||||
end component clk_100;
|
||||
|
||||
@@ -0,0 +1,145 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for clk_100</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">clk_100</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.05.11.21:03:48</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_altera_clock_bridge_inst"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>altera_clock_bridge_inst</h2>altera_clock_bridge v19.2.0
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">DERIVED_CLOCK_RATE</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EXPLICIT_CLOCK_RATE</td>
|
||||
<td class="parametervalue">100000000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">NUM_CLOCK_OUTPUTS</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.02 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,44 @@
|
||||
<?xml version="1.0" ?>
|
||||
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
|
||||
<instanceKey xsi:type="xs:string">clk_100</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters></parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>clk_100</className>
|
||||
<version>1.0</version>
|
||||
<name>clk_100</name>
|
||||
<uniqueName>clk_100</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
</instanceData>
|
||||
<children>
|
||||
<node>
|
||||
<instanceKey xsi:type="xs:string">altera_clock_bridge_inst</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters>
|
||||
<parameter>
|
||||
<name>DERIVED_CLOCK_RATE</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>EXPLICIT_CLOCK_RATE</name>
|
||||
<value>100000000</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>NUM_CLOCK_OUTPUTS</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
</parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>altera_clock_bridge</className>
|
||||
<version>19.2.0</version>
|
||||
<name>altera_clock_bridge_inst</name>
|
||||
<uniqueName>clk_100_altera_clock_bridge_1920_njakcna</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
<path>clk_100.altera_clock_bridge_inst</path>
|
||||
</instanceData>
|
||||
<children></children>
|
||||
</node>
|
||||
</children>
|
||||
</node>
|
||||
@@ -0,0 +1,29 @@
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_clock_bridge"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name PRE_COMPILED_MODULE "ON"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_FILE [file join $::quartus(qip_path) "../clk_100.ip"]
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_TYPE "altera_clock_bridge"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_VERSION "19.2.0"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_HASH "njakcna"
|
||||
set_global_assignment -library "clk_100" -name SOPCINFO_FILE [file join $::quartus(qip_path) "clk_100.sopcinfo"]
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name SLD_INFO "QSYS_NAME clk_100 HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "clk_100" -name MISC_FILE [file join $::quartus(qip_path) "clk_100.cmp"]
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "clk_100" -name MISC_FILE [file join $::quartus(qip_path) "../clk_100.ip"]
|
||||
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_NAME "Y2xrXzEwMA=="
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "clk_100" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/clk_100.v"]
|
||||
|
||||
@@ -0,0 +1,316 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="clk_100" kind="clk_100" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 26.1 110 (Future versions may contain additional information.) -->
|
||||
<!-- 2026.05.11.21:03:48 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_UNIQUE_ID">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE">
|
||||
<type>java.lang.String</type>
|
||||
<value>A5EB013BB23BE4SCS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
||||
<type>java.lang.String</type>
|
||||
<value>4</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_BOARD">
|
||||
<type>java.lang.String</type>
|
||||
<value>default</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>BOARD</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_RATE">
|
||||
<type>java.lang.Long</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_DOMAIN">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_RESET_DOMAIN">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="altera_clock_bridge_inst"
|
||||
kind="altera_clock_bridge"
|
||||
version="19.2.0"
|
||||
path="altera_clock_bridge_inst"
|
||||
className="altera_clock_bridge">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="DERIVED_CLOCK_RATE">
|
||||
<type>long</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="EXPLICIT_CLOCK_RATE">
|
||||
<type>long</type>
|
||||
<value>100000000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="NUM_CLOCK_OUTPUTS">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="in_clk" kind="clock_sink" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRateKnown">
|
||||
<type>java.lang.Boolean</type>
|
||||
<value>false</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRate">
|
||||
<type>java.lang.Long</type>
|
||||
<value>0</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<span>0</span>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>in_clk</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="out_clk" kind="clock_source" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedDirectClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>in_clk</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRate">
|
||||
<type>long</type>
|
||||
<value>100000000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRateKnown">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<span>0</span>
|
||||
<isStart>true</isStart>
|
||||
<port>
|
||||
<name>out_clk</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altera_clock_bridge</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>Clock Bridge IP</displayName>
|
||||
<version>19.2.0</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Clock Input</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_source</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Clock Output</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<reportVersion>26.1 110</reportVersion>
|
||||
<uniqueIdentifier></uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
@@ -0,0 +1,104 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.05.11.21:03:48"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5EB013BB23BE4SCS"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="6"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_CLOCK_RATE"
|
||||
type="Long"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_CLOCK_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_RESET_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="in_clk" kind="clock" start="0">
|
||||
<property name="clockRate" value="0" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="in_clk" direction="input" role="clk" width="1" />
|
||||
</interface>
|
||||
<interface name="out_clk" kind="clock" start="1">
|
||||
<property name="associatedDirectClock" value="in_clk" />
|
||||
<property name="clockRate" value="100000000" />
|
||||
<property name="clockRateKnown" value="true" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="out_clk" direction="output" role="clk" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity kind="clk_100" version="1.0" name="clk_100">
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_IN_CLK_RESET_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_DOMAIN" value="-1" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100/synth/clk_100.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100/synth/clk_100.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<messages>
|
||||
<message level="Info" culprit="clk_100">"Generating: clk_100"</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
@@ -0,0 +1,6 @@
|
||||
module clk_100 (
|
||||
input wire in_clk, // in_clk.clk, Clock Input
|
||||
output wire out_clk // out_clk.clk, Clock Output
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: clk_100: "Transforming system: clk_100"
|
||||
Info: clk_100: "Naming system components in system: clk_100"
|
||||
Info: clk_100: "Processing generation queue"
|
||||
Info: clk_100: "Generating: clk_100"
|
||||
Info: clk_100: Done "clk_100" with 1 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,9 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: clk_100: "Transforming system: clk_100"
|
||||
Info: clk_100: "Naming system components in system: clk_100"
|
||||
Info: clk_100: "Processing generation queue"
|
||||
Info: clk_100: "Generating: clk_100"
|
||||
Info: clk_100: Done "clk_100" with 1 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,5 @@
|
||||
clk_100 u0 (
|
||||
.in_clk (_connected_to_in_clk_), // input, width = 1, in_clk.clk
|
||||
.out_clk (_connected_to_out_clk_) // output, width = 1, out_clk.clk
|
||||
);
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
component clk_100 is
|
||||
port (
|
||||
in_clk : in std_logic := 'X'; -- clk
|
||||
out_clk : out std_logic -- clk
|
||||
);
|
||||
end component clk_100;
|
||||
|
||||
u0 : component clk_100
|
||||
port map (
|
||||
in_clk => CONNECTED_TO_in_clk, -- in_clk.clk
|
||||
out_clk => CONNECTED_TO_out_clk -- out_clk.clk
|
||||
);
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
// clk_100.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module clk_100 (
|
||||
input wire in_clk, // in_clk.clk, Clock Input
|
||||
output wire out_clk // out_clk.clk, Clock Output
|
||||
);
|
||||
|
||||
assign out_clk = in_clk;
|
||||
|
||||
endmodule
|
||||
Executable
+347
@@ -0,0 +1,347 @@
|
||||
<?xml version="1.0" ?>
|
||||
<!--Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.-->
|
||||
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
|
||||
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
||||
<ipxact:library>rst_in</ipxact:library>
|
||||
<ipxact:name>altera_reset_bridge_inst</ipxact:name>
|
||||
<ipxact:version>19.2.0</ipxact:version>
|
||||
<ipxact:busInterfaces>
|
||||
<ipxact:busInterface>
|
||||
<ipxact:name>in_reset</ipxact:name>
|
||||
<ipxact:busType vendor="intel" library="intel" name="reset" version="25.3"></ipxact:busType>
|
||||
<ipxact:abstractionTypes>
|
||||
<ipxact:abstractionType>
|
||||
<ipxact:abstractionRef vendor="intel" library="intel" name="reset" version="25.3"></ipxact:abstractionRef>
|
||||
<ipxact:portMaps>
|
||||
<ipxact:portMap>
|
||||
<ipxact:logicalPort>
|
||||
<ipxact:name>reset_n</ipxact:name>
|
||||
</ipxact:logicalPort>
|
||||
<ipxact:physicalPort>
|
||||
<ipxact:name>in_reset_n</ipxact:name>
|
||||
</ipxact:physicalPort>
|
||||
</ipxact:portMap>
|
||||
</ipxact:portMaps>
|
||||
</ipxact:abstractionType>
|
||||
</ipxact:abstractionTypes>
|
||||
<ipxact:slave></ipxact:slave>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="associatedClock" type="string">
|
||||
<ipxact:name>associatedClock</ipxact:name>
|
||||
<ipxact:displayName>Associated clock</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="synchronousEdges" type="string">
|
||||
<ipxact:name>synchronousEdges</ipxact:name>
|
||||
<ipxact:displayName>Synchronous edges</ipxact:displayName>
|
||||
<ipxact:value>NONE</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</ipxact:busInterface>
|
||||
<ipxact:busInterface>
|
||||
<ipxact:name>out_reset</ipxact:name>
|
||||
<ipxact:busType vendor="intel" library="intel" name="reset" version="25.3"></ipxact:busType>
|
||||
<ipxact:abstractionTypes>
|
||||
<ipxact:abstractionType>
|
||||
<ipxact:abstractionRef vendor="intel" library="intel" name="reset" version="25.3"></ipxact:abstractionRef>
|
||||
<ipxact:portMaps>
|
||||
<ipxact:portMap>
|
||||
<ipxact:logicalPort>
|
||||
<ipxact:name>reset_n</ipxact:name>
|
||||
</ipxact:logicalPort>
|
||||
<ipxact:physicalPort>
|
||||
<ipxact:name>out_reset_n</ipxact:name>
|
||||
</ipxact:physicalPort>
|
||||
</ipxact:portMap>
|
||||
</ipxact:portMaps>
|
||||
</ipxact:abstractionType>
|
||||
</ipxact:abstractionTypes>
|
||||
<ipxact:master></ipxact:master>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="associatedClock" type="string">
|
||||
<ipxact:name>associatedClock</ipxact:name>
|
||||
<ipxact:displayName>Associated clock</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="associatedDirectReset" type="string">
|
||||
<ipxact:name>associatedDirectReset</ipxact:name>
|
||||
<ipxact:displayName>Associated direct reset</ipxact:displayName>
|
||||
<ipxact:value>in_reset</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="associatedResetSinks" type="string">
|
||||
<ipxact:name>associatedResetSinks</ipxact:name>
|
||||
<ipxact:displayName>Associated reset sinks</ipxact:displayName>
|
||||
<ipxact:value>in_reset</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="synchronousEdges" type="string">
|
||||
<ipxact:name>synchronousEdges</ipxact:name>
|
||||
<ipxact:displayName>Synchronous edges</ipxact:displayName>
|
||||
<ipxact:value>NONE</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</ipxact:busInterface>
|
||||
</ipxact:busInterfaces>
|
||||
<ipxact:model>
|
||||
<ipxact:views>
|
||||
<ipxact:view>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
|
||||
<ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
|
||||
</ipxact:view>
|
||||
</ipxact:views>
|
||||
<ipxact:instantiations>
|
||||
<ipxact:componentInstantiation>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:moduleName>altera_reset_bridge</ipxact:moduleName>
|
||||
<ipxact:fileSetRef>
|
||||
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
|
||||
</ipxact:fileSetRef>
|
||||
<ipxact:parameters></ipxact:parameters>
|
||||
</ipxact:componentInstantiation>
|
||||
</ipxact:instantiations>
|
||||
<ipxact:ports>
|
||||
<ipxact:port>
|
||||
<ipxact:name>in_reset_n</ipxact:name>
|
||||
<ipxact:wire>
|
||||
<ipxact:direction>in</ipxact:direction>
|
||||
<ipxact:vectors></ipxact:vectors>
|
||||
<ipxact:wireTypeDefs>
|
||||
<ipxact:wireTypeDef>
|
||||
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
|
||||
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
|
||||
</ipxact:wireTypeDef>
|
||||
</ipxact:wireTypeDefs>
|
||||
</ipxact:wire>
|
||||
</ipxact:port>
|
||||
<ipxact:port>
|
||||
<ipxact:name>out_reset_n</ipxact:name>
|
||||
<ipxact:wire>
|
||||
<ipxact:direction>out</ipxact:direction>
|
||||
<ipxact:vectors></ipxact:vectors>
|
||||
<ipxact:wireTypeDefs>
|
||||
<ipxact:wireTypeDef>
|
||||
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
|
||||
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
|
||||
</ipxact:wireTypeDef>
|
||||
</ipxact:wireTypeDefs>
|
||||
</ipxact:wire>
|
||||
</ipxact:port>
|
||||
</ipxact:ports>
|
||||
</ipxact:model>
|
||||
<ipxact:vendorExtensions>
|
||||
<altera:entity_info>
|
||||
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
||||
<ipxact:library>rst_in</ipxact:library>
|
||||
<ipxact:name>altera_reset_bridge</ipxact:name>
|
||||
<ipxact:version>19.2.0</ipxact:version>
|
||||
</altera:entity_info>
|
||||
<altera:altera_module_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="ACTIVE_LOW_RESET" type="int">
|
||||
<ipxact:name>ACTIVE_LOW_RESET</ipxact:name>
|
||||
<ipxact:displayName>Active low reset</ipxact:displayName>
|
||||
<ipxact:value>1</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="SYNCHRONOUS_EDGES" type="string">
|
||||
<ipxact:name>SYNCHRONOUS_EDGES</ipxact:name>
|
||||
<ipxact:displayName>Input Synchronous edges</ipxact:displayName>
|
||||
<ipxact:value>none</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="NUM_RESET_OUTPUTS" type="int">
|
||||
<ipxact:name>NUM_RESET_OUTPUTS</ipxact:name>
|
||||
<ipxact:displayName>Number of reset outputs</ipxact:displayName>
|
||||
<ipxact:value>1</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="USE_RESET_REQUEST" type="int">
|
||||
<ipxact:name>USE_RESET_REQUEST</ipxact:name>
|
||||
<ipxact:displayName>Use reset request signal</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="SYNC_RESET" type="int">
|
||||
<ipxact:name>SYNC_RESET</ipxact:name>
|
||||
<ipxact:displayName>Use synchronous resets</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="AUTO_CLK_CLOCK_RATE" type="longint">
|
||||
<ipxact:name>AUTO_CLK_CLOCK_RATE</ipxact:name>
|
||||
<ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
|
||||
<ipxact:value>-1</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_module_parameters>
|
||||
<altera:altera_system_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="board" type="string">
|
||||
<ipxact:name>board</ipxact:name>
|
||||
<ipxact:displayName>Board</ipxact:displayName>
|
||||
<ipxact:value>default</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="device" type="string">
|
||||
<ipxact:name>device</ipxact:name>
|
||||
<ipxact:displayName>Device</ipxact:displayName>
|
||||
<ipxact:value>A5EB013BB23BE4SCS</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceFamily" type="string">
|
||||
<ipxact:name>deviceFamily</ipxact:name>
|
||||
<ipxact:displayName>Device family</ipxact:displayName>
|
||||
<ipxact:value>Agilex 5</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
|
||||
<ipxact:name>deviceSpeedGrade</ipxact:name>
|
||||
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
|
||||
<ipxact:value>6</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="generationId" type="int">
|
||||
<ipxact:name>generationId</ipxact:name>
|
||||
<ipxact:displayName>Generation Id</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="bonusData" type="string">
|
||||
<ipxact:name>bonusData</ipxact:name>
|
||||
<ipxact:displayName>bonusData</ipxact:displayName>
|
||||
<ipxact:value>bonusData
|
||||
{
|
||||
element $system
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Agilex 5";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element altera_reset_bridge_inst
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
|
||||
<ipxact:name>hideFromIPCatalog</ipxact:name>
|
||||
<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
|
||||
<ipxact:name>lockedInterfaceDefinition</ipxact:name>
|
||||
<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
|
||||
<ipxact:value><boundaryDefinition>
|
||||
<interfaces>
|
||||
<interface>
|
||||
<name>in_reset</name>
|
||||
<type>reset</type>
|
||||
<isStart>false</isStart>
|
||||
<ports>
|
||||
<port>
|
||||
<name>in_reset_n</name>
|
||||
<role>reset_n</role>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<lowerBound>0</lowerBound>
|
||||
<vhdlType>STD_LOGIC</vhdlType>
|
||||
<terminationValue>0</terminationValue>
|
||||
</port>
|
||||
</ports>
|
||||
<assignments>
|
||||
<assignmentValueMap/>
|
||||
</assignments>
|
||||
<parameters>
|
||||
<parameterValueMap>
|
||||
<entry>
|
||||
<key>associatedClock</key>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>synchronousEdges</key>
|
||||
<value>NONE</value>
|
||||
</entry>
|
||||
</parameterValueMap>
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface>
|
||||
<name>out_reset</name>
|
||||
<type>reset</type>
|
||||
<isStart>true</isStart>
|
||||
<ports>
|
||||
<port>
|
||||
<name>out_reset_n</name>
|
||||
<role>reset_n</role>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<lowerBound>0</lowerBound>
|
||||
<vhdlType>STD_LOGIC</vhdlType>
|
||||
<terminationValue>0</terminationValue>
|
||||
</port>
|
||||
</ports>
|
||||
<assignments>
|
||||
<assignmentValueMap/>
|
||||
</assignments>
|
||||
<parameters>
|
||||
<parameterValueMap>
|
||||
<entry>
|
||||
<key>associatedClock</key>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>associatedDirectReset</key>
|
||||
<value>in_reset</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>associatedResetSinks</key>
|
||||
<value>in_reset</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>synchronousEdges</key>
|
||||
<value>NONE</value>
|
||||
</entry>
|
||||
</parameterValueMap>
|
||||
</parameters>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</boundaryDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="systemInfos" type="string">
|
||||
<ipxact:name>systemInfos</ipxact:name>
|
||||
<ipxact:displayName>systemInfos</ipxact:displayName>
|
||||
<ipxact:value><systemInfosDefinition>
|
||||
<connPtSystemInfos/>
|
||||
</systemInfosDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="dflBitArray" type="string">
|
||||
<ipxact:name>dflBitArray</ipxact:name>
|
||||
<ipxact:displayName>dflBitArray</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="cpuInfo" type="string">
|
||||
<ipxact:name>cpuInfo</ipxact:name>
|
||||
<ipxact:displayName>cpuInfo</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_system_parameters>
|
||||
<altera:altera_interface_boundary>
|
||||
<altera:interface_mapping altera:name="clk" altera:internal="altera_reset_bridge_inst.clk"></altera:interface_mapping>
|
||||
<altera:interface_mapping altera:name="in_reset" altera:internal="altera_reset_bridge_inst.in_reset" altera:type="reset" altera:dir="end">
|
||||
<altera:port_mapping altera:name="in_reset_n" altera:internal="in_reset_n"></altera:port_mapping>
|
||||
</altera:interface_mapping>
|
||||
<altera:interface_mapping altera:name="out_reset" altera:internal="altera_reset_bridge_inst.out_reset" altera:type="reset" altera:dir="start">
|
||||
<altera:port_mapping altera:name="out_reset_n" altera:internal="out_reset_n"></altera:port_mapping>
|
||||
</altera:interface_mapping>
|
||||
</altera:altera_interface_boundary>
|
||||
<altera:altera_has_warnings>false</altera:altera_has_warnings>
|
||||
<altera:altera_has_errors>false</altera:altera_has_errors>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:component>
|
||||
@@ -0,0 +1,7 @@
|
||||
component rst_in is
|
||||
port (
|
||||
in_reset_n : in std_logic := 'X'; -- reset_n
|
||||
out_reset_n : out std_logic -- reset_n
|
||||
);
|
||||
end component rst_in;
|
||||
|
||||
@@ -0,0 +1,157 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for rst_in</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">rst_in</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.05.11.21:03:49</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_altera_reset_bridge_inst"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>altera_reset_bridge_inst</h2>altera_reset_bridge v19.2.0
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">ACTIVE_LOW_RESET</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">SYNCHRONOUS_EDGES</td>
|
||||
<td class="parametervalue">none</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">O_SYNCHRONOUS_EDGES</td>
|
||||
<td class="parametervalue">none</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">NUM_RESET_OUTPUTS</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">USE_RESET_REQUEST</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">SYNC_RESET</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.01 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,56 @@
|
||||
<?xml version="1.0" ?>
|
||||
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
|
||||
<instanceKey xsi:type="xs:string">rst_in</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters></parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>rst_in</className>
|
||||
<version>1.0</version>
|
||||
<name>rst_in</name>
|
||||
<uniqueName>rst_in</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
</instanceData>
|
||||
<children>
|
||||
<node>
|
||||
<instanceKey xsi:type="xs:string">altera_reset_bridge_inst</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters>
|
||||
<parameter>
|
||||
<name>ACTIVE_LOW_RESET</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>NUM_RESET_OUTPUTS</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>O_SYNCHRONOUS_EDGES</name>
|
||||
<value>none</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>SYNCHRONOUS_EDGES</name>
|
||||
<value>none</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>SYNC_RESET</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>USE_RESET_REQUEST</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
</parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>altera_reset_bridge</className>
|
||||
<version>19.2.0</version>
|
||||
<name>altera_reset_bridge_inst</name>
|
||||
<uniqueName>rst_in_altera_reset_bridge_1920_xf2264i</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
<path>rst_in.altera_reset_bridge_inst</path>
|
||||
</instanceData>
|
||||
<children></children>
|
||||
</node>
|
||||
</children>
|
||||
</node>
|
||||
@@ -0,0 +1,29 @@
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_reset_bridge"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name PRE_COMPILED_MODULE "ON"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name OCS_IP_FILE [file join $::quartus(qip_path) "../rst_in.ip"]
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name OCS_IP_TYPE "altera_reset_bridge"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name OCS_IP_VERSION "19.2.0"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name OCS_IP_HASH "xf2264i"
|
||||
set_global_assignment -library "rst_in" -name SOPCINFO_FILE [file join $::quartus(qip_path) "rst_in.sopcinfo"]
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name SLD_INFO "QSYS_NAME rst_in HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "rst_in" -name MISC_FILE [file join $::quartus(qip_path) "rst_in.cmp"]
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "rst_in" -name MISC_FILE [file join $::quartus(qip_path) "../rst_in.ip"]
|
||||
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_NAME "cnN0X2lu"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "rst_in" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/rst_in.v"]
|
||||
|
||||
@@ -0,0 +1,294 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="rst_in" kind="rst_in" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 26.1 110 (Future versions may contain additional information.) -->
|
||||
<!-- 2026.05.11.21:03:49 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_UNIQUE_ID">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE">
|
||||
<type>java.lang.String</type>
|
||||
<value>A5EB013BB23BE4SCS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
||||
<type>java.lang.String</type>
|
||||
<value>4</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_BOARD">
|
||||
<type>java.lang.String</type>
|
||||
<value>default</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>BOARD</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="altera_reset_bridge_inst"
|
||||
kind="altera_reset_bridge"
|
||||
version="19.2.0"
|
||||
path="altera_reset_bridge_inst"
|
||||
className="altera_reset_bridge">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="ACTIVE_LOW_RESET">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="SYNCHRONOUS_EDGES">
|
||||
<type>java.lang.String</type>
|
||||
<value>none</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="O_SYNCHRONOUS_EDGES">
|
||||
<type>java.lang.String</type>
|
||||
<value>none</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="NUM_RESET_OUTPUTS">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="USE_RESET_REQUEST">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="SYNC_RESET">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE">
|
||||
<type>java.lang.Long</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
||||
<sysinfo_arg>clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="in_reset" kind="reset_sink" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="synchronousEdges">
|
||||
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
||||
<value>NONE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>reset</type>
|
||||
<span>0</span>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>in_reset_n</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>reset_n</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="out_reset" kind="reset_source" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedDirectReset">
|
||||
<type>java.lang.String</type>
|
||||
<value>in_reset</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedResetSinks">
|
||||
<type>[Ljava.lang.String;</type>
|
||||
<value>in_reset</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="synchronousEdges">
|
||||
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
||||
<value>NONE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>reset</type>
|
||||
<span>0</span>
|
||||
<isStart>true</isStart>
|
||||
<port>
|
||||
<name>out_reset_n</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>reset_n</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altera_reset_bridge</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>Reset Bridge IP</displayName>
|
||||
<version>19.2.0</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>reset_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Reset Input</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>reset_source</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Reset Output</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<reportVersion>26.1 110</reportVersion>
|
||||
<uniqueIdentifier></uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
@@ -0,0 +1,81 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.05.11.21:03:49"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/rst_in/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5EB013BB23BE4SCS"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="6"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="in_reset" kind="reset" start="0">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="synchronousEdges" value="NONE" />
|
||||
<port name="in_reset_n" direction="input" role="reset_n" width="1" />
|
||||
</interface>
|
||||
<interface name="out_reset" kind="reset" start="1">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="associatedDirectReset" value="in_reset" />
|
||||
<property name="associatedResetSinks" value="in_reset" />
|
||||
<property name="synchronousEdges" value="NONE" />
|
||||
<port name="out_reset_n" direction="output" role="reset_n" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity kind="rst_in" version="1.0" name="rst_in">
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/rst_in/synth/rst_in.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/rst_in/synth/rst_in.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/rst_in.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<messages>
|
||||
<message level="Info" culprit="rst_in">"Generating: rst_in"</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
@@ -0,0 +1,6 @@
|
||||
module rst_in (
|
||||
input wire in_reset_n, // in_reset.reset_n, Reset Input
|
||||
output wire out_reset_n // out_reset.reset_n, Reset Output
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/rst_in.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/rst_in --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: rst_in: "Transforming system: rst_in"
|
||||
Info: rst_in: "Naming system components in system: rst_in"
|
||||
Info: rst_in: "Processing generation queue"
|
||||
Info: rst_in: "Generating: rst_in"
|
||||
Info: rst_in: Done "rst_in" with 1 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,9 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/rst_in.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/rst_in --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: rst_in: "Transforming system: rst_in"
|
||||
Info: rst_in: "Naming system components in system: rst_in"
|
||||
Info: rst_in: "Processing generation queue"
|
||||
Info: rst_in: "Generating: rst_in"
|
||||
Info: rst_in: Done "rst_in" with 1 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,5 @@
|
||||
rst_in u0 (
|
||||
.in_reset_n (_connected_to_in_reset_n_), // input, width = 1, in_reset.reset_n
|
||||
.out_reset_n (_connected_to_out_reset_n_) // output, width = 1, out_reset.reset_n
|
||||
);
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
component rst_in is
|
||||
port (
|
||||
in_reset_n : in std_logic := 'X'; -- reset_n
|
||||
out_reset_n : out std_logic -- reset_n
|
||||
);
|
||||
end component rst_in;
|
||||
|
||||
u0 : component rst_in
|
||||
port map (
|
||||
in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
|
||||
out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
|
||||
);
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
// rst_in.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module rst_in (
|
||||
input wire in_reset_n, // in_reset.reset_n, Reset Input
|
||||
output wire out_reset_n // out_reset.reset_n, Reset Output
|
||||
);
|
||||
|
||||
assign out_reset_n = in_reset_n;
|
||||
|
||||
endmodule
|
||||
Executable
+238
@@ -0,0 +1,238 @@
|
||||
<?xml version="1.0" ?>
|
||||
<!--Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.-->
|
||||
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
|
||||
<ipxact:vendor>Altera</ipxact:vendor>
|
||||
<ipxact:library>user_rst_clkgate_0</ipxact:library>
|
||||
<ipxact:name>intel_user_rst_clkgate_inst</ipxact:name>
|
||||
<ipxact:version>1.0.1</ipxact:version>
|
||||
<ipxact:busInterfaces>
|
||||
<ipxact:busInterface>
|
||||
<ipxact:name>ninit_done</ipxact:name>
|
||||
<ipxact:busType vendor="intel" library="intel" name="conduit" version="25.3"></ipxact:busType>
|
||||
<ipxact:abstractionTypes>
|
||||
<ipxact:abstractionType>
|
||||
<ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="25.3"></ipxact:abstractionRef>
|
||||
<ipxact:portMaps>
|
||||
<ipxact:portMap>
|
||||
<ipxact:logicalPort>
|
||||
<ipxact:name>ninit_done</ipxact:name>
|
||||
</ipxact:logicalPort>
|
||||
<ipxact:physicalPort>
|
||||
<ipxact:name>ninit_done</ipxact:name>
|
||||
</ipxact:physicalPort>
|
||||
</ipxact:portMap>
|
||||
</ipxact:portMaps>
|
||||
</ipxact:abstractionType>
|
||||
</ipxact:abstractionTypes>
|
||||
<ipxact:slave></ipxact:slave>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="associatedClock" type="string">
|
||||
<ipxact:name>associatedClock</ipxact:name>
|
||||
<ipxact:displayName>associatedClock</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="associatedReset" type="string">
|
||||
<ipxact:name>associatedReset</ipxact:name>
|
||||
<ipxact:displayName>associatedReset</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="prSafe" type="bit">
|
||||
<ipxact:name>prSafe</ipxact:name>
|
||||
<ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</ipxact:busInterface>
|
||||
</ipxact:busInterfaces>
|
||||
<ipxact:model>
|
||||
<ipxact:views>
|
||||
<ipxact:view>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
|
||||
<ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
|
||||
</ipxact:view>
|
||||
</ipxact:views>
|
||||
<ipxact:instantiations>
|
||||
<ipxact:componentInstantiation>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:moduleName>intel_user_rst_clkgate</ipxact:moduleName>
|
||||
<ipxact:fileSetRef>
|
||||
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
|
||||
</ipxact:fileSetRef>
|
||||
<ipxact:parameters></ipxact:parameters>
|
||||
</ipxact:componentInstantiation>
|
||||
</ipxact:instantiations>
|
||||
<ipxact:ports>
|
||||
<ipxact:port>
|
||||
<ipxact:name>ninit_done</ipxact:name>
|
||||
<ipxact:wire>
|
||||
<ipxact:direction>out</ipxact:direction>
|
||||
<ipxact:vectors></ipxact:vectors>
|
||||
<ipxact:wireTypeDefs>
|
||||
<ipxact:wireTypeDef>
|
||||
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
|
||||
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
|
||||
</ipxact:wireTypeDef>
|
||||
</ipxact:wireTypeDefs>
|
||||
</ipxact:wire>
|
||||
</ipxact:port>
|
||||
</ipxact:ports>
|
||||
</ipxact:model>
|
||||
<ipxact:vendorExtensions>
|
||||
<altera:entity_info>
|
||||
<ipxact:vendor>Altera</ipxact:vendor>
|
||||
<ipxact:library>user_rst_clkgate_0</ipxact:library>
|
||||
<ipxact:name>intel_user_rst_clkgate</ipxact:name>
|
||||
<ipxact:version>1.0.1</ipxact:version>
|
||||
</altera:entity_info>
|
||||
<altera:altera_module_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="outputType" type="string">
|
||||
<ipxact:name>outputType</ipxact:name>
|
||||
<ipxact:displayName>Type of reset output port</ipxact:displayName>
|
||||
<ipxact:value>Conduit Interface</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
|
||||
<ipxact:name>DEVICE_FAMILY</ipxact:name>
|
||||
<ipxact:displayName>Device family</ipxact:displayName>
|
||||
<ipxact:value>Agilex 5</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_module_parameters>
|
||||
<altera:altera_system_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="board" type="string">
|
||||
<ipxact:name>board</ipxact:name>
|
||||
<ipxact:displayName>Board</ipxact:displayName>
|
||||
<ipxact:value>default</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="device" type="string">
|
||||
<ipxact:name>device</ipxact:name>
|
||||
<ipxact:displayName>Device</ipxact:displayName>
|
||||
<ipxact:value>A5EB013BB23BE4SCS</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceFamily" type="string">
|
||||
<ipxact:name>deviceFamily</ipxact:name>
|
||||
<ipxact:displayName>Device family</ipxact:displayName>
|
||||
<ipxact:value>Agilex 5</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
|
||||
<ipxact:name>deviceSpeedGrade</ipxact:name>
|
||||
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
|
||||
<ipxact:value>6</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="generationId" type="int">
|
||||
<ipxact:name>generationId</ipxact:name>
|
||||
<ipxact:displayName>Generation Id</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="bonusData" type="string">
|
||||
<ipxact:name>bonusData</ipxact:name>
|
||||
<ipxact:displayName>bonusData</ipxact:displayName>
|
||||
<ipxact:value>bonusData
|
||||
{
|
||||
element $system
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Agilex 5";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element intel_user_rst_clkgate_inst
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
|
||||
<ipxact:name>hideFromIPCatalog</ipxact:name>
|
||||
<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
|
||||
<ipxact:name>lockedInterfaceDefinition</ipxact:name>
|
||||
<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
|
||||
<ipxact:value><boundaryDefinition>
|
||||
<interfaces>
|
||||
<interface>
|
||||
<name>ninit_done</name>
|
||||
<type>conduit</type>
|
||||
<isStart>false</isStart>
|
||||
<ports>
|
||||
<port>
|
||||
<name>ninit_done</name>
|
||||
<role>ninit_done</role>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<lowerBound>0</lowerBound>
|
||||
<vhdlType>STD_LOGIC</vhdlType>
|
||||
<terminationValue>0</terminationValue>
|
||||
</port>
|
||||
</ports>
|
||||
<assignments>
|
||||
<assignmentValueMap/>
|
||||
</assignments>
|
||||
<parameters>
|
||||
<parameterValueMap>
|
||||
<entry>
|
||||
<key>associatedClock</key>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>associatedReset</key>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>prSafe</key>
|
||||
<value>false</value>
|
||||
</entry>
|
||||
</parameterValueMap>
|
||||
</parameters>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</boundaryDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="systemInfos" type="string">
|
||||
<ipxact:name>systemInfos</ipxact:name>
|
||||
<ipxact:displayName>systemInfos</ipxact:displayName>
|
||||
<ipxact:value><systemInfosDefinition>
|
||||
<connPtSystemInfos/>
|
||||
</systemInfosDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="dflBitArray" type="string">
|
||||
<ipxact:name>dflBitArray</ipxact:name>
|
||||
<ipxact:displayName>dflBitArray</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="cpuInfo" type="string">
|
||||
<ipxact:name>cpuInfo</ipxact:name>
|
||||
<ipxact:displayName>cpuInfo</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_system_parameters>
|
||||
<altera:altera_interface_boundary>
|
||||
<altera:interface_mapping altera:name="ninit_done" altera:internal="intel_user_rst_clkgate_inst.ninit_done" altera:type="conduit" altera:dir="end">
|
||||
<altera:port_mapping altera:name="ninit_done" altera:internal="ninit_done"></altera:port_mapping>
|
||||
</altera:interface_mapping>
|
||||
</altera:altera_interface_boundary>
|
||||
<altera:altera_has_warnings>false</altera:altera_has_warnings>
|
||||
<altera:altera_has_errors>false</altera:altera_has_errors>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:component>
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// +-----------------------------------------------------------
|
||||
// | Nadder LSM GPO
|
||||
// +-----------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
module intel_user_rst_clkgate(
|
||||
output logic ninit_done
|
||||
);
|
||||
|
||||
localparam USER_RESET_DELAY = 20;
|
||||
|
||||
altera_agilex_config_reset_release_endpoint config_reset_release_endpoint(
|
||||
.conf_reset(ninit_done)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
+37
@@ -0,0 +1,37 @@
|
||||
# (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and other
|
||||
# software and tools, and its AMPP partner logic functions, and any output
|
||||
# files from any of the foregoing (including device programming or simulation
|
||||
# files), and any associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License Subscription
|
||||
# Agreement, Altera IP License Agreement, or other applicable
|
||||
# license agreement, including, without limitation, that your use is for the
|
||||
# sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
|
||||
#Create base clock with 100 MHz targetted for internal clocks if paths listed below found in the design
|
||||
|
||||
#Agilex
|
||||
#auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|agilexconfigreset|user_reset|sdm_gpo_out_user_reset~internal_ctrl_clock.reg
|
||||
|
||||
|
||||
set intrl_ctrl_reg_count 0
|
||||
|
||||
set intrl_ctrl_reg_collection [get_registers -nowarn "auto_fab*\|*\|*sdm_gpo_out_user_reset~internal_ctrl_clock.reg"]
|
||||
|
||||
set intrl_ctrl_reg_count [ get_collection_size $intrl_ctrl_reg_collection ]
|
||||
|
||||
|
||||
|
||||
if {$intrl_ctrl_reg_count > 0 && ![get_collection_size [get_clocks -nowarn {internal_clk}]]} {
|
||||
|
||||
create_clock -name internal_clk -period 10.000 -waveform {0.000 5.000} { auto_fab*|*|*sdm_gpo_out_user_reset~internal_ctrl_clock.reg }
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks {internal_clk}]
|
||||
|
||||
set intrl_clock_count [get_collection_size [get_clocks internal_clk]]
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
// user_rst_clkgate_0.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module user_rst_clkgate_0 (
|
||||
output wire ninit_done // ninit_done.ninit_done
|
||||
);
|
||||
|
||||
intel_user_rst_clkgate intel_user_rst_clkgate_inst (
|
||||
.ninit_done (ninit_done) // output, width = 1, ninit_done.ninit_done
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,6 @@
|
||||
component user_rst_clkgate_0 is
|
||||
port (
|
||||
ninit_done : out std_logic -- ninit_done
|
||||
);
|
||||
end component user_rst_clkgate_0;
|
||||
|
||||
@@ -0,0 +1,137 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for user_rst_clkgate_0</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">user_rst_clkgate_0</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.05.11.21:03:48</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_intel_user_rst_clkgate_inst"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>intel_user_rst_clkgate_inst</h2>intel_user_rst_clkgate v1.0.1
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">outputType</td>
|
||||
<td class="parametervalue">Conduit Interface</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.04 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,41 @@
|
||||
<?xml version="1.0" ?>
|
||||
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
|
||||
<instanceKey xsi:type="xs:string">user_rst_clkgate_0</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters></parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>user_rst_clkgate_0</className>
|
||||
<version>1.0</version>
|
||||
<name>user_rst_clkgate_0</name>
|
||||
<uniqueName>user_rst_clkgate_0</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
</instanceData>
|
||||
<children>
|
||||
<node>
|
||||
<instanceKey xsi:type="xs:string">intel_user_rst_clkgate_inst</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters>
|
||||
<parameter>
|
||||
<name>DEVICE_FAMILY</name>
|
||||
<value>Agilex 5</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>outputType</name>
|
||||
<value>Conduit Interface</value>
|
||||
</parameter>
|
||||
</parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>intel_user_rst_clkgate</className>
|
||||
<version>1.0.1</version>
|
||||
<name>intel_user_rst_clkgate_inst</name>
|
||||
<uniqueName>intel_user_rst_clkgate</uniqueName>
|
||||
<fixedName>intel_user_rst_clkgate</fixedName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
<path>user_rst_clkgate_0.intel_user_rst_clkgate_inst</path>
|
||||
</instanceData>
|
||||
<children></children>
|
||||
</node>
|
||||
</children>
|
||||
</node>
|
||||
@@ -0,0 +1,44 @@
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TOOL_VENDOR_NAME "Altera"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TOP_LEVEL_COMPONENT_NAME "intel_user_rst_clkgate"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name PRE_COMPILED_MODULE "ON"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name OCS_IP_FILE [file join $::quartus(qip_path) "../user_rst_clkgate_0.ip"]
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name OCS_IP_TYPE "intel_user_rst_clkgate"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name OCS_IP_VERSION "1.0.1"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name OCS_IP_HASH "nvr4dnq"
|
||||
set_global_assignment -library "user_rst_clkgate_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "user_rst_clkgate_0.sopcinfo"]
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name SLD_INFO "QSYS_NAME user_rst_clkgate_0 HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "user_rst_clkgate_0" -name MISC_FILE [file join $::quartus(qip_path) "user_rst_clkgate_0.cmp"]
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "user_rst_clkgate_0" -name MISC_FILE [file join $::quartus(qip_path) "../user_rst_clkgate_0.ip"]
|
||||
|
||||
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_NAME "aW50ZWxfdXNlcl9yc3RfY2xrZ2F0ZQ=="
|
||||
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_DISPLAY_NAME "UmVzZXQgUmVsZWFzZSBJUA=="
|
||||
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_INTERNAL "On"
|
||||
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
|
||||
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_VERSION "MS4wLjE="
|
||||
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_DESCRIPTION "VGhpcyBJUCBvdXRwdXRzIG5JTklUX0RPTkUgYWZ0ZXIgZmluaXNoaW5nIGRldmljZSBpbml0YWxpemF0aW9uLiBVc2VyIG1vZGUgaW5pdGlhbGl6YXRpb24gY2FuIGJlZ2luIGFzIHNvb24gYXMgdGhlIG5JTklUX0RPTkUgc2lnbmFsIGFzc2VydHMu"
|
||||
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0NvbmZpZ3VyYXRpb24gYW5kIFByb2dyYW1taW5n"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_NAME "dXNlcl9yc3RfY2xrZ2F0ZV8w"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
|
||||
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "intel_user_rst_clkgate_101" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate.sv"]
|
||||
set_instance_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name SDC_ENTITY_FILE [file join $::quartus(qip_path) "intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate_agilex.sdc"] -no_sdc_promotion -no_auto_inst_discovery
|
||||
set_global_assignment -library "user_rst_clkgate_0" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/user_rst_clkgate_0.v"]
|
||||
|
||||
|
||||
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_TOOL_NAME "intel_user_rst_clkgate"
|
||||
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_TOOL_VERSION "1.0.1"
|
||||
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
|
||||
@@ -0,0 +1,198 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport
|
||||
name="user_rst_clkgate_0"
|
||||
kind="user_rst_clkgate_0"
|
||||
version="1.0"
|
||||
fabric="QSYS">
|
||||
<!-- Format version 26.1 110 (Future versions may contain additional information.) -->
|
||||
<!-- 2026.05.11.21:03:49 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_UNIQUE_ID">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE">
|
||||
<type>java.lang.String</type>
|
||||
<value>A5EB013BB23BE4SCS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
||||
<type>java.lang.String</type>
|
||||
<value>4</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_BOARD">
|
||||
<type>java.lang.String</type>
|
||||
<value>default</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>BOARD</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="intel_user_rst_clkgate_inst"
|
||||
kind="intel_user_rst_clkgate"
|
||||
version="1.0.1"
|
||||
entity="intel_user_rst_clkgate"
|
||||
library="intel_user_rst_clkgate_101"
|
||||
path="intel_user_rst_clkgate_inst"
|
||||
hpath="intel_user_rst_clkgate_inst"
|
||||
className="intel_user_rst_clkgate">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="outputType">
|
||||
<type>java.lang.String</type>
|
||||
<value>Conduit Interface</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="ninit_done" kind="conduit_end" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="prSafe">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>conduit</type>
|
||||
<span>0</span>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>ninit_done</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>ninit_done</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>intel_user_rst_clkgate</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>Reset Release IP</displayName>
|
||||
<version>1.0.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>conduit_end</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Conduit</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<reportVersion>26.1 110</reportVersion>
|
||||
<uniqueIdentifier></uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
@@ -0,0 +1,113 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.05.11.21:03:49"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5EB013BB23BE4SCS"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="6"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="ninit_done" kind="conduit" start="0">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="associatedReset" value="" />
|
||||
<property name="prSafe" value="false" />
|
||||
<port name="ninit_done" direction="output" role="ninit_done" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity kind="user_rst_clkgate_0" version="1.0" name="user_rst_clkgate_0">
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/synth/user_rst_clkgate_0.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/synth/user_rst_clkgate_0.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/pgm/intel_user_rst_clkgate/intel_user_rst_clkgate_hw.tcl" />
|
||||
</childSourceFiles>
|
||||
<messages>
|
||||
<message level="Info" culprit="user_rst_clkgate_0">"Generating: user_rst_clkgate_0"</message>
|
||||
<message level="Info" culprit="user_rst_clkgate_0">"Generating: intel_user_rst_clkgate"</message>
|
||||
<message level="Info" culprit="intel_user_rst_clkgate_inst">generating top-level entity intel_user_rst_clkgate</message>
|
||||
</messages>
|
||||
</entity>
|
||||
<entity
|
||||
kind="intel_user_rst_clkgate"
|
||||
version="1.0.1"
|
||||
name="intel_user_rst_clkgate">
|
||||
<parameter name="DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="outputType" value="Conduit Interface" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate.sv"
|
||||
attributes="TOP_LEVEL_FILE" />
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate_agilex.sdc"
|
||||
attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate.sv"
|
||||
attributes="TOP_LEVEL_FILE" />
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate_agilex.sdc"
|
||||
attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/pgm/intel_user_rst_clkgate/intel_user_rst_clkgate_hw.tcl" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<instantiator instantiator="user_rst_clkgate_0" as="intel_user_rst_clkgate_inst" />
|
||||
<messages>
|
||||
<message level="Info" culprit="user_rst_clkgate_0">"Generating: intel_user_rst_clkgate"</message>
|
||||
<message level="Info" culprit="intel_user_rst_clkgate_inst">generating top-level entity intel_user_rst_clkgate</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
@@ -0,0 +1,5 @@
|
||||
module user_rst_clkgate_0 (
|
||||
output wire ninit_done // ninit_done.ninit_done
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: user_rst_clkgate_0.intel_user_rst_clkgate_inst: You are using the Reset Release IP called intel_user_rst_clkgate which is now no longer active in IP catalog. Please use the Reset Release IP named altera_s10_user_rst_clkgate.
|
||||
Info: user_rst_clkgate_0: "Transforming system: user_rst_clkgate_0"
|
||||
Info: user_rst_clkgate_0: "Naming system components in system: user_rst_clkgate_0"
|
||||
Info: user_rst_clkgate_0: "Processing generation queue"
|
||||
Info: user_rst_clkgate_0: "Generating: user_rst_clkgate_0"
|
||||
Info: user_rst_clkgate_0: "Generating: intel_user_rst_clkgate"
|
||||
Info: intel_user_rst_clkgate_inst: generating top-level entity intel_user_rst_clkgate
|
||||
Info: user_rst_clkgate_0: Done "user_rst_clkgate_0" with 2 modules, 3 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,12 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: user_rst_clkgate_0.intel_user_rst_clkgate_inst: You are using the Reset Release IP called intel_user_rst_clkgate which is now no longer active in IP catalog. Please use the Reset Release IP named altera_s10_user_rst_clkgate.
|
||||
Info: user_rst_clkgate_0: "Transforming system: user_rst_clkgate_0"
|
||||
Info: user_rst_clkgate_0: "Naming system components in system: user_rst_clkgate_0"
|
||||
Info: user_rst_clkgate_0: "Processing generation queue"
|
||||
Info: user_rst_clkgate_0: "Generating: user_rst_clkgate_0"
|
||||
Info: user_rst_clkgate_0: "Generating: intel_user_rst_clkgate"
|
||||
Info: intel_user_rst_clkgate_inst: generating top-level entity intel_user_rst_clkgate
|
||||
Info: user_rst_clkgate_0: Done "user_rst_clkgate_0" with 2 modules, 3 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,4 @@
|
||||
user_rst_clkgate_0 u0 (
|
||||
.ninit_done (_connected_to_ninit_done_) // output, width = 1, ninit_done.ninit_done
|
||||
);
|
||||
|
||||
@@ -0,0 +1,11 @@
|
||||
component user_rst_clkgate_0 is
|
||||
port (
|
||||
ninit_done : out std_logic -- ninit_done
|
||||
);
|
||||
end component user_rst_clkgate_0;
|
||||
|
||||
u0 : component user_rst_clkgate_0
|
||||
port map (
|
||||
ninit_done => CONNECTED_TO_ninit_done -- ninit_done.ninit_done
|
||||
);
|
||||
|
||||
Reference in New Issue
Block a user