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Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

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Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder
XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog
TBs, fidelity attribution tooling. Functional baseline before removing the dead
bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
thejayman77
2026-07-20 19:56:46 -04:00
parent ec82764bef
commit ba74bbd5aa
476 changed files with 696247 additions and 130119 deletions
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synth/de25_nano/top_psmct32_raster_demo/build_quartus.sh
+36 -30
View File
@@ -69,33 +69,26 @@ echo ""
echo "=== Re-baking .mem fixtures ==="
make -C "$REPO_ROOT/sim" --no-print-directory top_psmct32_raster_demo_mem
# Quartus runs from the repo root because the QSF references RTL via
# repo-root-relative paths (rtl/...). The project name is the QSF
# basename, but the $QSF_DIR/PROJECT.qsf path is the absolute file.
# Quartus's `-project` flag wants the project base path (no .qsf
# suffix). With Quartus Pro, we run from the project dir and the file
# paths inside the QSF resolve via PROJECT_OUTPUT_DIRECTORY +
# implicit project-relative search.
#
# Strategy: copy the QSF to a working directory at the repo root so
# that (a) the SYSTEMVERILOG_FILE rtl/... paths resolve and (b)
# Quartus puts its db/ and output_files/ under the project dir, not
# the repo root.
WORK_DIR="$QSF_DIR/work"
mkdir -p "$WORK_DIR"
# Symlink the QSF + SDC into the work dir (Quartus reads them from
# the dir it's invoked in by default), then symlink the rtl/ + sim/
# dirs so the QSF's relative paths resolve.
ln -sfn "$QSF_DIR/$PROJECT.qsf" "$WORK_DIR/$PROJECT.qsf"
ln -sfn "$QSF_DIR/$PROJECT.sdc" "$WORK_DIR/$PROJECT.sdc"
ln -sfn "$REPO_ROOT/rtl" "$WORK_DIR/rtl"
ln -sfn "$REPO_ROOT/sim" "$WORK_DIR/sim"
# Ch161 — IOPLL `.qip` references its synth/ subdir via paths
# relative to the .qip's own location. The QSF's QIP_FILE entry
# uses `ip/pll/pll.qip` (relative to the work dir), so symlink
# the synth-project's `ip/` tree into the work dir alongside
# `rtl/` and `sim/`.
ln -sfn "$QSF_DIR/ip" "$WORK_DIR/ip"
# The QSF deliberately mixes project-relative sources (`rtl/`, `sim/`,
# `qsys/`, `ip/`) with a sibling-repository source path
# (`../../../../retroDE_splash`). Run Quartus from the QSF directory so
# both path families retain their authored meaning. A former nested
# `work/` directory shifted the sibling path by one level and also omitted
# qsys/, making otherwise valid source trees appear missing during
# elaboration.
WORK_DIR="$QSF_DIR"
for required_path in rtl sim qsys ip; do
if [ ! -e "$WORK_DIR/$required_path" ]; then
echo "error: required Quartus source path missing: $WORK_DIR/$required_path" >&2
exit 1
fi
done
if [ ! -d "$REPO_ROOT/../retroDE_splash" ]; then
echo "error: sibling retroDE_splash checkout is required by the QSF" >&2
exit 1
fi
cd "$WORK_DIR"
@@ -217,7 +210,20 @@ else
if run_step "quartus_asm" \
"$QUARTUS/quartus_asm $PROJECT -c $PROJECT"
then
ASM_RC=0
# Direct quartus_asm invocation does not execute the QSF
# POST_FLOW_SCRIPT_FILE hook (that hook is normally dispatched by
# quartus_sh --flow compile). Run it explicitly so a successful
# command-line build always produces the loader-ready split RBF,
# not merely the .sof.
if run_step "post_flow" \
"$QUARTUS/quartus_sh -t post_flow.tcl quartus_asm $PROJECT $PROJECT" && \
[ -s "$OUT_DIR/retroDE_ps2.core.rbf" ]
then
ASM_RC=0
else
ASM_RC=2
echo "FAIL: assembler completed but loader-ready retroDE_ps2.core.rbf was not produced"
fi
else
ASM_RC=$?
fi
@@ -226,8 +232,8 @@ else
fi
fi
# Move output_files from work dir into the canonical location.
if [ -d "$WORK_DIR/output_files" ]; then
# Move output_files from a distinct work dir into the canonical location.
if [ "$WORK_DIR" != "$QSF_DIR" ] && [ -d "$WORK_DIR/output_files" ]; then
rsync -a --remove-source-files "$WORK_DIR/output_files/" "$OUT_DIR/" 2>/dev/null || \
cp -a "$WORK_DIR/output_files/." "$OUT_DIR/"
fi
synth/de25_nano/top_psmct32_raster_demo/de25_nano_psmct32_raster_demo_top.qsf
+18 -7
View File
@@ -857,8 +857,8 @@ set_location_assignment PIN_BC67 -to HPS_USB_STP
# demos (bios_clut/textured/alpha/zbuffer/triangle/tritex) keep GS_RMW_DEMO
# and drop the GS_*_DEMO line entirely.
# >>> DE25_PROFILE_FIXTURE (managed by scripts/select_de25_profile.sh — do not hand-edit) >>>
set_global_assignment -name VERILOG_MACRO "TOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE=\"sim/data/top_psmct32_raster_demo/bios_sh3_real.mem\""
set_global_assignment -name VERILOG_MACRO "TOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE=\"sim/data/top_psmct32_raster_demo/payload_sh3_real.mem\""
set_global_assignment -name VERILOG_MACRO "TOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE=\"sim/data/top_psmct32_raster_demo/bios_sh3_zs640c6.mem\""
set_global_assignment -name VERILOG_MACRO "TOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE=\"sim/data/top_psmct32_raster_demo/payload_sh3_zs640c6.mem\""
# <<< DE25_PROFILE_FIXTURE <<<
set_global_assignment -name VERILOG_MACRO "GS_RMW_DEMO=1"
# Ch305: MULTI-PRIMITIVE tiled scene over the 2x2 grid (3 combined prims per tile:
@@ -918,9 +918,10 @@ set_global_assignment -name VERILOG_MACRO "GS_RMW_DEMO=1"
# to the Ch321 128x128 LPDDR scanout demo: restore GS_TILE_LPDDR128_DEMO=1, drop the
# two Ch322 macros, and point the .mem paths back at bios/payload_tile_lpddr128.
# >>> DE25_PROFILE_SCENE (managed by scripts/select_de25_profile.sh — do not hand-edit) >>>
set_global_assignment -name VERILOG_MACRO "GS_SH3_REAL_DRAW_DEMO=1"
set_global_assignment -name VERILOG_MACRO "GS_SH3_LPDDR_FB=1"
set_global_assignment -name VERILOG_MACRO "GS_SH3_LPDDR_FB_Z=1"
set_global_assignment -name VERILOG_MACRO "GS_SH3_LPDDR_FB_640=1"
set_global_assignment -name VERILOG_MACRO "GS_LPDDR_TEX=1"
set_global_assignment -name VERILOG_MACRO "FEEDER_STG_INIT_FILE=\"sim/data/top_psmct32_raster_demo/feeder_sh3_real.mem\""
# <<< DE25_PROFILE_SCENE <<<
set_global_assignment -name VERILOG_MACRO "GS_LPDDR_FB=1"
# Ch319 Brick 1 — bring up the FPGA-private LPDDR4B EMIF (EMIF_Qsys) + prove calibration.
@@ -978,11 +979,15 @@ set_instance_assignment -name PRESERVE_FANOUT_FREE_NODE ON -to soc_inst|subsys_h
# fabric-driven config.
# ----------------------------------------------------------------------------
set_global_assignment -name HPS_INITIALIZATION "HPS FIRST"
# Area-focused synthesis — the fitter overflows on LAB capacity (placement),
# not timing (demo clocks are slow, large Fmax margin), so optimize for area
# and let Quartus share arithmetic/resources to recover LABs.
# Area-focused synthesis — the fitter is constrained by LAB placement, so
# optimize for area and permit arithmetic/resource sharing. Ch439f compiled
# AUTO_RESOURCE_SHARING=OFF from fresh synthesis through route and produced an
# identical netlist, resource count, placement, and timing path; sharing was
# therefore not the source of the tap-to-texture-cache STA arc.
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
set_global_assignment -name AUTO_RESOURCE_SHARING ON
# Ch357 (Codex) — SEED left at default (1): seed 1 gave -0.019 (quasi-static EMIF-lock ONLY, all real datapaths met);
# seed 2 was worse (-0.155, exposed a different marginal path). The last sliver is closed via the scoped false-path in the SDC.
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_125MHZ
set_global_assignment -name USE_CONF_DONE SDM_IO16
@@ -1026,6 +1031,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_persp_uv.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_tile_ram.sv
# Brick 2a — alpha-blend (transparency) unit, instantiated inside gs_stub.
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_alpha_blend.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_color_blend.sv
# Ch317/Ch318 — LPDDR framebuffer paths. gs_lpddr_axi_master (+ gs_async_fifo) is the
# board write path (GS_LPDDR_FB); gs_lpddr_fb_writer is the Ch317 sim model, gen-guarded
# OFF (LPDDR_FB_ENABLE=0) in the board build but listed so the source set is complete.
@@ -1042,6 +1048,10 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_wr_arb.sv
# Ch323 — tile COLOR+Z spill/reload (instantiated under GS_TILE_SPILL; idle otherwise).
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_z_flush_writer.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_tile_reload.sv
# Ch357 — persistent-Z ROP (instantiated under GS_SH3_LPDDR_FB_Z; idle otherwise). map_pkg first (package).
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_map_pkg.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_z_rmw.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_zc_emit.sv
# ----------------------------------------------------------------------------
# Design RTL added during the EE/qbert chapters (Ch287+) that reached the demo
# hierarchy (via ee_memory_map_stub) but were only added to the SIM build, not
@@ -1094,6 +1104,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/platform/ps2_hps_bridge_null.
# 0x00C CORE_CAPS, 0x010/0x014 CORE_CTRL/CORE_PULSE (read-zero stubs),
# 0x020 FRAME_COUNT, 0x024 DMA_DONE_COUNT, 0x028 RASTER_OVERFLOW_COUNT.
set_global_assignment -name SYSTEMVERILOG_FILE rtl/platform/ps2_hps_bridge.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/platform/clut_stage_cdc.sv
# Ch250 — PS2-fabric input consumer. Brings sio2_input_stub onto the
# synth top so bridge_input_p1_raw reaches a live fabric reader (Ch234
# built this module sim-only; Ch241 documented that the synth top
synth/de25_nano/top_psmct32_raster_demo/de25_nano_psmct32_raster_demo_top.sdc
+304 -43
View File
@@ -95,6 +95,24 @@ set_clock_groups -asynchronous \
-group [get_clocks {CLOCK1_50}] \
-group [get_clocks {CLOCK2_50}]
# ----------------------------------------------------------------------------
# Ch357 (Codex) — the HDMI I2C config FSM's internal work clock. I2C_HDMI_Config
# toggles mI2C_CTRL_CLK every 2501 CLOCK2_50 cycles (mI2C_CLK_DIV counts
# 0..CLK_Freq/I2C_Freq=2500, then resets+toggles), so its FULL period is a
# divide-by-5002 of CLOCK2_50. It clocks the I2C_Controller + the config FSM
# (.CLK(mI2C_CTRL_CLK) / posedge mI2C_CTRL_CLK), so it is a REAL generated clock —
# false-pathing the HDMI *pins* does NOT constrain it, which is why the last STA
# reported it unconstrained. Constrain it (~10 kHz class, trivially met) with a
# FATAL target-count check so a renamed register cannot silently orphan it. No
# extra cross-domain cut is needed: the module is a self-contained CLOCK2_50-rooted
# config sequencer whose only outputs are the already-false-pathed HDMI I2C pins.
# ----------------------------------------------------------------------------
set i2c_ctrl_clk_reg [get_registers -nowarn {u_hdmi_i2c|mI2C_CTRL_CLK}]
set i2c_ctrl_clk_n [get_collection_size $i2c_ctrl_clk_reg]
if { $i2c_ctrl_clk_n != 1 } { error "Ch357 SDC FATAL: u_hdmi_i2c|mI2C_CTRL_CLK register count $i2c_ctrl_clk_n != 1 (renamed? generated clock would orphan and STA would flag it unconstrained)" }
create_generated_clock -name mI2C_CTRL_CLK -source [get_ports {CLOCK2_50}] -divide_by 5002 $i2c_ctrl_clk_reg
post_message -type info "Ch357 SDC: mI2C_CTRL_CLK generated clock (divide-by-5002 of CLOCK2_50) applied to $i2c_ctrl_clk_n register"
# ----------------------------------------------------------------------------
# Reset synchronizer — async assert, sync deassert. BOTH stages of
# `rst_sync` are async-cleared by `(ninit_done | ~pll_locked)`, not
@@ -115,6 +133,33 @@ set_clock_groups -asynchronous \
# ----------------------------------------------------------------------------
set_false_path -to [get_registers -nowarn {*rst_sync[*]}]
# HPS CORE_CTRL reset request is a CLOCK2_50-domain level sampled by the
# explicit two-flop hps_reset_sync chain in design_clk. Cut only the first
# synchronizer stage; the second stage remains timed normally. Without this
# CDC exception TimeQuest compares unrelated refclk/outclk edges and reports a
# placement-dependent multi-nanosecond hold violation on an otherwise correct
# synchronizer.
set hps_reset_sync0 [get_registers -nowarn {*hps_reset_sync[0]}]
set hps_reset_sync0_n [get_collection_size $hps_reset_sync0]
if { $hps_reset_sync0_n != 1 } { error "SDC FATAL: hps_reset_sync[0] count $hps_reset_sync0_n != 1" }
set_false_path -to $hps_reset_sync0
post_message -type info "SDC: HPS core-reset CDC cut to first synchronizer stage ($hps_reset_sync0_n register)"
# The runtime CLUT commit and OSD tile-write event are bridge/refclk-domain
# toggles received by explicit three-stage design-clock synchronizers. Time
# only stages 1->2 internally; the asynchronous source->stage-0 paths have no
# meaningful setup/hold relationship. Target counts are fatal so hierarchy
# drift cannot silently broaden or orphan these cuts.
set clut_commit_sync0 [get_registers -nowarn {u_runtime_clut|commit_sync[0]}]
set tile_toggle_sync0 [get_registers -nowarn {u_tile_cdc|toggle_sync[0]}]
set clut_commit_sync0_n [get_collection_size $clut_commit_sync0]
set tile_toggle_sync0_n [get_collection_size $tile_toggle_sync0]
if { $clut_commit_sync0_n != 1 } { error "SDC FATAL: CLUT commit synchronizer stage-0 count $clut_commit_sync0_n != 1" }
if { $tile_toggle_sync0_n != 1 } { error "SDC FATAL: tile toggle synchronizer stage-0 count $tile_toggle_sync0_n != 1" }
set_false_path -to $clut_commit_sync0
set_false_path -to $tile_toggle_sync0
post_message -type info "SDC: explicit toggle CDC cuts applied to CLUT=$clut_commit_sync0_n tile=$tile_toggle_sync0_n first stages"
# ----------------------------------------------------------------------------
# gs_async_fifo gray-pointer CDC (Ch324). The dual-clock FIFOs (gs_z_flush_writer
# color/Z spill, gs_lpddr_axi_master FB writer, scanout) cross design_clk (u_pll,
@@ -131,8 +176,23 @@ set_false_path -to [get_registers -nowarn {*rst_sync[*]}]
# sync skew well under the fast emif period (3.225 ns) forces the tool to place the gray
# bits compactly for EVERY gs_async_fifo instance, so at most one bit is ever in flight ->
# the 2-FF synchronizers handle metastability normally. (1.0 ns << both clock periods.)
set_max_skew -from {*wgray[*]} -to {*wgray_s1[*]} 1.0
set_max_skew -from {*rgray[*]} -to {*rgray_s1[*]} 1.0
# Ch357 (Codex) — PER-INSTANCE gray-skew. Keep the global 1 ns for every gs_async_fifo EXCEPT the two Z-path FIFOs
# (u_zc_emit request FIFO + its color-writer FIFO): those route into the fast 310 MHz EMIF domain and route+placement
# put them just over 1 ns (worst -0.346). Give THEM a justified 2 ns bound — still < the 3.225 ns fast-source period, so
# at most one gray bit is ever in flight and the 2-FF synchronizers handle metastability normally. Overlapping
# set_max_skew take the TIGHTEST, so the Z FIFOs are CARVED OUT of the global 1 ns set (remove_from_collection) — the
# broad rule must not keep overriding the 2 ns exception.
set z_wgray [get_keepers -nowarn {*u_zc_emit|*wgray[*]}]
set z_rgray [get_keepers -nowarn {*u_zc_emit|*rgray[*]}]
set other_wgray [remove_from_collection [get_keepers -nowarn {*wgray[*]}] $z_wgray]
set other_rgray [remove_from_collection [get_keepers -nowarn {*rgray[*]}] $z_rgray]
set_max_skew -from $other_wgray -to {*wgray_s1[*]} 1.0
set_max_skew -from $other_rgray -to {*rgray_s1[*]} 1.0
set_max_skew -from {*u_zc_emit|*wgray[*]} -to {*u_zc_emit|*wgray_s1[*]} 2.0
set_max_skew -from {*u_zc_emit|*rgray[*]} -to {*u_zc_emit|*rgray_s1[*]} 2.0
set z_wgray_n [get_collection_size $z_wgray]
set z_rgray_n [get_collection_size $z_rgray]
post_message -type info "Ch357 SDC: gray-skew 1ns global (Z FIFOs carved out), 2ns for $z_wgray_n u_zc_emit wgray + $z_rgray_n rgray bits"
# ----------------------------------------------------------------------------
# Ch352 — design fabric <-> EMIF user clock are ASYNCHRONOUS (Codex). Every
@@ -154,23 +214,27 @@ set_max_skew -from {*rgray[*]} -to {*rgray_s1[*]} 1.0
# an empty/1-clock collection, the group never activated, and placement burned ~76
# min on the impossible fabric<->emif paths. The collection-size checks are now a
# FATAL Tcl `error` (not a warning): a renamed/mistyped clock HALTS SDC immediately.
# Ch352 DIAG — collections + fatal checks DISABLED with their constraints (orphaned otherwise).
# set ch352_fabric_clks [get_clocks -nowarn {u_pll|iopll_0_refclk u_pll|iopll_0_outclk0}]
# set ch352_emif_user [get_clocks -nowarn {u_emif_lpddr4b|iopll|iopll_0_outclk0}]
# Ch352 LEAD CHANGE — false_path (both directions) INSTEAD of set_clock_groups. The clock-group declared the
# EMIF user clock ASYNC to u_pll|iopll_0_refclk = CLOCK2_50 = the EMIF IP's OWN refclk source
# (iopll_refclk_clk(CLOCK2_50)). Declaring a GENERATED clock asynchronous to the clock that GENERATES it is the
# leading suspect for the fitter's pathological Place grind (June-26 placed in 19 min; the only timing-constraint
# deltas since are this group + the gradient multicycle, and "ample RAM still stalled" ruled out congestion).
# false_path CUTS the same fabric<->emif DATA paths — all RTL-synchronized (gray FIFOs + bridge snapshots + the
# gs_lpddr_axi_master commit snapshot) — WITHOUT re-declaring the clock relationship the EMIF IP owns. set_max_skew
# is a separate analysis and survives false_path, so the gray pointers stay bounded.
# Ch352 DIAG (binary SDC-vs-RTL bisect) — fabric<->EMIF cut DISABLED. RTL CDC synchronizers make these crossings
# safe regardless; STA will report the -5.7/-7.5ns false violations, which (like June-26's -66ns) do not block a
# working board. Re-enable after the bisect tells us whether the SDC was the Place grind.
# set_false_path -from $ch352_fabric_clks -to $ch352_emif_user
# set_false_path -from $ch352_emif_user -to $ch352_fabric_clks
# (post_message removed — it falsely claimed false_path was applied while the two lines above are commented out.)
# Ch357 — RESTORED (signoff-clean for the persistent-Z fit). The Ch352 diagnostic/bisect that commented these
# out is over: STA is being closed properly, so the fabric<->EMIF crossings are cut with a TARGETED bidirectional
# set_false_path (NOT the asynchronous clock-group, which declared a generated clock async to its own generator and
# triggered the Place grind). Every fabric<->emif transfer is RTL-synchronized (gray-pointer FIFOs [max_skew below],
# bridge status snapshots/toggle syncs, the gs_lpddr_axi_master commit snapshot + admission-stable AXI, the zc_emit
# request FIFO), so cutting the raw setup/hold analysis on these two clock relationships is correct. set_max_skew is
# a SEPARATE analysis that survives false_path, so the gray pointers stay bounded.
#
# FATAL collection-size checks (Codex): a renamed/mistyped clock would silently orphan the exception and let Place
# churn the impossible fabric<->emif paths, so HALT immediately if the collection sizes are wrong. Clock names pinned
# from the post-fit STA summary: fabric = {u_pll|iopll_0_refclk, u_pll|iopll_0_outclk0} (2), EMIF user =
# {u_emif_lpddr4b|iopll|iopll_0_outclk0} (1). Do NOT wildcard the EMIF PHY/internal clocks — the EMIF IP owns those.
set ch352_fabric_clks [get_clocks -nowarn {u_pll|iopll_0_refclk u_pll|iopll_0_outclk0}]
set ch352_emif_user [get_clocks -nowarn {u_emif_lpddr4b|iopll|iopll_0_outclk0}]
set ch352_fabric_n [get_collection_size $ch352_fabric_clks]
set ch352_emif_n [get_collection_size $ch352_emif_user]
if { $ch352_fabric_n != 2 } { error "Ch352 SDC FATAL: fabric clock collection size $ch352_fabric_n != 2 (clock renamed? fabric<->emif cut would orphan)" }
if { $ch352_emif_n != 1 } { error "Ch352 SDC FATAL: emif user clock collection size $ch352_emif_n != 1 (clock renamed? fabric<->emif cut would orphan)" }
set_false_path -from $ch352_fabric_clks -to $ch352_emif_user
set_false_path -from $ch352_emif_user -to $ch352_fabric_clks
post_message -type info "Ch357 SDC: fabric<->EMIF bidirectional false_path applied (fabric=$ch352_fabric_n clks, emif_user=$ch352_emif_n clk)"
# DEFERRED (Codex, acknowledged NOT hidden): the Ch323/324 tile-spill/reload + writer DEBUG counters at
# 0x080-0x0FC (spill_*_errs, dbg_z/c_*_count, feeder_addr) are read by the bridge directly from the emif
# domain and are now inside the async group above. They are explicitly DEFERRED "stable-after-scene
@@ -231,28 +295,225 @@ set_false_path -from [get_ports {HDMI_TX_INT}]
set_false_path -to [get_ports {HDMI_MCLK}]
# ----------------------------------------------------------------------------
# Ch352 — triangle-setup gradient divide is a MULTICYCLE path, terminated at ONE
# result register (Codex). gs_stub's gradient solve uses one shared combinational
# signed divide (grad_num_q[grad_step] / grad_det_q); the RTL holds the sources
# stable for GRAD_DIV_CYCLES=4 and captures the settled quotient into grad_result_q,
# which is then written to the selected gradient FIFO on the following (single-cycle)
# cycle. The exception DESTINATION is grad_result_q ALONE (~32 regs) — NOT the
# {*u_gs|fifo_d*} fields. The old fifo_d* wildcard matched 5120 destinations x 837
# sources (~4M endpoint pairs); the timing-driven placer churned on that matrix
# indefinitely (Place stalled <1% for 50min+). Targeting grad_result_q drops the
# matrix ~160x. The grad_result_q -> fifo write stays an ordinary single-cycle path.
# Ch357 — DS2 (PSX-style SPI) controller pins on the GPIO_0 header, driven by
# ds2_controller at the slow SPI bit-clock (async to design_clk; timing dominated
# by the SPI period, not the fabric clock). Same treatment as the HDMI I2C control
# pins — false-path so STA reports NO unconstrained I2C/DS2 ports (Codex signoff).
# ----------------------------------------------------------------------------
# Bind the collections to variables and make the DESTINATION count fatal: grad_result_q is (* preserve *)'d to
# exactly 32 regs. If synthesis still optimizes/renames it (count != 32) the exception would silently apply to
# NOTHING and Place would churn the -66ns divider — so HALT here (same fail-fast policy as the clock-name checks),
# before A&S->Place, instead of discovering a dead exception 50 minutes into Place.
# Ch352 DIAG — collections + fatal check DISABLED with the multicycle (orphaned otherwise). NOTE: the error
# string above had a Tcl `[31:0]` command-substitution bug that fired during routing once the check tripped.
# set grad_mc_from [get_keepers -nowarn {*u_gs|grad_num_q* *u_gs|grad_det_q* *u_gs|grad_step*}]
# set grad_mc_to [get_keepers -nowarn {*u_gs|grad_result_q*}]
# Ch352 DIAG (binary SDC-vs-RTL bisect) — gradient multicycle DISABLED. The RTL grad_settle holds the divide
# for GRAD_DIV_CYCLES=4 real cycles, so the divider is FUNCTIONALLY correct without this exception; STA will
# report the divide as a -66ns single-cycle path (false — same as June-26, which placed and ran). Re-enable
# after the bisect tells us whether the SDC was the Place grind.
# set_multicycle_path -setup -end 4 -from $grad_mc_from -to $grad_mc_to
# set_multicycle_path -hold -end 3 -from $grad_mc_from -to $grad_mc_to
set_false_path -to [get_ports {GPIO_0_DS2_CLK}]
set_false_path -to [get_ports {GPIO_0_DS2_CMD}]
set_false_path -to [get_ports {GPIO_0_DS2_ATTN}]
set_false_path -from [get_ports {GPIO_0_DS2_DATA}]
# ----------------------------------------------------------------------------
# Ch357 (Codex) — tile_ram_cdc bundled-bus CDC. The bridge writes {tile_wr_index, tile_wr_data} as a STABLE bus and the
# receiver samples it into shadow_mem ONLY after a 2-FF-synchronized toggle (tile_ram_cdc.sv:18 guarantees >=2 dclk of
# stability before the sample). So the raw HOLD check bridge->shadow_mem is FALSE (the bus never changes near the capture
# edge). Cut HOLD only (targeted, NOT a blanket clock waiver), and bound the datapath skew so the bus bits still arrive
# compactly inside the stability window. FATAL count checks so a rename can't silently orphan the exception.
# Cut the (spurious) HOLD only, then bound the ACTUAL requirement (Codex): the bus must arrive within the >=2 dclk
# stability window before the synchronized toggle samples it. set_max_skew alone bounds only bit-to-bit spread, NOT
# arrival. NOTE: `set_max_delay -datapath_only` is a Quartus Prime STANDARD option and DOES NOT EXIST in Pro 25.3.1
# (Error 332000 "Unknown option -datapath_only" aborts the fitter). The Pro-correct tool to bound CDC data-net arrival
# is `set_net_delay -max`, which bounds interconnect (routing) delay from source to destination. So the recipe is:
# HOLD false-path + set_max_skew (bit spread) + set_net_delay -max (arrival). Source = {tile_wr_index[9:0],
# tile_wr_data[31:0]} = 42 simple bridge regs (stable -> exact-count check); dest shadow_mem is M20K (nonzero check).
set tile_cdc_src [get_keepers -nowarn {*u_hps_bridge|tile_wr_data[*] *u_hps_bridge|tile_wr_index[*]}]
set tile_cdc_dst [get_keepers -nowarn {*u_tile_cdc|shadow_mem*}]
set tile_src_n [get_collection_size $tile_cdc_src]
set tile_dst_n [get_collection_size $tile_cdc_dst]
# This optional OSD tile path is correctly absent in profiles where the
# platform overlay is optimized away. Only a one-sided disappearance is an
# orphaned active CDC and therefore fatal; both sides absent needs no cut.
if { $tile_src_n == 0 && $tile_dst_n == 0 } {
post_message -type info "Ch357 SDC: tile_ram_cdc inactive in this profile (0 src, 0 dst)"
} else {
if { $tile_src_n != 42 } { error "Ch357 SDC FATAL: tile_ram_cdc source tile_wr_index+tile_wr_data count $tile_src_n != 42 (10+32; renamed/optimized? hold cut + net_delay would orphan)" }
if { $tile_dst_n == 0 } { error "Ch357 SDC FATAL: tile_ram_cdc dest u_tile_cdc|shadow_mem EMPTY (renamed? hold cut would orphan)" }
set_false_path -hold -from $tile_cdc_src -to $tile_cdc_dst
set_max_skew -from $tile_cdc_src -to $tile_cdc_dst 2.0
set_net_delay -max -from $tile_cdc_src -to $tile_cdc_dst 2.0
post_message -type info "Ch357 SDC: tile_ram_cdc hold-false-path + 2ns max_skew + 2ns net_delay ($tile_src_n src -> $tile_dst_n shadow_mem dst)"
}
# Ch357 (Codex) — osd_cfg QUASI-STATIC config CDC. osd_cfg{0,1}_q (bridge, refclk/fabric domain) cross into
# osd_cfg{0,1}_sync[0] (design_clk, first synchronizer stage; 2-FF, (* dont_merge, preserve *)). The config is quasi-
# static and resolved by the 2-FF sync -> CUT the async crossing INTO stage 0 (setup+hold). Do NOT touch sync[0]->sync[1]
# (the timed MTBF leg). Counts are NONZERO-checked, NOT exact: unused OSD_CFG bits are pruned, so the surviving sync FF
# count is < 64 (dst observed = 35). A nonzero check confirms the pattern binds without ever halting the fit on a count.
set osd_cfg_src [get_keepers -nowarn {*u_hps_bridge|osd_cfg0_q[*] *u_hps_bridge|osd_cfg1_q[*]}]
set osd_cfg_dst [get_keepers -nowarn {*osd_cfg0_sync[0][*] *osd_cfg1_sync[0][*]}]
set osd_src_n [get_collection_size $osd_cfg_src]
set osd_dst_n [get_collection_size $osd_cfg_dst]
if { $osd_src_n == 0 } { post_message -type warning "Ch357 SDC WARN: osd_cfg src pattern matched 0 keepers (renamed? osd_cfg false-path NOT applied)" }
if { $osd_dst_n == 0 } { post_message -type warning "Ch357 SDC WARN: osd_cfg dst pattern matched 0 keepers (renamed? osd_cfg false-path NOT applied)" }
set_false_path -from $osd_cfg_src -to $osd_cfg_dst
post_message -type info "Ch357 SDC: osd_cfg refclk->design_clk synchronizer false-path ($osd_src_n src -> $osd_dst_n stage0 dst)"
# Ch357 (Codex) — OSD MENU-STATE synchronizers (same quasi-static class as osd_cfg): cursor_row + osd_active cross
# refclk/menu -> design_clk via 2-FF (* dont_merge, preserve *) syncs. They change only on user menu input, never at the
# raster/EMIF rate. Cut the async input INTO the FIRST stage (sync[0]) only; sync[0]->sync[1] stays timed. Using -to (no
# -from) is the canonical synchronizer cut and needs no launch-reg name. Covers cursor_row (the -0.223 hold) + osd_active
# together so a future placement roll can't surface another OSD sync as the next hold. Nonzero-warn (never a fatal).
set osd_msync_dst [get_keepers -nowarn {*cursor_row_sync[0][*] *osd_active_sync[0]}]
set osd_msync_n [get_collection_size $osd_msync_dst]
if { $osd_msync_n == 0 } { post_message -type warning "Ch357 SDC WARN: OSD menu-state sync[0] matched 0 keepers (renamed? cursor_row/osd_active false-path NOT applied)" }
set_false_path -to $osd_msync_dst
post_message -type info "Ch357 SDC: OSD menu-state (cursor_row/osd_active) synchronizer stage-0 false-path ($osd_msync_n sync0 dst)"
# Ch397 — LPDDR control-commit toggle enters design_clk through a three-flop
# synchronizer. Cut only the asynchronous/quasi-static source -> stage-0 leg;
# commit_d_sync[0] -> [1] -> [2] remains timed for metastability settling.
set lpddr_commit_sync0 [get_keepers -nowarn {*commit_d_sync[0]}]
set lpddr_commit_sync0_n [get_collection_size $lpddr_commit_sync0]
if { $lpddr_commit_sync0_n == 0 } { post_message -type warning "Ch397 SDC WARN: commit_d_sync[0] matched 0 keepers (LPDDR commit sync cut NOT applied)" }
set_false_path -to $lpddr_commit_sync0
post_message -type info "Ch397 SDC: LPDDR commit synchronizer stage-0 false-path ($lpddr_commit_sync0_n sync0 dst)"
# Ch439 — LPDDR video-source is a one-bit bundled control crossing from the
# bridge/refclk domain into design_clk. The source is written before
# lpddr_ctrl_commit toggles; vsrc_cap_d samples it only after that toggle has
# traversed commit_d_sync. Consequently the raw zero-cycle HOLD relationship
# between the unrelated clocks is not functional. Cut HOLD only and retain a
# 2 ns interconnect bound so the data remains well inside the commit-toggle
# stability window. Setup remains analyzed.
set lpddr_vsrc_src [get_keepers -nowarn {*u_hps_bridge|lpddr_video_src_q}]
set lpddr_vsrc_dst [get_keepers -nowarn {*vsrc_cap_d}]
set lpddr_vsrc_src_n [get_collection_size $lpddr_vsrc_src]
set lpddr_vsrc_dst_n [get_collection_size $lpddr_vsrc_dst]
if { $lpddr_vsrc_src_n == 0 } { post_message -type warning "Ch439 SDC WARN: LPDDR video-src source matched 0 keepers (bundled-CDC hold cut NOT applied)" }
if { $lpddr_vsrc_dst_n == 0 } { post_message -type warning "Ch439 SDC WARN: vsrc_cap_d matched 0 keepers (bundled-CDC hold cut NOT applied)" }
set_false_path -hold -from $lpddr_vsrc_src -to $lpddr_vsrc_dst
set_net_delay -max -from $lpddr_vsrc_src -to $lpddr_vsrc_dst 2.0
post_message -type info "Ch439 SDC: LPDDR video-src bundled-CDC hold-false + 2ns net_delay ($lpddr_vsrc_src_n src -> $lpddr_vsrc_dst_n dst)"
# Ch357 (Codex) — feeder staging BUNDLED-BUS CDC (same shape as tile_ram_cdc). {feeder_waddr_q[11:0], feeder_wdata_q[63:0]}
# = 76 stable bits cross from the bridge (refclk) into the feeder staging RAM (design_clk), sampled ONLY after the
# feeder_stg_we toggle 2-FF-syncs (fdr_we_sync). Cut the spurious HOLD, bound bit spread (max_skew) + arrival (net_delay).
# All counts NONZERO-checked, never exact (no count can halt the fit). Expected src ~76 (waddr 12 + wdata 64); the actual
# is recorded in the post_message. dest = the staging RAM (altsyncram) write registers, nonzero. Also false-path the toggle.
set fdr_cdc_src [get_keepers -nowarn {*u_hps_bridge|feeder_wdata_q[*] *u_hps_bridge|feeder_waddr_q[*]}]
set fdr_cdc_dst [get_keepers -nowarn {*g_feeder*feeder_stg*}]
set fdr_src_n [get_collection_size $fdr_cdc_src]
set fdr_dst_n [get_collection_size $fdr_cdc_dst]
if { $fdr_src_n == 0 } { post_message -type warning "Ch357 SDC WARN: feeder src pattern matched 0 keepers (renamed? feeder-CDC NOT applied)" }
if { $fdr_dst_n == 0 } { post_message -type warning "Ch357 SDC WARN: feeder staging RAM dest EMPTY (pattern *g_feeder*feeder_stg* matched 0 keepers; feeder-CDC hold NOT constrained this run)" }
set_false_path -hold -from $fdr_cdc_src -to $fdr_cdc_dst
set_max_skew -from $fdr_cdc_src -to $fdr_cdc_dst 2.0
set_net_delay -max -from $fdr_cdc_src -to $fdr_cdc_dst 2.0
set fdr_tgl_dst [get_keepers -nowarn {*fdr_we_sync[0] *fdr_go_sync[0]}]
if { [get_collection_size $fdr_tgl_dst] > 0 } { set_false_path -to $fdr_tgl_dst }
post_message -type info "Ch357 SDC: feeder staging bundled-CDC hold-false + 2ns max_skew + 2ns net_delay ($fdr_src_n src -> $fdr_dst_n RAM dst)"
# Ch357 (Codex) — EMIF calibration-ready (lock) -> texture-cache RAM. emif_reset_n is the EMIF's calibrated/ready
# indicator (RTL comment: "low during cal, high when done"): QUASI-STATIC — it asserts once when calibration completes,
# BEFORE any texture access, and never toggles at runtime. Its lock synchronizer (lock_sync_inst|dreg) feeds the tex_mem
# init/reset, leaving a residual ~-0.019ns setup that is functionally irrelevant (the texcache is inactive until cal is
# stable). Cut the NARROWEST possible crossing: from ONLY the EMIF lock-sync node to ONLY the tex_mem endpoints. This is
# NOT a clock-group cut and NOT a multicycle. Nonzero-warn (never fatal) so a rename can't halt the fit.
set emif_lock_src [get_keepers -nowarn {*lock_sync_inst|dreg[*]}]
set tex_mem_dst [get_keepers -nowarn {*u_texcache|tex_mem*}]
set eln [get_collection_size $emif_lock_src]
set tdn [get_collection_size $tex_mem_dst]
if { $eln == 0 } { post_message -type warning "Ch357 SDC WARN: EMIF lock-sync src matched 0 keepers (renamed? lock->tex_mem false-path NOT applied)" }
if { $tdn == 0 } { post_message -type warning "Ch357 SDC WARN: tex_mem dst matched 0 keepers (renamed? lock->tex_mem false-path NOT applied)" }
set_false_path -from $emif_lock_src -to $tex_mem_dst
post_message -type info "Ch357 SDC: EMIF lock-sync -> tex_mem quasi-static false-path ($eln src -> $tdn dst)"
# Ch439g — the bilinear tap bank is separated from every externally visible
# texture result by tex_color_hold (captured only in BS_DONE, exposed only in
# the following BS_OUT state). RTL has no combinational tap -> tex_rd_addr
# path. Nevertheless Agilex DSP packing creates a conservative STA arc from
# tap[*], through mutually exclusive bilinear/modulation/interpolation DSP
# modes, to tex_mem's registered address port. That address port is enabled
# only by tex_rd_en in BS_ISSUE/nearest-issue cycles; the tap blend is consumed
# only in BS_DONE, so the reported arc can never be captured functionally.
#
# Cut only this impossible launch family into the texture cache. Real address
# timing from walker/UV/perspective registers to tex_mem remains fully timed.
# Fail closed on the exact architectural 4x32 tap register population, and on
# a nonempty cache destination, so hierarchy drift cannot silently broaden or
# orphan the exception.
set ch439_bili_taps [get_registers -nowarn {*u_demo|u_gs|u_tex|g_bilinear.tap[*]}]
set ch439_bili_taps_n [get_collection_size $ch439_bili_taps]
if { $ch439_bili_taps_n != 128 } { error "Ch439g SDC FATAL: bilinear tap register count $ch439_bili_taps_n != 128 (4x32; false-path would orphan or broaden)" }
if { $tdn == 0 } { error "Ch439g SDC FATAL: tex_mem destination collection empty" }
set_false_path -from $ch439_bili_taps -to $tex_mem_dst
post_message -type info "Ch439g SDC: impossible bilinear-tap -> tex_mem packed-DSP arc cut ($ch439_bili_taps_n src -> $tdn dst); all non-tap texture-address launches remain timed"
# Ch358 (Codex) — the SAME quasi-static EMIF calibration-ready signal also reaches the scanout LINE-BUFFER RAMs
# (26.1 fit at 640x480: lock_sync_inst|dreg[1] -> u_lpddr_scan_lb|lb0/lb1, 10 endpoints at -0.010ns). These are
# startup/reset-derived line-buffer control paths, NOT runtime scanout data (the line buffers are inactive until
# calibration is stable, exactly like tex_mem). Extend the SAME narrow waiver to the lb RAM endpoints ONLY —
# same source collection, endpoints-only dst, nonzero-warn guard; NOT a clock cut, NOT a whole-module waiver.
set scan_lb_dst [get_keepers -nowarn {*u_lpddr_scan_lb|lb*}]
set sln [get_collection_size $scan_lb_dst]
if { $sln == 0 } { post_message -type warning "Ch358 SDC WARN: scanout lb dst matched 0 keepers (renamed? lock->scan_lb false-path NOT applied)" }
set_false_path -from $emif_lock_src -to $scan_lb_dst
post_message -type info "Ch358 SDC: EMIF lock-sync -> u_lpddr_scan_lb|lb* quasi-static false-path ($eln src -> $sln dst)"
# ----------------------------------------------------------------------------
# Ch357 (Codex) — triangle-setup gradient divide MULTICYCLE, now with a REGISTERED numerator so both endpoints are
# tiny. The RTL (gs_stub) captures grad_num_q[grad_step] into grad_num_sel_q, holds grad_num_sel_q + grad_det_q stable
# for the GRAD_DIV_CYCLES=5 settle window, captures the quotient into grad_result_q, THEN advances grad_step. So the
# combinational divide is grad_num_sel_q / grad_det_q -> grad_result_q: a clean register->register multicycle.
#
# WHY THIS REPLACES the Ch352 {grad_num_q,grad_det_q,grad_step} -from set: that set matched ~1157 regs (grad_num_q is
# 20x56 bits) x 32 dests = ~37k relaxed paths. Even after Ch352 shrank the DEST side (fifo_d* 5120 -> grad_result_q 32),
# the ~1157-source cone (the 20-way dynamic numerator mux) still made the timing-driven placer churn ~6 h in Place.
# Registering the mux output removes it from the divide's LAUNCH cone: -from is now {grad_num_sel_q, grad_det_q} ~88
# regs -> ~2.8k pairs (~13x smaller), and the divide is fed by 2 registers, not a 20-way mux. This is a structural fix
# (the mux is gone before the divider), not an SDC negotiation.
#
# FATAL checks (Codex): grad_num_sel_q + grad_det_q are (* preserve *)'d / real regs — HALT if the -from set is EMPTY
# (source orphaned) or the -to grad_result_q count != 32 (dest orphaned), before A&S->Place. Error strings interpolate
# only $vars (no square brackets -> no Tcl command-substitution bug).
# ----------------------------------------------------------------------------
# CONDITIONAL (Codex): apply the gradient multicycle ONLY when the COMBINATIONAL divider exists. On the board profile
# (GRAD_SEQ_DIVIDER=1) gs_stub's generate strips the `/` entirely and instantiates gs_grad_divider (registered
# iterations) instead — there is no divide cone, so a gradient exception would be meaningless and must NOT be applied.
# Detect the build by the sequential divider's own registers (qbuild/iter live ONLY inside gs_grad_divider).
set seqdiv_regs [get_keepers -nowarn {*u_grad_div|qbuild* *u_grad_div|iter*}]
set seqdiv_n [get_collection_size $seqdiv_regs]
if { $seqdiv_n > 0 } {
# SEQUENTIAL build (board): combinational `/` generate-stripped -> NO gradient exception.
post_message -type info "Ch357 SDC: sequential gradient divider present ($seqdiv_n regs) -> combinational divide absent, NO gradient multicycle applied"
} else {
# COMBINATIONAL build (board): registered-numerator divide grad_num_sel_q/grad_det_q -> grad_result_q. Routed data
# delay was 108.132 ns at 56/32 bits. Ch417 widens the operands to 64/35 bits, so GRAD_DIV_CYCLES=5 gives a
# 200 ns functional window at design_clk = 40 ns (25 MHz). The RTL holds the sources for all five cycles before
# capturing grad_result_q; final STA therefore fail-closes the widened cone against the real 200 ns contract.
#
# STA-ONLY multicycle (Codex, 2026-07-05; widened Ch417 contract): setup=5/hold=4 is applied ONLY during final quartus_sta,
# NOT during quartus_fit. During the fit, a gradient multicycle makes the timing-driven placer treat the ~108 ns
# combinational divide as a "closeable" cone and GRIND (proven twice: 6 h and 13 min). Without it the fitter keeps
# its known-CONVERGENT "hopeless single-cycle" behavior (drops the path, places in seconds). Final quartus_sta then
# applies the multicycle and fail-closes against the real 200 ns window. Fatal source/dest
# collection checks live in this STA-only branch too. grad_result_q replicates for fanout during P&R (32 -> 55), so
# the dest check is ">= 32" (preserve blocks REMOVAL, not duplication), not "== 32".
if { [string match "quartus_sta*" $::quartus(nameofexecutable)] } {
set grad_mc_from [get_keepers -nowarn {*u_gs|grad_num_sel_q* *u_gs|grad_det_q*}]
set grad_mc_to [get_keepers -nowarn {*u_gs|grad_result_q*}]
set grad_from_n [get_collection_size $grad_mc_from]
set grad_to_n [get_collection_size $grad_mc_to]
# -to grad_result_q ONLY (no -from): the Agilex Hyper-Retimer pushes a register INTO the LPM divider
# (div_*_rtl_0|...|my_abs_den|dff), so the worst combinational launch is that INTERNAL register, NOT grad_num_sel_q.
# The named source set is diagnostics only; it may be optimized away while the retimed destination and its real
# divide cone survive. Keep the actual destination constraint in that case. If BOTH source tracking and the
# destination are absent, this profile has no combinational divider and no multicycle is needed.
if { $grad_to_n == 0 } {
post_message -type info "Ch357 SDC: gradient combinational divider inactive in this profile (0 grad_result_q destinations)"
} else {
if { $grad_to_n < 32 } { error "Ch357 SDC FATAL: grad_result_q destination count $grad_to_n < 32 (preserve lost? multicycle would orphan)" }
set_multicycle_path -setup -end 5 -to $grad_mc_to
set_multicycle_path -hold -end 4 -to $grad_mc_to
if { $grad_from_n == 0 } {
post_message -type warning "Ch357 SDC: grad_num_sel_q/grad_det_q tracker optimized away; retained destination-only gradient multicycle on $grad_to_n grad_result_q registers"
} else {
post_message -type info "Ch417 SDC (STA-only): widened gradient multicycle setup=5/hold=4 -to grad_result_q ($grad_to_n regs, all launches incl. retimed divider internals) — 200ns functional window; source set grad_num_sel_q+grad_det_q = $grad_from_n regs"
}
}
} else {
post_message -type info "Ch417 SDC (fit stage): gradient multicycle NOT applied (STA-only) -> fitter keeps convergent single-cycle behavior; final quartus_sta fail-closes the widened divide at the 200ns 5-cycle window"
}
}
synth/de25_nano/top_psmct32_raster_demo/serv_req_info.txt
+35 -30
View File
@@ -1,37 +1,42 @@
<?xml version="1.0" encoding="utf-8"?>
<internal_error>
<sub_system>ERR</sub_system>
<callstack> 0x7f3a10511fd8: fitter_fitcc + 0x111fd8 (_ZN9FITCC_ENVC2EP10CMP_FACADEiPFP12FITCC_DEVICEPS_E + 0x1158)
0x7f3a11701e54: fitter_fdrgn + 0x101e54 (_Z23fdrgn_initialize_fitterP10CMP_FACADEb + 0xa4)
0x7f39fab870c8: comp_fit2 + 0x320c8 (fit2_create_fitter_netlist + 0x20e6)
0x7f3a3f2a8b47: tcl8.6 + 0x4bb47 (TclNRRunCallbacks + 0x67)
0x7f3a3f2a9f29: tcl8.6 + 0x4cf29 (TclEvalEx + 0x599)
0x7f3a3f2aa646: tcl8.6 + 0x4d646 (Tcl_EvalEx + 0x16)
0x7f3a3fce51e1: ccl_atcl + 0x331e1 (_Z13atcl_tcl_evalP10Tcl_InterpRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEb + 0x1c1)
0x7f39fabd4563: comp_fit2 + 0x7f563 (_Z30fit2_run_create_fitter_netlistP10Tcl_InterpRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEER9ATCL_ARGSRib + 0x98b)
0x7f39fab9bd9b: comp_fit2 + 0x46d9b (fit2_fit_plan + 0x2dd)
0x7f3a3f2a8b47: tcl8.6 + 0x4bb47 (TclNRRunCallbacks + 0x67)
0x7f3a3f2a9f29: tcl8.6 + 0x4cf29 (TclEvalEx + 0x599)
0x7f3a3f3510de: tcl8.6 + 0xf40de (Tcl_FSEvalFileEx + 0x21e)
0x7f3a3f351226: tcl8.6 + 0xf4226 (Tcl_EvalFile + 0x26)
0x7f3a406f7a6b: comp_qexe + 0x2ba6b (_Z24qexe_evaluate_tcl_scriptRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE + 0x3b8)
0x7f3a406fa17c: comp_qexe + 0x2e17c (_ZL11qexe_do_tclP14QEXE_FRAMEWORKRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES8_RKNS1_4listIS6_SaIS6_EEEbb + 0x7bb)
0x7f3a406fb4db: comp_qexe + 0x2f4db (_Z19qexe_run_tcl_optionP14QEXE_FRAMEWORKPKcPNSt7__cxx114listINS3_12basic_stringIcSt11char_traitsIcESaIcEEESaIS9_EEEb + 0xa38)
0x7f3a405ecdfc: comp_qcu + 0x8edfc (_ZN3QCU6DETAIL26intialise_qhd_and_run_qexeER13QCU_FRAMEWORKRK8FIO_PATHRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESD_PKcPNS6_4listISB_SaISB_EEEb + 0x99)
0x7f3a405ed143: comp_qcu + 0x8f143 (_Z18qcu_run_tcl_optionP13QCU_FRAMEWORKPKcPNSt7__cxx114listINS3_12basic_stringIcSt11char_traitsIcESaIcEEESaIS9_EEEb + 0x2c5)
0x7f3a40701b92: comp_qexe + 0x35b92 (_Z18qexe_standard_mainP14QEXE_FRAMEWORKPPK22QEXE_OPTION_DEFINITIONiPPKc + 0x1589)
0x40bf79: quartus_fit + 0x40bf79 (_Z10qfit2_mainiPPKc + 0x99)
0x7f3a400e3e4c: ccl_msg + 0x44e4c (_Z15msg_main_threadPv + 0x10)
0x7f3a400e58f9: ccl_msg + 0x468f9 (_Z18msg_thread_wrapperPFPvS_ES_ + 0x8c)
0x7f3a4052175d: ccl_mem + 0x1375d (_Z18mem_thread_wrapperPFPvS_ES_ + 0x9d)
0x7f3a296882c8: ccl_err + 0xe2c8 (_Z18err_thread_wrapperPFPvS_ES_ + 0x1e)
0x7f3a400e4646: ccl_msg + 0x45646 (_Z12msg_exe_mainiPPKcPFiiS1_E + 0xc2)
0x7f3a3a22a1ca: c + 0x2a1ca
0x7f3a3a22a28b: c + 0x2a28b (__libc_start_main + 0x8b)
0x404e1a: quartus_fit + 0x404e1a (_start + 0x2a)
<callstack> 0x74bed1866211: synth_vrfx2 + 0x866211 (_ZN8VRFX_DDM22create_gtn_assignmentsEv + 0xd9f)
0x74bed1878597: synth_vrfx2 + 0x878597 (_ZN8VRFX_DDM18process_attributesEv + 0x581)
0x74bed188b73b: synth_vrfx2 + 0x88b73b (_ZN8VRFX_DDM15convert_netlistEPN17VRFX2_TOPDOWN_MGR15ELAB_INST_ENTRYE + 0x6e5)
0x74bed188c525: synth_vrfx2 + 0x88c525 (_Z30vrfx2_ddm_convert_all_netlistsP20BASEX_ELABORATE_INFOP7NetlistPN11new_verific30VRFX2_ENTITY_EXISTENCE_CHECKERE + 0x83d)
0x74bed18e839e: synth_vrfx2 + 0x8e839e (_ZN11new_verific15VRFX2_EXTRACTOR17extract_hierarchyEPKcRKSt6vectorIP12BASEX_ENTITYSaIS5_EEP20BASEX_ELABORATE_INFObbbbbb + 0x2180)
0x74bef09452b6: synth_qis + 0x1452b6 (_ZN13QIS_RTL_STAGE4IMPL17elaborate_verificEP13QHD_PARTITIONP12BASEX_ENTITYR20BASEX_ELAB_INFO_CORERKSt6vectorIS4_SaIS4_EEb + 0x302)
0x74bef098bd1d: synth_qis + 0x18bd1d (_ZN13QIS_RTL_STAGE4IMPL20elaborate_ddm_moduleEP10DDM_MODULEP12BASEX_ENTITYRKSt6vectorIS4_SaIS4_EERS5_IS2_SaIS2_EE + 0xdf)
0x74bef098c8b4: synth_qis + 0x18c8b4 (_ZN13QIS_RTL_STAGE4IMPL13elaborate_ddmEP10DDM_MODULE + 0x3d8)
0x74bef09938d9: synth_qis + 0x1938d9 (_ZN13QIS_RTL_STAGE4IMPL13elaborate_ddmEv + 0x3bd)
0x74bef0994072: synth_qis + 0x194072 (_ZN13QIS_RTL_STAGE13elaborate_ddmEv + 0xc)
0x74beb1267cd0: synth_scmd + 0x3dcd0 (_ZN14SCMD_ELABORATE7executeEP10Tcl_InterpR9DTCL_ARGS + 0x65c)
0x74bed539d931: mss_dtcl + 0xc931 (_ZN16DTCL_COMMAND_PKG8eval_cmdEPvP10Tcl_InterpiPKP7Tcl_Obj + 0xb7)
0x74beee2a8b47: tcl8.6 + 0x4bb47 (TclNRRunCallbacks + 0x67)
0x74beee2a9f29: tcl8.6 + 0x4cf29 (TclEvalEx + 0x599)
0x74beee3510de: tcl8.6 + 0xf40de (Tcl_FSEvalFileEx + 0x21e)
0x74beee351226: tcl8.6 + 0xf4226 (Tcl_EvalFile + 0x26)
0x74bef19ada6b: comp_qexe + 0x2ba6b (_Z24qexe_evaluate_tcl_scriptRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE + 0x3b8)
0x74bef19b017c: comp_qexe + 0x2e17c (_ZL11qexe_do_tclP14QEXE_FRAMEWORKRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES8_RKNS1_4listIS6_SaIS6_EEEbb + 0x7bb)
0x74bef19b14db: comp_qexe + 0x2f4db (_Z19qexe_run_tcl_optionP14QEXE_FRAMEWORKPKcPNSt7__cxx114listINS3_12basic_stringIcSt11char_traitsIcESaIcEEESaIS9_EEEb + 0xa38)
0x74bef1be0dfc: comp_qcu + 0x8edfc (_ZN3QCU6DETAIL26intialise_qhd_and_run_qexeER13QCU_FRAMEWORKRK8FIO_PATHRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESD_PKcPNS6_4listISB_SaISB_EEEb + 0x99)
0x74bef1be1143: comp_qcu + 0x8f143 (_Z18qcu_run_tcl_optionP13QCU_FRAMEWORKPKcPNSt7__cxx114listINS3_12basic_stringIcSt11char_traitsIcESaIcEEESaIS9_EEEb + 0x2c5)
0x407735: quartus_syn + 0x407735 (_ZL37qsyn2_tcl_process_default_flow_option22ACF_VARIABLE_TYPE_ENUMPKc + 0x575)
0x74bef19b7b92: comp_qexe + 0x35b92 (_Z18qexe_standard_mainP14QEXE_FRAMEWORKPPK22QEXE_OPTION_DEFINITIONiPPKc + 0x1589)
0x40709e: quartus_syn + 0x40709e (_Z10qsyn2_mainiPPKc + 0x155)
0x74bef02e3e4c: ccl_msg + 0x44e4c (_Z15msg_main_threadPv + 0x10)
0x74bef02e58f9: ccl_msg + 0x468f9 (_Z18msg_thread_wrapperPFPvS_ES_ + 0x8c)
0x74bef117b75d: ccl_mem + 0x1375d (_Z18mem_thread_wrapperPFPvS_ES_ + 0x9d)
0x74bed5a7e2c8: ccl_err + 0xe2c8 (_Z18err_thread_wrapperPFPvS_ES_ + 0x1e)
0x74bef02e4646: ccl_msg + 0x45646 (_Z12msg_exe_mainiPPKcPFiiS1_E + 0xc2)
0x406f42: quartus_syn + 0x406f42 (main + 0x26)
0x74beea82a1ca: c + 0x2a1ca
0x74beea82a28b: c + 0x2a28b (__libc_start_main + 0x8b)
0x406e6a: quartus_syn + 0x406e6a (_start + 0x2a)
</callstack>
<error>*** Fatal Error: Neither FAST FIT nor AUTO FIT is not supported by this family, but FAST FIT is requested in QSF</error>
<date>Mon Jun 29 05:22:29 2026
<error>*** Fatal Error: net</error>
<date>Sat Jul 11 17:34:52 2026
</date>
<version>Version 26.1.0 Build 110 03/26/2026 SC Pro Edition</version>
</internal_error>
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/a_dpfifo_pa9f.tdf
-154
View File
@@ -1,154 +0,0 @@
--a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" ENABLE_ECC="FALSE" LPM_NUMWORDS=32 LPM_SHOWAHEAD="ON" lpm_width=9 lpm_widthu=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" clock data empty full q rreq sclr usedw wreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Agilex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0
--VERSION_BEGIN 26.1 cbx_altdpram 2026:03:19:21:42:37:SC cbx_altera_counter 2026:03:19:21:42:37:SC cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_fifo_common 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_counter 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_scfifo 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_counter (clk, enable, reset, sreset, updown)
WITH ( DIRECTION, MODULUS, WIDTH = 6)
RETURNS ( count[WIDTH-1..0], cout);
FUNCTION altera_syncram_4kqp (address_a[4..0], address_b[4..0], clock0, clock1, clocken1, data_a[8..0], wren_a)
RETURNS ( q_b[8..0]);
FUNCTION cmpr_jdut1 (dataa[4..0], datab[4..0])
RETURNS ( aeb);
--synthesis_resources = altera_counter 3 ram_bits (AUTO) 288 reg 13
SUBDESIGN a_dpfifo_pa9f
(
clock : input;
data[8..0] : input;
empty : output;
full : output;
q[8..0] : output;
rreq : input;
sclr : input;
usedw[4..0] : output;
wreq : input;
)
VARIABLE
rd_ptr_msb : altera_counter
WITH (
DIRECTION = "UP",
WIDTH = 4
);
usedw_counter : altera_counter
WITH (
DIRECTION = "UPDOWN",
WIDTH = 5
);
wr_ptr : altera_counter
WITH (
DIRECTION = "UP",
WIDTH = 5
);
FIFOram : altera_syncram_4kqp;
empty_dff : dffe;
full_dff : dffe;
low_addressa[4..0] : dffe;
rd_ptr_lsb : dffe;
usedw_is_0_dff : dffe;
usedw_is_1_dff : dffe;
usedw_is_2_dff : dffe;
wrreq_delaya[1..0] : dffe;
almost_full_comparer : cmpr_jdut1;
three_comparison : cmpr_jdut1;
aclr : NODE;
asynch_read_counter_enable : WIRE;
empty_out : WIRE;
full_out : WIRE;
pulse_ram_output : WIRE;
ram_read_address[4..0] : WIRE;
rd_ptr[4..0] : WIRE;
usedw_is_0 : WIRE;
usedw_is_1 : WIRE;
usedw_is_2 : WIRE;
usedw_will_be_0 : WIRE;
usedw_will_be_1 : WIRE;
usedw_will_be_2 : WIRE;
valid_rreq : WIRE;
valid_wreq : WIRE;
wait_state : WIRE;
BEGIN
rd_ptr_msb.clk = clock;
rd_ptr_msb.enable = (asynch_read_counter_enable & (! rd_ptr_lsb.q));
rd_ptr_msb.sreset = sclr;
usedw_counter.clk = clock;
usedw_counter.enable = (valid_wreq $ valid_rreq);
usedw_counter.sreset = sclr;
usedw_counter.updown = valid_wreq;
wr_ptr.clk = clock;
wr_ptr.enable = valid_wreq;
wr_ptr.sreset = sclr;
FIFOram.address_a[] = wr_ptr.count[];
FIFOram.address_b[] = ram_read_address[];
FIFOram.clock0 = clock;
FIFOram.clock1 = clock;
FIFOram.clocken1 = pulse_ram_output;
FIFOram.data_a[] = data[];
FIFOram.wren_a = valid_wreq;
empty_dff.clk = clock;
empty_dff.clrn = (! aclr);
empty_dff.d = ((! (usedw_will_be_0 # wait_state)) & (! sclr));
full_dff.clk = clock;
full_dff.clrn = (! aclr);
full_dff.d = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer.aeb) # (full_dff.q & (! (valid_wreq $ valid_rreq)))));
low_addressa[].clk = clock;
low_addressa[].clrn = (! aclr);
low_addressa[].d = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].q)));
rd_ptr_lsb.clk = clock;
rd_ptr_lsb.clrn = (! aclr);
rd_ptr_lsb.d = ((! rd_ptr_lsb.q) & (! sclr));
rd_ptr_lsb.ena = (asynch_read_counter_enable # sclr);
usedw_is_0_dff.clk = clock;
usedw_is_0_dff.clrn = (! aclr);
usedw_is_0_dff.d = (! usedw_will_be_0);
usedw_is_1_dff.clk = clock;
usedw_is_1_dff.clrn = (! aclr);
usedw_is_1_dff.d = usedw_will_be_1;
usedw_is_2_dff.clk = clock;
usedw_is_2_dff.clrn = (! aclr);
usedw_is_2_dff.d = usedw_will_be_2;
wrreq_delaya[].clk = clock;
wrreq_delaya[].clrn = (! aclr);
wrreq_delaya[].d = ( ((! sclr) & valid_wreq), ((! sclr) & wrreq_delaya[1].q));
almost_full_comparer.dataa[] = B"11111";
almost_full_comparer.datab[] = usedw_counter.count[];
three_comparison.dataa[] = usedw_counter.count[];
three_comparison.datab[] = B"00011";
aclr = GND;
asynch_read_counter_enable = pulse_ram_output;
empty = empty_out;
empty_out = (! empty_dff.q);
full = full_out;
full_out = full_dff.q;
pulse_ram_output = ((((usedw_is_1 & wrreq_delaya[0].q) # ((usedw_is_2 & wrreq_delaya[1].q) & wrreq_delaya[0].q)) # ((! (usedw_is_1 # usedw_is_2)) & valid_rreq)) # ((usedw_is_2 & (! wrreq_delaya[1].q)) & valid_rreq));
q[] = FIFOram.q_b[];
ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].q) # (asynch_read_counter_enable & rd_ptr[]));
rd_ptr[] = ( rd_ptr_msb.count[], (! rd_ptr_lsb.q));
usedw[] = usedw_counter.count[];
usedw_is_0 = (! usedw_is_0_dff.q);
usedw_is_1 = usedw_is_1_dff.q;
usedw_is_2 = usedw_is_2_dff.q;
usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq)))))));
usedw_will_be_1 = ((! sclr) & (((usedw_is_1 & (! (valid_wreq $ valid_rreq))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq))) # ((usedw_is_2 & valid_rreq) & (! valid_wreq))));
usedw_will_be_2 = ((! sclr) & (((usedw_is_2_dff.q & (! (valid_wreq $ valid_rreq))) # ((usedw_is_1 & valid_wreq) & (! valid_rreq))) # ((three_comparison.aeb & valid_rreq) & (! valid_wreq))));
valid_rreq = rreq;
valid_wreq = wreq;
wait_state = ((usedw_will_be_1 & (valid_wreq $ wrreq_delaya[1].q)) # ((usedw_will_be_2 & valid_wreq) & wrreq_delaya[1].q));
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/a_dpfifo_rntb1.tdf
-154
View File
@@ -1,154 +0,0 @@
--a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" ENABLE_ECC="FALSE" LPM_NUMWORDS=32 LPM_SHOWAHEAD="ON" lpm_width=266 lpm_widthu=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" clock data empty full q rreq sclr usedw wreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Agilex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0
--VERSION_BEGIN 26.1 cbx_altdpram 2026:03:19:21:42:37:SC cbx_altera_counter 2026:03:19:21:42:37:SC cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_fifo_common 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_counter 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_scfifo 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_counter (clk, enable, reset, sreset, updown)
WITH ( DIRECTION, MODULUS, WIDTH = 6)
RETURNS ( count[WIDTH-1..0], cout);
FUNCTION altera_syncram_k8rl1 (address_a[4..0], address_b[4..0], clock0, clock1, clocken1, data_a[265..0], wren_a)
RETURNS ( q_b[265..0]);
FUNCTION cmpr_jdut1 (dataa[4..0], datab[4..0])
RETURNS ( aeb);
--synthesis_resources = altera_counter 3 ram_bits (AUTO) 8512 reg 13
SUBDESIGN a_dpfifo_rntb1
(
clock : input;
data[265..0] : input;
empty : output;
full : output;
q[265..0] : output;
rreq : input;
sclr : input;
usedw[4..0] : output;
wreq : input;
)
VARIABLE
rd_ptr_msb : altera_counter
WITH (
DIRECTION = "UP",
WIDTH = 4
);
usedw_counter : altera_counter
WITH (
DIRECTION = "UPDOWN",
WIDTH = 5
);
wr_ptr : altera_counter
WITH (
DIRECTION = "UP",
WIDTH = 5
);
FIFOram : altera_syncram_k8rl1;
empty_dff : dffe;
full_dff : dffe;
low_addressa[4..0] : dffe;
rd_ptr_lsb : dffe;
usedw_is_0_dff : dffe;
usedw_is_1_dff : dffe;
usedw_is_2_dff : dffe;
wrreq_delaya[1..0] : dffe;
almost_full_comparer : cmpr_jdut1;
three_comparison : cmpr_jdut1;
aclr : NODE;
asynch_read_counter_enable : WIRE;
empty_out : WIRE;
full_out : WIRE;
pulse_ram_output : WIRE;
ram_read_address[4..0] : WIRE;
rd_ptr[4..0] : WIRE;
usedw_is_0 : WIRE;
usedw_is_1 : WIRE;
usedw_is_2 : WIRE;
usedw_will_be_0 : WIRE;
usedw_will_be_1 : WIRE;
usedw_will_be_2 : WIRE;
valid_rreq : WIRE;
valid_wreq : WIRE;
wait_state : WIRE;
BEGIN
rd_ptr_msb.clk = clock;
rd_ptr_msb.enable = (asynch_read_counter_enable & (! rd_ptr_lsb.q));
rd_ptr_msb.sreset = sclr;
usedw_counter.clk = clock;
usedw_counter.enable = (valid_wreq $ valid_rreq);
usedw_counter.sreset = sclr;
usedw_counter.updown = valid_wreq;
wr_ptr.clk = clock;
wr_ptr.enable = valid_wreq;
wr_ptr.sreset = sclr;
FIFOram.address_a[] = wr_ptr.count[];
FIFOram.address_b[] = ram_read_address[];
FIFOram.clock0 = clock;
FIFOram.clock1 = clock;
FIFOram.clocken1 = pulse_ram_output;
FIFOram.data_a[] = data[];
FIFOram.wren_a = valid_wreq;
empty_dff.clk = clock;
empty_dff.clrn = (! aclr);
empty_dff.d = ((! (usedw_will_be_0 # wait_state)) & (! sclr));
full_dff.clk = clock;
full_dff.clrn = (! aclr);
full_dff.d = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer.aeb) # (full_dff.q & (! (valid_wreq $ valid_rreq)))));
low_addressa[].clk = clock;
low_addressa[].clrn = (! aclr);
low_addressa[].d = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].q)));
rd_ptr_lsb.clk = clock;
rd_ptr_lsb.clrn = (! aclr);
rd_ptr_lsb.d = ((! rd_ptr_lsb.q) & (! sclr));
rd_ptr_lsb.ena = (asynch_read_counter_enable # sclr);
usedw_is_0_dff.clk = clock;
usedw_is_0_dff.clrn = (! aclr);
usedw_is_0_dff.d = (! usedw_will_be_0);
usedw_is_1_dff.clk = clock;
usedw_is_1_dff.clrn = (! aclr);
usedw_is_1_dff.d = usedw_will_be_1;
usedw_is_2_dff.clk = clock;
usedw_is_2_dff.clrn = (! aclr);
usedw_is_2_dff.d = usedw_will_be_2;
wrreq_delaya[].clk = clock;
wrreq_delaya[].clrn = (! aclr);
wrreq_delaya[].d = ( ((! sclr) & valid_wreq), ((! sclr) & wrreq_delaya[1].q));
almost_full_comparer.dataa[] = B"11111";
almost_full_comparer.datab[] = usedw_counter.count[];
three_comparison.dataa[] = usedw_counter.count[];
three_comparison.datab[] = B"00011";
aclr = GND;
asynch_read_counter_enable = pulse_ram_output;
empty = empty_out;
empty_out = (! empty_dff.q);
full = full_out;
full_out = full_dff.q;
pulse_ram_output = ((((usedw_is_1 & wrreq_delaya[0].q) # ((usedw_is_2 & wrreq_delaya[1].q) & wrreq_delaya[0].q)) # ((! (usedw_is_1 # usedw_is_2)) & valid_rreq)) # ((usedw_is_2 & (! wrreq_delaya[1].q)) & valid_rreq));
q[] = FIFOram.q_b[];
ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].q) # (asynch_read_counter_enable & rd_ptr[]));
rd_ptr[] = ( rd_ptr_msb.count[], (! rd_ptr_lsb.q));
usedw[] = usedw_counter.count[];
usedw_is_0 = (! usedw_is_0_dff.q);
usedw_is_1 = usedw_is_1_dff.q;
usedw_is_2 = usedw_is_2_dff.q;
usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq)))))));
usedw_will_be_1 = ((! sclr) & (((usedw_is_1 & (! (valid_wreq $ valid_rreq))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq))) # ((usedw_is_2 & valid_rreq) & (! valid_wreq))));
usedw_will_be_2 = ((! sclr) & (((usedw_is_2_dff.q & (! (valid_wreq $ valid_rreq))) # ((usedw_is_1 & valid_wreq) & (! valid_rreq))) # ((three_comparison.aeb & valid_rreq) & (! valid_wreq))));
valid_rreq = rreq;
valid_wreq = wreq;
wait_state = ((usedw_will_be_1 & (valid_wreq $ wrreq_delaya[1].q)) # ((usedw_will_be_2 & valid_wreq) & wrreq_delaya[1].q));
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/abs_divider_nsr72.tdf
-89
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@@ -1,89 +0,0 @@
--abs_divider CBX_SINGLE_OUTPUT_FILE="OFF" DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=32 WIDTH_N=33 denominator numerator quotient remainder
--VERSION_BEGIN 26.1 cbx_lpm_abs 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_divide 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION alt_u_div_6gam1 (denominator[31..0], numerator[32..0])
RETURNS ( quotient[32..0], remainder[31..0]);
FUNCTION lpm_abs_unir (data[31..0])
RETURNS ( overflow, result[31..0]);
FUNCTION lpm_abs_952f1 (data[32..0])
RETURNS ( overflow, result[32..0]);
--synthesis_resources = lut 724
SUBDESIGN abs_divider_nsr72
(
denominator[31..0] : input;
numerator[32..0] : input;
quotient[32..0] : output;
remainder[31..0] : output;
)
VARIABLE
divider : alt_u_div_6gam1;
my_abs_den : lpm_abs_unir;
my_abs_num : lpm_abs_952f1;
compl_add_quot_result_int[33..0] : WIRE;
compl_add_quot_cin : WIRE;
compl_add_quot_dataa[32..0] : WIRE;
compl_add_quot_datab[32..0] : WIRE;
compl_add_quot_result[32..0] : WIRE;
compl_add_rem_result_int[32..0] : WIRE;
compl_add_rem_cin : WIRE;
compl_add_rem_dataa[31..0] : WIRE;
compl_add_rem_datab[31..0] : WIRE;
compl_add_rem_result[31..0] : WIRE;
diff_signs : WIRE;
gnd_wire : WIRE;
neg_quot[32..0] : WIRE;
neg_rem[31..0] : WIRE;
norm_den[31..0] : WIRE;
norm_num[32..0] : WIRE;
num_sign : WIRE;
protect_quotient[32..0] : WIRE;
protect_remainder[31..0] : WIRE;
vcc_wire : WIRE;
BEGIN
divider.denominator[] = norm_den[];
divider.numerator[] = norm_num[];
my_abs_den.data[] = denominator[];
my_abs_num.data[] = numerator[];
compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
compl_add_quot_result[] = compl_add_quot_result_int[33..1];
compl_add_quot_cin = vcc_wire;
compl_add_quot_dataa[] = (! protect_quotient[]);
compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
compl_add_rem_result[] = compl_add_rem_result_int[32..1];
compl_add_rem_cin = vcc_wire;
compl_add_rem_dataa[] = (! protect_remainder[]);
compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
diff_signs = (numerator[32..32] $ denominator[31..31]);
gnd_wire = B"0";
neg_quot[] = compl_add_quot_result[];
neg_rem[] = compl_add_rem_result[];
norm_den[] = my_abs_den.result[];
norm_num[] = my_abs_num.result[];
num_sign = numerator[32..32];
protect_quotient[] = divider.quotient[];
protect_remainder[] = divider.remainder[];
quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
vcc_wire = B"1";
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/alt_u_div_6gam1.tdf
-392
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/alt_u_div_8oak.tdf
-102
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@@ -1,102 +0,0 @@
--alt_u_div CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=2 WIDTH_N=4 WIDTH_Q=4 WIDTH_R=2 denominator numerator quotient remainder
--VERSION_BEGIN 26.1 cbx_lpm_abs 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_divide 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
--synthesis_resources = lut 13
SUBDESIGN alt_u_div_8oak
(
denominator[1..0] : input;
numerator[3..0] : input;
quotient[3..0] : output;
remainder[1..0] : output;
)
VARIABLE
add_sub_0_result_int[1..0] : WIRE;
add_sub_0_cout : WIRE;
add_sub_0_dataa[0..0] : WIRE;
add_sub_0_datab[0..0] : WIRE;
add_sub_0_result[0..0] : WIRE;
add_sub_1_result_int[2..0] : WIRE;
add_sub_1_cout : WIRE;
add_sub_1_dataa[1..0] : WIRE;
add_sub_1_datab[1..0] : WIRE;
add_sub_1_result[1..0] : WIRE;
add_sub_2_result_int[3..0] : WIRE;
add_sub_2_cout : WIRE;
add_sub_2_dataa[2..0] : WIRE;
add_sub_2_datab[2..0] : WIRE;
add_sub_2_result[2..0] : WIRE;
add_sub_3_result_int[3..0] : WIRE;
add_sub_3_cout : WIRE;
add_sub_3_dataa[2..0] : WIRE;
add_sub_3_datab[2..0] : WIRE;
add_sub_3_result[2..0] : WIRE;
DenominatorIn[14..0] : WIRE;
DenominatorIn_tmp[14..0] : WIRE;
gnd_wire : WIRE;
nose[19..0] : WIRE;
NumeratorIn[19..0] : WIRE;
NumeratorIn_tmp[19..0] : WIRE;
prestg[11..0] : WIRE;
quotient_tmp[3..0] : WIRE;
sel[9..0] : WIRE;
selnose[19..0] : WIRE;
StageIn[14..0] : WIRE;
StageIn_tmp[14..0] : WIRE;
StageOut[11..0] : WIRE;
BEGIN
add_sub_0_result_int[] = (0, add_sub_0_dataa[]) - (0, add_sub_0_datab[]);
add_sub_0_result[] = add_sub_0_result_int[0..0];
add_sub_0_cout = !add_sub_0_result_int[1];
add_sub_0_dataa[] = NumeratorIn[3..3];
add_sub_0_datab[] = DenominatorIn[0..0];
add_sub_1_result_int[] = (0, add_sub_1_dataa[]) - (0, add_sub_1_datab[]);
add_sub_1_result[] = add_sub_1_result_int[1..0];
add_sub_1_cout = !add_sub_1_result_int[2];
add_sub_1_dataa[] = ( StageIn[3..3], NumeratorIn[6..6]);
add_sub_1_datab[] = DenominatorIn[4..3];
add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
add_sub_2_result[] = add_sub_2_result_int[2..0];
add_sub_2_cout = !add_sub_2_result_int[3];
add_sub_2_dataa[] = ( StageIn[7..6], NumeratorIn[9..9]);
add_sub_2_datab[] = DenominatorIn[8..6];
add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
add_sub_3_result[] = add_sub_3_result_int[2..0];
add_sub_3_cout = !add_sub_3_result_int[3];
add_sub_3_dataa[] = ( StageIn[10..9], NumeratorIn[12..12]);
add_sub_3_datab[] = DenominatorIn[11..9];
DenominatorIn[] = DenominatorIn_tmp[];
DenominatorIn_tmp[] = ( DenominatorIn[11..0], ( gnd_wire, denominator[]));
gnd_wire = B"0";
nose[] = ( B"0000", add_sub_3_cout, B"0000", add_sub_2_cout, B"0000", add_sub_1_cout, B"0000", add_sub_0_cout);
NumeratorIn[] = NumeratorIn_tmp[];
NumeratorIn_tmp[] = ( NumeratorIn[15..0], numerator[]);
prestg[] = ( add_sub_3_result[], add_sub_2_result[], GND, add_sub_1_result[], B"00", add_sub_0_result[]);
quotient[] = quotient_tmp[];
quotient_tmp[] = ( (! selnose[0..0]), (! selnose[5..5]), (! selnose[10..10]), (! selnose[15..15]));
remainder[1..0] = StageIn[13..12];
sel[] = ( gnd_wire, (sel[9..9] # DenominatorIn[13..13]), gnd_wire, (sel[7..7] # DenominatorIn[10..10]), gnd_wire, (sel[5..5] # DenominatorIn[7..7]), gnd_wire, (sel[3..3] # DenominatorIn[4..4]), gnd_wire, (sel[1..1] # DenominatorIn[1..1]));
selnose[] = ( (! nose[19..19]), (! nose[18..18]), ((! nose[17..17]) # sel[9..9]), ((! nose[16..16]) # sel[8..8]), (! nose[15..15]), (! nose[14..14]), ((! nose[13..13]) # sel[7..7]), ((! nose[12..12]) # sel[6..6]), (! nose[11..11]), (! nose[10..10]), ((! nose[9..9]) # sel[5..5]), ((! nose[8..8]) # sel[4..4]), (! nose[7..7]), (! nose[6..6]), ((! nose[5..5]) # sel[3..3]), ((! nose[4..4]) # sel[2..2]), (! nose[3..3]), (! nose[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0]));
StageIn[] = StageIn_tmp[];
StageIn_tmp[] = ( StageOut[11..0], B"000");
StageOut[] = ( ((( StageIn[10..9], NumeratorIn[12..12]) & selnose[15..15]) # (prestg[11..9] & (! selnose[15..15]))), ((( StageIn[7..6], NumeratorIn[9..9]) & selnose[10..10]) # (prestg[8..6] & (! selnose[10..10]))), ((( StageIn[4..3], NumeratorIn[6..6]) & selnose[5..5]) # (prestg[5..3] & (! selnose[5..5]))), ((( StageIn[1..0], NumeratorIn[3..3]) & selnose[0..0]) # (prestg[2..0] & (! selnose[0..0]))));
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_40oq1.tdf
-43
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@@ -1,43 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" INIT_FILE="qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram5_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_SCLR_A="SCLEAR" WIDTH_A=32 WIDTHAD_A=10 address_a clock0 q_a rden_a sclr CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_fihn1 (address_a[9..0], clock0, rden_a, sclr)
RETURNS ( q_a[31..0]);
--synthesis_resources = ram_bits (AUTO) 32768
SUBDESIGN altera_syncram_40oq1
(
address_a[9..0] : input;
clock0 : input;
q_a[31..0] : output;
rden_a : input;
sclr : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_fihn1;
BEGIN
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.rden_a = rden_a;
altera_syncram_impl1.sclr = sclr;
q_a[] = altera_syncram_impl1.q_a[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_4kqp.tdf
-49
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@@ -1,49 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_SINGLE_OUTPUT_FILE="OFF" CLOCK_ENABLE_INPUT_B="BYPASS" DEVICE_FAMILY="Agilex 5" ENABLE_ECC="FALSE" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" WIDTH_A=9 WIDTH_B=9 WIDTH_BYTEENA_A=1 WIDTH_ECCSTATUS=2 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_1q3n (address_a[4..0], address_b[4..0], clock0, clock1, clocken1, data_a[8..0], wren_a)
RETURNS ( q_b[8..0]);
--synthesis_resources = ram_bits (AUTO) 288
SUBDESIGN altera_syncram_4kqp
(
address_a[4..0] : input;
address_b[4..0] : input;
clock0 : input;
clock1 : input;
clocken1 : input;
data_a[8..0] : input;
q_b[8..0] : output;
wren_a : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_1q3n;
BEGIN
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.address_b[] = address_b[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.clock1 = clock1;
altera_syncram_impl1.clocken1 = clocken1;
altera_syncram_impl1.data_a[] = data_a[];
altera_syncram_impl1.wren_a = wren_a;
q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_5brq1.tdf
-45
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@@ -1,45 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LOW_POWER_MODE="AUTO" NUMWORDS_A=8 NUMWORDS_B=8 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="M20K" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=1053 WIDTH_B=1053 WIDTHAD_A=3 WIDTHAD_B=3 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_gsmn (address_a[2..0], address_b[2..0], clock0, data_a[1052..0], wren_a)
RETURNS ( q_b[1052..0]);
--synthesis_resources = M20K 27
SUBDESIGN altera_syncram_5brq1
(
address_a[2..0] : input;
address_b[2..0] : input;
clock0 : input;
data_a[1052..0] : input;
q_b[1052..0] : output;
wren_a : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_gsmn;
BEGIN
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.address_b[] = address_b[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.data_a[] = data_a[];
altera_syncram_impl1.wren_a = wren_a;
q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_5om81.tdf
-39
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@@ -1,39 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" INIT_FILE="qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram2_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=8 WIDTHAD_A=11 address_a clock0 q_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_bnt71 (address_a[10..0], clock0)
RETURNS ( q_a[7..0]);
--synthesis_resources = ram_bits (AUTO) 16384
SUBDESIGN altera_syncram_5om81
(
address_a[10..0] : input;
clock0 : input;
q_a[7..0] : output;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_bnt71;
BEGIN
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.clock0 = clock0;
q_a[] = altera_syncram_impl1.q_a[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_71ha1.tdf
-45
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@@ -1,45 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" INIT_FILE="qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram0_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=768 NUMWORDS_B=768 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=64 WIDTH_B=64 WIDTHAD_A=10 WIDTHAD_B=10 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_scbg (address_a[9..0], address_b[9..0], clock0, data_a[63..0], wren_a)
RETURNS ( q_b[63..0]);
--synthesis_resources = ram_bits (AUTO) 49152
SUBDESIGN altera_syncram_71ha1
(
address_a[9..0] : input;
address_b[9..0] : input;
clock0 : input;
data_a[63..0] : input;
q_b[63..0] : output;
wren_a : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_scbg;
BEGIN
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.address_b[] = address_b[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.data_a[] = data_a[];
altera_syncram_impl1.wren_a = wren_a;
q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_cd5h1.tdf
-45
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@@ -1,45 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" INIT_FILE="qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram3_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 NUMWORDS_B=1024 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="M20K" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=10 WIDTHAD_B=10 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_hlsq1 (address_a[9..0], address_b[9..0], clock0, data_a[31..0], wren_a)
RETURNS ( q_b[31..0]);
--synthesis_resources = M20K 2
SUBDESIGN altera_syncram_cd5h1
(
address_a[9..0] : input;
address_b[9..0] : input;
clock0 : input;
data_a[31..0] : input;
q_b[31..0] : output;
wren_a : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_hlsq1;
BEGIN
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.address_b[] = address_b[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.data_a[] = data_a[];
altera_syncram_impl1.wren_a = wren_a;
q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_esnu1.tdf
-47
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@@ -1,47 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=240 WIDTH_B=240 WIDTHAD_A=8 WIDTHAD_B=8 address_a address_b clock0 clock1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_8q921 (address_a[7..0], address_b[7..0], clock0, clock1, data_a[239..0], wren_a)
RETURNS ( q_b[239..0]);
--synthesis_resources = ram_bits (AUTO) 61440
SUBDESIGN altera_syncram_esnu1
(
address_a[7..0] : input;
address_b[7..0] : input;
clock0 : input;
clock1 : input;
data_a[239..0] : input;
q_b[239..0] : output;
wren_a : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_8q921;
BEGIN
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.address_b[] = address_b[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.clock1 = clock1;
altera_syncram_impl1.data_a[] = data_a[];
altera_syncram_impl1.wren_a = wren_a;
q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_hhrf1.tdf
-49
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@@ -1,49 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LOW_POWER_MODE="AUTO" NUMWORDS_A=65536 NUMWORDS_B=65536 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="M20K" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=16 WIDTHAD_B=16 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_rq6n (address_a[15..0], address_b[15..0], clock0, clock1, clocken1, data_a[31..0], wren_a)
RETURNS ( q_b[31..0]);
--synthesis_resources = lut 367 M20K 128 reg 5
SUBDESIGN altera_syncram_hhrf1
(
address_a[15..0] : input;
address_b[15..0] : input;
clock0 : input;
clock1 : input;
clocken1 : input;
data_a[31..0] : input;
q_b[31..0] : output;
wren_a : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_rq6n;
BEGIN
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.address_b[] = address_b[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.clock1 = clock1;
altera_syncram_impl1.clocken1 = clocken1;
altera_syncram_impl1.data_a[] = data_a[];
altera_syncram_impl1.wren_a = wren_a;
q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_hin22.tdf
-47
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@@ -1,47 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="CLEAR0" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" INIT_FILE="qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram1_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 NUMWORDS_B=1024 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="M20K" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=10 WIDTHAD_B=10 aclr0 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_anr2 (aclr0, address_a[9..0], address_b[9..0], clock0, data_a[31..0], wren_a)
RETURNS ( q_b[31..0]);
--synthesis_resources = M20K 2
SUBDESIGN altera_syncram_hin22
(
aclr0 : input;
address_a[9..0] : input;
address_b[9..0] : input;
clock0 : input;
data_a[31..0] : input;
q_b[31..0] : output;
wren_a : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_anr2;
BEGIN
altera_syncram_impl1.aclr0 = aclr0;
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.address_b[] = address_b[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.data_a[] = data_a[];
altera_syncram_impl1.wren_a = wren_a;
q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_iihv.tdf
-41
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@@ -1,41 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" INIT_FILE="qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 OPERATION_MODE="ROM" OUTDATA_ACLR_A="CLEAR0" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=25 WIDTHAD_A=11 aclr0 address_a clock0 q_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_su9o (aclr0, address_a[10..0], clock0)
RETURNS ( q_a[24..0]);
--synthesis_resources = ram_bits (AUTO) 51200
SUBDESIGN altera_syncram_iihv
(
aclr0 : input;
address_a[10..0] : input;
clock0 : input;
q_a[24..0] : output;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_su9o;
BEGIN
altera_syncram_impl1.aclr0 = aclr0;
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.clock0 = clock0;
q_a[] = altera_syncram_impl1.q_a[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_1q3n.tdf
-345
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@@ -1,345 +0,0 @@
--altera_syncram_nd_impl ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS="AUTO" ACF_DISABLE_MLAB_RAM_USE="FALSE" ACF_IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE="FALSE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_REG_B="CLOCK1" CBX_SINGLE_OUTPUT_FILE="OFF" CLKEN_POWER_OPTIMIZATION="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" DEVICE_FAMILY="Agilex 5" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_COHERENT_READ="FALSE" ENABLE_ECC="FALSE" ENABLE_ECC_ENCODER_BYPASS="FALSE" ENABLE_FORCE_TO_ZERO="FALSE" IMPLEMENT_IN_LES="OFF" INDATA_REG_B="CLOCK1" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OPTIMIZATION_OPTION="AUTO" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="CLOCK1" OUTDATA_SCLR_A="NONE" OUTDATA_SCLR_B="NONE" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK1" RDEN_POWER_OPTIMIZATION="OFF" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" READ_DURING_WRITE_MODE_PORT_A="NEW_DATA_NO_NBE_READ" READ_DURING_WRITE_MODE_PORT_B="NEW_DATA_NO_NBE_READ" WIDTH_A=9 WIDTH_B=9 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCENCPARITY=8 WIDTH_ECCSTATUS=2 WIDTHAD2_A=1 WIDTHAD2_B=1 WIDTHAD_A=5 WIDTHAD_B=5 WREN_POWER_OPTIMIZATION="OFF" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL"
--VERSION_BEGIN 26.1 cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION tennm_ram_block (aclr, clk0, clk1, eccencbypass, eccencparity[WIDTH_ECCENCPARITY-1..0], ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddr2[PORT_A_ADDRESS2_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddr2[PORT_B_ADDRESS2_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe, sclr)
WITH ( CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ECC_PIPELINE_STAGE_ENABLED, ENABLE_COHERENT_READ, ENABLE_ECC, ENABLE_ECC_ENCODER_BYPASS, ENABLE_FORCE_TO_ZERO, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, OPTIMIZATION_OPTION, PORT_A_ADDRESS2_WIDTH = 1, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_RDADDRESS_CLEAR, PORT_B_ADDRESS2_WIDTH = 1, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_RDADDRESS_CLEAR, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCENCPARITY = 1, WIDTH_ECCSTATUS = 2)
RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = ram_bits (AUTO) 288
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altera_syncram_impl_1q3n
(
address_a[4..0] : input;
address_b[4..0] : input;
clock0 : input;
clock1 : input;
clocken1 : input;
data_a[8..0] : input;
q_b[8..0] : output;
wren_a : input;
)
VARIABLE
ram_block2a0 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 9,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 9,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a1 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 9,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 9,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a2 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 9,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 9,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a3 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 9,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 9,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a4 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 9,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 9,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a5 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 9,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 9,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a6 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 9,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 9,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a7 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 9,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 9,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a8 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 9,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 8,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 9,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[4..0] : WIRE;
address_b_wire[4..0] : WIRE;
q_b_wire[8..0] : WIRE;
BEGIN
ram_block2a[8..0].clk0 = clock0;
ram_block2a[8..0].clk1 = clock1;
ram_block2a[8..0].ena1 = clocken1;
ram_block2a[8..0].portaaddr[] = ( address_a_wire[4..0]);
ram_block2a[0].portadatain[] = ( data_a[0..0]);
ram_block2a[1].portadatain[] = ( data_a[1..1]);
ram_block2a[2].portadatain[] = ( data_a[2..2]);
ram_block2a[3].portadatain[] = ( data_a[3..3]);
ram_block2a[4].portadatain[] = ( data_a[4..4]);
ram_block2a[5].portadatain[] = ( data_a[5..5]);
ram_block2a[6].portadatain[] = ( data_a[6..6]);
ram_block2a[7].portadatain[] = ( data_a[7..7]);
ram_block2a[8].portadatain[] = ( data_a[8..8]);
ram_block2a[8..0].portawe = wren_a;
ram_block2a[8..0].portbaddr[] = ( address_b_wire[4..0]);
ram_block2a[8..0].portbre = B"111111111";
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
q_b[] = q_b_wire[];
q_b_wire[] = ( ram_block2a[8..0].portbdataout[0..0]);
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_8q921.tdf
-7255
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_8sj71.tdf
-16005
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_8u7u1.tdf
-8569
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_anr2.tdf
-1047
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_bnt71.tdf
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@@ -1,298 +0,0 @@
--altera_syncram_nd_impl ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS="AUTO" ACF_DISABLE_MLAB_RAM_USE="FALSE" ACF_IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE="FALSE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" CLKEN_POWER_OPTIMIZATION="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" DEVICE_FAMILY="Agilex 5" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_COHERENT_READ="FALSE" ENABLE_ECC="FALSE" ENABLE_ECC_ENCODER_BYPASS="FALSE" ENABLE_FORCE_TO_ZERO="FALSE" IMPLEMENT_IN_LES="OFF" INIT_FILE="qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram2_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=2048 NUMWORDS_B=0 OPERATION_MODE="ROM" OPTIMIZATION_OPTION="AUTO" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" OUTDATA_SCLR_A="NONE" OUTDATA_SCLR_B="NONE" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDEN_POWER_OPTIMIZATION="OFF" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" READ_DURING_WRITE_MODE_PORT_A="NEW_DATA_NO_NBE_READ" READ_DURING_WRITE_MODE_PORT_B="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=1 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCENCPARITY=8 WIDTH_ECCSTATUS=3 WIDTHAD2_A=1 WIDTHAD2_B=1 WIDTHAD_A=11 WIDTHAD_B=1 WREN_POWER_OPTIMIZATION="OFF" address_a clock0 q_a CARRY_CHAIN="MANUAL"
--VERSION_BEGIN 26.1 cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION tennm_ram_block (aclr, clk0, clk1, eccencbypass, eccencparity[WIDTH_ECCENCPARITY-1..0], ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddr2[PORT_A_ADDRESS2_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddr2[PORT_B_ADDRESS2_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe, sclr)
WITH ( CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ECC_PIPELINE_STAGE_ENABLED, ENABLE_COHERENT_READ, ENABLE_ECC, ENABLE_ECC_ENCODER_BYPASS, ENABLE_FORCE_TO_ZERO, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, OPTIMIZATION_OPTION, PORT_A_ADDRESS2_WIDTH = 1, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_RDADDRESS_CLEAR, PORT_B_ADDRESS2_WIDTH = 1, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_RDADDRESS_CLEAR, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCENCPARITY = 1, WIDTH_ECCSTATUS = 2)
RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = ram_bits (AUTO) 16384
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altera_syncram_impl_bnt71
(
address_a[10..0] : input;
clock0 : input;
q_a[7..0] : output;
)
VARIABLE
ram_block2a0 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram2_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a1 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram2_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a2 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram2_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a3 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram2_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a4 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram2_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a5 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram2_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a6 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram2_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a7 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram2_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[10..0] : WIRE;
data_a[7..0] : NODE;
wren_a : NODE;
BEGIN
ram_block2a[7..0].clk0 = clock0;
ram_block2a[7..0].portaaddr[] = ( address_a_wire[10..0]);
ram_block2a[0].portadatain[] = ( data_a[0..0]);
ram_block2a[1].portadatain[] = ( data_a[1..1]);
ram_block2a[2].portadatain[] = ( data_a[2..2]);
ram_block2a[3].portadatain[] = ( data_a[3..3]);
ram_block2a[4].portadatain[] = ( data_a[4..4]);
ram_block2a[5].portadatain[] = ( data_a[5..5]);
ram_block2a[6].portadatain[] = ( data_a[6..6]);
ram_block2a[7].portadatain[] = ( data_a[7..7]);
ram_block2a[7..0].portawe = wren_a;
ram_block2a[7..0].portbaddr[] = ( address_a_wire[10..0]);
ram_block2a[7..0].portbre = B"11111111";
address_a_wire[] = address_a[];
data_a[] = VCC;
q_a[] = ( ram_block2a[7..0].portbdataout[0..0]);
wren_a = GND;
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_d2gq.tdf
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_fihn1.tdf
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_gsmn.tdf
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_hlsq1.tdf
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_j85g1.tdf
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_rq6n.tdf
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_scbg.tdf
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_su9o.tdf
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--altera_syncram_nd_impl ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS="AUTO" ACF_DISABLE_MLAB_RAM_USE="FALSE" ACF_IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE="FALSE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" CLKEN_POWER_OPTIMIZATION="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" DEVICE_FAMILY="Agilex 5" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_COHERENT_READ="FALSE" ENABLE_ECC="FALSE" ENABLE_ECC_ENCODER_BYPASS="FALSE" ENABLE_FORCE_TO_ZERO="FALSE" IMPLEMENT_IN_LES="OFF" INIT_FILE="qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=2048 NUMWORDS_B=0 OPERATION_MODE="ROM" OPTIMIZATION_OPTION="AUTO" OUTDATA_ACLR_A="CLEAR0" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" OUTDATA_SCLR_A="NONE" OUTDATA_SCLR_B="NONE" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDEN_POWER_OPTIMIZATION="OFF" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" READ_DURING_WRITE_MODE_PORT_A="NEW_DATA_NO_NBE_READ" READ_DURING_WRITE_MODE_PORT_B="NEW_DATA_NO_NBE_READ" WIDTH_A=25 WIDTH_B=1 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCENCPARITY=8 WIDTH_ECCSTATUS=3 WIDTHAD2_A=1 WIDTHAD2_B=1 WIDTHAD_A=11 WIDTHAD_B=1 WREN_POWER_OPTIMIZATION="OFF" aclr0 address_a clock0 q_a CARRY_CHAIN="MANUAL"
--VERSION_BEGIN 26.1 cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION tennm_ram_block (aclr, clk0, clk1, eccencbypass, eccencparity[WIDTH_ECCENCPARITY-1..0], ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddr2[PORT_A_ADDRESS2_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddr2[PORT_B_ADDRESS2_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe, sclr)
WITH ( CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ECC_PIPELINE_STAGE_ENABLED, ENABLE_COHERENT_READ, ENABLE_ECC, ENABLE_ECC_ENCODER_BYPASS, ENABLE_FORCE_TO_ZERO, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, OPTIMIZATION_OPTION, PORT_A_ADDRESS2_WIDTH = 1, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_RDADDRESS_CLEAR, PORT_B_ADDRESS2_WIDTH = 1, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_RDADDRESS_CLEAR, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCENCPARITY = 1, WIDTH_ECCSTATUS = 2)
RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = ram_bits (AUTO) 51200
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altera_syncram_impl_su9o
(
aclr0 : input;
address_a[10..0] : input;
clock0 : input;
q_a[24..0] : output;
)
VARIABLE
ram_block2a0 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a1 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a2 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a3 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a4 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a5 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a6 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a7 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a8 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 8,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a9 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 9,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 9,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a10 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 10,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 10,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a11 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 11,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 11,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a12 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 12,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 12,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a13 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 13,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 13,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a14 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 14,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a15 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 15,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a16 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 16,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a17 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 17,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 17,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a18 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 18,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a19 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 19,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a20 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 20,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a21 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 21,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a22 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 22,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a23 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 23,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 23,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block2a24 : tennm_ram_block
WITH (
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram7_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
OPERATION_MODE = "dual_port",
OPTIMIZATION_OPTION = "auto",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 25,
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 11,
PORT_B_DATA_OUT_CLEAR = "aclear",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 24,
PORT_B_LAST_ADDRESS = 2047,
PORT_B_LOGICAL_RAM_DEPTH = 2048,
PORT_B_LOGICAL_RAM_WIDTH = 25,
PORT_B_RDADDRESS_CLEAR = "none",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[10..0] : WIRE;
data_a[24..0] : NODE;
wren_a : NODE;
BEGIN
ram_block2a[24..0].aclr = aclr0;
ram_block2a[24..0].clk0 = clock0;
ram_block2a[24..0].portaaddr[] = ( address_a_wire[10..0]);
ram_block2a[0].portadatain[] = ( data_a[0..0]);
ram_block2a[1].portadatain[] = ( data_a[1..1]);
ram_block2a[2].portadatain[] = ( data_a[2..2]);
ram_block2a[3].portadatain[] = ( data_a[3..3]);
ram_block2a[4].portadatain[] = ( data_a[4..4]);
ram_block2a[5].portadatain[] = ( data_a[5..5]);
ram_block2a[6].portadatain[] = ( data_a[6..6]);
ram_block2a[7].portadatain[] = ( data_a[7..7]);
ram_block2a[8].portadatain[] = ( data_a[8..8]);
ram_block2a[9].portadatain[] = ( data_a[9..9]);
ram_block2a[10].portadatain[] = ( data_a[10..10]);
ram_block2a[11].portadatain[] = ( data_a[11..11]);
ram_block2a[12].portadatain[] = ( data_a[12..12]);
ram_block2a[13].portadatain[] = ( data_a[13..13]);
ram_block2a[14].portadatain[] = ( data_a[14..14]);
ram_block2a[15].portadatain[] = ( data_a[15..15]);
ram_block2a[16].portadatain[] = ( data_a[16..16]);
ram_block2a[17].portadatain[] = ( data_a[17..17]);
ram_block2a[18].portadatain[] = ( data_a[18..18]);
ram_block2a[19].portadatain[] = ( data_a[19..19]);
ram_block2a[20].portadatain[] = ( data_a[20..20]);
ram_block2a[21].portadatain[] = ( data_a[21..21]);
ram_block2a[22].portadatain[] = ( data_a[22..22]);
ram_block2a[23].portadatain[] = ( data_a[23..23]);
ram_block2a[24].portadatain[] = ( data_a[24..24]);
ram_block2a[24..0].portawe = wren_a;
ram_block2a[24..0].portbaddr[] = ( address_a_wire[10..0]);
ram_block2a[24..0].portbre = B"1111111111111111111111111";
address_a_wire[] = address_a[];
data_a[] = VCC;
q_a[] = ( ram_block2a[24..0].portbdataout[0..0]);
wren_a = GND;
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_impl_t0ga1.tdf
-7257
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File diff suppressed because it is too large Load Diff
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_j2gd1.tdf
-49
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@@ -1,49 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="CLEAR0" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LOW_POWER_MODE="AUTO" NUMWORDS_A=16 NUMWORDS_B=16 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=320 WIDTH_B=320 WIDTHAD_A=4 WIDTHAD_B=4 aclr0 address_a address_b clock0 clock1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_j85g1 (aclr0, address_a[3..0], address_b[3..0], clock0, clock1, data_a[319..0], wren_a)
RETURNS ( q_b[319..0]);
--synthesis_resources = ram_bits (AUTO) 5120
SUBDESIGN altera_syncram_j2gd1
(
aclr0 : input;
address_a[3..0] : input;
address_b[3..0] : input;
clock0 : input;
clock1 : input;
data_a[319..0] : input;
q_b[319..0] : output;
wren_a : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_j85g1;
BEGIN
altera_syncram_impl1.aclr0 = aclr0;
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.address_b[] = address_b[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.clock1 = clock1;
altera_syncram_impl1.data_a[] = data_a[];
altera_syncram_impl1.wren_a = wren_a;
q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_k8rl1.tdf
-49
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@@ -1,49 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_SINGLE_OUTPUT_FILE="OFF" CLOCK_ENABLE_INPUT_B="BYPASS" DEVICE_FAMILY="Agilex 5" ENABLE_ECC="FALSE" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" WIDTH_A=266 WIDTH_B=266 WIDTH_BYTEENA_A=1 WIDTH_ECCSTATUS=2 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_8u7u1 (address_a[4..0], address_b[4..0], clock0, clock1, clocken1, data_a[265..0], wren_a)
RETURNS ( q_b[265..0]);
--synthesis_resources = ram_bits (AUTO) 8512
SUBDESIGN altera_syncram_k8rl1
(
address_a[4..0] : input;
address_b[4..0] : input;
clock0 : input;
clock1 : input;
clocken1 : input;
data_a[265..0] : input;
q_b[265..0] : output;
wren_a : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_8u7u1;
BEGIN
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.address_b[] = address_b[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.clock1 = clock1;
altera_syncram_impl1.clocken1 = clocken1;
altera_syncram_impl1.data_a[] = data_a[];
altera_syncram_impl1.wren_a = wren_a;
q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_mj1c1.tdf
-47
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@@ -1,47 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LOW_POWER_MODE="AUTO" NUMWORDS_A=32768 NUMWORDS_B=32768 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=15 WIDTHAD_B=15 address_a address_b byteena_a clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_8sj71 (address_a[14..0], address_b[14..0], byteena_a[3..0], clock0, data_a[31..0], wren_a)
RETURNS ( q_b[31..0]);
--synthesis_resources = lut 178 ram_bits (AUTO) 1048576 reg 4
SUBDESIGN altera_syncram_mj1c1
(
address_a[14..0] : input;
address_b[14..0] : input;
byteena_a[3..0] : input;
clock0 : input;
data_a[31..0] : input;
q_b[31..0] : output;
wren_a : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_8sj71;
BEGIN
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.address_b[] = address_b[];
altera_syncram_impl1.byteena_a[] = byteena_a[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.data_a[] = data_a[];
altera_syncram_impl1.wren_a = wren_a;
q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_mjo02.tdf
-49
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@@ -1,49 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="CLEAR0" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LOW_POWER_MODE="AUTO" NUMWORDS_A=8 NUMWORDS_B=8 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=240 WIDTH_B=240 WIDTHAD_A=3 WIDTHAD_B=3 aclr0 address_a address_b clock0 clock1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_t0ga1 (aclr0, address_a[2..0], address_b[2..0], clock0, clock1, data_a[239..0], wren_a)
RETURNS ( q_b[239..0]);
--synthesis_resources = ram_bits (AUTO) 1920
SUBDESIGN altera_syncram_mjo02
(
aclr0 : input;
address_a[2..0] : input;
address_b[2..0] : input;
clock0 : input;
clock1 : input;
data_a[239..0] : input;
q_b[239..0] : output;
wren_a : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_t0ga1;
BEGIN
altera_syncram_impl1.aclr0 = aclr0;
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.address_b[] = address_b[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.clock1 = clock1;
altera_syncram_impl1.data_a[] = data_a[];
altera_syncram_impl1.wren_a = wren_a;
q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/altera_syncram_pgtk.tdf
-45
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@@ -1,45 +0,0 @@
--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" INIT_FILE="qdb/_compiler/de25_nano_psmct32_raster_demo_top/root_partition/26.1.0/partitioned/1/mifs/ram4_de25_nano_psmct32_raster_demo_top_24852d2f.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_SCLR_A="SCLEAR" WIDTH_A=128 WIDTH_BYTEENA_A=16 WIDTHAD_A=11 address_a byteena_a clock0 q_a rden_a sclr CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 26.1 cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION altera_syncram_impl_d2gq (address_a[10..0], byteena_a[15..0], clock0, rden_a, sclr)
RETURNS ( q_a[127..0]);
--synthesis_resources = ram_bits (AUTO) 262144
SUBDESIGN altera_syncram_pgtk
(
address_a[10..0] : input;
byteena_a[15..0] : input;
clock0 : input;
q_a[127..0] : output;
rden_a : input;
sclr : input;
)
VARIABLE
altera_syncram_impl1 : altera_syncram_impl_d2gq;
BEGIN
altera_syncram_impl1.address_a[] = address_a[];
altera_syncram_impl1.byteena_a[] = byteena_a[];
altera_syncram_impl1.clock0 = clock0;
altera_syncram_impl1.rden_a = rden_a;
altera_syncram_impl1.sclr = sclr;
q_a[] = altera_syncram_impl1.q_a[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/cmpr_jdut1.tdf
-42
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@@ -1,42 +0,0 @@
--lpm_compare CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LPM_WIDTH=5 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
--VERSION_BEGIN 26.1 cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
--synthesis_resources =
SUBDESIGN cmpr_jdut1
(
aeb : output;
dataa[4..0] : input;
datab[4..0] : input;
)
VARIABLE
aeb_result_wire[0..0] : WIRE;
aneb_result_wire[0..0] : WIRE;
data_wire[12..0] : WIRE;
eq_wire : WIRE;
BEGIN
aeb = eq_wire;
aeb_result_wire[] = (! aneb_result_wire[]);
aneb_result_wire[] = ((data_wire[0..0] # data_wire[1..1]) # data_wire[2..2]);
data_wire[] = ( datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[11..11] $ data_wire[12..12]), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), ((data_wire[3..3] $ data_wire[4..4]) # (data_wire[5..5] $ data_wire[6..6])));
eq_wire = aeb_result_wire[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/decode_1j971.tdf
-116
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@@ -1,116 +0,0 @@
--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LPM_DECODES=32 LPM_WIDTH=5 data enable eq
--VERSION_BEGIN 26.1 cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
--synthesis_resources = lut 36
SUBDESIGN decode_1j971
(
data[4..0] : input;
enable : input;
eq[31..0] : output;
)
VARIABLE
data_wire[4..0] : WIRE;
enable_wire : WIRE;
eq_node[31..0] : WIRE;
eq_wire[31..0] : WIRE;
w_anode8297w[2..0] : WIRE;
w_anode8310w[3..0] : WIRE;
w_anode8327w[3..0] : WIRE;
w_anode8337w[3..0] : WIRE;
w_anode8347w[3..0] : WIRE;
w_anode8357w[3..0] : WIRE;
w_anode8367w[3..0] : WIRE;
w_anode8377w[3..0] : WIRE;
w_anode8387w[3..0] : WIRE;
w_anode8399w[2..0] : WIRE;
w_anode8408w[3..0] : WIRE;
w_anode8419w[3..0] : WIRE;
w_anode8429w[3..0] : WIRE;
w_anode8439w[3..0] : WIRE;
w_anode8449w[3..0] : WIRE;
w_anode8459w[3..0] : WIRE;
w_anode8469w[3..0] : WIRE;
w_anode8479w[3..0] : WIRE;
w_anode8490w[2..0] : WIRE;
w_anode8499w[3..0] : WIRE;
w_anode8510w[3..0] : WIRE;
w_anode8520w[3..0] : WIRE;
w_anode8530w[3..0] : WIRE;
w_anode8540w[3..0] : WIRE;
w_anode8550w[3..0] : WIRE;
w_anode8560w[3..0] : WIRE;
w_anode8570w[3..0] : WIRE;
w_anode8581w[2..0] : WIRE;
w_anode8590w[3..0] : WIRE;
w_anode8601w[3..0] : WIRE;
w_anode8611w[3..0] : WIRE;
w_anode8621w[3..0] : WIRE;
w_anode8631w[3..0] : WIRE;
w_anode8641w[3..0] : WIRE;
w_anode8651w[3..0] : WIRE;
w_anode8661w[3..0] : WIRE;
w_data8295w[2..0] : WIRE;
BEGIN
data_wire[] = data[];
enable_wire = enable;
eq[] = eq_node[];
eq_node[31..0] = eq_wire[31..0];
eq_wire[] = ( ( w_anode8661w[3..3], w_anode8651w[3..3], w_anode8641w[3..3], w_anode8631w[3..3], w_anode8621w[3..3], w_anode8611w[3..3], w_anode8601w[3..3], w_anode8590w[3..3]), ( w_anode8570w[3..3], w_anode8560w[3..3], w_anode8550w[3..3], w_anode8540w[3..3], w_anode8530w[3..3], w_anode8520w[3..3], w_anode8510w[3..3], w_anode8499w[3..3]), ( w_anode8479w[3..3], w_anode8469w[3..3], w_anode8459w[3..3], w_anode8449w[3..3], w_anode8439w[3..3], w_anode8429w[3..3], w_anode8419w[3..3], w_anode8408w[3..3]), ( w_anode8387w[3..3], w_anode8377w[3..3], w_anode8367w[3..3], w_anode8357w[3..3], w_anode8347w[3..3], w_anode8337w[3..3], w_anode8327w[3..3], w_anode8310w[3..3]));
w_anode8297w[] = ( (w_anode8297w[1..1] & (! data_wire[4..4])), (w_anode8297w[0..0] & (! data_wire[3..3])), enable_wire);
w_anode8310w[] = ( (w_anode8310w[2..2] & (! w_data8295w[2..2])), (w_anode8310w[1..1] & (! w_data8295w[1..1])), (w_anode8310w[0..0] & (! w_data8295w[0..0])), w_anode8297w[2..2]);
w_anode8327w[] = ( (w_anode8327w[2..2] & (! w_data8295w[2..2])), (w_anode8327w[1..1] & (! w_data8295w[1..1])), (w_anode8327w[0..0] & w_data8295w[0..0]), w_anode8297w[2..2]);
w_anode8337w[] = ( (w_anode8337w[2..2] & (! w_data8295w[2..2])), (w_anode8337w[1..1] & w_data8295w[1..1]), (w_anode8337w[0..0] & (! w_data8295w[0..0])), w_anode8297w[2..2]);
w_anode8347w[] = ( (w_anode8347w[2..2] & (! w_data8295w[2..2])), (w_anode8347w[1..1] & w_data8295w[1..1]), (w_anode8347w[0..0] & w_data8295w[0..0]), w_anode8297w[2..2]);
w_anode8357w[] = ( (w_anode8357w[2..2] & w_data8295w[2..2]), (w_anode8357w[1..1] & (! w_data8295w[1..1])), (w_anode8357w[0..0] & (! w_data8295w[0..0])), w_anode8297w[2..2]);
w_anode8367w[] = ( (w_anode8367w[2..2] & w_data8295w[2..2]), (w_anode8367w[1..1] & (! w_data8295w[1..1])), (w_anode8367w[0..0] & w_data8295w[0..0]), w_anode8297w[2..2]);
w_anode8377w[] = ( (w_anode8377w[2..2] & w_data8295w[2..2]), (w_anode8377w[1..1] & w_data8295w[1..1]), (w_anode8377w[0..0] & (! w_data8295w[0..0])), w_anode8297w[2..2]);
w_anode8387w[] = ( (w_anode8387w[2..2] & w_data8295w[2..2]), (w_anode8387w[1..1] & w_data8295w[1..1]), (w_anode8387w[0..0] & w_data8295w[0..0]), w_anode8297w[2..2]);
w_anode8399w[] = ( (w_anode8399w[1..1] & (! data_wire[4..4])), (w_anode8399w[0..0] & data_wire[3..3]), enable_wire);
w_anode8408w[] = ( (w_anode8408w[2..2] & (! w_data8295w[2..2])), (w_anode8408w[1..1] & (! w_data8295w[1..1])), (w_anode8408w[0..0] & (! w_data8295w[0..0])), w_anode8399w[2..2]);
w_anode8419w[] = ( (w_anode8419w[2..2] & (! w_data8295w[2..2])), (w_anode8419w[1..1] & (! w_data8295w[1..1])), (w_anode8419w[0..0] & w_data8295w[0..0]), w_anode8399w[2..2]);
w_anode8429w[] = ( (w_anode8429w[2..2] & (! w_data8295w[2..2])), (w_anode8429w[1..1] & w_data8295w[1..1]), (w_anode8429w[0..0] & (! w_data8295w[0..0])), w_anode8399w[2..2]);
w_anode8439w[] = ( (w_anode8439w[2..2] & (! w_data8295w[2..2])), (w_anode8439w[1..1] & w_data8295w[1..1]), (w_anode8439w[0..0] & w_data8295w[0..0]), w_anode8399w[2..2]);
w_anode8449w[] = ( (w_anode8449w[2..2] & w_data8295w[2..2]), (w_anode8449w[1..1] & (! w_data8295w[1..1])), (w_anode8449w[0..0] & (! w_data8295w[0..0])), w_anode8399w[2..2]);
w_anode8459w[] = ( (w_anode8459w[2..2] & w_data8295w[2..2]), (w_anode8459w[1..1] & (! w_data8295w[1..1])), (w_anode8459w[0..0] & w_data8295w[0..0]), w_anode8399w[2..2]);
w_anode8469w[] = ( (w_anode8469w[2..2] & w_data8295w[2..2]), (w_anode8469w[1..1] & w_data8295w[1..1]), (w_anode8469w[0..0] & (! w_data8295w[0..0])), w_anode8399w[2..2]);
w_anode8479w[] = ( (w_anode8479w[2..2] & w_data8295w[2..2]), (w_anode8479w[1..1] & w_data8295w[1..1]), (w_anode8479w[0..0] & w_data8295w[0..0]), w_anode8399w[2..2]);
w_anode8490w[] = ( (w_anode8490w[1..1] & data_wire[4..4]), (w_anode8490w[0..0] & (! data_wire[3..3])), enable_wire);
w_anode8499w[] = ( (w_anode8499w[2..2] & (! w_data8295w[2..2])), (w_anode8499w[1..1] & (! w_data8295w[1..1])), (w_anode8499w[0..0] & (! w_data8295w[0..0])), w_anode8490w[2..2]);
w_anode8510w[] = ( (w_anode8510w[2..2] & (! w_data8295w[2..2])), (w_anode8510w[1..1] & (! w_data8295w[1..1])), (w_anode8510w[0..0] & w_data8295w[0..0]), w_anode8490w[2..2]);
w_anode8520w[] = ( (w_anode8520w[2..2] & (! w_data8295w[2..2])), (w_anode8520w[1..1] & w_data8295w[1..1]), (w_anode8520w[0..0] & (! w_data8295w[0..0])), w_anode8490w[2..2]);
w_anode8530w[] = ( (w_anode8530w[2..2] & (! w_data8295w[2..2])), (w_anode8530w[1..1] & w_data8295w[1..1]), (w_anode8530w[0..0] & w_data8295w[0..0]), w_anode8490w[2..2]);
w_anode8540w[] = ( (w_anode8540w[2..2] & w_data8295w[2..2]), (w_anode8540w[1..1] & (! w_data8295w[1..1])), (w_anode8540w[0..0] & (! w_data8295w[0..0])), w_anode8490w[2..2]);
w_anode8550w[] = ( (w_anode8550w[2..2] & w_data8295w[2..2]), (w_anode8550w[1..1] & (! w_data8295w[1..1])), (w_anode8550w[0..0] & w_data8295w[0..0]), w_anode8490w[2..2]);
w_anode8560w[] = ( (w_anode8560w[2..2] & w_data8295w[2..2]), (w_anode8560w[1..1] & w_data8295w[1..1]), (w_anode8560w[0..0] & (! w_data8295w[0..0])), w_anode8490w[2..2]);
w_anode8570w[] = ( (w_anode8570w[2..2] & w_data8295w[2..2]), (w_anode8570w[1..1] & w_data8295w[1..1]), (w_anode8570w[0..0] & w_data8295w[0..0]), w_anode8490w[2..2]);
w_anode8581w[] = ( (w_anode8581w[1..1] & data_wire[4..4]), (w_anode8581w[0..0] & data_wire[3..3]), enable_wire);
w_anode8590w[] = ( (w_anode8590w[2..2] & (! w_data8295w[2..2])), (w_anode8590w[1..1] & (! w_data8295w[1..1])), (w_anode8590w[0..0] & (! w_data8295w[0..0])), w_anode8581w[2..2]);
w_anode8601w[] = ( (w_anode8601w[2..2] & (! w_data8295w[2..2])), (w_anode8601w[1..1] & (! w_data8295w[1..1])), (w_anode8601w[0..0] & w_data8295w[0..0]), w_anode8581w[2..2]);
w_anode8611w[] = ( (w_anode8611w[2..2] & (! w_data8295w[2..2])), (w_anode8611w[1..1] & w_data8295w[1..1]), (w_anode8611w[0..0] & (! w_data8295w[0..0])), w_anode8581w[2..2]);
w_anode8621w[] = ( (w_anode8621w[2..2] & (! w_data8295w[2..2])), (w_anode8621w[1..1] & w_data8295w[1..1]), (w_anode8621w[0..0] & w_data8295w[0..0]), w_anode8581w[2..2]);
w_anode8631w[] = ( (w_anode8631w[2..2] & w_data8295w[2..2]), (w_anode8631w[1..1] & (! w_data8295w[1..1])), (w_anode8631w[0..0] & (! w_data8295w[0..0])), w_anode8581w[2..2]);
w_anode8641w[] = ( (w_anode8641w[2..2] & w_data8295w[2..2]), (w_anode8641w[1..1] & (! w_data8295w[1..1])), (w_anode8641w[0..0] & w_data8295w[0..0]), w_anode8581w[2..2]);
w_anode8651w[] = ( (w_anode8651w[2..2] & w_data8295w[2..2]), (w_anode8651w[1..1] & w_data8295w[1..1]), (w_anode8651w[0..0] & (! w_data8295w[0..0])), w_anode8581w[2..2]);
w_anode8661w[] = ( (w_anode8661w[2..2] & w_data8295w[2..2]), (w_anode8661w[1..1] & w_data8295w[1..1]), (w_anode8661w[0..0] & w_data8295w[0..0]), w_anode8581w[2..2]);
w_data8295w[2..0] = data_wire[2..0];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/decode_m7op.tdf
-80
View File
@@ -1,80 +0,0 @@
--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LPM_DECODES=16 LPM_WIDTH=4 data enable eq
--VERSION_BEGIN 26.1 cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
--synthesis_resources = lut 18
SUBDESIGN decode_m7op
(
data[3..0] : input;
enable : input;
eq[15..0] : output;
)
VARIABLE
data_wire[3..0] : WIRE;
enable_wire : WIRE;
eq_node[15..0] : WIRE;
eq_wire[15..0] : WIRE;
w_anode5197w[1..0] : WIRE;
w_anode5206w[3..0] : WIRE;
w_anode5223w[3..0] : WIRE;
w_anode5233w[3..0] : WIRE;
w_anode5243w[3..0] : WIRE;
w_anode5253w[3..0] : WIRE;
w_anode5263w[3..0] : WIRE;
w_anode5273w[3..0] : WIRE;
w_anode5283w[3..0] : WIRE;
w_anode5295w[1..0] : WIRE;
w_anode5302w[3..0] : WIRE;
w_anode5313w[3..0] : WIRE;
w_anode5323w[3..0] : WIRE;
w_anode5333w[3..0] : WIRE;
w_anode5343w[3..0] : WIRE;
w_anode5353w[3..0] : WIRE;
w_anode5363w[3..0] : WIRE;
w_anode5373w[3..0] : WIRE;
w_data5195w[2..0] : WIRE;
BEGIN
data_wire[] = data[];
enable_wire = enable;
eq[] = eq_node[];
eq_node[15..0] = eq_wire[15..0];
eq_wire[] = ( ( w_anode5373w[3..3], w_anode5363w[3..3], w_anode5353w[3..3], w_anode5343w[3..3], w_anode5333w[3..3], w_anode5323w[3..3], w_anode5313w[3..3], w_anode5302w[3..3]), ( w_anode5283w[3..3], w_anode5273w[3..3], w_anode5263w[3..3], w_anode5253w[3..3], w_anode5243w[3..3], w_anode5233w[3..3], w_anode5223w[3..3], w_anode5206w[3..3]));
w_anode5197w[] = ( (w_anode5197w[0..0] & (! data_wire[3..3])), enable_wire);
w_anode5206w[] = ( (w_anode5206w[2..2] & (! w_data5195w[2..2])), (w_anode5206w[1..1] & (! w_data5195w[1..1])), (w_anode5206w[0..0] & (! w_data5195w[0..0])), w_anode5197w[1..1]);
w_anode5223w[] = ( (w_anode5223w[2..2] & (! w_data5195w[2..2])), (w_anode5223w[1..1] & (! w_data5195w[1..1])), (w_anode5223w[0..0] & w_data5195w[0..0]), w_anode5197w[1..1]);
w_anode5233w[] = ( (w_anode5233w[2..2] & (! w_data5195w[2..2])), (w_anode5233w[1..1] & w_data5195w[1..1]), (w_anode5233w[0..0] & (! w_data5195w[0..0])), w_anode5197w[1..1]);
w_anode5243w[] = ( (w_anode5243w[2..2] & (! w_data5195w[2..2])), (w_anode5243w[1..1] & w_data5195w[1..1]), (w_anode5243w[0..0] & w_data5195w[0..0]), w_anode5197w[1..1]);
w_anode5253w[] = ( (w_anode5253w[2..2] & w_data5195w[2..2]), (w_anode5253w[1..1] & (! w_data5195w[1..1])), (w_anode5253w[0..0] & (! w_data5195w[0..0])), w_anode5197w[1..1]);
w_anode5263w[] = ( (w_anode5263w[2..2] & w_data5195w[2..2]), (w_anode5263w[1..1] & (! w_data5195w[1..1])), (w_anode5263w[0..0] & w_data5195w[0..0]), w_anode5197w[1..1]);
w_anode5273w[] = ( (w_anode5273w[2..2] & w_data5195w[2..2]), (w_anode5273w[1..1] & w_data5195w[1..1]), (w_anode5273w[0..0] & (! w_data5195w[0..0])), w_anode5197w[1..1]);
w_anode5283w[] = ( (w_anode5283w[2..2] & w_data5195w[2..2]), (w_anode5283w[1..1] & w_data5195w[1..1]), (w_anode5283w[0..0] & w_data5195w[0..0]), w_anode5197w[1..1]);
w_anode5295w[] = ( (w_anode5295w[0..0] & data_wire[3..3]), enable_wire);
w_anode5302w[] = ( (w_anode5302w[2..2] & (! w_data5195w[2..2])), (w_anode5302w[1..1] & (! w_data5195w[1..1])), (w_anode5302w[0..0] & (! w_data5195w[0..0])), w_anode5295w[1..1]);
w_anode5313w[] = ( (w_anode5313w[2..2] & (! w_data5195w[2..2])), (w_anode5313w[1..1] & (! w_data5195w[1..1])), (w_anode5313w[0..0] & w_data5195w[0..0]), w_anode5295w[1..1]);
w_anode5323w[] = ( (w_anode5323w[2..2] & (! w_data5195w[2..2])), (w_anode5323w[1..1] & w_data5195w[1..1]), (w_anode5323w[0..0] & (! w_data5195w[0..0])), w_anode5295w[1..1]);
w_anode5333w[] = ( (w_anode5333w[2..2] & (! w_data5195w[2..2])), (w_anode5333w[1..1] & w_data5195w[1..1]), (w_anode5333w[0..0] & w_data5195w[0..0]), w_anode5295w[1..1]);
w_anode5343w[] = ( (w_anode5343w[2..2] & w_data5195w[2..2]), (w_anode5343w[1..1] & (! w_data5195w[1..1])), (w_anode5343w[0..0] & (! w_data5195w[0..0])), w_anode5295w[1..1]);
w_anode5353w[] = ( (w_anode5353w[2..2] & w_data5195w[2..2]), (w_anode5353w[1..1] & (! w_data5195w[1..1])), (w_anode5353w[0..0] & w_data5195w[0..0]), w_anode5295w[1..1]);
w_anode5363w[] = ( (w_anode5363w[2..2] & w_data5195w[2..2]), (w_anode5363w[1..1] & w_data5195w[1..1]), (w_anode5363w[0..0] & (! w_data5195w[0..0])), w_anode5295w[1..1]);
w_anode5373w[] = ( (w_anode5373w[2..2] & w_data5195w[2..2]), (w_anode5373w[1..1] & w_data5195w[1..1]), (w_anode5373w[0..0] & w_data5195w[0..0]), w_anode5295w[1..1]);
w_data5195w[2..0] = data_wire[2..0];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/dpram_6mgv1.tdf
-658
View File
@@ -1,658 +0,0 @@
--altdpram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" INDATA_ACLR="OFF" INDATA_REG="INCLOCK" NUMWORDS=8 OUTDATA_ACLR="OFF" OUTDATA_REG="UNREGISTERED" RAM_BLOCK_TYPE="MLAB" RDADDRESS_ACLR="OFF" RDADDRESS_REG="OUTCLOCK" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" WIDTH=46 WIDTHAD=3 WRADDRESS_ACLR="OFF" WRADDRESS_REG="INCLOCK" WRCONTROL_ACLR="OFF" WRCONTROL_REG="INCLOCK" data inclock outclock q rdaddress wraddress wren CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 26.1 cbx_altdpram 2026:03:19:21:42:37:SC cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION tennm_mlab_cell (clk0, clk1, clr, ena0, ena1, ena2, portaaddr[address_width-1..0], portabyteenamasks[byte_enable_mask_width-1..0], portadatain[data_width-1..0], portbaddr[address_width-1..0])
WITH ( address_width = 1, byte_enable_mask_width = 2, data_width = 1, first_address, first_bit_number, init_file, last_address, logical_ram_depth, logical_ram_name, logical_ram_width, mem_init0, mixed_port_feed_through_mode, port_b_data_out_clear, port_b_data_out_clock)
RETURNS ( portbdataout[data_width-1..0]);
--synthesis_resources = MLAB 3 reg 3
SUBDESIGN dpram_6mgv1
(
data[45..0] : input;
inclock : input;
outclock : input;
q[45..0] : output;
rdaddress[2..0] : input;
wraddress[2..0] : input;
wren : input;
)
VARIABLE
lutrama0 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 0,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama1 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 1,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama2 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 2,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama3 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 3,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama4 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 4,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama5 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 5,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama6 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 6,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama7 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 7,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama8 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 8,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama9 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 9,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama10 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 10,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama11 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 11,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama12 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 12,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama13 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 13,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama14 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 14,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama15 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 15,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama16 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 16,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama17 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 17,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama18 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 18,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama19 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 19,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama20 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 20,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama21 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 21,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama22 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 22,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama23 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 23,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama24 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 24,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama25 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 25,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama26 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 26,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama27 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 27,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama28 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 28,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama29 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 29,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama30 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 30,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama31 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 31,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama32 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 32,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama33 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 33,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama34 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 34,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama35 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 35,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama36 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 36,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama37 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 37,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama38 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 38,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama39 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 39,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama40 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 40,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama41 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 41,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama42 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 42,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama43 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 43,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama44 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 44,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
lutrama45 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 45,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 46,
mixed_port_feed_through_mode = "dont care"
);
rdaddr_reg[2..0] : dffe;
datain_wire[45..0] : WIRE;
dataout_latch[45..0] : WIRE;
dataout_wire[45..0] : WIRE;
rdaddr_wire[2..0] : WIRE;
wr_en : WIRE;
wraddr_wire[2..0] : WIRE;
BEGIN
lutrama[45..0].clk0 = inclock;
lutrama[45..0].ena0 = wr_en;
lutrama[45..0].portaaddr[2..0] = wraddr_wire[2..0];
lutrama[0].portadatain[0..0] = datain_wire[0..0];
lutrama[1].portadatain[0..0] = datain_wire[1..1];
lutrama[2].portadatain[0..0] = datain_wire[2..2];
lutrama[3].portadatain[0..0] = datain_wire[3..3];
lutrama[4].portadatain[0..0] = datain_wire[4..4];
lutrama[5].portadatain[0..0] = datain_wire[5..5];
lutrama[6].portadatain[0..0] = datain_wire[6..6];
lutrama[7].portadatain[0..0] = datain_wire[7..7];
lutrama[8].portadatain[0..0] = datain_wire[8..8];
lutrama[9].portadatain[0..0] = datain_wire[9..9];
lutrama[10].portadatain[0..0] = datain_wire[10..10];
lutrama[11].portadatain[0..0] = datain_wire[11..11];
lutrama[12].portadatain[0..0] = datain_wire[12..12];
lutrama[13].portadatain[0..0] = datain_wire[13..13];
lutrama[14].portadatain[0..0] = datain_wire[14..14];
lutrama[15].portadatain[0..0] = datain_wire[15..15];
lutrama[16].portadatain[0..0] = datain_wire[16..16];
lutrama[17].portadatain[0..0] = datain_wire[17..17];
lutrama[18].portadatain[0..0] = datain_wire[18..18];
lutrama[19].portadatain[0..0] = datain_wire[19..19];
lutrama[20].portadatain[0..0] = datain_wire[20..20];
lutrama[21].portadatain[0..0] = datain_wire[21..21];
lutrama[22].portadatain[0..0] = datain_wire[22..22];
lutrama[23].portadatain[0..0] = datain_wire[23..23];
lutrama[24].portadatain[0..0] = datain_wire[24..24];
lutrama[25].portadatain[0..0] = datain_wire[25..25];
lutrama[26].portadatain[0..0] = datain_wire[26..26];
lutrama[27].portadatain[0..0] = datain_wire[27..27];
lutrama[28].portadatain[0..0] = datain_wire[28..28];
lutrama[29].portadatain[0..0] = datain_wire[29..29];
lutrama[30].portadatain[0..0] = datain_wire[30..30];
lutrama[31].portadatain[0..0] = datain_wire[31..31];
lutrama[32].portadatain[0..0] = datain_wire[32..32];
lutrama[33].portadatain[0..0] = datain_wire[33..33];
lutrama[34].portadatain[0..0] = datain_wire[34..34];
lutrama[35].portadatain[0..0] = datain_wire[35..35];
lutrama[36].portadatain[0..0] = datain_wire[36..36];
lutrama[37].portadatain[0..0] = datain_wire[37..37];
lutrama[38].portadatain[0..0] = datain_wire[38..38];
lutrama[39].portadatain[0..0] = datain_wire[39..39];
lutrama[40].portadatain[0..0] = datain_wire[40..40];
lutrama[41].portadatain[0..0] = datain_wire[41..41];
lutrama[42].portadatain[0..0] = datain_wire[42..42];
lutrama[43].portadatain[0..0] = datain_wire[43..43];
lutrama[44].portadatain[0..0] = datain_wire[44..44];
lutrama[45].portadatain[0..0] = datain_wire[45..45];
lutrama[45..0].portbaddr[2..0] = rdaddr_wire[2..0];
rdaddr_reg[].clk = outclock;
rdaddr_reg[].d = rdaddress[];
datain_wire[] = data[];
dataout_latch[] = dataout_wire[];
dataout_wire[] = lutrama[45..0].portbdataout[];
q[] = dataout_latch[];
rdaddr_wire[] = rdaddr_reg[].q;
wr_en = wren;
wraddr_wire[] = wraddress[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/dpram_6vba.tdf
-580
View File
@@ -1,580 +0,0 @@
--altdpram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" INDATA_ACLR="OFF" INDATA_REG="INCLOCK" NUMWORDS=8 OUTDATA_ACLR="OFF" OUTDATA_REG="UNREGISTERED" RAM_BLOCK_TYPE="MLAB" RDADDRESS_ACLR="OFF" RDADDRESS_REG="OUTCLOCK" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" WIDTH=40 WIDTHAD=3 WRADDRESS_ACLR="OFF" WRADDRESS_REG="INCLOCK" WRCONTROL_ACLR="OFF" WRCONTROL_REG="INCLOCK" data inclock outclock q rdaddress wraddress wren CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 26.1 cbx_altdpram 2026:03:19:21:42:37:SC cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION tennm_mlab_cell (clk0, clk1, clr, ena0, ena1, ena2, portaaddr[address_width-1..0], portabyteenamasks[byte_enable_mask_width-1..0], portadatain[data_width-1..0], portbaddr[address_width-1..0])
WITH ( address_width = 1, byte_enable_mask_width = 2, data_width = 1, first_address, first_bit_number, init_file, last_address, logical_ram_depth, logical_ram_name, logical_ram_width, mem_init0, mixed_port_feed_through_mode, port_b_data_out_clear, port_b_data_out_clock)
RETURNS ( portbdataout[data_width-1..0]);
--synthesis_resources = MLAB 2 reg 3
SUBDESIGN dpram_6vba
(
data[39..0] : input;
inclock : input;
outclock : input;
q[39..0] : output;
rdaddress[2..0] : input;
wraddress[2..0] : input;
wren : input;
)
VARIABLE
lutrama0 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 0,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama1 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 1,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama2 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 2,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama3 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 3,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama4 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 4,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama5 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 5,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama6 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 6,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama7 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 7,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama8 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 8,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama9 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 9,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama10 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 10,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama11 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 11,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama12 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 12,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama13 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 13,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama14 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 14,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama15 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 15,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama16 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 16,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama17 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 17,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama18 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 18,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama19 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 19,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama20 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 20,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama21 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 21,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama22 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 22,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama23 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 23,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama24 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 24,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama25 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 25,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama26 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 26,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama27 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 27,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama28 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 28,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama29 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 29,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama30 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 30,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama31 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 31,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama32 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 32,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama33 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 33,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama34 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 34,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama35 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 35,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama36 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 36,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama37 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 37,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama38 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 38,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
lutrama39 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 39,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 40,
mixed_port_feed_through_mode = "dont care"
);
rdaddr_reg[2..0] : dffe;
datain_wire[39..0] : WIRE;
dataout_latch[39..0] : WIRE;
dataout_wire[39..0] : WIRE;
rdaddr_wire[2..0] : WIRE;
wr_en : WIRE;
wraddr_wire[2..0] : WIRE;
BEGIN
lutrama[39..0].clk0 = inclock;
lutrama[39..0].ena0 = wr_en;
lutrama[39..0].portaaddr[2..0] = wraddr_wire[2..0];
lutrama[0].portadatain[0..0] = datain_wire[0..0];
lutrama[1].portadatain[0..0] = datain_wire[1..1];
lutrama[2].portadatain[0..0] = datain_wire[2..2];
lutrama[3].portadatain[0..0] = datain_wire[3..3];
lutrama[4].portadatain[0..0] = datain_wire[4..4];
lutrama[5].portadatain[0..0] = datain_wire[5..5];
lutrama[6].portadatain[0..0] = datain_wire[6..6];
lutrama[7].portadatain[0..0] = datain_wire[7..7];
lutrama[8].portadatain[0..0] = datain_wire[8..8];
lutrama[9].portadatain[0..0] = datain_wire[9..9];
lutrama[10].portadatain[0..0] = datain_wire[10..10];
lutrama[11].portadatain[0..0] = datain_wire[11..11];
lutrama[12].portadatain[0..0] = datain_wire[12..12];
lutrama[13].portadatain[0..0] = datain_wire[13..13];
lutrama[14].portadatain[0..0] = datain_wire[14..14];
lutrama[15].portadatain[0..0] = datain_wire[15..15];
lutrama[16].portadatain[0..0] = datain_wire[16..16];
lutrama[17].portadatain[0..0] = datain_wire[17..17];
lutrama[18].portadatain[0..0] = datain_wire[18..18];
lutrama[19].portadatain[0..0] = datain_wire[19..19];
lutrama[20].portadatain[0..0] = datain_wire[20..20];
lutrama[21].portadatain[0..0] = datain_wire[21..21];
lutrama[22].portadatain[0..0] = datain_wire[22..22];
lutrama[23].portadatain[0..0] = datain_wire[23..23];
lutrama[24].portadatain[0..0] = datain_wire[24..24];
lutrama[25].portadatain[0..0] = datain_wire[25..25];
lutrama[26].portadatain[0..0] = datain_wire[26..26];
lutrama[27].portadatain[0..0] = datain_wire[27..27];
lutrama[28].portadatain[0..0] = datain_wire[28..28];
lutrama[29].portadatain[0..0] = datain_wire[29..29];
lutrama[30].portadatain[0..0] = datain_wire[30..30];
lutrama[31].portadatain[0..0] = datain_wire[31..31];
lutrama[32].portadatain[0..0] = datain_wire[32..32];
lutrama[33].portadatain[0..0] = datain_wire[33..33];
lutrama[34].portadatain[0..0] = datain_wire[34..34];
lutrama[35].portadatain[0..0] = datain_wire[35..35];
lutrama[36].portadatain[0..0] = datain_wire[36..36];
lutrama[37].portadatain[0..0] = datain_wire[37..37];
lutrama[38].portadatain[0..0] = datain_wire[38..38];
lutrama[39].portadatain[0..0] = datain_wire[39..39];
lutrama[39..0].portbaddr[2..0] = rdaddr_wire[2..0];
rdaddr_reg[].clk = outclock;
rdaddr_reg[].d = rdaddress[];
datain_wire[] = data[];
dataout_latch[] = dataout_wire[];
dataout_wire[] = lutrama[39..0].portbdataout[];
q[] = dataout_latch[];
rdaddr_wire[] = rdaddr_reg[].q;
wr_en = wren;
wraddr_wire[] = wraddress[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/dpram_gtv62.tdf
-1724
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File diff suppressed because it is too large Load Diff
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/dpram_qkuh.tdf
-177
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@@ -1,177 +0,0 @@
--altdpram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" INDATA_ACLR="OFF" INDATA_REG="INCLOCK" NUMWORDS=8 OUTDATA_ACLR="OFF" OUTDATA_REG="UNREGISTERED" RAM_BLOCK_TYPE="MLAB" RDADDRESS_ACLR="OFF" RDADDRESS_REG="OUTCLOCK" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" WIDTH=9 WIDTHAD=3 WRADDRESS_ACLR="OFF" WRADDRESS_REG="INCLOCK" WRCONTROL_ACLR="OFF" WRCONTROL_REG="INCLOCK" data inclock outclock q rdaddress wraddress wren CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 26.1 cbx_altdpram 2026:03:19:21:42:37:SC cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION tennm_mlab_cell (clk0, clk1, clr, ena0, ena1, ena2, portaaddr[address_width-1..0], portabyteenamasks[byte_enable_mask_width-1..0], portadatain[data_width-1..0], portbaddr[address_width-1..0])
WITH ( address_width = 1, byte_enable_mask_width = 2, data_width = 1, first_address, first_bit_number, init_file, last_address, logical_ram_depth, logical_ram_name, logical_ram_width, mem_init0, mixed_port_feed_through_mode, port_b_data_out_clear, port_b_data_out_clock)
RETURNS ( portbdataout[data_width-1..0]);
--synthesis_resources = MLAB 1 reg 3
SUBDESIGN dpram_qkuh
(
data[8..0] : input;
inclock : input;
outclock : input;
q[8..0] : output;
rdaddress[2..0] : input;
wraddress[2..0] : input;
wren : input;
)
VARIABLE
lutrama0 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 0,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 9,
mixed_port_feed_through_mode = "dont care"
);
lutrama1 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 1,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 9,
mixed_port_feed_through_mode = "dont care"
);
lutrama2 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 2,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 9,
mixed_port_feed_through_mode = "dont care"
);
lutrama3 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 3,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 9,
mixed_port_feed_through_mode = "dont care"
);
lutrama4 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 4,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 9,
mixed_port_feed_through_mode = "dont care"
);
lutrama5 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 5,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 9,
mixed_port_feed_through_mode = "dont care"
);
lutrama6 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 6,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 9,
mixed_port_feed_through_mode = "dont care"
);
lutrama7 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 7,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 9,
mixed_port_feed_through_mode = "dont care"
);
lutrama8 : tennm_mlab_cell
WITH (
address_width = 3,
data_width = 1,
first_address = 0,
first_bit_number = 8,
last_address = 7,
logical_ram_depth = 8,
logical_ram_name = "ALTDPRAM_INSTANCE",
logical_ram_width = 9,
mixed_port_feed_through_mode = "dont care"
);
rdaddr_reg[2..0] : dffe;
datain_wire[8..0] : WIRE;
dataout_latch[8..0] : WIRE;
dataout_wire[8..0] : WIRE;
rdaddr_wire[2..0] : WIRE;
wr_en : WIRE;
wraddr_wire[2..0] : WIRE;
BEGIN
lutrama[8..0].clk0 = inclock;
lutrama[8..0].ena0 = wr_en;
lutrama[8..0].portaaddr[2..0] = wraddr_wire[2..0];
lutrama[0].portadatain[0..0] = datain_wire[0..0];
lutrama[1].portadatain[0..0] = datain_wire[1..1];
lutrama[2].portadatain[0..0] = datain_wire[2..2];
lutrama[3].portadatain[0..0] = datain_wire[3..3];
lutrama[4].portadatain[0..0] = datain_wire[4..4];
lutrama[5].portadatain[0..0] = datain_wire[5..5];
lutrama[6].portadatain[0..0] = datain_wire[6..6];
lutrama[7].portadatain[0..0] = datain_wire[7..7];
lutrama[8].portadatain[0..0] = datain_wire[8..8];
lutrama[8..0].portbaddr[2..0] = rdaddr_wire[2..0];
rdaddr_reg[].clk = outclock;
rdaddr_reg[].d = rdaddress[];
datain_wire[] = data[];
dataout_latch[] = dataout_wire[];
dataout_wire[] = lutrama[8..0].portbdataout[];
q[] = dataout_latch[];
rdaddr_wire[] = rdaddr_reg[].q;
wr_en = wren;
wraddr_wire[] = wraddress[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/lpm_abs_952f1.tdf
-49
View File
@@ -1,49 +0,0 @@
--lpm_abs CARRY_CHAIN="MANUAL" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LPM_WIDTH=33 data result
--VERSION_BEGIN 26.1 cbx_lpm_abs 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
--synthesis_resources = lut 33
SUBDESIGN lpm_abs_952f1
(
data[32..0] : input;
overflow : output;
result[32..0] : output;
)
VARIABLE
adder_result_int[33..0] : WIRE;
adder_cin : WIRE;
adder_dataa[32..0] : WIRE;
adder_datab[32..0] : WIRE;
adder_result[32..0] : WIRE;
gnd_wire : WIRE;
result_tmp[32..0] : WIRE;
BEGIN
adder_result_int[] = (adder_dataa[], adder_cin) + (adder_datab[], adder_cin);
adder_result[] = adder_result_int[33..1];
adder_cin = data[32..32];
adder_dataa[] = (data[] $ data[32..32]);
adder_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
gnd_wire = B"0";
overflow = (result_tmp[32..32] & data[32..32]);
result[] = result_tmp[];
result_tmp[] = adder_result[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/lpm_abs_unir.tdf
-49
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@@ -1,49 +0,0 @@
--lpm_abs CARRY_CHAIN="MANUAL" CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LPM_WIDTH=32 data result
--VERSION_BEGIN 26.1 cbx_lpm_abs 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
--synthesis_resources = lut 32
SUBDESIGN lpm_abs_unir
(
data[31..0] : input;
overflow : output;
result[31..0] : output;
)
VARIABLE
adder_result_int[32..0] : WIRE;
adder_cin : WIRE;
adder_dataa[31..0] : WIRE;
adder_datab[31..0] : WIRE;
adder_result[31..0] : WIRE;
gnd_wire : WIRE;
result_tmp[31..0] : WIRE;
BEGIN
adder_result_int[] = (adder_dataa[], adder_cin) + (adder_datab[], adder_cin);
adder_result[] = adder_result_int[32..1];
adder_cin = data[31..31];
adder_dataa[] = (data[] $ data[31..31]);
adder_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
gnd_wire = B"0";
overflow = (result_tmp[31..31] & data[31..31]);
result[] = result_tmp[];
result_tmp[] = adder_result[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/lpm_divide_clj31.tdf
-43
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@@ -1,43 +0,0 @@
--lpm_divide CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=32 LPM_WIDTHN=33 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL"
--VERSION_BEGIN 26.1 cbx_lpm_abs 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_divide 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION abs_divider_nsr72 (denominator[31..0], numerator[32..0])
RETURNS ( quotient[32..0], remainder[31..0]);
--synthesis_resources = lut 724
SUBDESIGN lpm_divide_clj31
(
denom[31..0] : input;
numer[32..0] : input;
quotient[32..0] : output;
remain[31..0] : output;
)
VARIABLE
divider : abs_divider_nsr72;
numer_tmp[32..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/lpm_divide_erdi1.tdf
-43
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@@ -1,43 +0,0 @@
--lpm_divide CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=2 LPM_WIDTHN=4 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL"
--VERSION_BEGIN 26.1 cbx_lpm_abs 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_divide 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION sign_div_unsign_1bss1 (denominator[1..0], numerator[3..0])
RETURNS ( quotient[3..0], remainder[1..0]);
--synthesis_resources = lut 13
SUBDESIGN lpm_divide_erdi1
(
denom[1..0] : input;
numer[3..0] : input;
quotient[3..0] : output;
remain[1..0] : output;
)
VARIABLE
divider : sign_div_unsign_1bss1;
numer_tmp[3..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/mux_33p31.tdf
-2024
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/mux_lrsc1.tdf
-1000
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synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/scfifo_lale.tdf
-112
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--scfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" ALMOST_EMPTY_VALUE=2 ALMOST_FULL_VALUE=26 CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" ENABLE_ECC="FALSE" LPM_NUMWORDS=32 LPM_SHOWAHEAD="ON" LPM_WIDTH=9 LPM_WIDTHU=5 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr(gnd) almost_empty almost_full clock data empty full q rdreq sclr usedw wrreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Agilex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0
--VERSION_BEGIN 26.1 cbx_altdpram 2026:03:19:21:42:37:SC cbx_altera_counter 2026:03:19:21:42:37:SC cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_fifo_common 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_counter 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_scfifo 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION a_dpfifo_pa9f (clock, data[8..0], rreq, sclr, wreq)
RETURNS ( empty, full, q[8..0], usedw[4..0]);
--synthesis_resources = altera_counter 3 ram_bits (AUTO) 288 reg 15
SUBDESIGN scfifo_lale
(
aclr : input;
almost_empty : output;
almost_full : output;
clock : input;
data[8..0] : input;
empty : output;
full : output;
q[8..0] : output;
rdreq : input;
sclr : input;
usedw[4..0] : output;
wrreq : input;
)
VARIABLE
dpfifo : a_dpfifo_pa9f;
dffe_af : dffe;
dffe_nae : dffe;
const_node_aclr : NODE;
comparison_ae0 : WIRE;
comparison_ae1 : WIRE;
comparison_ae2 : WIRE;
comparison_ae3 : WIRE;
comparison_ae4 : WIRE;
comparison_af0 : WIRE;
comparison_af1 : WIRE;
comparison_af2 : WIRE;
comparison_af3 : WIRE;
comparison_af4 : WIRE;
comparison_pre_ae0 : WIRE;
comparison_pre_ae1 : WIRE;
comparison_pre_ae2 : WIRE;
comparison_pre_ae3 : WIRE;
comparison_pre_ae4 : WIRE;
comparison_pre_af0 : WIRE;
comparison_pre_af1 : WIRE;
comparison_pre_af2 : WIRE;
comparison_pre_af3 : WIRE;
comparison_pre_af4 : WIRE;
wire_ae[4..0] : WIRE;
wire_af[4..0] : WIRE;
wire_pre_ae[4..0] : WIRE;
wire_pre_af[4..0] : WIRE;
BEGIN
dpfifo.clock = clock;
dpfifo.data[] = data[];
dpfifo.rreq = rdreq;
dpfifo.sclr = sclr;
dpfifo.wreq = wrreq;
dffe_af.clk = clock;
dffe_af.d = ((dffe_af.q & (dffe_af.q $ (sclr # ((comparison_af4 & (! wrreq)) & rdreq)))) # ((! dffe_af.q) & ((((! sclr) & comparison_pre_af4) & wrreq) & (! rdreq))));
dffe_nae.clk = clock;
dffe_nae.d = ((dffe_nae.q & (dffe_nae.q $ (sclr # ((comparison_ae4 & (! wrreq)) & (rdreq & (! dpfifo.empty)))))) # ((! dffe_nae.q) & ((((! sclr) & comparison_pre_ae4) & wrreq) & (! (rdreq & (! dpfifo.empty))))));
const_node_aclr = aclr;
almost_empty = (! dffe_nae.q);
almost_full = dffe_af.q;
comparison_ae0 = (dpfifo.usedw[0..0] $ wire_ae[0..0]);
comparison_ae1 = ((dpfifo.usedw[1..1] $ wire_ae[1..1]) & comparison_ae0);
comparison_ae2 = ((dpfifo.usedw[2..2] $ wire_ae[2..2]) & comparison_ae1);
comparison_ae3 = ((dpfifo.usedw[3..3] $ wire_ae[3..3]) & comparison_ae2);
comparison_ae4 = ((dpfifo.usedw[4..4] $ wire_ae[4..4]) & comparison_ae3);
comparison_af0 = (dpfifo.usedw[0..0] $ wire_af[0..0]);
comparison_af1 = ((dpfifo.usedw[1..1] $ wire_af[1..1]) & comparison_af0);
comparison_af2 = ((dpfifo.usedw[2..2] $ wire_af[2..2]) & comparison_af1);
comparison_af3 = ((dpfifo.usedw[3..3] $ wire_af[3..3]) & comparison_af2);
comparison_af4 = ((dpfifo.usedw[4..4] $ wire_af[4..4]) & comparison_af3);
comparison_pre_ae0 = (dpfifo.usedw[0..0] $ wire_pre_ae[0..0]);
comparison_pre_ae1 = ((dpfifo.usedw[1..1] $ wire_pre_ae[1..1]) & comparison_pre_ae0);
comparison_pre_ae2 = ((dpfifo.usedw[2..2] $ wire_pre_ae[2..2]) & comparison_pre_ae1);
comparison_pre_ae3 = ((dpfifo.usedw[3..3] $ wire_pre_ae[3..3]) & comparison_pre_ae2);
comparison_pre_ae4 = ((dpfifo.usedw[4..4] $ wire_pre_ae[4..4]) & comparison_pre_ae3);
comparison_pre_af0 = (dpfifo.usedw[0..0] $ wire_pre_af[0..0]);
comparison_pre_af1 = ((dpfifo.usedw[1..1] $ wire_pre_af[1..1]) & comparison_pre_af0);
comparison_pre_af2 = ((dpfifo.usedw[2..2] $ wire_pre_af[2..2]) & comparison_pre_af1);
comparison_pre_af3 = ((dpfifo.usedw[3..3] $ wire_pre_af[3..3]) & comparison_pre_af2);
comparison_pre_af4 = ((dpfifo.usedw[4..4] $ wire_pre_af[4..4]) & comparison_pre_af3);
empty = dpfifo.empty;
full = dpfifo.full;
q[] = dpfifo.q[];
usedw[] = dpfifo.usedw[];
wire_ae[] = ( B"1", B"1", B"1", B"0", B"1");
wire_af[] = ( B"0", B"0", B"1", B"0", B"1");
wire_pre_ae[] = ( B"1", B"1", B"1", B"1", B"0");
wire_pre_af[] = ( B"0", B"0", B"1", B"1", B"0");
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/scfifo_n8hs.tdf
-112
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@@ -1,112 +0,0 @@
--scfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" ALMOST_EMPTY_VALUE=2 ALMOST_FULL_VALUE=26 CBX_SINGLE_OUTPUT_FILE="OFF" DEVICE_FAMILY="Agilex 5" ENABLE_ECC="FALSE" LPM_NUMWORDS=32 LPM_SHOWAHEAD="ON" LPM_WIDTH=266 LPM_WIDTHU=5 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr(gnd) almost_empty almost_full clock data empty full q rdreq sclr usedw wrreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Agilex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0
--VERSION_BEGIN 26.1 cbx_altdpram 2026:03:19:21:42:37:SC cbx_altera_counter 2026:03:19:21:42:37:SC cbx_altera_syncram 2026:03:19:21:42:37:SC cbx_altera_syncram_ltm 2026:03:19:21:42:37:SC cbx_altera_syncram_nd_impl 2026:03:19:21:42:37:SC cbx_altsyncram 2026:03:19:21:42:37:SC cbx_fifo_common 2026:03:19:21:42:37:SC cbx_libertymesa 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_compare 2026:03:19:21:42:37:SC cbx_lpm_counter 2026:03:19:21:42:37:SC cbx_lpm_decode 2026:03:19:21:42:37:SC cbx_lpm_mux 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_scfifo 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_stratixiii 2026:03:19:21:42:37:SC cbx_stratixv 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION a_dpfifo_rntb1 (clock, data[265..0], rreq, sclr, wreq)
RETURNS ( empty, full, q[265..0], usedw[4..0]);
--synthesis_resources = altera_counter 3 ram_bits (AUTO) 8512 reg 15
SUBDESIGN scfifo_n8hs
(
aclr : input;
almost_empty : output;
almost_full : output;
clock : input;
data[265..0] : input;
empty : output;
full : output;
q[265..0] : output;
rdreq : input;
sclr : input;
usedw[4..0] : output;
wrreq : input;
)
VARIABLE
dpfifo : a_dpfifo_rntb1;
dffe_af : dffe;
dffe_nae : dffe;
const_node_aclr : NODE;
comparison_ae0 : WIRE;
comparison_ae1 : WIRE;
comparison_ae2 : WIRE;
comparison_ae3 : WIRE;
comparison_ae4 : WIRE;
comparison_af0 : WIRE;
comparison_af1 : WIRE;
comparison_af2 : WIRE;
comparison_af3 : WIRE;
comparison_af4 : WIRE;
comparison_pre_ae0 : WIRE;
comparison_pre_ae1 : WIRE;
comparison_pre_ae2 : WIRE;
comparison_pre_ae3 : WIRE;
comparison_pre_ae4 : WIRE;
comparison_pre_af0 : WIRE;
comparison_pre_af1 : WIRE;
comparison_pre_af2 : WIRE;
comparison_pre_af3 : WIRE;
comparison_pre_af4 : WIRE;
wire_ae[4..0] : WIRE;
wire_af[4..0] : WIRE;
wire_pre_ae[4..0] : WIRE;
wire_pre_af[4..0] : WIRE;
BEGIN
dpfifo.clock = clock;
dpfifo.data[] = data[];
dpfifo.rreq = rdreq;
dpfifo.sclr = sclr;
dpfifo.wreq = wrreq;
dffe_af.clk = clock;
dffe_af.d = ((dffe_af.q & (dffe_af.q $ (sclr # ((comparison_af4 & (! wrreq)) & rdreq)))) # ((! dffe_af.q) & ((((! sclr) & comparison_pre_af4) & wrreq) & (! rdreq))));
dffe_nae.clk = clock;
dffe_nae.d = ((dffe_nae.q & (dffe_nae.q $ (sclr # ((comparison_ae4 & (! wrreq)) & (rdreq & (! dpfifo.empty)))))) # ((! dffe_nae.q) & ((((! sclr) & comparison_pre_ae4) & wrreq) & (! (rdreq & (! dpfifo.empty))))));
const_node_aclr = aclr;
almost_empty = (! dffe_nae.q);
almost_full = dffe_af.q;
comparison_ae0 = (dpfifo.usedw[0..0] $ wire_ae[0..0]);
comparison_ae1 = ((dpfifo.usedw[1..1] $ wire_ae[1..1]) & comparison_ae0);
comparison_ae2 = ((dpfifo.usedw[2..2] $ wire_ae[2..2]) & comparison_ae1);
comparison_ae3 = ((dpfifo.usedw[3..3] $ wire_ae[3..3]) & comparison_ae2);
comparison_ae4 = ((dpfifo.usedw[4..4] $ wire_ae[4..4]) & comparison_ae3);
comparison_af0 = (dpfifo.usedw[0..0] $ wire_af[0..0]);
comparison_af1 = ((dpfifo.usedw[1..1] $ wire_af[1..1]) & comparison_af0);
comparison_af2 = ((dpfifo.usedw[2..2] $ wire_af[2..2]) & comparison_af1);
comparison_af3 = ((dpfifo.usedw[3..3] $ wire_af[3..3]) & comparison_af2);
comparison_af4 = ((dpfifo.usedw[4..4] $ wire_af[4..4]) & comparison_af3);
comparison_pre_ae0 = (dpfifo.usedw[0..0] $ wire_pre_ae[0..0]);
comparison_pre_ae1 = ((dpfifo.usedw[1..1] $ wire_pre_ae[1..1]) & comparison_pre_ae0);
comparison_pre_ae2 = ((dpfifo.usedw[2..2] $ wire_pre_ae[2..2]) & comparison_pre_ae1);
comparison_pre_ae3 = ((dpfifo.usedw[3..3] $ wire_pre_ae[3..3]) & comparison_pre_ae2);
comparison_pre_ae4 = ((dpfifo.usedw[4..4] $ wire_pre_ae[4..4]) & comparison_pre_ae3);
comparison_pre_af0 = (dpfifo.usedw[0..0] $ wire_pre_af[0..0]);
comparison_pre_af1 = ((dpfifo.usedw[1..1] $ wire_pre_af[1..1]) & comparison_pre_af0);
comparison_pre_af2 = ((dpfifo.usedw[2..2] $ wire_pre_af[2..2]) & comparison_pre_af1);
comparison_pre_af3 = ((dpfifo.usedw[3..3] $ wire_pre_af[3..3]) & comparison_pre_af2);
comparison_pre_af4 = ((dpfifo.usedw[4..4] $ wire_pre_af[4..4]) & comparison_pre_af3);
empty = dpfifo.empty;
full = dpfifo.full;
q[] = dpfifo.q[];
usedw[] = dpfifo.usedw[];
wire_ae[] = ( B"1", B"1", B"1", B"0", B"1");
wire_af[] = ( B"0", B"0", B"1", B"0", B"1");
wire_pre_ae[] = ( B"1", B"1", B"1", B"1", B"0");
wire_pre_af[] = ( B"0", B"0", B"1", B"1", B"0");
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/tmp-clearbox/de25_nano_psmct32_raster_demo_top/2231719/sign_div_unsign_1bss1.tdf
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--sign_div_unsign CBX_SINGLE_OUTPUT_FILE="OFF" DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=2 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=4 SKIP_BITS=0 denominator numerator quotient remainder
--VERSION_BEGIN 26.1 cbx_lpm_abs 2026:03:19:21:42:37:SC cbx_lpm_add_sub 2026:03:19:21:42:37:SC cbx_lpm_divide 2026:03:19:21:42:37:SC cbx_mgl 2026:03:19:21:42:40:SC cbx_nadder 2026:03:19:21:42:37:SC cbx_stratix 2026:03:19:21:42:37:SC cbx_stratixii 2026:03:19:21:42:37:SC cbx_util_mgl 2026:03:19:21:42:37:SC VERSION_END
-- Copyright (C) 2026 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION alt_u_div_8oak (denominator[1..0], numerator[3..0])
RETURNS ( quotient[3..0], remainder[1..0]);
--synthesis_resources = lut 13
SUBDESIGN sign_div_unsign_1bss1
(
denominator[1..0] : input;
numerator[3..0] : input;
quotient[3..0] : output;
remainder[1..0] : output;
)
VARIABLE
divider : alt_u_div_8oak;
norm_num[3..0] : WIRE;
protect_quotient[3..0] : WIRE;
protect_remainder[1..0] : WIRE;
BEGIN
divider.denominator[] = denominator[];
divider.numerator[] = norm_num[];
norm_num[] = numerator[];
protect_quotient[] = divider.quotient[];
protect_remainder[] = divider.remainder[];
quotient[] = protect_quotient[];
remainder[] = protect_remainder[];
END;
--VALID FILE
synth/de25_nano/top_psmct32_raster_demo/work/de25_nano_psmct32_raster_demo_top.qpf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2025 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Altera and sold by Altera or its authorized distributors. Please
# refer to the Altera Software License Subscription Agreements
# on the Quartus Prime software download page.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 25.3.1 Build 100 12/19/2025 Patches 1.02 SC Pro Edition
# Date created = 19:21:51 July 15, 2026
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "25.3"
DATE = "19:21:51 July 15, 2026"
# Revisions
PROJECT_REVISION = "de25_nano_psmct32_raster_demo_top"
synth/de25_nano/top_psmct32_raster_demo/work/de25_nano_psmct32_raster_demo_top.qsf
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/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/de25_nano_psmct32_raster_demo_top.qsf
synth/de25_nano/top_psmct32_raster_demo/work/de25_nano_psmct32_raster_demo_top.sdc
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/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/de25_nano_psmct32_raster_demo_top.sdc
synth/de25_nano/top_psmct32_raster_demo/work/ip
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/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/ip
synth/de25_nano/top_psmct32_raster_demo/work/rtl
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/home/ubuntu/FPGA_Projects/retroDE_ps2/rtl
synth/de25_nano/top_psmct32_raster_demo/work/sim
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/home/ubuntu/FPGA_Projects/retroDE_ps2/sim