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Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

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Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder
XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog
TBs, fidelity attribution tooling. Functional baseline before removing the dead
bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
thejayman77
2026-07-20 19:56:46 -04:00
parent ec82764bef
commit ba74bbd5aa
476 changed files with 696247 additions and 130119 deletions
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rtl/gif_gs/gs_lpddr_rd_probe.sv
+19 -10
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@@ -58,7 +58,11 @@ module gs_lpddr_rd_probe #(
reg [2:0] rd_lane; // which 32-bit lane of the 256-bit beat (addr[4:2])
typedef enum logic [1:0] { S_IDLE, S_AR, S_R } st_t;
// Capture the complete EMIF beat before lane selection. Selecting one of
// eight 32-bit lanes directly from the EMIF response into rd_data placed a
// two-level mux plus long EMIF routing in one 310 MHz cycle.
logic [255:0] rdata_q;
typedef enum logic [1:0] { S_IDLE, S_AR, S_R, S_SEL } st_t;
st_t st;
always_ff @(posedge axi_clk) begin
@@ -72,6 +76,7 @@ module gs_lpddr_rd_probe #(
rd_data <= 32'd0;
rd_busy <= 1'b0;
rd_lane <= 3'd0;
rdata_q <= 256'd0;
end else begin
pulse_sync <= {pulse_sync[1:0], rd_pulse};
@@ -95,20 +100,24 @@ module gs_lpddr_rd_probe #(
S_R: begin
if (rvalid) begin
rready <= 1'b0;
rdata_q <= rdata;
st <= S_SEL;
end
end
S_SEL: begin
case (rd_lane)
3'd0: rd_data <= rdata[31:0];
3'd1: rd_data <= rdata[63:32];
3'd2: rd_data <= rdata[95:64];
3'd3: rd_data <= rdata[127:96];
3'd4: rd_data <= rdata[159:128];
3'd5: rd_data <= rdata[191:160];
3'd6: rd_data <= rdata[223:192];
default: rd_data <= rdata[255:224];
3'd0: rd_data <= rdata_q[31:0];
3'd1: rd_data <= rdata_q[63:32];
3'd2: rd_data <= rdata_q[95:64];
3'd3: rd_data <= rdata_q[127:96];
3'd4: rd_data <= rdata_q[159:128];
3'd5: rd_data <= rdata_q[191:160];
3'd6: rd_data <= rdata_q[223:192];
default: rd_data <= rdata_q[255:224];
endcase
rd_busy <= 1'b0;
rd_done <= ~rd_done;
st <= S_IDLE;
end
end
default: st <= S_IDLE;
endcase