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Ch441 TB review fixes: complete stall check + full&&d_wready coverage [READY FOR REVIEW]

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Per Codex review of dd7ca4f (testbench only, RTL unchanged):
1. Stall check now requires d_wvalid to REMAIN asserted (catches a deassert) and
   compares the COMPLETE {d_wdata,d_wstrb,d_wlast} against the held beat, not just
   d_wdata.
2. Added saw_full_and_ready coverage flag (set on dut.full && d_wready) and a final
   check that FAILS if the distinguishing no-bypass case was never observed.

No RTL change, no simulations, no Quartus.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
thejayman77
2026-07-21 14:25:17 -04:00
parent dd7ca4fb8e
commit 96d23ea8ee
1 changed files with 17 additions and 5 deletions
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sim/tb/gif_gs/tb_gs_axi_w_regbuf.sv
+17 -5
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@@ -82,17 +82,28 @@ module tb_gs_axi_w_regbuf;
errors++;
end
end
// Coverage: prove the distinguishing full && d_wready case was actually hit;
// otherwise the no-bypass check above never exercised its meaningful case.
logic saw_full_and_ready; initial saw_full_and_ready = 1'b0;
always_ff @(posedge clk) if (rst_n && dut.full && d_wready) saw_full_and_ready <= 1'b1;
// (3) stable downstream payload while stalled (d_wvalid && !d_wready)
logic [WD-1:0] hold_d; logic hold_v;
// (3) while stalled (prev cycle d_wvalid && !d_wready), the SAME beat must still
// be presented: d_wvalid asserted AND {d_wdata,d_wstrb,d_wlast} unchanged.
logic [WD-1:0] hold_d; logic [WS-1:0] hold_s; logic hold_l; logic hold_v;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin hold_v <= 1'b0; hold_d <= '0; end
if (!rst_n) begin hold_v <= 1'b0; hold_d <= '0; hold_s <= '0; hold_l <= 1'b0; end
else begin
if (hold_v && d_wvalid && (d_wdata !== hold_d)) begin
if (errors < 20) $error("[wbuf] downstream payload changed while stalled"); errors++;
if (hold_v) begin
if (!d_wvalid) begin
if (errors < 20) $error("[wbuf] d_wvalid deasserted while stalled"); errors++;
end else if (d_wdata !== hold_d || d_wstrb !== hold_s || d_wlast !== hold_l) begin
if (errors < 20) $error("[wbuf] downstream {wdata,wstrb,wlast} changed while stalled"); errors++;
end
end
hold_v <= d_wvalid && !d_wready;
hold_d <= d_wdata;
hold_s <= d_wstrb;
hold_l <= d_wlast;
end
end
@@ -120,6 +131,7 @@ module tb_gs_axi_w_regbuf;
if (d_wvalid !== 1'b0) begin $error("[wbuf] not empty after drain (d_wvalid=%b)", d_wvalid); errors++; end
if (wr_seq !== rd_seq) begin $error("[wbuf] count mismatch: in %0d out %0d", wr_seq, rd_seq); errors++; end
if (wr_seq < 32'd2000) begin $error("[wbuf] too few transfers (%0d) — not meaningful", wr_seq); errors++; end
if (!saw_full_and_ready) begin $error("[wbuf] coverage: full && d_wready never observed — no-bypass case unexercised"); errors++; end
$display("[tb_gs_axi_w_regbuf] in=%0d out=%0d errors=%0d", wr_seq, rd_seq, errors);
if (errors == 0) $display("[tb_gs_axi_w_regbuf] PASS");