Ch443b: revert texture 4-bank split; 2-cycle drain (F_SETTLE + multicycle)

The four-bank tex_mem split (27dfd0b) closed the -0.370 EMIF drain
write-address fanout but the owner GUI fit showed the fitter SCATTERED
the banks, pushing the DESIGN-clock sampler read cone
(ras_v0_x -> perspective-UV -> texel addr -> tex_mem portbaddr, the
design's fundamental ~40ns critical path) to -2.208 ns. Net worse.

Codex's call (Option 1 + honest write-side multicycle), implemented:
- Restore the MONOLITHIC 65536x32 tex_mem, recovering the clean 25 MHz
  read-cone placement. Sampler/read-address path stays fully timed
  (Ch439g); nothing about it is relaxed.
- Make the EMIF drain write genuinely two-cycle: new F_SETTLE state
  between F_DRAIN and F_WRITE. drain_idx_q/drain_word_q are loaded in
  F_DRAIN, HELD unchanged through F_SETTLE (the load block gates on
  F_DRAIN), and the RAM write + CRC happen at the later F_WRITE edge.
- SDC: fail-closed 2-cycle-setup / 1-cycle-hold multicycle from ONLY
  u_texcache|drain_idx_q[*] to tex_mem (a 6.45 ns EMIF window for the
  drain write-address). Scoped -from the drain regs, so the sampler
  read path (different launch regs) is untouched. HALTs if tex_mem is
  present but drain_idx_q renamed.

The AW buffer (gs_axi_aw_regbuf) and the tile-CDC max-skew 2.5 relax
from 27dfd0b are KEPT unchanged (both closed their families in the fit).

Verified: tb_gs_texture_cache (monolithic + F_SETTLE, distinct-per-byte-
lane + full-word, 0 errors), aw/w regbuf, texture_psmt8_clut,
scanout_diag, ps2_hps_bridge, and the complete f52 replay BYTE-IDENTICAL
(Z 0/307200, COLOR 0/245760). No Quartus/board/push from here.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

synth/de25_nano/top_psmct32_raster_demo/de25_nano_psmct32_raster_demo_top.sdc

@@ -491,6 +491,28 @@ if { $tdn == 0 } { error "Ch439g SDC FATAL: tex_mem destination collection empty
 set_false_path -from $ch439_bili_taps -to $tex_mem_dst
 post_message -type info "Ch439g SDC: impossible bilinear-tap -> tex_mem packed-DSP arc cut ($ch439_bili_taps_n src -> $tdn dst); all non-tap texture-address launches remain timed"
 
+# Ch443 (Codex) — texture-cache EMIF DRAIN write-address multicycle. The fill FSM now holds
+# drain_idx_q/drain_word_q stable across F_DRAIN -> F_SETTLE -> F_WRITE and asserts the RAM
+# write-enable ONLY at the later F_WRITE edge, so the drain address is functionally required
+# 2 EMIF cycles after launch. Give ONLY drain_idx_q -> tex_mem a 2-cycle setup / 1-cycle hold
+# multicycle (a 6.45 ns window for the -0.370 ns drain write-address fanout that closing the
+# four-bank split had opened). SCOPED -from the drain registers, so it does NOT touch the
+# sampler/read-address path (ras_v0_x / walker / UV / perspective -> tex_mem portbaddr) — that
+# launches from DIFFERENT registers and stays fully timed (Ch439g above). Reuses the tex_mem
+# destination collection $tex_mem_dst / $tdn defined for the Ch357/Ch439g exceptions.
+# Fail-closed: if tex_mem exists but drain_idx_q[*] is gone (renamed), HALT — never silently
+# omit the exception (which would let the drain path refail setup unconstrained).
+set tex_drain_src   [get_keepers -nowarn {*u_texcache|drain_idx_q[*]}]
+set tex_drain_src_n [get_collection_size $tex_drain_src]
+if { $tdn == 0 } {
+    post_message -type info "Ch443 SDC: texture drain multicycle inactive (no tex_mem in this profile)"
+} else {
+    if { $tex_drain_src_n == 0 } { error "Ch443 SDC FATAL: tex_mem present but u_texcache|drain_idx_q[*] matched 0 keepers (renamed? drain multicycle orphaned -> write-address would silently refail setup)" }
+    set_multicycle_path -setup -end 2 -from $tex_drain_src -to $tex_mem_dst
+    set_multicycle_path -hold  -end 1 -from $tex_drain_src -to $tex_mem_dst
+    post_message -type info "Ch443 SDC: texture drain_idx_q -> tex_mem 2-cycle setup / 1-cycle hold multicycle ($tex_drain_src_n src -> $tdn dst)"
+}
+
 # Ch358 (Codex) — the SAME quasi-static EMIF calibration-ready signal also reaches the scanout LINE-BUFFER RAMs
 # (26.1 fit at 640x480: lock_sync_inst|dreg[1] -> u_lpddr_scan_lb|lb0/lb1, 10 endpoints at -0.010ns). These are
 # startup/reset-derived line-buffer control paths, NOT runtime scanout data (the line buffers are inactive until