Ch443b: revert texture 4-bank split; 2-cycle drain (F_SETTLE + multicycle)

The four-bank tex_mem split (27dfd0b) closed the -0.370 EMIF drain
write-address fanout but the owner GUI fit showed the fitter SCATTERED
the banks, pushing the DESIGN-clock sampler read cone
(ras_v0_x -> perspective-UV -> texel addr -> tex_mem portbaddr, the
design's fundamental ~40ns critical path) to -2.208 ns. Net worse.

Codex's call (Option 1 + honest write-side multicycle), implemented:
- Restore the MONOLITHIC 65536x32 tex_mem, recovering the clean 25 MHz
  read-cone placement. Sampler/read-address path stays fully timed
  (Ch439g); nothing about it is relaxed.
- Make the EMIF drain write genuinely two-cycle: new F_SETTLE state
  between F_DRAIN and F_WRITE. drain_idx_q/drain_word_q are loaded in
  F_DRAIN, HELD unchanged through F_SETTLE (the load block gates on
  F_DRAIN), and the RAM write + CRC happen at the later F_WRITE edge.
- SDC: fail-closed 2-cycle-setup / 1-cycle-hold multicycle from ONLY
  u_texcache|drain_idx_q[*] to tex_mem (a 6.45 ns EMIF window for the
  drain write-address). Scoped -from the drain regs, so the sampler
  read path (different launch regs) is untouched. HALTs if tex_mem is
  present but drain_idx_q renamed.

The AW buffer (gs_axi_aw_regbuf) and the tile-CDC max-skew 2.5 relax
from 27dfd0b are KEPT unchanged (both closed their families in the fit).

Verified: tb_gs_texture_cache (monolithic + F_SETTLE, distinct-per-byte-
lane + full-word, 0 errors), aw/w regbuf, texture_psmt8_clut,
scanout_diag, ps2_hps_bridge, and the complete f52 replay BYTE-IDENTICAL
(Z 0/307200, COLOR 0/245760). No Quartus/board/push from here.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

sim/tb/gif_gs/tb_gs_texture_cache.sv

@@ -131,16 +131,17 @@ module tb_gs_texture_cache;
         check(tex_ready, "tex_ready never synced");
 
         // ---- verify every word via the sampler 1-cycle read port ----
-        // Full reconstructed word AND per-bank byte pinpoint (Ch443 four-bank split).
+        // Full reconstructed word AND per-byte-lane pinpoint. The distinct-per-byte golden
+        // exercises all four byte lanes of the monolithic 32-bit word (Ch443).
         for (int i=0; i<TEX_WORDS; i++) begin
             logic [31:0] exp;
             read_word(i, got);
             exp = tex_word(i);   // temp: iverilog forbids part-select on a function-call result
             check(got == exp,          $sformatf("word[%0d]=%08x exp %08x", i, got, exp));
-            check(got[7:0]   === exp[7:0],   $sformatf("bank0 byte[%0d]=%02x exp %02x", i, got[7:0],   exp[7:0]));
-            check(got[15:8]  === exp[15:8],  $sformatf("bank1 byte[%0d]=%02x exp %02x", i, got[15:8],  exp[15:8]));
-            check(got[23:16] === exp[23:16], $sformatf("bank2 byte[%0d]=%02x exp %02x", i, got[23:16], exp[23:16]));
-            check(got[31:24] === exp[31:24], $sformatf("bank3 byte[%0d]=%02x exp %02x", i, got[31:24], exp[31:24]));
+            check(got[7:0]   === exp[7:0],   $sformatf("lane0 byte[%0d]=%02x exp %02x", i, got[7:0],   exp[7:0]));
+            check(got[15:8]  === exp[15:8],  $sformatf("lane1 byte[%0d]=%02x exp %02x", i, got[15:8],  exp[15:8]));
+            check(got[23:16] === exp[23:16], $sformatf("lane2 byte[%0d]=%02x exp %02x", i, got[23:16], exp[23:16]));
+            check(got[31:24] === exp[31:24], $sformatf("lane3 byte[%0d]=%02x exp %02x", i, got[31:24], exp[31:24]));
         end
 
         $display("[texcache] clean: fill_done=%0d beats=%0d bytes=%0d rd_errs=%0d words_checked=%0d errors=%0d",