Ch443: combined timing repair for both Ch442 setup families

Ch442's fit exposed two failing setup families (plus a stale max-skew).
Attack both structurally; no reseeding.

Family 1 - AWREADY -> Z-FSM (-0.410): gen_p2c_ff[23] (EMIF AWREADY)
reached u_zc_emit|u_z's S_SFLUSH_AW/S_FILL_R next-state combinationally.
Ch441 registered only the W channel; add the AW twin:
- new gs_axi_aw_regbuf (one-entry fully-registered AW buffer), inserted
  in zc_emit between u_z's AW output and the arbiter s2 AW port. The FSM
  now sees registered occupancy, never EMIF's combinational AWREADY.

Family 2 - texcache drain_idx_q -> tex_mem (-0.370, x7): a single index
fanned across the whole 65536x32, 128-M20K macro. Split by WIDTH into
four 65536x8 banks, each with its own (* preserve, dont_merge *) write-
address launch register; write the four byte lanes together in F_WRITE;
reconstruct the sample word by concatenating four registered read bytes.
Selector structure and 1-cycle read latency unchanged; total M20Ks
unchanged (4x32 == 128); fill_crc still sums the full 32-bit word.

Max-skew: relax ONLY the Ch357 tile-write CDC set_max_skew 2.0 -> 2.5
(quasi-static bundle, >=2 dclk stability window); retain set_net_delay
2.0 (the real arrival bound). SDC comment updated.

Tests: new tb_gs_axi_aw_regbuf (AW scoreboard: exactly-once/order/no-
combinational-AWREADY-bypass/stable-while-stalled); tb_gs_texture_cache
strengthened to distinct-per-byte-bank data + per-bank + full-word
checks. All pass: aw/w regbuf, texture_cache, texture_psmt8_clut,
scanout_diag, ps2_hps_bridge, and the complete f52 replay BYTE-IDENTICAL
(Z 0/307200, COLOR 0/245760).

No Quartus, board, or push from here. Ready for one owner GUI fit.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

rtl/gif_gs/gs_lpddr_zc_emit.sv

@@ -155,6 +155,10 @@ module gs_lpddr_zc_emit #(
     // ports (write arbiter s2). This cuts the combinational EMIF WREADY -> z_rmw
     // FSM path. AW and B pass straight through (z_awaddr.../z_bvalid... unchanged).
     logic [255:0] zi_wdata; logic [31:0] zi_wstrb; logic zi_wlast, zi_wvalid, zi_wready;
+    // Ch443: the Z RMW master's AW output ALSO goes through a one-entry registered
+    // buffer (gs_axi_aw_regbuf u_z_awbuf, below) so the FSM sees a REGISTERED awready
+    // (buffer occupancy), never EMIF's combinational AWREADY (gen_p2c_ff[23]).
+    logic [31:0] zi_awaddr; logic [7:0] zi_awlen; logic [2:0] zi_awsize; logic [1:0] zi_awburst; logic zi_awvalid, zi_awready;
     gs_lpddr_z_rmw #(.ZBASE(ZBASE), .FB_PXW(FB_PXW), .FB_H(FB_H), .Z_CLEAR(Z_CLEAR)) u_z (
         .clk(axi_clk), .rst_n(axi_rst_n), .enable(enable), .clear_start(clear_start), .clear_done(clear_done),
         .scene_flush(z_sflush), .z_drained(z_drained),
@@ -163,20 +167,28 @@ module gs_lpddr_zc_emit #(
         .p_valid(z_pvalid), .p_ready(z_pready), .p_pass(z_ppass), .p_x(z_px), .p_y(z_py), .p_zq(z_pzq),
         .araddr(z_araddr), .arlen(z_arlen), .arsize(z_arsize), .arburst(z_arburst), .arvalid(z_arvalid), .arready(z_arready),
         .rdata(z_rdata), .rresp(z_rresp), .rlast(z_rlast), .rvalid(z_rvalid), .rready(z_rready),
-        .awaddr(z_awaddr), .awlen(z_awlen), .awsize(z_awsize), .awburst(z_awburst), .awvalid(z_awvalid), .awready(z_awready),
+        .awaddr(zi_awaddr), .awlen(zi_awlen), .awsize(zi_awsize), .awburst(zi_awburst), .awvalid(zi_awvalid), .awready(zi_awready),
         .wdata(zi_wdata), .wstrb(zi_wstrb), .wlast(zi_wlast), .wvalid(zi_wvalid), .wready(zi_wready),
         .bvalid(z_bvalid), .bready(z_bready), .bresp(z_bresp),
         .beats_read(z_beats_read), .beats_written(z_beats_written), .bresp_err(bresp_err), .idle(z_idle)
     );
     // Ch441: one-entry fully-registered W-channel buffer between the Z RMW master
     // (u_z) and the write arbiter s2 (via the z_w* ports). Breaks the combinational
-    // EMIF WREADY -> z_rmw FSM path. AW/B untouched; the arbiter's bready_q still
+    // EMIF WREADY -> z_rmw FSM path. B untouched; the arbiter's bready_q still
     // arms on the real EMIF m_wvalid && m_wready && m_wlast (buffer is upstream).
     gs_axi_w_regbuf #(.WDATA_W(256), .WSTRB_W(32)) u_z_wbuf (
         .clk(axi_clk), .rst_n(axi_rst_n),
         .u_wdata(zi_wdata), .u_wstrb(zi_wstrb), .u_wlast(zi_wlast), .u_wvalid(zi_wvalid), .u_wready(zi_wready),
         .d_wdata(z_wdata),  .d_wstrb(z_wstrb),  .d_wlast(z_wlast),  .d_wvalid(z_wvalid),  .d_wready(z_wready)
     );
+    // Ch443: one-entry fully-registered AW-channel buffer, the AW twin of u_z_wbuf.
+    // Cuts the combinational EMIF AWREADY -> z_rmw FSM next-state (S_SFLUSH_AW/
+    // S_FILL_R) path — the -0.410 ns setup family Ch442's fit exposed.
+    gs_axi_aw_regbuf #(.ADDR_W(32), .LEN_W(8), .SIZE_W(3), .BURST_W(2)) u_z_awbuf (
+        .clk(axi_clk), .rst_n(axi_rst_n),
+        .u_awaddr(zi_awaddr), .u_awlen(zi_awlen), .u_awsize(zi_awsize), .u_awburst(zi_awburst), .u_awvalid(zi_awvalid), .u_awready(zi_awready),
+        .d_awaddr(z_awaddr),  .d_awlen(z_awlen),  .d_awsize(z_awsize),  .d_awburst(z_awburst),  .d_awvalid(z_awvalid),  .d_awready(z_awready)
+    );
     // A fragment carries ztest: when ztest=0 it must ALWAYS pass. Feed the RMW a zmsk so it never writes Z for a
     // non-Z fragment, and force its zq to max so GEQUAL always passes. (All scheduler draws are ztest=1.)
     // (Handled at feed below via the always-pass override on the pass decision.)