thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
489 lines
20 KiB
Systemverilog
489 lines
20 KiB
Systemverilog
// retroDE_ps2 — tb_bridge_iop_pad_input (Ch235)
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// ============================================================================
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// First end-to-end integration TB for the HPS → bridge → IOP-fabric
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// input path. Wires `ps2_hps_bridge` (Ch222 INPUT_P1/P2 store) into
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// `iop_memory_map_stub` (Ch234 sio2_input_stub region) across two
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// distinct clocks so the bridge-clk → IOP-clk CDC is exercised end-to-end:
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//
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// HPS AXI write @ 0x040 (INPUT_P1) →
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// ps2_hps_bridge.input_p1_q latch (bclk @ 100 MHz) →
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// ps2_hps_bridge.input_p1_o output →
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// iop_memory_map_stub.input_p1 →
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// u_sio2_input.input_p1 →
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// 2-FF sync into iclk @ 33 MHz →
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// PAD_P1_STATE readable at IOP phys 0x1F80_8500
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//
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// Verifies:
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// §1. Reset: IOP-side PAD_P1/P2 = 0xFFFF, PAD_STATUS = 1.
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// §2. AXI write INPUT_P1 single bit → after CDC latency, IOP read
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// shows the corresponding Sony bit cleared.
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// §3. AXI write INPUT_P2 with a different pattern → P1 unchanged,
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// P2 reflects new state (independence).
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// §4. Multi-bit AXI write → IOP sees the matching combo word.
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// §5. AXI clear → IOP reads back to 0xFFFF.
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// §6. Bridge reset cycle → IOP sees 0xFFFF (Ch222 latches clear),
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// even if iclk reset stays asserted.
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// ============================================================================
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`timescale 1ns/1ps
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module tb_bridge_iop_pad_input;
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// ------------------------------------------------------------------
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// Two clocks — bridge on bclk @ 100 MHz, IOP on iclk @ 33 MHz.
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// Different periods deliberately exercise the bclk → iclk CDC.
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// ------------------------------------------------------------------
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logic bclk;
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logic iclk;
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initial bclk = 1'b0;
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initial iclk = 1'b0;
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always #5 bclk = ~bclk; // 100 MHz
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always #15 iclk = ~iclk; // 33 MHz
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logic breset_n;
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logic ireset_n;
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// ------------------------------------------------------------------
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// Bridge status inputs (tied LOW — we don't exercise CORE_STATUS).
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// ------------------------------------------------------------------
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logic core_halt;
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logic dma_done_seen;
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logic frame_seen;
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logic hdmi_init_done;
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logic hdmi_i2c_error;
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logic raster_overflow;
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logic frame_toggle;
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logic dma_done_toggle;
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// ------------------------------------------------------------------
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// Bridge AXI slave (TB drives master).
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// ------------------------------------------------------------------
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logic [3:0] s_axi_awid;
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logic [37:0] s_axi_awaddr;
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logic [7:0] s_axi_awlen;
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logic [2:0] s_axi_awsize;
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logic [1:0] s_axi_awburst;
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logic s_axi_awlock;
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logic [3:0] s_axi_awcache;
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logic [2:0] s_axi_awprot;
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logic s_axi_awvalid;
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logic s_axi_awready;
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logic [127:0] s_axi_wdata;
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logic [15:0] s_axi_wstrb;
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logic s_axi_wlast;
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logic s_axi_wvalid;
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logic s_axi_wready;
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logic [3:0] s_axi_bid;
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logic [1:0] s_axi_bresp;
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logic s_axi_bvalid;
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logic s_axi_bready;
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logic [3:0] s_axi_arid;
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logic [37:0] s_axi_araddr;
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logic [7:0] s_axi_arlen;
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logic [2:0] s_axi_arsize;
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logic [1:0] s_axi_arburst;
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logic s_axi_arlock;
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logic [3:0] s_axi_arcache;
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logic [2:0] s_axi_arprot;
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logic s_axi_arvalid;
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logic s_axi_arready;
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logic [3:0] s_axi_rid;
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logic [127:0] s_axi_rdata;
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logic [1:0] s_axi_rresp;
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logic s_axi_rlast;
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logic s_axi_rvalid;
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logic s_axi_rready;
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// ------------------------------------------------------------------
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// Bridge outputs we ignore (Ch176/Ch229/Ch230).
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// ------------------------------------------------------------------
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logic core_reset_req;
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logic tile_wr_toggle;
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logic [9:0] tile_wr_index;
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logic [31:0] tile_wr_data;
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// Ch245 — platform OSD register-surface ports (unused by this
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// integration TB; declared so the `.*` wildcard binds them).
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wire [31:0] osd_ctrl_o;
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wire [31:0] osd_cfg0_o;
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wire [31:0] osd_cfg1_o;
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logic osd_active_i = 1'b0;
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logic [4:0] osd_cursor_row_i = 5'd0;
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logic osd_set_trigger_i = 1'b0;
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logic osd_back_trigger_i = 1'b0;
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logic osd_scroll_down_trigger_i = 1'b0;
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logic osd_scroll_up_trigger_i = 1'b0;
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logic osd_open_trigger_i = 1'b0;
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logic [4:0] osd_trigger_row_i = 5'd0;
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// Ch248 DS2 wired-controller inputs (unused by this TB; tied
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// unplugged so the bridge's DS2_STATUS reads as such).
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logic [31:0] ds2_buttons_i = 32'd0;
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logic ds2_connected_i = 1'b0;
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logic ds2_error_i = 1'b0;
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// ------------------------------------------------------------------
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// The new Ch235 broadcast — bridge → IOP map.
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// ------------------------------------------------------------------
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wire [31:0] bridge_input_p1;
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wire [31:0] bridge_input_p2;
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// ------------------------------------------------------------------
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// ps2_hps_bridge instance.
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// ------------------------------------------------------------------
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// Ch318 — LPDDR test ports (this TB doesn't exercise them; nets exist so the
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// bridge's .* connects, status inputs tied safe).
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logic lpddr_arm_o, lpddr_canary_o;
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logic lpddr_ctrl_commit_o;
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logic [31:0] lpddr_fb_base_o;
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logic [31:0] lpddr_bytes_i = 32'd0, lpddr_bursts_i = 32'd0, lpddr_bresp_err_i = 32'd0, lpddr_fifo_ovf_i = 32'd0;
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logic lpddr_idle_i = 1'b1;
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// Ch319 — read-probe nets (tie inputs safe; .* binds them).
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logic [31:0] lpddr_rd_addr_o; logic lpddr_rd_pulse_o;
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logic [31:0] lpddr_rd_data_i = 32'd0; logic lpddr_rd_done_i = 1'b0;
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logic lpddr_video_src_o;
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logic lpddr_scanout_lb_o;
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logic lpddr_scan_valid_i = 1'b0, lpddr_scan_err_i = 1'b0;
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// Ch322 — write-probe + texture-cache fill nets (matched by the .* below).
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logic [31:0] lpddr_wr_addr_o, lpddr_wr_data_o; logic lpddr_wr_pulse_o;
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logic lpddr_wr_busy_i = 1'b0, lpddr_wr_done_i = 1'b0; logic [31:0] lpddr_wr_bresp_err_i = 32'd0;
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logic tex_fill_start_o, tex_fill_done_i = 1'b0;
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logic [31:0] tex_fill_beats_i = 32'd0, tex_fill_bytes_i = 32'd0, tex_rd_errs_i = 32'd0, tex_fill_crc_i = 32'd0;
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logic [31:0] tex_cache_hits_i = 32'd0, tex_bram_hits_i = 32'd0;
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// Ch323 — tile COLOR+Z spill/reload counters (unused here; 0 so the .* connect resolves).
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logic [31:0] spill_color_beats_i = 32'd0, spill_z_beats_i = 32'd0;
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logic [31:0] reload_color_beats_i = 32'd0, reload_z_beats_i = 32'd0;
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logic [31:0] reload_rd_errs_i = 32'd0, spill_color_errs_i = 32'd0, spill_z_errs_i = 32'd0;
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logic spill_color_ovf_i = 1'b0, spill_z_ovf_i = 1'b0;
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logic [1:0] diag_ctrl_o; // Ch323 diag DIAG_CTRL output
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logic [31:0] color_spill_awaddr_i=0, color_spill_wdata0_i=0;
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logic [31:0] dbg_c_first_awaddr_i=0, dbg_c_first_wdata0_i=0, dbg_c_first_wstrb_i=0, dbg_c_last_wstrb_i=0, dbg_c_beat_count_i=0;
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logic [31:0] dbg_c_emit_count_i=0, dbg_c_push_count_i=0, dbg_c_pop_count_i=0; // Ch323 pipeline-split (.* tie-off)
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logic [31:0] dbg_z_beat_count_i=0, dbg_z_emit_count_i=0, dbg_z_push_count_i=0, dbg_z_pop_count_i=0; // Ch324 (.* tie-off)
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logic [31:0] dbg_m_first_awaddr_i=0, dbg_m_first_wdata0_i=0, dbg_m_first_wstrb_i=0;
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logic [31:0] ev_tp_flush_i=0, ev_tp_zflush_i=0, ev_tp_reload_i=0, ev_tp_render_i=0;
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logic [31:0] ev_flush_emit_i=0, ev_zflush_emit_i=0, ev_reload_start_i=0, ev_reload_ready_i=0;
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// Ch330 Brick 4 — feeder control ports (.* tie-off; this TB doesn't exercise the feeder).
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logic feeder_stg_we_tgl_o, feeder_go_tgl_o;
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logic [11:0] feeder_stg_waddr_o;
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logic [63:0] feeder_stg_wdata_o;
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logic feeder_ready_i = 1'b0;
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logic [15:0] feeder_records_i = 16'd0;
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logic [31:0] feeder_waits_i = 32'd0;
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ps2_hps_bridge u_bridge (
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.clk (bclk),
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.reset_n (breset_n),
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.h2f_reset (1'b0),
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.core_halt (core_halt),
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.dma_done_seen (dma_done_seen),
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.frame_seen (frame_seen),
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.hdmi_init_done (hdmi_init_done),
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.hdmi_i2c_error (hdmi_i2c_error),
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.raster_overflow(raster_overflow),
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.frame_toggle (frame_toggle),
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.dma_done_toggle(dma_done_toggle),
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.core_reset_req (core_reset_req),
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.tile_wr_toggle (tile_wr_toggle),
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.tile_wr_index (tile_wr_index),
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.tile_wr_data (tile_wr_data),
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.input_p1_o (bridge_input_p1),
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.input_p2_o (bridge_input_p2),
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.input_p1_raw_o (),
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.* // AXI signals
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);
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// ------------------------------------------------------------------
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// IOP map signals (TB drives the CPU-side read; all other ports
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// tied off since we only care about the pad path).
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// ------------------------------------------------------------------
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logic iop_rd_en;
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logic [31:0] iop_rd_addr;
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wire [31:0] iop_rd_data;
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wire iop_rd_valid;
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logic [7:0] iop_master_id;
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// Trace outputs (ignored).
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wire tr_valid;
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wire [3:0] tr_subsys;
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wire [3:0] tr_event;
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wire [63:0] tr_arg0, tr_arg1, tr_arg2, tr_arg3;
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wire [31:0] tr_flags;
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iop_memory_map_stub u_map (
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.clk(iclk), .rst_n(ireset_n),
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// CPU side — TB drives reads only.
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.iop_rd_en(iop_rd_en), .iop_rd_addr(iop_rd_addr),
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.iop_rd_data(iop_rd_data), .iop_rd_valid(iop_rd_valid),
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.iop_wr_en(1'b0), .iop_wr_addr(32'd0),
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.iop_wr_data(32'd0), .iop_wr_be(4'd0),
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.master_id(iop_master_id),
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// Bridge-side write port — unused by this TB.
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.bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
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.bridge_wr_data(32'd0), .bridge_wr_be(4'd0),
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.bridge_master_id(8'd0),
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// DMA-side read port — unused.
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.dma_rd_en(1'b0), .dma_rd_addr(32'd0),
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.dma_master_id(8'd0),
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.dma_rd_data(), .dma_rd_valid(),
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// RAM port — tied off; CPU reads of RAM aren't exercised.
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.ram_rd_en(), .ram_rd_addr(),
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.ram_rd_data(32'd0), .ram_rd_valid(1'b0),
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.ram_wr_en(), .ram_wr_addr(),
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.ram_wr_data(), .ram_wr_be(),
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.ram_master_id(),
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// SIF port — tied off.
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.sif_rd_en(), .sif_rd_addr(),
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.sif_rd_data(32'd0), .sif_rd_valid(1'b0),
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.sif_wr_en(), .sif_wr_addr(), .sif_wr_data(),
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// IOP DMAC port — tied off.
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.iop_dmac_rd_en(), .iop_dmac_rd_addr(),
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.iop_dmac_rd_data(32'd0), .iop_dmac_rd_valid(1'b0),
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.iop_dmac_wr_en(), .iop_dmac_wr_addr(), .iop_dmac_wr_data(),
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// IOP INTC port — tied off.
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.iop_intc_rd_en(), .iop_intc_rd_addr(),
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.iop_intc_rd_data(32'd0), .iop_intc_rd_valid(1'b0),
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.iop_intc_wr_en(), .iop_intc_wr_addr(), .iop_intc_wr_data(),
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// Ch235 — bridge → IOP wiring (the whole point of this TB).
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.input_p1(bridge_input_p1),
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.input_p2(bridge_input_p2),
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// BIOS port — tied off.
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.bios_rd_en(), .bios_rd_addr(),
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.bios_rd_data(32'd0), .bios_rd_valid(1'b0),
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// Trace outputs.
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.ev_valid(tr_valid), .ev_subsys(tr_subsys), .ev_event(tr_event),
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.ev_arg0(tr_arg0), .ev_arg1(tr_arg1),
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.ev_arg2(tr_arg2), .ev_arg3(tr_arg3),
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.ev_flags(tr_flags)
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);
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int errors;
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task automatic check_eq(input string label,
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input logic [31:0] got,
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input logic [31:0] expected);
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if (got !== expected) begin
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$error("[%s] got 0x%08x expected 0x%08x", label, got, expected);
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errors = errors + 1;
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end
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endtask
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// ------------------------------------------------------------------
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// AXI master tasks (mirror tb_ps2_hps_bridge.sv).
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// ------------------------------------------------------------------
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task automatic axi_write32(input logic [37:0] addr,
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input logic [31:0] data);
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@(posedge bclk);
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s_axi_awid <= 4'd0;
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s_axi_awaddr <= addr;
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s_axi_awlen <= 8'd0;
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s_axi_awsize <= 3'd2;
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s_axi_awburst <= 2'b01;
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s_axi_awlock <= 1'b0;
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s_axi_awcache <= 4'd0;
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s_axi_awprot <= 3'd0;
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s_axi_awvalid <= 1'b1;
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case (addr[3:2])
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2'b00: s_axi_wdata <= {96'd0, data};
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2'b01: s_axi_wdata <= {64'd0, data, 32'd0};
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2'b10: s_axi_wdata <= {32'd0, data, 64'd0};
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default: s_axi_wdata <= {data, 96'd0};
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endcase
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s_axi_wstrb <= 16'h000F << ({addr[3:2], 2'b00});
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s_axi_wlast <= 1'b1;
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s_axi_wvalid <= 1'b1;
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s_axi_bready <= 1'b1;
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wait (s_axi_awready);
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@(posedge bclk);
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s_axi_awvalid <= 1'b0;
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wait (s_axi_wready);
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@(posedge bclk);
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s_axi_wvalid <= 1'b0;
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wait (s_axi_bvalid);
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@(posedge bclk);
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s_axi_bready <= 1'b0;
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endtask
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// ------------------------------------------------------------------
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// IOP read helper. Follows the existing tb_iop_memory_map_stub
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// pattern: drive on @(negedge iclk) with BLOCKING assigns so the
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// address is stable through the next posedge that registers
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// rd_pending. Sample iop_rd_data on the following negedge — by
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// then the map's read response (and the stub's pad_rd_data) have
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// both been registered, and iop_rd_valid is HIGH for one cycle.
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// ------------------------------------------------------------------
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task automatic iop_read32(input logic [31:0] addr,
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output logic [31:0] data);
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@(negedge iclk);
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iop_rd_en = 1'b1;
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iop_rd_addr = addr;
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@(negedge iclk);
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iop_rd_en = 1'b0;
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iop_rd_addr = 32'd0;
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data = iop_rd_data;
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if (iop_rd_valid !== 1'b1) begin
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$error("[iop_read32] iop_rd_valid not high at sample (addr=0x%08x)", addr);
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errors = errors + 1;
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end
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endtask
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// ------------------------------------------------------------------
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// Sony pad-word expected-value helper (mirrors sio2_input_stub).
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// ------------------------------------------------------------------
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function automatic logic [15:0] expected_sony(input logic [31:0] joy);
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logic [7:0] b3, b4;
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b3 = ~{joy[1], joy[2], joy[0], joy[3], joy[4], joy[15], joy[14], joy[5]};
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b4 = ~{joy[8], joy[7], joy[9], joy[6], joy[11], joy[10], joy[13], joy[12]};
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expected_sony = {b4, b3};
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endfunction
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// ------------------------------------------------------------------
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// Wait long enough for an AXI-written value to propagate through
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// the bridge latch + the 2-FF sync inside sio2_input_stub.
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// Conservative — 20 iclk cycles is many sync windows.
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// ------------------------------------------------------------------
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task automatic settle_cdc();
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repeat (20) @(posedge iclk);
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endtask
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logic [31:0] rd;
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localparam logic [31:0] PAD_P1_ADDR = 32'h1F80_8500;
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localparam logic [31:0] PAD_P2_ADDR = 32'h1F80_8504;
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localparam logic [31:0] PAD_ST_ADDR = 32'h1F80_8508;
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initial begin
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errors = 0;
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breset_n = 1'b0;
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ireset_n = 1'b0;
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// AXI defaults.
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s_axi_arvalid = 1'b0;
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s_axi_awvalid = 1'b0;
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s_axi_wvalid = 1'b0;
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s_axi_rready = 1'b0;
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s_axi_bready = 1'b0;
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// Bridge status (all LOW — we don't exercise CORE_STATUS).
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core_halt = 1'b0;
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dma_done_seen = 1'b0;
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frame_seen = 1'b0;
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hdmi_init_done = 1'b0;
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hdmi_i2c_error = 1'b0;
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raster_overflow = 1'b0;
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frame_toggle = 1'b0;
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dma_done_toggle = 1'b0;
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// IOP-side defaults.
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iop_rd_en = 1'b0;
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iop_rd_addr = 32'd0;
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iop_master_id = 8'd0;
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repeat (4) @(posedge bclk);
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@(posedge iclk);
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breset_n = 1'b1;
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ireset_n = 1'b1;
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// Settle both domains.
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repeat (8) @(posedge bclk);
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repeat (8) @(posedge iclk);
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|
|
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// ----------------------------------------------------------
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// §1. Reset state — bridge latches at 0 → Sony word 0xFFFF.
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// PAD_STATUS = 1.
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// ----------------------------------------------------------
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iop_read32(PAD_P1_ADDR, rd); check_eq("rst_P1", rd, 32'h0000_FFFF);
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iop_read32(PAD_P2_ADDR, rd); check_eq("rst_P2", rd, 32'h0000_FFFF);
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iop_read32(PAD_ST_ADDR, rd); check_eq("rst_ST", rd, 32'h0000_0001);
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|
|
|
// ----------------------------------------------------------
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// §2. AXI write JOY_RIGHT (bit 0) into INPUT_P1 @ 0x040.
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// After CDC settle, IOP-side P1 has byte3.5 (RIGHT)
|
|
// cleared.
|
|
// ----------------------------------------------------------
|
|
axi_write32(38'h040, 32'h0000_0001);
|
|
settle_cdc();
|
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iop_read32(PAD_P1_ADDR, rd);
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check_eq("P1_RIGHT_only",
|
|
rd, {16'd0, expected_sony(32'h0000_0001)});
|
|
// P2 unchanged.
|
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iop_read32(PAD_P2_ADDR, rd);
|
|
check_eq("P2_unaffected_by_P1_write", rd, 32'h0000_FFFF);
|
|
|
|
// ----------------------------------------------------------
|
|
// §3. AXI write a different pattern into INPUT_P2 @ 0x044
|
|
// (JOY_DOWN | JOY_A = bits 2 | 9). P1 retains its
|
|
// previous state.
|
|
// ----------------------------------------------------------
|
|
axi_write32(38'h044, 32'h0000_0204);
|
|
settle_cdc();
|
|
iop_read32(PAD_P2_ADDR, rd);
|
|
check_eq("P2_DOWN_A",
|
|
rd, {16'd0, expected_sony(32'h0000_0204)});
|
|
iop_read32(PAD_P1_ADDR, rd);
|
|
check_eq("P1_persist_after_P2_write",
|
|
rd, {16'd0, expected_sony(32'h0000_0001)});
|
|
|
|
// ----------------------------------------------------------
|
|
// §4. Multi-bit combo. All D-pad + START + SELECT pressed
|
|
// on P1 (bits 0..5).
|
|
// ----------------------------------------------------------
|
|
axi_write32(38'h040, 32'h0000_003F);
|
|
settle_cdc();
|
|
iop_read32(PAD_P1_ADDR, rd);
|
|
check_eq("P1_dpad_start_sel_combo",
|
|
rd, {16'd0, expected_sony(32'h0000_003F)});
|
|
|
|
// ----------------------------------------------------------
|
|
// §5. AXI clear INPUT_P1 → IOP reads back to 0xFFFF.
|
|
// INPUT_P2 unchanged.
|
|
// ----------------------------------------------------------
|
|
axi_write32(38'h040, 32'h0000_0000);
|
|
settle_cdc();
|
|
iop_read32(PAD_P1_ADDR, rd);
|
|
check_eq("P1_cleared", rd, 32'h0000_FFFF);
|
|
iop_read32(PAD_P2_ADDR, rd);
|
|
check_eq("P2_persist_after_P1_clear",
|
|
rd, {16'd0, expected_sony(32'h0000_0204)});
|
|
|
|
// ----------------------------------------------------------
|
|
// §6. Bridge reset cycle — Ch222 latches clear; IOP sees
|
|
// 0xFFFF for both pads regardless of any prior state.
|
|
// ----------------------------------------------------------
|
|
@(posedge bclk); breset_n = 1'b0;
|
|
// Hold reset long enough to cycle through the sync chain.
|
|
repeat (8) @(posedge bclk);
|
|
repeat (8) @(posedge iclk);
|
|
@(posedge bclk); breset_n = 1'b1;
|
|
// Need more iclk settle: bridge clears at bclk, sio2_input
|
|
// sync takes 2 iclk to propagate the new value.
|
|
repeat (8) @(posedge bclk);
|
|
settle_cdc();
|
|
iop_read32(PAD_P1_ADDR, rd); check_eq("rst_clr_P1", rd, 32'h0000_FFFF);
|
|
iop_read32(PAD_P2_ADDR, rd); check_eq("rst_clr_P2", rd, 32'h0000_FFFF);
|
|
iop_read32(PAD_ST_ADDR, rd); check_eq("rst_clr_ST", rd, 32'h0000_0001);
|
|
|
|
// ----------------------------------------------------------
|
|
// Done.
|
|
// ----------------------------------------------------------
|
|
$display("[tb_bridge_iop_pad_input] errors=%0d", errors);
|
|
if (errors == 0) $display("[tb_bridge_iop_pad_input] PASS");
|
|
else $display("[tb_bridge_iop_pad_input] FAIL");
|
|
$finish;
|
|
end
|
|
|
|
initial begin
|
|
#5_000_000;
|
|
$error("[tb_bridge_iop_pad_input] TIMEOUT");
|
|
$finish;
|
|
end
|
|
|
|
endmodule : tb_bridge_iop_pad_input
|