thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
122 lines
6.2 KiB
Systemverilog
122 lines
6.2 KiB
Systemverilog
// ============================================================================
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// tb_gs_tile_reload.sv (Ch323 Brick 2)
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//
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// Unit-proves the tile color+Z reload staging engine (the gs_texture_cache clone):
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// preload a behavioral single-beat EMIF with a 16x16 tile's color (at COLOR_BASE)
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// and Z (at a DISTINCT Z_BASE), strided STRIDE_BYTES/row; fill; then verify:
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// (1) reload_done; color_beats=32, z_beats=32 (16 rows x 2 beats each); rd_errs=0
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// (2) every served (color,Z) for tile index 0..255 == the source (1-cycle read)
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// (3) a forced non-OKAY rresp increments rd_errs
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// ============================================================================
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`timescale 1ns/1ps
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module tb_gs_tile_reload;
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localparam int TILE_W=16, TILE_H=16, STRIDE_BYTES=256, ROW_BEATS=2, COLOR_W=32;
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localparam [29:0] COLOR_BASE = 30'd0;
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localparam [29:0] Z_BASE = 30'h0000_4000; // distinct, small for the TB mem
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localparam int N_ENTRIES = TILE_W*TILE_H; // 256
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logic axi_clk=0, serve_clk=0, axi_rst_n=0;
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always #5 axi_clk = ~axi_clk;
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always #7 serve_clk = ~serve_clk; // asynchronous
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logic reload_start, reload_done;
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logic [31:0] color_beats, z_beats, rd_errs;
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logic [29:0] araddr; logic [1:0] arburst; logic [6:0] arid;
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logic [7:0] arlen; logic [2:0] arsize; logic arvalid, arready;
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logic [255:0] rdata; logic [1:0] rresp; logic rlast, rvalid, rready;
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logic [7:0] raddr; logic [31:0] color_o, z_o; logic reload_ready;
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function automatic [31:0] cval(input int i); cval = 32'hC0DE_0000 | i[31:0]; endfunction
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function automatic [31:0] zval(input int i); zval = 32'h5A5A_0000 | i[31:0]; endfunction
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int err_beat = -1;
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gs_tile_reload #(
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.COLOR_BASE(COLOR_BASE), .Z_BASE(Z_BASE), .TILE_W(TILE_W), .TILE_H(TILE_H),
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.STRIDE_BYTES(STRIDE_BYTES), .ROW_BEATS(ROW_BEATS), .COLOR_W(COLOR_W)
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) dut (
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.axi_clk(axi_clk), .axi_rst_n(axi_rst_n), .reload_start(reload_start), .reload_base(30'd0),
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.reload_done(reload_done), .color_beats(color_beats), .z_beats(z_beats), .rd_errs(rd_errs),
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.araddr(araddr), .arburst(arburst), .arid(arid), .arlen(arlen), .arsize(arsize),
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.arvalid(arvalid), .arready(arready), .rdata(rdata), .rresp(rresp), .rlast(rlast),
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.rvalid(rvalid), .rready(rready),
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.serve_clk(serve_clk), .raddr(raddr), .color_o(color_o), .z_o(z_o), .reload_ready(reload_ready)
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);
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// behavioral 256-bit EMIF read model, preloaded with the strided tile color+Z.
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logic [255:0] mem [0:1023];
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initial begin
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for (int i=0;i<1024;i++) mem[i]=256'd0;
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for (int row=0; row<TILE_H; row++) for (int col=0; col<TILE_W; col++) begin
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int idx; logic [29:0] ca, za;
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idx = row*TILE_W + col;
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ca = COLOR_BASE + row*STRIDE_BYTES + col*4;
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za = Z_BASE + row*STRIDE_BYTES + col*4;
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mem[ca >> 5][((ca >> 2) & 3'd7)*32 +: 32] = cval(idx);
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mem[za >> 5][((za >> 2) & 3'd7)*32 +: 32] = zval(idx);
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end
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end
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int beat_cnt;
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typedef enum logic [1:0] { S_IDLE,S_WAIT,S_DATA } sst_t; sst_t sst;
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logic [29:0] ba; logic [3:0] dly;
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always_ff @(posedge axi_clk) begin
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if (!axi_rst_n) begin sst<=S_IDLE; arready<=0; rvalid<=0; rlast<=0; rresp<=0; rdata<=0; dly<=0; beat_cnt<=0;
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end else begin
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arready<=0; rvalid<=0; rlast<=0;
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case (sst)
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S_IDLE: if (arvalid) begin ba<=araddr; arready<=1; dly<=4'd3; sst<=S_WAIT; end
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S_WAIT: if (dly==0) sst<=S_DATA; else dly<=dly-1'b1;
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S_DATA: if (rready) begin
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rdata <= mem[ba >> 5];
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rresp <= (beat_cnt==err_beat) ? 2'b10 : 2'b00;
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rvalid <= 1; rlast <= 1; beat_cnt <= beat_cnt+1; sst<=S_IDLE;
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end
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endcase
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end
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end
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int errors=0;
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task automatic chk(input bit c, input string m); if (!c) begin errors++; $display("[tilereload] FAIL: %s", m); end endtask
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task automatic rd(input int idx, output logic [31:0] cg, output logic [31:0] zg);
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@(posedge serve_clk); raddr <= idx[7:0];
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@(posedge serve_clk); @(posedge serve_clk); cg = color_o; zg = z_o;
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endtask
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logic [31:0] cg, zg;
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initial begin
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reload_start=0; raddr=0;
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repeat(4) @(posedge axi_clk); axi_rst_n=1; repeat(2) @(posedge axi_clk);
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// clean fill (PULSE reload_start once — rising-edge strobe)
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@(posedge axi_clk) reload_start<=1'b1;
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@(posedge axi_clk) reload_start<=1'b0;
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begin int g=0; while(!reload_done && g<5000) begin @(posedge axi_clk); g++; end end
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chk(reload_done, "reload_done never asserted");
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chk(color_beats==32, $sformatf("color_beats=%0d exp 32", color_beats));
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chk(z_beats==32, $sformatf("z_beats=%0d exp 32", z_beats));
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chk(rd_errs==0, $sformatf("rd_errs=%0d exp 0", rd_errs));
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begin int g=0; while(!reload_ready && g<200) begin @(posedge serve_clk); g++; end end
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chk(reload_ready, "reload_ready never synced");
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for (int i=0;i<N_ENTRIES;i++) begin
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rd(i, cg, zg);
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chk(cg===cval(i), $sformatf("color[%0d]=%08x exp %08x", i, cg, cval(i)));
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chk(zg===zval(i), $sformatf("z[%0d]=%08x exp %08x", i, zg, zval(i)));
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end
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$display("[tilereload] clean: done=%0d color_beats=%0d z_beats=%0d rd_errs=%0d entries=%0d errors=%0d",
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reload_done, color_beats, z_beats, rd_errs, N_ENTRIES, errors);
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// err-inject: reset, force SLVERR on beat 5
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axi_rst_n=0; err_beat=5; repeat(3) @(posedge axi_clk); axi_rst_n=1; repeat(2) @(posedge axi_clk);
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@(posedge axi_clk) reload_start<=1'b1; // PULSE again -> rising edge -> refill
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@(posedge axi_clk) reload_start<=1'b0;
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begin int g=0; while(!reload_done && g<5000) begin @(posedge axi_clk); g++; end end
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chk(rd_errs==1, $sformatf("forced-err rd_errs=%0d exp 1", rd_errs));
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$display("[tilereload] err-inject: rd_errs=%0d (exp 1)", rd_errs);
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if (errors==0) $display("[tb_gs_tile_reload] PASS"); else $display("[tb_gs_tile_reload] FAIL (%0d errors)", errors);
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$finish;
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end
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initial begin #800000; $display("[tb_gs_tile_reload] TIMEOUT"); $finish; end
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endmodule
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