thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
116 lines
3.6 KiB
Systemverilog
116 lines
3.6 KiB
Systemverilog
// retroDE_ps2 — tb_gs_texture_unit
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//
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// Verifies gs_texture_unit end-to-end against a stand-in VRAM: preload known
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// 32-bit texels, stream a sequence of (u,v) coords in, and check the sampled
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// color comes out aligned with out_valid and matches the preloaded texel at
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// the address the unit computed. Exercises the read-latency pipeline.
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`timescale 1ns/1ps
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module tb_gs_texture_unit;
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localparam logic [5:0] PSMCT32 = 6'h00;
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localparam int RD_LATENCY = 1;
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logic clk = 0, rst_n = 0;
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logic in_valid;
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logic [10:0] u, v;
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logic [31:0] tbp0_base_bytes;
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logic [13:0] tbw;
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logic [5:0] psm;
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logic tex_rd_en;
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logic [31:0] tex_rd_addr;
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logic [31:0] tex_rd_data;
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logic out_valid;
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logic [31:0] tex_color;
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int errors = 0;
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always #5 clk = ~clk;
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gs_texture_unit #(.RD_LATENCY(RD_LATENCY)) dut (
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.clk(clk), .rst_n(rst_n),
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.in_valid(in_valid), .u(u), .v(v),
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.tbp0_base_bytes(tbp0_base_bytes), .tbw(tbw), .psm(psm),
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.tex_rd_en(tex_rd_en), .tex_rd_addr(tex_rd_addr), .tex_rd_data(tex_rd_data),
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.out_valid(out_valid), .tex_color(tex_color)
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);
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// --- stand-in VRAM: byte-addressed, 32-bit word, registered 1-cycle read ---
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logic [31:0] mem [0:1023]; // 4 KiB window
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always_ff @(posedge clk) begin
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if (tex_rd_en)
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tex_rd_data <= mem[tex_rd_addr[31:2]]; // word index = byte addr >> 2
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end
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// expected-color shadow, delayed to align with out_valid
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logic [31:0] exp_color_q;
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logic exp_valid_q;
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task automatic feed(input logic [10:0] uu, input logic [10:0] vv,
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input logic [31:0] expect_color);
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@(negedge clk);
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in_valid = 1'b1;
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u = uu;
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v = vv;
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exp_color_q = expect_color;
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exp_valid_q = 1'b1;
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@(posedge clk); // address presented; VRAM registers data
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#1;
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in_valid = 1'b0;
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// out_valid + tex_color valid RD_LATENCY cycles after this posedge
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endtask
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// checker: whenever out_valid, compare against the pipelined expectation
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logic [31:0] exp_pipe;
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logic expv_pipe;
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always_ff @(posedge clk) begin
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if (!rst_n) begin expv_pipe <= 0; exp_pipe <= 0; end
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else begin
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expv_pipe <= exp_valid_q;
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exp_pipe <= exp_color_q;
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exp_valid_q <= 1'b0; // one-shot per feed
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end
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end
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always_ff @(posedge clk) begin
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if (out_valid) begin
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if (tex_color !== exp_pipe) begin
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$display("FAIL: tex_color=%08x expected=%08x (addr=%0d)",
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tex_color, exp_pipe, tex_rd_addr);
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errors++;
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end else begin
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$display("ok : tex_color=%08x", tex_color);
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end
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end
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end
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initial begin
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// preload texels. tbw=1 -> 64 texels/row, base 0, PSMCT32 (4 B/texel)
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// texel (u,v) lives at word index v*64 + u.
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mem[2*64 + 3] = 32'hDEADBEEF; // (u=3, v=2)
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mem[0] = 32'h11223344; // (u=0, v=0)
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mem[1*64 + 5] = 32'hA5A5F00D; // (u=5, v=1)
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tbp0_base_bytes = 0; tbw = 1; psm = PSMCT32;
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in_valid = 0; u = 0; v = 0;
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repeat (3) @(posedge clk);
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rst_n = 1;
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@(negedge clk);
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feed(11'd3, 11'd2, 32'hDEADBEEF);
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feed(11'd0, 11'd0, 32'h11223344);
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feed(11'd5, 11'd1, 32'hA5A5F00D);
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repeat (4) @(posedge clk);
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if (errors == 0)
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$display("\nPASS tb_gs_texture_unit");
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else
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$display("\nFAIL tb_gs_texture_unit (%0d errors)", errors);
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$finish;
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end
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endmodule
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