thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
235 lines
9.6 KiB
Verilog
235 lines
9.6 KiB
Verilog
// ============================================================================
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// I2C_Controller.v — Fixed-frame I2C master (3-byte write transactions)
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// ============================================================================
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//
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2026 retroDE contributors
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//
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// Clean-room implementation, not derived from any GPL upstream. Released
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// under the MIT license to allow reuse outside the retroDE project. The
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// retroDE project as a whole is distributed under GPLv3 — see ../LICENSE
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// for the combined-work terms. See ../LICENSES/MIT.txt for the full MIT
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// text.
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//
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// ----------------------------------------------------------------------------
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// Purpose
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// Simple I2C master that sends a fixed 24-bit frame per transaction:
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// I2C_DATA = { slave_addr[6:0], rw, reg_addr[7:0], data[7:0] }
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// Slave ACK is sampled after each of the three bytes. A STOP condition is
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// generated at the end of the frame.
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//
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// Timing contract (compatible with legacy I2C_HDMI_Config parent)
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// CLK Fabric clock; state is registered on its rising edge.
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// CLK_EN One-cycle pulse at the desired I2C bit rate. State only advances
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// when CLK_EN is asserted.
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// CLK_PHASE Square wave at the SCL rate. During actively clocked bit cells,
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// I2C_SCLK is driven as ~CLK_PHASE. Dedicated START/STOP hold
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// phases force SCL high or low for a full cell.
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// I2C_SDAT Open-drain: driven low via 1'b0 or released to 1'bz. An
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// external or FPGA internal pull-up is required on this line.
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// I2C_SCLK Actively driven (not open-drain). This matches the known-good
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// DE25-Nano HDMI path and avoids relying on board-side pull-ups.
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//
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// Interface
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// Port list is preserved verbatim from the legacy module so this file is
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// a drop-in replacement. W_R is retained as a no-op input for source-
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// compatibility; direction is encoded in I2C_DATA[16] by convention.
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// SD_COUNTER and SDO are exposed for debug/observation only.
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//
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// Implementation note
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// The transaction is modeled as explicit phases rather than implicit state
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// updates. This keeps the START, bit, ACK, and STOP cells easy to inspect
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// while preserving the known-good bus waveform used by retroDE_splash.
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// ============================================================================
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`timescale 1ns/1ps
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module I2C_Controller (
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input wire CLK,
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input wire CLK_EN,
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input wire CLK_PHASE,
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output wire I2C_SCLK,
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inout wire I2C_SDAT,
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input wire [23:0] I2C_DATA,
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input wire GO,
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output reg END,
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input wire W_R, // retained for interface compat; unused
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output wire ACK,
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input wire RESET,
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output wire [5:0] SD_COUNTER, // debug: current transaction phase
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output wire SDO // debug: current SDA release state
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);
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localparam [5:0] PH_IDLE = 6'd0,
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PH_START_HOLD = 6'd1,
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PH_START_LOW = 6'd2,
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PH_B0_7 = 6'd3,
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PH_B0_6 = 6'd4,
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PH_B0_5 = 6'd5,
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PH_B0_4 = 6'd6,
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PH_B0_3 = 6'd7,
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PH_B0_2 = 6'd8,
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PH_B0_1 = 6'd9,
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PH_B0_0 = 6'd10,
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PH_ACK0 = 6'd11,
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PH_B1_7 = 6'd12,
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PH_B1_6 = 6'd13,
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PH_B1_5 = 6'd14,
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PH_B1_4 = 6'd15,
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PH_B1_3 = 6'd16,
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PH_B1_2 = 6'd17,
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PH_B1_1 = 6'd18,
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PH_B1_0 = 6'd19,
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PH_ACK1 = 6'd20,
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PH_B2_7 = 6'd21,
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PH_B2_6 = 6'd22,
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PH_B2_5 = 6'd23,
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PH_B2_4 = 6'd24,
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PH_B2_3 = 6'd25,
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PH_B2_2 = 6'd26,
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PH_B2_1 = 6'd27,
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PH_B2_0 = 6'd28,
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PH_ACK2 = 6'd29,
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PH_STOP_LOW = 6'd30,
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PH_STOP_HIGH = 6'd31,
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PH_DONE = 6'd32;
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reg [5:0] phase;
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reg [23:0] frame_data;
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reg [2:0] ack_bits;
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reg sda_release;
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reg [5:0] phase_next;
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reg [23:0] frame_data_next;
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reg [2:0] ack_bits_next;
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reg sda_release_next;
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reg end_next;
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assign I2C_SCLK =
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(phase == PH_IDLE || phase == PH_START_HOLD || phase == PH_STOP_HIGH || phase == PH_DONE) ? 1'b1 :
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(phase == PH_START_LOW || phase == PH_STOP_LOW) ? 1'b0 :
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~CLK_PHASE;
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assign I2C_SDAT = sda_release ? 1'bz : 1'b0;
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assign ACK = |ack_bits;
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assign SDO = sda_release;
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assign SD_COUNTER = phase;
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always @(*) begin
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phase_next = phase;
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frame_data_next = frame_data;
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ack_bits_next = ack_bits;
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sda_release_next = sda_release;
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end_next = END;
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case (phase)
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PH_IDLE: begin
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end_next = 1'b0;
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sda_release_next = 1'b1;
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if (GO) begin
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phase_next = PH_START_HOLD;
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frame_data_next = I2C_DATA;
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ack_bits_next = 3'd0;
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sda_release_next = 1'b0;
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end
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end
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PH_START_HOLD: begin
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phase_next = PH_START_LOW;
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sda_release_next = 1'b0;
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end
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PH_START_LOW: begin
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phase_next = PH_B0_7;
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sda_release_next = frame_data[23];
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end
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PH_B0_7: begin phase_next = PH_B0_6; sda_release_next = frame_data[22]; end
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PH_B0_6: begin phase_next = PH_B0_5; sda_release_next = frame_data[21]; end
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PH_B0_5: begin phase_next = PH_B0_4; sda_release_next = frame_data[20]; end
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PH_B0_4: begin phase_next = PH_B0_3; sda_release_next = frame_data[19]; end
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PH_B0_3: begin phase_next = PH_B0_2; sda_release_next = frame_data[18]; end
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PH_B0_2: begin phase_next = PH_B0_1; sda_release_next = frame_data[17]; end
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PH_B0_1: begin phase_next = PH_B0_0; sda_release_next = frame_data[16]; end
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PH_B0_0: begin phase_next = PH_ACK0; sda_release_next = 1'b1; end
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PH_ACK0: begin
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phase_next = PH_B1_7;
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ack_bits_next[0] = I2C_SDAT;
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sda_release_next = frame_data[15];
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end
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PH_B1_7: begin phase_next = PH_B1_6; sda_release_next = frame_data[14]; end
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PH_B1_6: begin phase_next = PH_B1_5; sda_release_next = frame_data[13]; end
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PH_B1_5: begin phase_next = PH_B1_4; sda_release_next = frame_data[12]; end
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PH_B1_4: begin phase_next = PH_B1_3; sda_release_next = frame_data[11]; end
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PH_B1_3: begin phase_next = PH_B1_2; sda_release_next = frame_data[10]; end
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PH_B1_2: begin phase_next = PH_B1_1; sda_release_next = frame_data[9]; end
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PH_B1_1: begin phase_next = PH_B1_0; sda_release_next = frame_data[8]; end
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PH_B1_0: begin phase_next = PH_ACK1; sda_release_next = 1'b1; end
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PH_ACK1: begin
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phase_next = PH_B2_7;
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ack_bits_next[1] = I2C_SDAT;
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sda_release_next = frame_data[7];
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end
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PH_B2_7: begin phase_next = PH_B2_6; sda_release_next = frame_data[6]; end
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PH_B2_6: begin phase_next = PH_B2_5; sda_release_next = frame_data[5]; end
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PH_B2_5: begin phase_next = PH_B2_4; sda_release_next = frame_data[4]; end
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PH_B2_4: begin phase_next = PH_B2_3; sda_release_next = frame_data[3]; end
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PH_B2_3: begin phase_next = PH_B2_2; sda_release_next = frame_data[2]; end
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PH_B2_2: begin phase_next = PH_B2_1; sda_release_next = frame_data[1]; end
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PH_B2_1: begin phase_next = PH_B2_0; sda_release_next = frame_data[0]; end
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PH_B2_0: begin phase_next = PH_ACK2; sda_release_next = 1'b1; end
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PH_ACK2: begin
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phase_next = PH_STOP_LOW;
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ack_bits_next[2] = I2C_SDAT;
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sda_release_next = 1'b0;
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end
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PH_STOP_LOW: begin
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phase_next = PH_STOP_HIGH;
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sda_release_next = 1'b0;
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end
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PH_STOP_HIGH: begin
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phase_next = PH_DONE;
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sda_release_next = 1'b1;
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end
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PH_DONE: begin
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end_next = 1'b1;
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sda_release_next = 1'b1;
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if (!GO)
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phase_next = PH_IDLE;
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end
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default: begin
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phase_next = PH_IDLE;
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sda_release_next = 1'b1;
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end_next = 1'b0;
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end
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endcase
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end
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always @(posedge CLK or negedge RESET) begin
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if (!RESET) begin
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phase <= PH_IDLE;
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frame_data <= 24'd0;
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ack_bits <= 3'd0;
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sda_release <= 1'b1;
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END <= 1'b0;
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end
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else if (CLK_EN) begin
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phase <= phase_next;
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frame_data <= frame_data_next;
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ack_bits <= ack_bits_next;
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sda_release <= sda_release_next;
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END <= end_next;
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end
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end
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endmodule
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