thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
712 lines
28 KiB
Systemverilog
712 lines
28 KiB
Systemverilog
// retroDE_ps2 — iop_core_stub
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//
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// Minimal MIPS R3000 subset for the IOP side, now with real interrupt
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// exception entry. The engine sits where `iop_exec_stub` sat, drives
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// `iop_memory_map_stub`'s CPU-side port for ifetch and data accesses,
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// and finally *uses* `cpu_irq` from the IOP INTC instead of ignoring it.
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//
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// Wave 1 (decode): LUI/ORI/ADDIU/LW/SW/BEQ/BNE/J/NOP/SYSCALL, honest
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// branch delay slots. Programs polled INTC_STAT through the real map.
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//
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// Wave 2 (this module revision): minimal COP0 + asynchronous interrupt
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// exception entry. cpu_irq becomes a real vectoring event when
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// enabled through Status. Mainline no longer needs to touch INTC_STAT;
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// an ISR at the exception vector handles acknowledgement.
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//
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// Intentionally still NOT a full R3000:
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// - No TLB / cache / HI/LO / R-type ALU / shifts / mul / div.
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// - No syscall / break exception *handling* beyond SYSCALL-as-halt.
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// - No BD bit in Cause for branch-delay exceptions (we simply
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// refuse to take exceptions between a taken branch and its delay
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// slot — see "delay-slot rule" below).
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// - No kernel/user mode enforcement: KU state exists on the stack
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// for forward compatibility but nothing in the core consults it.
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//
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// Supported opcodes (MIPS encoding):
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// SPECIAL (opcode = 0x00):
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// func 0x08 (JR) — pc <= rs_val; has delay slot.
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// func 0x0C (SYSCALL) — halt_o asserts; FSM stops fetching.
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// any other func — treated as NOP (incl. SLL $0,$0,0).
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// 0x02 J — jump; has delay slot.
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// 0x04 BEQ / 0x05 BNE — conditional branch; has delay slot.
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// 0x09 ADDIU — no overflow trap.
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// 0x0D ORI / 0x0F LUI — logical immediate / upper load.
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// 0x10 COP0:
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// rs 0x00 (MFC0) — rt <= COP0[rd]
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// rs 0x04 (MTC0) — COP0[rd] <= rt
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// rs 0x10, func 0x10 (RFE)
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// — shift IE/KU stack right (pop)
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// 0x23 LW / 0x2B SW — word memory access.
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// Anything else — treated as NOP.
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//
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// COP0 register surface (subset):
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// 12 Status [0]=IEc [1]=KUc [2]=IEp [3]=KUp [4]=IEo [5]=KUo
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// [15:8]=IM (bit 10 = IM2 gates the HW interrupt
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// wired to cpu_irq)
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// 13 Cause [6:2]=ExcCode, [15:8]=IP. IP[2] reflects cpu_irq.
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// Software may write Cause but we only latch SW
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// interrupt pending bits IP[1:0] — not load-bearing
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// in the first TB.
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// 14 EPC saved PC on exception entry.
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//
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// Exception entry semantics:
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// Sampled at *instruction-retire boundaries*, never mid-fetch or
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// mid-memory. An exception is taken iff all of the following hold
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// at the retire boundary:
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// - Status.IEc == 1 (master interrupts enabled)
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// - Cause.IP[i] & Status.IM[i] (any unmasked pending source)
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// - new_branch_pending == 0 (delay slot already resolved)
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// On entry:
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// EPC <= next_pc (the pc that would have been
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// fetched next; branch_target
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// if a delay slot just resolved,
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// pc+4 otherwise)
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// Cause.ExcCode <= 5'h00 (Int exception)
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// Status stack pushes left:
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// IEo <= IEp; IEp <= IEc; IEc <= 0
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// KUo <= KUp; KUp <= KUc; KUc <= 0
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// pc <= EXC_VECTOR (fixed, parameter)
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// branch_pending <= 0 (any pending control flow is
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// canceled; EPC captured it)
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//
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// RFE semantics (pop stack, one level):
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// IEc <= IEp; IEp <= IEo
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// KUc <= KUp; KUp <= KUo
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// (IEo, KUo left intact — matches impl-defined R3000 behaviour
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// for non-nested use)
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//
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// Trace (SUBSYS_IOP, EV_IFETCH one-per-retire as before):
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// flags bit 0 = SW (write) (unchanged)
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// flags bit 1 = LW (read) (unchanged)
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// flags bit 2 = branch / jump taken (unchanged)
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// flags bit 3 = SYSCALL (halt) (unchanged)
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// flags bit 4 = this instruction was in a delay slot
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// flags bit 5 = exception taken at the end of this instruction
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// (EPC saved = next_pc, PC redirected to EXC_VECTOR)
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// flags bit 6 = RFE retired (IE stack popped)
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// flags bit 7 = strict trap (unsupported instruction halted the core)
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//
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// Strict mode (STRICT_UNSUPPORTED parameter):
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// Default is 0 (lenient) to preserve every prior bench's regression
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// behaviour — any instruction the core doesn't actively decode retires
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// as a NOP. When STRICT_UNSUPPORTED=1, the core instead halts on the
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// first unsupported opcode it encounters, latches the offending PC +
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// instruction word into trap_pc_o / trap_instr_o, asserts trap_o, and
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// emits a retire trace with flag bit 7 set. Intended for real-BIOS
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// smoke bring-up — "the first missing opcode is the one the core
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// needs to grow next." The canonical NOP (32'h0000_0000 =
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// SLL $0,$0,0) is always treated as a NOP regardless of strict mode.
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`timescale 1ns/1ps
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module iop_core_stub
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import trace_pkg::*;
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#(
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// Architectural MIPS R3000 reset vector (kseg1 into the shared BIOS
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// window). kseg1 strip in iop_memory_map_stub maps this to physical
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// 0x1FC0_0000, which the map now routes to bios_rom_stub.
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// Tests that don't have a BIOS image must override PC_RESET.
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parameter logic [31:0] PC_RESET = 32'hBFC0_0000,
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parameter logic [31:0] EXC_VECTOR = 32'h0000_0080,
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// See header comment "Strict mode". Default 0 preserves existing
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// regression behaviour; BIOS-oriented benches should set to 1.
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parameter bit STRICT_UNSUPPORTED = 1'b0
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) (
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input logic clk,
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input logic rst_n,
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input logic go_i,
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output logic map_rd_en,
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output logic [31:0] map_rd_addr,
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input logic [31:0] map_rd_data,
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input logic map_rd_valid,
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output logic map_wr_en,
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output logic [31:0] map_wr_addr,
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output logic [31:0] map_wr_data,
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output logic [3:0] map_wr_be,
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input logic cpu_irq,
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output logic halt_o,
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output logic [31:0] pc_o,
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// Strict-mode trap reporting. `trap_o` rises the cycle the core
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// halts on an unsupported instruction; `trap_pc_o` / `trap_instr_o`
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// latch the offending fetch. All three stay stable after the halt.
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output logic trap_o,
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output logic [31:0] trap_pc_o,
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output logic [31:0] trap_instr_o,
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output logic ev_valid,
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output subsys_e ev_subsys,
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output event_e ev_event,
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output logic [63:0] ev_arg0,
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output logic [63:0] ev_arg1,
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output logic [63:0] ev_arg2,
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output logic [63:0] ev_arg3,
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output logic [31:0] ev_flags
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);
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// ------------------------------------------------------------------
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// Opcode / func / COP0 rs constants
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// ------------------------------------------------------------------
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localparam logic [5:0] OP_SPECIAL = 6'h00;
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localparam logic [5:0] OP_J = 6'h02;
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localparam logic [5:0] OP_BEQ = 6'h04;
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localparam logic [5:0] OP_BNE = 6'h05;
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localparam logic [5:0] OP_ADDIU = 6'h09;
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localparam logic [5:0] OP_ORI = 6'h0D;
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localparam logic [5:0] OP_LUI = 6'h0F;
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localparam logic [5:0] OP_COP0 = 6'h10;
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localparam logic [5:0] OP_LW = 6'h23;
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localparam logic [5:0] OP_SW = 6'h2B;
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localparam logic [5:0] FUNC_JR = 6'h08;
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localparam logic [5:0] FUNC_SYSCALL = 6'h0C;
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localparam logic [5:0] FUNC_RFE = 6'h10;
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localparam logic [4:0] COP0_RS_MF = 5'h00;
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localparam logic [4:0] COP0_RS_MT = 5'h04;
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localparam logic [4:0] COP0_RS_CO = 5'h10;
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localparam logic [4:0] COP0_REG_STATUS = 5'd12;
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localparam logic [4:0] COP0_REG_CAUSE = 5'd13;
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localparam logic [4:0] COP0_REG_EPC = 5'd14;
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// ------------------------------------------------------------------
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// FSM state
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// ------------------------------------------------------------------
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typedef enum logic [3:0] {
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S_IDLE = 4'd0,
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S_IFETCH_REQ = 4'd1,
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S_IFETCH_WAIT = 4'd2,
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S_EXECUTE = 4'd3,
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S_MEM_REQ = 4'd4,
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S_MEM_WAIT = 4'd5,
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S_MEM_WRITE = 4'd6,
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S_HALT = 4'd7
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} state_e;
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state_e state;
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// Architectural state
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logic [31:0] pc;
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logic [31:0] instr;
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logic [31:0] regfile [0:31];
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// Branch delay-slot tracking
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logic branch_pending;
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logic [31:0] branch_target;
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logic instr_in_delay_slot;
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// COP0 — Status (IE/KU triple stack + IM)
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logic status_iec, status_iep, status_ieo;
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logic status_kuc, status_kup, status_kuo;
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logic [7:0] status_im;
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// COP0 — Cause / EPC
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logic [4:0] cause_exc_code;
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logic [7:0] cause_ip_sw; // software-writable pending bits (IP[1:0])
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logic [31:0] epc;
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// Combinational composition of IP. IP[2] mirrors cpu_irq directly;
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// higher sources are not wired in the current scope.
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logic [7:0] cause_ip;
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always_comb begin
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cause_ip = 8'd0;
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cause_ip[1:0] = cause_ip_sw[1:0];
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cause_ip[2] = cpu_irq;
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end
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// Composed Status word (for MFC0) and Cause word (for MFC0)
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logic [31:0] status_word;
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logic [31:0] cause_word;
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always_comb begin
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status_word = 32'd0;
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status_word[0] = status_iec;
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status_word[1] = status_kuc;
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status_word[2] = status_iep;
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status_word[3] = status_kup;
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status_word[4] = status_ieo;
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status_word[5] = status_kuo;
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status_word[15:8] = status_im;
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cause_word = 32'd0;
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cause_word[6:2] = cause_exc_code;
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cause_word[15:8] = cause_ip;
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end
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// ------------------------------------------------------------------
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// Decode — combinational extraction from `instr`
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// ------------------------------------------------------------------
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logic [5:0] opcode;
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logic [4:0] rs_idx;
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logic [4:0] rt_idx;
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logic [4:0] rd_idx;
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logic [5:0] func;
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logic [15:0] imm16;
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logic [25:0] imm26;
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logic [31:0] imm_sx;
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logic [31:0] imm_zx;
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logic [31:0] branch_offset;
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logic [31:0] branch_tgt;
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logic [31:0] j_tgt;
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logic [31:0] rs_val;
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logic [31:0] rt_val;
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logic [31:0] ea;
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assign opcode = instr[31:26];
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assign rs_idx = instr[25:21];
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assign rt_idx = instr[20:16];
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assign rd_idx = instr[15:11];
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assign imm16 = instr[15:0];
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assign imm26 = instr[25:0];
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assign func = instr[5:0];
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assign imm_sx = {{16{imm16[15]}}, imm16};
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assign imm_zx = {16'd0, imm16};
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assign branch_offset = {{14{imm16[15]}}, imm16, 2'b00};
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assign branch_tgt = pc + 32'd4 + branch_offset;
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assign j_tgt = {pc[31:28], imm26, 2'b00};
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assign rs_val = (rs_idx == 5'd0) ? 32'd0 : regfile[rs_idx];
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assign rt_val = (rt_idx == 5'd0) ? 32'd0 : regfile[rt_idx];
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assign ea = rs_val + imm_sx;
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// Instruction classification
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logic is_special, is_syscall, is_jr;
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logic is_cop0, is_mfc0, is_mtc0, is_rfe;
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logic is_nop_class;
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logic is_lui, is_ori, is_addiu, is_lw, is_sw, is_beq, is_bne, is_j;
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logic is_branch, is_jump;
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logic branch_taken;
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logic is_taken_branch_or_jump;
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assign is_special = (opcode == OP_SPECIAL);
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assign is_syscall = is_special && (func == FUNC_SYSCALL);
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assign is_jr = is_special && (func == FUNC_JR);
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assign is_cop0 = (opcode == OP_COP0);
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assign is_mfc0 = is_cop0 && (rs_idx == COP0_RS_MF);
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assign is_mtc0 = is_cop0 && (rs_idx == COP0_RS_MT);
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assign is_rfe = is_cop0 && (rs_idx == COP0_RS_CO) && (func == FUNC_RFE);
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assign is_lui = (opcode == OP_LUI);
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assign is_ori = (opcode == OP_ORI);
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assign is_addiu = (opcode == OP_ADDIU);
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assign is_lw = (opcode == OP_LW);
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assign is_sw = (opcode == OP_SW);
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assign is_beq = (opcode == OP_BEQ);
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assign is_bne = (opcode == OP_BNE);
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assign is_j = (opcode == OP_J);
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assign is_branch = is_beq || is_bne;
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assign is_jump = is_j || is_jr;
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assign branch_taken = (is_beq && (rs_val == rt_val)) ||
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(is_bne && (rs_val != rt_val));
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assign is_taken_branch_or_jump = branch_taken || is_jump;
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// "NOP class" = anything we don't actively decode. In lenient mode
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// these retire as a NOP; in strict mode the core halts on them
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// (see `is_unsupported` / `strict_trap` below).
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assign is_nop_class = (is_special && !is_syscall && !is_jr)
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|| (is_cop0 && !is_mfc0 && !is_mtc0 && !is_rfe)
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|| (!is_special && !is_cop0
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&& !is_lui && !is_ori && !is_addiu
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&& !is_lw && !is_sw && !is_beq && !is_bne
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&& !is_j);
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// The canonical NOP is the all-zero instruction word
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// (SLL $0,$0,0). It is always treated as a NOP even in strict mode
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// so the bios_rom_stub default NOP sled doesn't look like a field
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// of traps.
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logic is_nop_instr;
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logic is_unsupported;
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logic strict_trap;
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assign is_nop_instr = (instr == 32'd0);
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assign is_unsupported = is_nop_class && !is_nop_instr;
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assign strict_trap = STRICT_UNSUPPORTED && is_unsupported;
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// ALU writeback value (for LUI/ORI/ADDIU)
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logic [31:0] alu_wb;
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always_comb begin
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if (is_lui) alu_wb = {imm16, 16'd0};
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else if (is_ori) alu_wb = rs_val | imm_zx;
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else if (is_addiu) alu_wb = rs_val + imm_sx;
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else alu_wb = 32'd0;
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end
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// MFC0 source value (selected by rd_idx)
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logic [31:0] cop0_read_val;
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always_comb begin
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unique case (rd_idx)
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COP0_REG_STATUS: cop0_read_val = status_word;
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COP0_REG_CAUSE: cop0_read_val = cause_word;
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COP0_REG_EPC: cop0_read_val = epc;
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default: cop0_read_val = 32'd0;
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endcase
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end
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// Taken-branch / jump target selection
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logic [31:0] taken_target;
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always_comb begin
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if (is_jr) taken_target = rs_val;
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else if (is_j) taken_target = j_tgt;
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else taken_target = branch_tgt;
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end
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// ------------------------------------------------------------------
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// Trace book-keeping (captured at retire)
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// ------------------------------------------------------------------
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logic [31:0] retired_pc;
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logic [31:0] retired_instr;
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logic [31:0] retired_arg2;
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logic [31:0] retired_arg3;
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logic retired_flag_write;
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logic retired_flag_read;
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logic retired_flag_branch;
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logic retired_flag_halt;
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logic retired_flag_in_delay;
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logic retired_flag_except;
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logic retired_flag_rfe;
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logic retired_flag_trap;
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logic retire_pulse;
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// ------------------------------------------------------------------
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// Map-port drive (combinational on state)
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// ------------------------------------------------------------------
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always_comb begin
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map_rd_en = 1'b0;
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map_rd_addr = 32'd0;
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map_wr_en = 1'b0;
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map_wr_addr = 32'd0;
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map_wr_data = 32'd0;
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map_wr_be = 4'd0;
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case (state)
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S_IFETCH_REQ: begin
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map_rd_en = 1'b1;
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map_rd_addr = pc;
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end
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S_MEM_REQ: begin
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map_rd_en = 1'b1;
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map_rd_addr = ea;
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end
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S_MEM_WRITE: begin
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map_wr_en = 1'b1;
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map_wr_addr = ea;
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map_wr_data = rt_val;
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map_wr_be = 4'b1111;
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end
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default: ;
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endcase
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end
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// ------------------------------------------------------------------
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// Retire helper — applies pc advance, branch queuing, and
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// exception entry at a clean instruction boundary.
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//
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// Inputs (implicit from decoded state):
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// - is_taken_branch_or_jump, taken_target
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// - branch_pending (current, pre-advance)
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// - branch_target (the pending target if any)
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// - Status / Cause state for exception gating
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//
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// Outputs (all registered on this clock edge):
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// - pc, branch_pending, branch_target
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// - epc, status/cause on exception
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// - retired_flag_except set when exception fires
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// ------------------------------------------------------------------
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task automatic retire_advance;
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logic [31:0] next_pc;
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logic new_branch_pending;
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logic [31:0] new_branch_target;
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logic irq_pending_masked;
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logic exception_now;
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next_pc = branch_pending ? branch_target : pc + 32'd4;
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new_branch_pending = is_taken_branch_or_jump;
|
|
new_branch_target = taken_target;
|
|
|
|
irq_pending_masked = |(cause_ip & status_im);
|
|
exception_now = !new_branch_pending
|
|
&& status_iec
|
|
&& irq_pending_masked;
|
|
|
|
if (exception_now) begin
|
|
epc <= next_pc;
|
|
cause_exc_code <= 5'h00; // Int exception code
|
|
status_ieo <= status_iep;
|
|
status_iep <= status_iec;
|
|
status_iec <= 1'b0;
|
|
status_kuo <= status_kup;
|
|
status_kup <= status_kuc;
|
|
status_kuc <= 1'b0;
|
|
pc <= EXC_VECTOR;
|
|
branch_pending <= 1'b0;
|
|
retired_flag_except <= 1'b1;
|
|
end else begin
|
|
pc <= next_pc;
|
|
branch_pending <= new_branch_pending;
|
|
if (new_branch_pending) branch_target <= new_branch_target;
|
|
retired_flag_except <= 1'b0;
|
|
end
|
|
endtask
|
|
|
|
// ------------------------------------------------------------------
|
|
// Main FSM
|
|
// ------------------------------------------------------------------
|
|
|
|
always_ff @(posedge clk) begin
|
|
if (!rst_n) begin
|
|
state <= S_IDLE;
|
|
pc <= PC_RESET;
|
|
instr <= 32'd0;
|
|
branch_pending <= 1'b0;
|
|
branch_target <= 32'd0;
|
|
instr_in_delay_slot <= 1'b0;
|
|
|
|
// COP0 reset state: interrupts disabled, mask cleared.
|
|
status_iec <= 1'b0;
|
|
status_iep <= 1'b0;
|
|
status_ieo <= 1'b0;
|
|
status_kuc <= 1'b0;
|
|
status_kup <= 1'b0;
|
|
status_kuo <= 1'b0;
|
|
status_im <= 8'd0;
|
|
cause_exc_code <= 5'd0;
|
|
cause_ip_sw <= 8'd0;
|
|
epc <= 32'd0;
|
|
|
|
retire_pulse <= 1'b0;
|
|
retired_pc <= 32'd0;
|
|
retired_instr <= 32'd0;
|
|
retired_arg2 <= 32'd0;
|
|
retired_arg3 <= 32'd0;
|
|
retired_flag_write <= 1'b0;
|
|
retired_flag_read <= 1'b0;
|
|
retired_flag_branch <= 1'b0;
|
|
retired_flag_halt <= 1'b0;
|
|
retired_flag_in_delay <= 1'b0;
|
|
retired_flag_except <= 1'b0;
|
|
retired_flag_rfe <= 1'b0;
|
|
retired_flag_trap <= 1'b0;
|
|
|
|
trap_o <= 1'b0;
|
|
trap_pc_o <= 32'd0;
|
|
trap_instr_o <= 32'd0;
|
|
|
|
for (int i = 0; i < 32; i++) regfile[i] <= 32'd0;
|
|
end else begin
|
|
retire_pulse <= 1'b0;
|
|
|
|
case (state)
|
|
S_IDLE: begin
|
|
if (go_i) state <= S_IFETCH_REQ;
|
|
end
|
|
|
|
S_IFETCH_REQ: state <= S_IFETCH_WAIT;
|
|
|
|
S_IFETCH_WAIT: begin
|
|
if (map_rd_valid) begin
|
|
instr <= map_rd_data;
|
|
instr_in_delay_slot <= branch_pending;
|
|
state <= S_EXECUTE;
|
|
end
|
|
end
|
|
|
|
S_EXECUTE: begin
|
|
// Defaults for retire bookkeeping
|
|
retired_pc <= pc;
|
|
retired_instr <= instr;
|
|
retired_arg2 <= 32'd0;
|
|
retired_arg3 <= 32'd0;
|
|
retired_flag_write <= 1'b0;
|
|
retired_flag_read <= 1'b0;
|
|
retired_flag_branch <= is_taken_branch_or_jump;
|
|
retired_flag_halt <= 1'b0;
|
|
retired_flag_in_delay <= instr_in_delay_slot;
|
|
retired_flag_except <= 1'b0;
|
|
retired_flag_rfe <= 1'b0;
|
|
retired_flag_trap <= 1'b0;
|
|
|
|
if (is_syscall) begin
|
|
// SYSCALL halts the core unconditionally; no
|
|
// exception vectoring in this scope.
|
|
retired_flag_halt <= 1'b1;
|
|
retire_pulse <= 1'b1;
|
|
state <= S_HALT;
|
|
end else if (strict_trap) begin
|
|
// Unsupported instruction under strict mode.
|
|
// Halt and latch the offending fetch; no pc
|
|
// advance, no regfile write, no COP0 side
|
|
// effect. Trap output stays asserted for the
|
|
// TB to inspect after halt_o rises.
|
|
retired_flag_trap <= 1'b1;
|
|
retire_pulse <= 1'b1;
|
|
trap_o <= 1'b1;
|
|
trap_pc_o <= pc;
|
|
trap_instr_o <= instr;
|
|
state <= S_HALT;
|
|
end else if (is_lw) begin
|
|
state <= S_MEM_REQ;
|
|
end else if (is_sw) begin
|
|
state <= S_MEM_WRITE;
|
|
end else begin
|
|
// ALU / branch / COP0 / NOP: retire in this
|
|
// cycle. Handle per-op writebacks and COP0
|
|
// side effects, then advance pc.
|
|
|
|
if ((is_lui || is_ori || is_addiu) && (rt_idx != 5'd0))
|
|
regfile[rt_idx] <= alu_wb;
|
|
|
|
if (is_mfc0 && (rt_idx != 5'd0))
|
|
regfile[rt_idx] <= cop0_read_val;
|
|
|
|
if (is_mtc0) begin
|
|
unique case (rd_idx)
|
|
COP0_REG_STATUS: begin
|
|
status_iec <= rt_val[0];
|
|
status_kuc <= rt_val[1];
|
|
status_iep <= rt_val[2];
|
|
status_kup <= rt_val[3];
|
|
status_ieo <= rt_val[4];
|
|
status_kuo <= rt_val[5];
|
|
status_im <= rt_val[15:8];
|
|
end
|
|
COP0_REG_CAUSE: begin
|
|
// Only the software IP[1:0] bits
|
|
// are writable; ExcCode is normally
|
|
// written by the core on exception
|
|
// entry, but allow SW override too
|
|
// since the minimal scope doesn't
|
|
// dispatch on ExcCode.
|
|
cause_exc_code <= rt_val[6:2];
|
|
cause_ip_sw[1:0] <= rt_val[9:8];
|
|
end
|
|
COP0_REG_EPC: epc <= rt_val;
|
|
default: ;
|
|
endcase
|
|
end
|
|
|
|
if (is_rfe) begin
|
|
status_iec <= status_iep;
|
|
status_iep <= status_ieo;
|
|
status_kuc <= status_kup;
|
|
status_kup <= status_kuo;
|
|
retired_flag_rfe <= 1'b1;
|
|
end
|
|
|
|
// Trace payload for ALU / branch / COP0 / NOP
|
|
if (is_mfc0) begin
|
|
retired_arg2 <= {27'd0, rd_idx};
|
|
retired_arg3 <= cop0_read_val;
|
|
end else if (is_mtc0) begin
|
|
retired_arg2 <= {27'd0, rd_idx};
|
|
retired_arg3 <= rt_val;
|
|
end else if (is_taken_branch_or_jump) begin
|
|
retired_arg2 <= taken_target;
|
|
retired_arg3 <= 32'd0;
|
|
end else if (is_lui || is_ori || is_addiu) begin
|
|
retired_arg3 <= alu_wb;
|
|
end
|
|
|
|
retire_pulse <= 1'b1;
|
|
retire_advance();
|
|
state <= S_IFETCH_REQ;
|
|
end
|
|
end
|
|
|
|
S_MEM_REQ: state <= S_MEM_WAIT;
|
|
|
|
S_MEM_WAIT: begin
|
|
if (map_rd_valid) begin
|
|
if (rt_idx != 5'd0) regfile[rt_idx] <= map_rd_data;
|
|
|
|
retired_pc <= pc;
|
|
retired_instr <= instr;
|
|
retired_arg2 <= ea;
|
|
retired_arg3 <= map_rd_data;
|
|
retired_flag_write <= 1'b0;
|
|
retired_flag_read <= 1'b1;
|
|
retired_flag_branch <= 1'b0;
|
|
retired_flag_halt <= 1'b0;
|
|
retired_flag_in_delay <= instr_in_delay_slot;
|
|
retired_flag_rfe <= 1'b0;
|
|
retire_pulse <= 1'b1;
|
|
|
|
retire_advance();
|
|
state <= S_IFETCH_REQ;
|
|
end
|
|
end
|
|
|
|
S_MEM_WRITE: begin
|
|
retired_pc <= pc;
|
|
retired_instr <= instr;
|
|
retired_arg2 <= ea;
|
|
retired_arg3 <= rt_val;
|
|
retired_flag_write <= 1'b1;
|
|
retired_flag_read <= 1'b0;
|
|
retired_flag_branch <= 1'b0;
|
|
retired_flag_halt <= 1'b0;
|
|
retired_flag_in_delay <= instr_in_delay_slot;
|
|
retired_flag_rfe <= 1'b0;
|
|
retire_pulse <= 1'b1;
|
|
|
|
retire_advance();
|
|
state <= S_IFETCH_REQ;
|
|
end
|
|
|
|
S_HALT: state <= S_HALT;
|
|
|
|
default: state <= S_IDLE;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
assign halt_o = (state == S_HALT);
|
|
assign pc_o = pc;
|
|
|
|
// ------------------------------------------------------------------
|
|
// Trace emission — one event per retire
|
|
// ------------------------------------------------------------------
|
|
|
|
always_ff @(posedge clk) begin
|
|
if (!rst_n) begin
|
|
ev_valid <= 1'b0;
|
|
ev_subsys <= SUBSYS_IOP;
|
|
ev_event <= EV_IFETCH;
|
|
ev_arg0 <= 64'd0;
|
|
ev_arg1 <= 64'd0;
|
|
ev_arg2 <= 64'd0;
|
|
ev_arg3 <= 64'd0;
|
|
ev_flags <= 32'd0;
|
|
end else if (retire_pulse) begin
|
|
ev_valid <= 1'b1;
|
|
ev_subsys <= SUBSYS_IOP;
|
|
ev_event <= EV_IFETCH;
|
|
ev_arg0 <= {32'd0, retired_pc};
|
|
ev_arg1 <= {32'd0, retired_instr};
|
|
ev_arg2 <= {32'd0, retired_arg2};
|
|
ev_arg3 <= {32'd0, retired_arg3};
|
|
ev_flags <= {24'd0,
|
|
retired_flag_trap,
|
|
retired_flag_rfe,
|
|
retired_flag_except,
|
|
retired_flag_in_delay,
|
|
retired_flag_halt,
|
|
retired_flag_branch,
|
|
retired_flag_read,
|
|
retired_flag_write};
|
|
end else begin
|
|
ev_valid <= 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule : iop_core_stub
|