thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
197 lines
10 KiB
Systemverilog
197 lines
10 KiB
Systemverilog
// ============================================================================
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// gs_texture_cache.sv (Ch322 — PREFILLED texture cache, correctness-first)
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//
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// Proves texture bytes can live in FPGA-private LPDDR4B and be consumed by the
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// GS sampler through an on-chip RAM at the EXISTING 1-cycle texel latency.
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//
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// This is a PREFILLED cache, NOT a demand cache. The whole known texture is
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// filled from LPDDR into an on-chip RAM ONCE, before rendering (mirroring the
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// Ch321 line-buffer trick: warm a bounded buffer, then serve at native latency).
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// Every sampler read is therefore a HIT at 1-cycle latency — the nearest-path
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// sampler's fixed-latency contract (gs_texture_unit valid_pipe, RD_LATENCY=1) is
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// preserved with ZERO pipeline/stall surgery. Demand miss/stall is explicitly
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// DEFERRED to a later chapter (it would be a raster-walker pipeline redesign).
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//
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// Two clock domains (same split as gs_lpddr_scanout_lb):
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// axi_clk (emif_clk) — fill FSM: single-beat 256-bit reads (arlen=0, the
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// only read pattern proven on this EMIF) from LPDDR.
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// sample_clk (design) — the sampler's texel read port; 1-cycle registered,
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// byte-identical timing to the vram_bram_stub read2.
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//
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// The fill is one-shot before raster, so the on-chip RAM is static when the
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// sampler reads it (write side idle) — a plain dual-clock simple-dual-port RAM,
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// no read/write CDC hazard. `fill_done` is 2-FF synced into sample_clk so the
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// read mux only goes live after the texture is fully resident.
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// ============================================================================
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`timescale 1ns/1ps
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module gs_texture_cache #(
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parameter [29:0] LPDDR_TEX_BASE = 30'd0, // byte base of the texture in LPDDR4B
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parameter [31:0] TEX_VRAM_BASE = 32'd2048,// VRAM byte base the sampler addresses (TBP0*256)
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parameter int TEX_BYTES = 256, // texture size in bytes (8x8 PSMCT32 = 256)
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parameter int N_BEATS = 8 // TEX_BYTES / 32
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)(
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// ---- AXI read clock domain (emif_clk) — fill side ----
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input logic axi_clk,
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input logic axi_rst_n,
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input logic fill_start, // TOGGLE (bridge domain, CDC-synced): each edge (re)fills
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output logic fill_done, // texture fully resident (until the next fill arm)
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output logic [31:0] fill_beats, // beats completed (cumulative)
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output logic [31:0] fill_bytes, // bytes filled (cumulative)
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output logic [31:0] rd_errs, // non-OKAY read responses (cumulative)
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output logic [31:0] fill_crc, // Ch352 — sum32 of EVERY 32-bit word actually written into tex_mem. The
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// host compares this to the file's sum32 to PROVE tex_mem integrity on
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// silicon (the LPDDR readback only proves LPDDR, not the cache contents).
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// ---- AXI4 read channel to the EMIF user port (axi_clk, 256-bit) ----
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output logic [29:0] araddr,
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output logic [1:0] arburst,
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output logic [6:0] arid,
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output logic [7:0] arlen,
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output logic [2:0] arsize,
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output logic arvalid,
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input logic arready,
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input logic [255:0] rdata,
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input logic [1:0] rresp,
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input logic rlast,
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input logic rvalid,
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output logic rready,
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// ---- sampler clock domain (design_clk) — texel read port ----
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input logic sample_clk,
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input logic tex_rd_en, // sampler issues a texel read this cycle
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input logic [31:0] tex_rd_addr, // VRAM byte address (TEX_VRAM_BASE + offset)
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output logic [31:0] tex_rd_data, // 1-cycle REGISTERED texel word (matches read2)
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output logic tex_ready // fill_done synced into sample_clk (mux gate)
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);
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localparam int TEX_WORDS = TEX_BYTES/4; // 32-bit words in the cache
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localparam int WIDX_BITS = (TEX_WORDS <= 1) ? 1 : $clog2(TEX_WORDS);
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localparam int BIDX_BITS = (N_BEATS <= 1) ? 1 : $clog2(N_BEATS);
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assign arburst = 2'b01; // INCR
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assign arid = 7'd4; // distinct id: writer=0, probe=1, frame-cache=2, line-buf=3, tex-fill=4
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assign arlen = 8'd0; // SINGLE-BEAT (the only AXI read pattern proven on this EMIF)
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assign arsize = 3'b101; // 32 bytes
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// On-chip texture RAM: written by the fill FSM (axi_clk), read by the sampler
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// (sample_clk). One-shot warm fill => static during reads => no CDC hazard.
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//
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// One ordinary 32-bit simple-dual-port RAM. History of cache geometry vs Quartus Place:
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// flat 8-write array -> exploded to flops (707k ALUT)
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// 8x 8192x32 banks -> width fragmentation, 344/358, 9h Place thrash
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// 1x 8192x256 RAM -> count OK (320/358) but one ~104-M20K macro too WIDE -> Place 40min+, no QDB
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// 2x 8192x128 halves -> still rigid, Place 50min+ no progress
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// 4x 8192x64 banks -> 328/358; Place still stalled with ample RAM after read2 was removed.
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// 1x 65536x32 (HERE) -> latch each AXI beat, drain 8 lanes over 8 axi_clk cycles.
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// Serializing the fill removes the multi-bank/multi-write geometry while preserving the sampler's
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// one-cycle registered 32-bit read. The one-shot fill is still tiny compared with board startup.
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(* ramstyle = "M20K" *) logic [31:0] tex_mem [0:TEX_WORDS-1];
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// ================= fill side (axi_clk) =================
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typedef enum logic [2:0] { F_IDLE, F_AR, F_R, F_DRAIN, F_DONE } fstate_t;
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fstate_t fst;
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logic [$clog2(N_BEATS):0] beat; // 0..N_BEATS
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logic [255:0] fill_data_q;
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logic [2:0] fill_lane;
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logic [WIDX_BITS-1:0] fill_word_base;
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wire [WIDX_BITS-1:0] fill_word_idx = fill_word_base + WIDX_BITS'(fill_lane);
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// fill_start is an EDGE/TOGGLE (bridge toggles it on each arm), CDC-synced here so the
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// cache is RE-FILLABLE: each arm reloads the texture (lets the HPS re-stage a different
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// texture without a board reset). 3-FF sync + edge-detect, like the read/write probes.
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logic [2:0] fs_sync;
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wire fs_edge = (fs_sync[2] != fs_sync[1]);
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always_ff @(posedge axi_clk) begin
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if (!axi_rst_n) begin
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fst <= F_IDLE; araddr <= '0; arvalid <= 1'b0; rready <= 1'b0;
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beat <= '0; fill_done <= 1'b0; fill_beats <= 32'd0; fill_bytes <= 32'd0;
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rd_errs <= 32'd0; fs_sync <= 3'd0; fill_data_q <= '0;
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fill_lane <= 3'd0; fill_word_base <= '0; fill_crc <= 32'd0;
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end else begin
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fs_sync <= {fs_sync[1:0], fill_start};
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case (fst)
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F_IDLE: begin
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if (fs_edge) begin
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araddr <= LPDDR_TEX_BASE;
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beat <= '0;
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fill_done <= 1'b0; // re-arm: drop ready until reloaded
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fill_beats <= 32'd0;
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fill_bytes <= 32'd0;
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rd_errs <= 32'd0;
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fill_crc <= 32'd0; // Ch352 — restart the tex_mem integrity sum for this fill
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arvalid <= 1'b1;
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fst <= F_AR;
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end
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end
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F_AR: begin
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if (arready) begin
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arvalid <= 1'b0;
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rready <= 1'b1;
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fst <= F_R;
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end
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end
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F_R: begin
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if (rvalid) begin
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// Capture the AXI beat, then issue one M20K-native 32-bit write per cycle.
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fill_data_q <= rdata;
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fill_lane <= 3'd0;
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fill_word_base <= {beat[BIDX_BITS-1:0], 3'b000};
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if (rresp != 2'b00) rd_errs <= rd_errs + 32'd1;
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rready <= 1'b0;
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fst <= F_DRAIN;
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end
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end
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F_DRAIN: begin
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tex_mem[fill_word_idx] <= fill_data_q[fill_lane*32 +: 32];
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fill_crc <= fill_crc + fill_data_q[fill_lane*32 +: 32]; // sum32 over the words written
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if (fill_lane == 3'd7) begin
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fill_beats <= fill_beats + 32'd1;
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fill_bytes <= fill_bytes + 32'd32;
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if (beat == N_BEATS-1) begin
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fill_done <= 1'b1;
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fst <= F_DONE;
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end else begin
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beat <= beat + 1'b1;
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araddr <= araddr + 30'd32; // next single-beat read
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arvalid <= 1'b1;
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fst <= F_AR;
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end
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end else begin
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fill_lane <= fill_lane + 3'd1;
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end
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end
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F_DONE: begin
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// resident until the next arm. A fresh fill_start edge re-loads the
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// texture (e.g. HPS re-stages a different one) — start a new fill.
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if (fs_edge) begin
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araddr <= LPDDR_TEX_BASE;
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beat <= '0;
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fill_done <= 1'b0;
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fill_beats <= 32'd0;
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fill_bytes <= 32'd0;
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rd_errs <= 32'd0;
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fill_crc <= 32'd0; // Ch352 — restart the tex_mem integrity sum for this fill
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arvalid <= 1'b1;
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fst <= F_AR;
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end
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end
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default: fst <= F_IDLE;
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endcase
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end
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end
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// ================= sampler side (sample_clk) =================
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// 1-cycle REGISTERED read, identical timing to vram_bram_stub.read2:
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// present (tex_rd_addr) when tex_rd_en, data lands next cycle.
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wire [31:0] word_off = (tex_rd_addr - TEX_VRAM_BASE) >> 2;
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wire [WIDX_BITS-1:0] rd_word = word_off[WIDX_BITS-1:0];
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always_ff @(posedge sample_clk) begin
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if (tex_rd_en) tex_rd_data <= tex_mem[rd_word];
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end
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// fill_done -> sample_clk (2-FF). The read mux only goes live once warm.
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logic [1:0] done_sync;
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always_ff @(posedge sample_clk) done_sync <= {done_sync[0], fill_done};
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assign tex_ready = done_sync[1];
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endmodule
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