thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
102 lines
4.1 KiB
XML
102 lines
4.1 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<simPackage>
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<file
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path="altera_merlin_master_translator_193/sim/peripheral_subsys_altera_merlin_master_translator_193_lgcew2q.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_master_translator_193" />
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<file
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path="altera_merlin_slave_translator_191/sim/peripheral_subsys_altera_merlin_slave_translator_191_xg7rzxi.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_slave_translator_191" />
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<file
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path="altera_merlin_master_agent_1940/sim/peripheral_subsys_altera_merlin_master_agent_1940_r3ep6da.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_master_agent_1940" />
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<file
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path="altera_merlin_slave_agent_1930/sim/peripheral_subsys_altera_merlin_slave_agent_1930_jxauz3i.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_slave_agent_1930" />
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<file
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path="altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_slave_agent_1930" />
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<file
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path="altera_avalon_sc_fifo_1932/sim/peripheral_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v"
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type="VERILOG"
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library="altera_avalon_sc_fifo_1932" />
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<file
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path="altera_merlin_router_1921/sim/peripheral_subsys_altera_merlin_router_1921_iesulwy.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_router_1921" />
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<file
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path="altera_merlin_router_1921/sim/peripheral_subsys_altera_merlin_router_1921_wxl7gvy.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_router_1921" />
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<file
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path="altera_merlin_traffic_limiter_1922/sim/peripheral_subsys_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1922_25262sa.v"
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type="VERILOG"
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library="altera_merlin_traffic_limiter_1922"
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hasInlineConfiguration="true" />
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<file
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path="altera_merlin_traffic_limiter_1922/sim/altera_merlin_reorder_memory.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_traffic_limiter_1922" />
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<file
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path="altera_merlin_traffic_limiter_1922/sim/altera_avalon_st_pipeline_base.v"
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type="SYSTEM_VERILOG"
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library="altera_merlin_traffic_limiter_1922" />
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<file
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path="altera_merlin_traffic_limiter_1922/sim/peripheral_subsys_altera_merlin_traffic_limiter_1922_y23fybq.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_traffic_limiter_1922" />
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<file
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path="altera_merlin_demultiplexer_1921/sim/peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_demultiplexer_1921" />
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<file
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path="altera_merlin_multiplexer_1922/sim/peripheral_subsys_altera_merlin_multiplexer_1922_ufdjdoq.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_multiplexer_1922" />
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<file
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path="altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_multiplexer_1922" />
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<file
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path="altera_merlin_demultiplexer_1921/sim/peripheral_subsys_altera_merlin_demultiplexer_1921_4xqokvi.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_demultiplexer_1921" />
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<file
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path="altera_merlin_multiplexer_1922/sim/peripheral_subsys_altera_merlin_multiplexer_1922_cbyifnq.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_multiplexer_1922" />
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<file
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path="altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"
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type="SYSTEM_VERILOG"
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library="altera_merlin_multiplexer_1922" />
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<file
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path="altera_mm_interconnect_1920/sim/peripheral_subsys_altera_mm_interconnect_1920_553jo7i.v"
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type="VERILOG"
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library="altera_mm_interconnect_1920"
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hasInlineConfiguration="true" />
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<file
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path="altera_reset_controller_1924/sim/altera_reset_controller.v"
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type="VERILOG"
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library="altera_reset_controller_1924" />
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<file
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path="altera_reset_controller_1924/sim/altera_reset_synchronizer.v"
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type="VERILOG"
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library="altera_reset_controller_1924" />
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<file
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path="altera_reset_controller_1924/sim/altera_reset_controller.sdc"
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type="SDC_ENTITY"
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library="altera_reset_controller_1924" />
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<file
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path="sim/peripheral_subsys.v"
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type="VERILOG"
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library="peripheral_subsys"
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hasInlineConfiguration="true" />
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<topLevel name="peripheral_subsys.peripheral_subsys" />
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<deviceFamily name="agilex5" />
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<device name="A5EB013BB23BE4SCS" />
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</simPackage>
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