thejayman77
dd7ca4fb8e
Cuts the lone remaining EMIF setup fail (-0.016 ns, -0.259 skew): the combinational EMIF gen_p2c_ff -> wr_arb s2_wready -> gs_lpddr_z_rmw next-state (st, endpoint labelled S_FILL_R via the shared encoded state register). New gs_axi_w_regbuf: fully-registered one-entry W buffer (Option B per Codex). - u_wready = !full ONLY (registered occupancy) -> EMIF WREADY never reaches the Z FSM combinationally. NOT a fall-through skid (no !full-OR-d_wready term). - Buffers WDATA/WSTRB/WLAST; downstream held stable until accepted; exactly-once. - AW/B untouched; arbiter bready_q unchanged (still arms on real EMIF W handshake). - z_rmw may enter B-wait once the beat is buffered -- safe: EMIF cannot return B until the buffered beat reaches it. Single-beat writes -> the 1-beat/2-cycle buffer rate is far above the Z write rate (no new FIFO pressure). Wired in zc_emit between u_z W output (zi_*) and the z_w* ports. New file in sim Makefile RTL_SRCS + synth QSF (both). Focused tb_gs_axi_w_regbuf: exactly-once/order/ payload scoreboard + no-combinational-bypass check (u_wready===!full incl. full && d_wready) + downstream-stable check; standalone target + in make run. Texture-cache +0.016 paths NOT touched. No simulations or Quartus run. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
sim/tb — Testbenches
Per-subsystem SystemVerilog / Verilog testbenches.
Planned layout (created as each subsystem lands its first stub):
tb/memory/— memory map and arbitration tests.tb/dmac/— EE DMAC channel tests.tb/gif_gs/— GIF packet intake and GS register decode tests.tb/sif/— EE<->IOP mailbox/DMA tests.tb/ee/— EE core directed tests.tb/iop/— IOP core and IOP-DMA directed tests.tb/vif_vu/— VIF unpack and VU microprogram tests.
Rule: no testbench directory is created until the matching subsystem has a
contract in docs/contracts/ and a stub in rtl/.