thejayman77
ba74bbd5aa
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog TBs, fidelity attribution tooling. Functional baseline before removing the dead bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
369 lines
22 KiB
Systemverilog
369 lines
22 KiB
Systemverilog
// retroDE_ps2 — gs_lpddr_zc_emit (Ch357 — Z-then-color emit integration: request FIFO + persistent-Z RMW + color writer)
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//
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// Codex Ch357 integration constraints:
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// (1) Cross gs_clk->axi_clk with ONE async request FIFO carrying the COMPLETE fragment packet {XY, clamped Z, color,
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// masks, scene marker}. No raw level-bus CDC.
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// (2) Z decision FIRST; enqueue color ONLY on pass. A rejected fragment produces NO color write.
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// (3) Ordered end-of-scene marker through the SAME FIFO: on it, flush the dirty Z line, wait Z BRESP + all accepted color
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// BRESPs, then assert combined frame_drained.
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// (4) Z cache persists across scheduler epochs (texture rebind must not clear it) — handled by gs_lpddr_z_rmw (scene_flush
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// keeps the line valid+clean).
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// (5) Preclear/invalidate Z once at frame start (clear_start).
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// (6) LPDDR map (gs_lpddr_map_pkg): color 0x000000, Z 0x140000, tex 0x200000 — disjoint.
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//
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// Structure: the request async FIFO is the ONLY CDC. Everything downstream runs in axi_clk: the Z RMW (its own Z AXI
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// read+write master), and the reused gs_lpddr_axi_master COLOR writer (its gs_clk tied to axi_clk, so its internal CDC FIFO
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// is same-clock). A tiny in-order COLOR-ALIGN FIFO carries {coladdr,color} beside the Z pipeline so the pass decision lands
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// with the right pixel. Two AXI masters are exposed (z_* and c_*); the system arbitrates them onto the shared LPDDR port.
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module gs_lpddr_zc_emit #(
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parameter [31:0] COLBASE = 32'h0000_0000,
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parameter [31:0] ZBASE = 32'h0014_0000,
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parameter int FB_PXW = 256,
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parameter int FB_H = 210,
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parameter [15:0] Z_CLEAR = 16'h0000,
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parameter int REQ_DEPTH= 32,
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parameter int COL_DEPTH= 64
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) (
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// ---- gs_clk fragment/marker producer ----
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input logic gs_clk,
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input logic gs_rst_n,
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input logic enable,
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input logic g_valid,
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output logic g_ready,
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input logic [11:0] g_x,
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input logic [11:0] g_y,
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input logic [15:0] g_zq, // clamped Z (clamp16 done upstream)
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input logic g_zmsk,
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input logic g_ztest, // 1 = depth-test this fragment; 0 = always pass (non-Z draw)
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input logic [1:0] g_ztst, // GS TEST.ZTST: NEVER/ALWAYS/GEQUAL/GREATER
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input logic [31:0] g_color,
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input logic [16:0] g_alpha, // {ABE,A,B,C,D,FIX}, snapped at raster emit
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input logic [3:0] g_be, // FRAME.FBMSK-compressed byte enables
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input logic g_scene, // 1 = end-of-scene marker (x/y/z/color ignored)
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// ---- axi_clk ----
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input logic axi_clk,
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input logic axi_rst_n,
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input logic clear_start, // preclear Z once at frame start
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output logic clear_done,
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output logic frame_drained, // combined: color drained AND Z drained for the scene
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// ---- Z AXI master (read+write) ----
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output logic [31:0] z_araddr, output logic [7:0] z_arlen, output logic [2:0] z_arsize, output logic [1:0] z_arburst,
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output logic z_arvalid, input logic z_arready,
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input logic [255:0] z_rdata, input logic [1:0] z_rresp, input logic z_rlast, input logic z_rvalid, output logic z_rready,
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output logic [31:0] z_awaddr, output logic [7:0] z_awlen, output logic [2:0] z_awsize, output logic [1:0] z_awburst,
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output logic z_awvalid, input logic z_awready,
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output logic [255:0] z_wdata, output logic [31:0] z_wstrb, output logic z_wlast, output logic z_wvalid, input logic z_wready,
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input logic z_bvalid, output logic z_bready, input logic [1:0] z_bresp,
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// ---- Color AXI master (write only) ----
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output logic [31:0] c_awaddr, output logic [7:0] c_awlen, output logic [2:0] c_awsize, output logic [1:0] c_awburst,
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output logic c_awvalid, input logic c_awready,
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output logic [255:0] c_wdata, output logic [31:0] c_wstrb, output logic c_wlast, output logic c_wvalid, input logic c_wready,
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input logic c_bvalid, output logic c_bready, input logic [1:0] c_bresp,
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// ---- status ----
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output logic [31:0] z_beats_read, z_beats_written, c_beats_written, col_ovf, bresp_err,
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// Destination-color read AXI master. Inert for full-byte opaque writes;
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// ABE and partial FRAME.FBMSK writes both use it for destination RMW.
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output logic [31:0] d_araddr, output logic [7:0] d_arlen, output logic [2:0] d_arsize, output logic [1:0] d_arburst,
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output logic d_arvalid, input logic d_arready,
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input logic [255:0] d_rdata, input logic [1:0] d_rresp, input logic d_rlast, input logic d_rvalid, output logic d_rready,
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output logic idle
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);
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// ---------------- request async FIFO (the ONLY CDC) ----------------
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// X/Y have already been clipped to this framebuffer before reaching the
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// external ROP. Do not spend twelve FIFO bits on each coordinate: the
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// production 640x480 path needs only 10+9. Besides saving storage, this
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// keeps the deep request FIFO below the RAM-banking threshold that put a
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// bank mux on its 310 MHz registered-read path after ZTST was added.
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localparam int XW = (FB_PXW <= 1) ? 1 : $clog2(FB_PXW);
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localparam int YW = (FB_H <= 1) ? 1 : $clog2(FB_H);
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localparam int PW = 74 + XW + YW; // {scene,be,alpha,color,ztest,ztst,zmsk,zq,y[YW],x[XW]}
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localparam int Y_LSB = XW;
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localparam int ZQ_LSB = XW + YW;
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localparam int ZMSK_BIT = ZQ_LSB + 16;
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localparam int ZTST_LSB = ZMSK_BIT + 1;
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localparam int ZTEST_BIT = ZTST_LSB + 2;
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localparam int COLOR_LSB = ZTEST_BIT + 1;
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localparam int ALPHA_LSB = COLOR_LSB + 32;
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localparam int BE_LSB = ALPHA_LSB + 17;
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logic [PW-1:0] req_wdata, req_rdata; logic req_wfull, req_rempty, req_rd;
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assign req_wdata = {g_scene, g_be, g_alpha, g_color, g_ztest, g_ztst, g_zmsk,
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g_zq, g_y[YW-1:0], g_x[XW-1:0]};
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assign g_ready = enable && !req_wfull;
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// Ch439e — the measured f52 occupancy peak is 6,115, so 8K cannot be cut
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// without dropping fragments from the intentionally unthrottled producer.
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// Split that fixed capacity by both depth and width instead: each physical
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// address copy drives one quarter of the original deep/wide RAM tree.
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gs_async_fifo #(.WIDTH(PW), .DEPTH(REQ_DEPTH), .REGISTERED_READ(1'b1),
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.QUADRANT_READ(1'b1)) u_req (
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.wclk(gs_clk), .wrst_n(gs_rst_n), .wr(g_valid && g_ready), .wdata(req_wdata), .wfull(req_wfull),
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.rclk(axi_clk), .rrst_n(axi_rst_n), .rd(req_rd), .rdata(req_rdata), .rempty(req_rempty)
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);
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// REGISTERED request-HEAD stage. Ch406 makes the deep request FIFO read
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// synchronous: an accepted req_rd is followed by req_read_pending, which
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// captures the complete registered RAM output here one cycle later.
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// Ch421 keeps stage occupancy independent of packet contents: decoding the
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// RAM's scene bit directly into separate fragment/marker valid registers
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// was the complete post-Ch420 setup family. A single validity register is
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// driven only by req_read_pending; scene/type decode happens after the full
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// packet register boundary.
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logic req_stage_valid;
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logic req_read_pending;
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logic [PW-1:0] req_stage_packet;
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// Ch423 — packet DATA is intentionally unreset and lives outside the
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// async-reset control process. Keeping the lone unreset data register in
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// that process made Quartus fold axi_rst_n (the 4k-fanout EMIF-cal signal)
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// into its clock enable. Only req_stage_valid makes this payload
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// observable, so the local registered pending pulse is the complete and
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// sufficient capture enable.
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always_ff @(posedge axi_clk)
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if (req_read_pending) req_stage_packet <= req_rdata;
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wire [PW-2:0] req_stage_data = req_stage_packet[PW-2:0];
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wire req_stage_frag_valid = req_stage_valid && !req_stage_packet[PW-1];
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wire req_stage_marker_valid = req_stage_valid && req_stage_packet[PW-1];
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wire rq_scene = req_stage_marker_valid;
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wire [16:0] rq_alpha = req_stage_data[ALPHA_LSB +: 17];
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wire [3:0] rq_be = req_stage_data[BE_LSB +: 4];
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wire [31:0] rq_color = req_stage_data[COLOR_LSB +: 32];
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wire rq_ztest = req_stage_data[ZTEST_BIT];
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wire [1:0] rq_ztst = req_stage_data[ZTST_LSB +: 2];
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wire rq_zmsk = req_stage_data[ZMSK_BIT];
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wire [15:0] rq_zq = req_stage_data[ZQ_LSB +: 16];
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wire [11:0] rq_y = {{(12-YW){1'b0}}, req_stage_data[Y_LSB +: YW]};
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wire [11:0] rq_x = {{(12-XW){1'b0}}, req_stage_data[0 +: XW]};
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`ifndef SYNTHESIS
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initial begin
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if (XW > 12 || YW > 12)
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$fatal(1, "gs_lpddr_zc_emit framebuffer dimensions exceed 12-bit fragment coordinates");
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end
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`endif
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// ---------------- Z RMW (axi_clk) ----------------
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logic z_fvalid, z_fready, z_pvalid, z_pready, z_ppass, z_sflush, z_drained;
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logic [11:0] z_px, z_py; logic [15:0] z_pzq;
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gs_lpddr_z_rmw #(.ZBASE(ZBASE), .FB_PXW(FB_PXW), .FB_H(FB_H), .Z_CLEAR(Z_CLEAR)) u_z (
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.clk(axi_clk), .rst_n(axi_rst_n), .enable(enable), .clear_start(clear_start), .clear_done(clear_done),
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.scene_flush(z_sflush), .z_drained(z_drained),
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.f_valid(z_fvalid), .f_ready(z_fready), .f_x(rq_x), .f_y(rq_y), .f_z({16'd0, rq_zq}),
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.f_zmsk(rq_zmsk || !rq_ztest), .f_ztst(rq_ztest ? rq_ztst : 2'd1),
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.p_valid(z_pvalid), .p_ready(z_pready), .p_pass(z_ppass), .p_x(z_px), .p_y(z_py), .p_zq(z_pzq),
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.araddr(z_araddr), .arlen(z_arlen), .arsize(z_arsize), .arburst(z_arburst), .arvalid(z_arvalid), .arready(z_arready),
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.rdata(z_rdata), .rresp(z_rresp), .rlast(z_rlast), .rvalid(z_rvalid), .rready(z_rready),
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.awaddr(z_awaddr), .awlen(z_awlen), .awsize(z_awsize), .awburst(z_awburst), .awvalid(z_awvalid), .awready(z_awready),
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.wdata(z_wdata), .wstrb(z_wstrb), .wlast(z_wlast), .wvalid(z_wvalid), .wready(z_wready),
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.bvalid(z_bvalid), .bready(z_bready), .bresp(z_bresp),
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.beats_read(z_beats_read), .beats_written(z_beats_written), .bresp_err(bresp_err), .idle(z_idle)
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);
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// A fragment carries ztest: when ztest=0 it must ALWAYS pass. Feed the RMW a zmsk so it never writes Z for a
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// non-Z fragment, and force its zq to max so GEQUAL always passes. (All scheduler draws are ztest=1.)
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// (Handled at feed below via the always-pass override on the pass decision.)
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// ---------------- color-align FIFO (in-order {coladdr,color,ztest}) ----------------
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localparam int CAW = 86; // {ztest, be[3:0], alpha[16:0], coladdr[31:0], color[31:0]}
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localparam int CAPTR_W = $clog2(COL_DEPTH);
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logic [CAW-1:0] ca_mem [0:COL_DEPTH-1];
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logic [CAPTR_W:0] ca_head, ca_tail;
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logic ca_wr_q;
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logic [CAPTR_W-1:0] ca_waddr_q;
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logic [CAW-1:0] ca_wdata_q;
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wire ca_empty = (ca_head==ca_tail);
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// Power-of-two ring full test: same low address with opposite wrap bit.
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// This is equivalent to (tail-head)==COL_DEPTH while occupancy is bounded,
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// but removes the pointer subtract/carry chain from feed_ok -> ca_mem write
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// enable (the post-scanout fit's final -0.007 ns, two-endpoint family).
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wire ca_full = (ca_tail[CAPTR_W] != ca_head[CAPTR_W])
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&& (ca_tail[CAPTR_W-1:0] == ca_head[CAPTR_W-1:0]);
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wire [31:0] frag_coladdr = COLBASE + (((rq_y*FB_PXW) + rq_x) << 2);
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// Register the color-align RAM write port. Ch423 captures address/data
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// every cycle instead of enabling these wide DATA registers with feed_ok.
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// Their contents are observable only when the separately-reset ca_wr_q is
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// high, so this removes ca_tail->ca_full->feed_ok from 82 data-register
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// enables without changing the committed address/data/write-strobe tuple.
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// Nonblocking ordering makes the RAM consume the prior cycle's captured
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// tuple exactly when the prior feed_ok raised ca_wr_q.
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always_ff @(posedge axi_clk) begin
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ca_waddr_q <= ca_tail[CAPTR_W-1:0];
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ca_wdata_q <= {rq_ztest, rq_be, rq_alpha, frag_coladdr, rq_color};
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end
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always_ff @(posedge axi_clk)
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if (ca_wr_q) ca_mem[ca_waddr_q] <= ca_wdata_q;
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// ---------------- color writer (reused; gs_clk tied to axi_clk => internal FIFO is same-clock) ----------------
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logic col_px_emit; logic [31:0] col_px_addr; logic [31:0] col_px_pix32; logic col_flush, col_drained;
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logic col_px_ready; // Ch357 (Codex) — color-writer producer-backpressure ready (elastic stage can accept)
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// Ch357 (Codex) — ONE-ENTRY color output register. Registering the payload here breaks the ca_mem->barrel-insert
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// cone (the -0.98ns 310MHz path) AND holds the emit valid until u_c accepts it, so no pixel is dropped.
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logic col_out_valid; logic [31:0] col_out_addr; logic [31:0] col_out_color; logic [16:0] col_out_alpha; logic [3:0] col_out_be;
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logic blend_in_ready, blend_out_valid, blend_idle, col_writer_idle;
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logic blend_write_pending, blend_flush_issued, blend_drain_seen_low;
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wire blend_input_gate = !blend_write_pending;
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logic [31:0] blend_out_addr, blend_out_color;
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gs_lpddr_color_blend u_blend (
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.clk(axi_clk), .rst_n(axi_rst_n),
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.in_valid(col_out_valid && blend_input_gate), .in_ready(blend_in_ready), .in_addr(col_out_addr), .in_color(col_out_color), .in_alpha(col_out_alpha), .in_be(col_out_be),
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.out_valid(blend_out_valid), .out_ready(col_px_ready), .out_addr(blend_out_addr), .out_color(blend_out_color), .idle(blend_idle),
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.araddr(d_araddr), .arlen(d_arlen), .arsize(d_arsize), .arburst(d_arburst), .arvalid(d_arvalid), .arready(d_arready),
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.rdata(d_rdata), .rresp(d_rresp), .rlast(d_rlast), .rvalid(d_rvalid), .rready(d_rready)
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);
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logic col_commit; logic [1:0] commit_sr;
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// one-shot ctrl_commit toggle after reset to latch fb_base=COLBASE
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always_ff @(posedge axi_clk or negedge axi_rst_n)
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if (!axi_rst_n) begin commit_sr<=2'b00; col_commit<=1'b0; end
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else begin commit_sr<={commit_sr[0],1'b1}; if (commit_sr==2'b01) col_commit<=~col_commit; end
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gs_lpddr_axi_master #(.FIFO_DEPTH(COL_DEPTH), .PIX_BYTES(4), .ELASTIC_BACKPRESSURE(1'b1)) u_c (
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.gs_clk(axi_clk), .gs_rst_n(axi_rst_n), .enable(enable),
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.arm(enable), .canary(1'b0), .fb_base(COLBASE), .ctrl_commit(col_commit),
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.px_emit(col_px_emit), .px_addr(col_px_addr), .px_pix32(col_px_pix32), .px_ready(col_px_ready), .flush(col_flush),
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.axi_clk(axi_clk), .axi_rst_n(axi_rst_n),
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.awaddr(c_awaddr), .awlen(c_awlen), .awsize(c_awsize), .awburst(c_awburst), .awvalid(c_awvalid), .awready(c_awready),
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.wdata(c_wdata), .wstrb(c_wstrb), .wlast(c_wlast), .wvalid(c_wvalid), .wready(c_wready),
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.bvalid(c_bvalid), .bready(c_bready), .bresp(c_bresp),
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.beats_written(c_beats_written), .bursts_issued(), .bresp_err_count(),
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.fifo_overflow_count(col_ovf), .idle(col_writer_idle), .frame_drained(col_drained)
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);
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// Destination RMW reads must observe the preceding blended/masked write. Merely
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// waiting for u_c.idle is insufficient: the elastic packer can hold a
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// partial beat while the AXI-side FIFO still reports empty. Flush an
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// ordered marker after every blended output and wait for col_drained to go
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// low then high. That high transition is after the data beat's BRESP, so
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// the next destination read sees the committed result. This deliberately
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// serializes the color stream only while an ABE or partial-byte write is
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// being committed.
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wire blend_rmw_in_accept = col_out_valid && blend_in_ready && blend_input_gate
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&& (col_out_alpha[16] || (col_out_be != 4'hF));
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wire blend_write_accept = blend_out_valid && col_px_ready && blend_write_pending;
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always_ff @(posedge axi_clk or negedge axi_rst_n) begin
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if (!axi_rst_n) begin
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blend_write_pending <= 1'b0;
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blend_flush_issued <= 1'b0;
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blend_drain_seen_low <= 1'b0;
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end else begin
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if (blend_rmw_in_accept) begin
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blend_write_pending <= 1'b1;
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blend_flush_issued <= 1'b0;
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blend_drain_seen_low <= 1'b0;
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end else if (blend_write_accept) begin
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blend_flush_issued <= 1'b1;
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end else if (blend_write_pending && blend_flush_issued) begin
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if (!col_drained)
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blend_drain_seen_low <= 1'b1;
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else if (blend_drain_seen_low) begin
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blend_write_pending <= 1'b0;
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blend_flush_issued <= 1'b0;
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blend_drain_seen_low <= 1'b0;
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end
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end
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end
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end
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// ---------------- control FSM (axi_clk): feed Z, emit color on pass, drain on scene marker ----------------
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typedef enum logic [1:0] { C_RUN, C_MARK_WAIT, C_DRAIN } cst_t; cst_t cst;
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// POP only when the head stage and the synchronous-read pipeline are empty;
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// CONSUME the staged fragment via feed_ok. req_rd remains a registered
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// pulse, isolated from feed_ok and the color-align control cones.
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wire req_read_accept = req_rd && !req_rempty;
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// feed the STAGED fragment into the Z RMW (and push its color) when it is a fragment and both can accept
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wire feed_ok = (cst==C_RUN) && req_stage_frag_valid && z_fready && !ca_full;
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// consume the STAGED end-of-scene marker once all fed fragments have drained (see C_MARK_WAIT)
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wire marker_consume = (cst==C_MARK_WAIT) && req_stage_marker_valid && ca_empty && z_idle && !col_out_valid && blend_idle && !blend_write_pending;
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assign z_fvalid = feed_ok;
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// Ch357 (Codex) — PRODUCER BACKPRESSURE via a ONE-ENTRY output register (col_out_*). Consume a Z result only when the
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// output register can accept the color it would emit: z_pready = !col_out_valid || col_px_ready (empty, OR draining
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// this cycle -> simultaneous drain/refill). ca_head pops on z_pvalid && z_pready (pass OR reject; a reject consumes its
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// CA entry WITHOUT loading the output register). col_px_* are driven from the REGISTER (not combinationally from
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// ca_mem), which breaks the ca_mem->u_c barrel-insert cone (the -0.98ns 310MHz path) AND holds the payload valid until
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// u_c accepts it (px_ready), so no pixel is dropped. No comb loop: col_px_ready depends only on u_c's registered stage.
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assign z_pready = !col_out_valid || (blend_in_ready && blend_input_gate);
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wire [CAW-1:0] ca_headword = ca_mem[ca_head[CAPTR_W-1:0]];
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wire ca_head_zt = ca_headword[85];
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wire [3:0] ca_head_be = ca_headword[84:81];
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wire [16:0] ca_head_alpha= ca_headword[80:64];
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wire [31:0] ca_head_addr = ca_headword[63:32];
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wire [31:0] ca_head_col = ca_headword[31:0];
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wire z_consume = z_pvalid && z_pready; // pop the color-align head this cycle
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wire z_emit_pass = z_consume && (z_ppass || !ca_head_zt); // load the output register (Z pass or non-Z frag)
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assign col_px_emit = blend_out_valid;
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assign col_px_addr = blend_out_addr;
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assign col_px_pix32 = blend_out_color;
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always_ff @(posedge axi_clk or negedge axi_rst_n) begin
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if (!axi_rst_n) begin
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cst<=C_RUN; ca_head<=0; ca_tail<=0;
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ca_wr_q<=1'b0;
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col_flush<=0; z_sflush<=0; frame_drained<=0;
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col_out_valid<=0; col_out_addr<=0; col_out_color<=0; col_out_alpha<=0; col_out_be<=4'hF;
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req_stage_valid<=1'b0;
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req_rd<=1'b0; req_read_pending<=1'b0;
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end else begin
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col_flush<=blend_write_accept;
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ca_wr_q<=1'b0;
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// u_req has a registered read port. Allow one accepted pop, wait
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// one cycle for its RAM output, then fill the request-head stage.
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// The pending gate prevents a second pop while that word is in
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// flight but req_stage_valid has not asserted yet.
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req_rd <= !req_stage_valid && !req_read_pending && !req_rempty && !req_rd;
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req_read_pending <= req_read_accept;
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// Capture one cycle after the synchronous FIFO pop. Capture needs
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// an empty stage; consume needs a full one, so they remain mutually
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// exclusive.
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if (req_read_pending) begin
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req_stage_valid <= 1'b1;
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end
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if (feed_ok || marker_consume) req_stage_valid <= 1'b0;
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// push color-align entry as we feed a fragment
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if (feed_ok) begin
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ca_wr_q <= 1'b1;
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ca_tail <= ca_tail + 1'b1;
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end
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// ONE-ENTRY color output register. DRAIN when u_c accepts (px_ready); may be re-loaded the same cycle (refill
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// below) for simultaneous drain/refill. A consumed Z result (z_consume = z_pvalid && z_pready) pops the
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// color-align head (pass OR reject); a PASS additionally loads the register (a reject writes no color).
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if (col_out_valid && blend_in_ready && blend_input_gate) col_out_valid <= 1'b0;
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if (z_consume) begin
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ca_head <= ca_head + 1'b1;
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if (z_emit_pass) begin
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col_out_valid <= 1'b1;
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col_out_addr <= ca_head_addr;
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col_out_color <= ca_head_col;
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col_out_alpha <= ca_head_alpha;
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col_out_be <= ca_head_be;
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end
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end
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case (cst)
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C_RUN: if (req_stage_marker_valid) cst<=C_MARK_WAIT; // staged marker: stop feeding, wait in-flight to drain
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C_MARK_WAIT: begin
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// all fed fragments have resulted (CA empty), Z idle, AND the output register drained to u_c
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if (ca_empty && z_idle && !col_out_valid && blend_idle && !blend_write_pending) begin
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col_flush<=1'b1; // push color partial beat + EOF marker
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z_sflush <=1'b1; // flush the dirty Z line (cache persists)
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// req_rd pops the marker this cycle (see assign)
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cst<=C_DRAIN;
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end
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end
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C_DRAIN: begin
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z_sflush<=1'b1; // hold until z_drained
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if (col_drained && z_drained) begin
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frame_drained<=1'b1; z_sflush<=1'b0; cst<=C_RUN;
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end
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end
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default: cst<=C_RUN;
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endcase
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// frame_drained is a per-scene ack; drop it once new fragments flow again (feed_ok => a fresh fragment consumed)
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if (feed_ok) frame_drained<=1'b0;
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end
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end
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assign idle = (cst==C_RUN) && req_rempty && !req_stage_valid && ca_empty && z_idle && !col_out_valid && blend_idle && !blend_write_pending;
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endmodule : gs_lpddr_zc_emit
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