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retroDE_ps2/docs/ch406_request_fifo_timing_prefit.md
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thejayman77 ba74bbd5aa Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder
XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog
TBs, fidelity attribution tooling. Functional baseline before removing the dead
bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-07-20 19:56:46 -04:00

2.8 KiB

Ch406 — deep request-FIFO timing repair (pre-fit gate)

Trigger

The owner Quartus 26.1 GUI compile for Ch405 fit in the device but failed the 310 MHz EMIF clock by 0.267 ns, with design-wide TNS of -4.802 ns. All 77 failing endpoints belong to u_zc_emit|u_req. The leading path is the registered empty flag through the 15-bit binary-pointer increment, Gray conversion, equality reduction, and back into the empty flag. Secondary violations are the same empty/pointer cone feeding the 16K FIFO RAM address, plus the asynchronous RAM bank mux feeding request-head decode.

This is a local consequence of increasing the Ch405 request FIFO from 4K to 16K. Hold timing, Gray-pointer skew constraints, and all other clock domains pass.

Structural repair

  • Treat gs_async_fifo.rd according to its existing interface contract: it is an accepted read, already qualified by !rempty in each wrapper. Remove the redundant internal !rempty gate from the read-pointer increment. This removes the empty-to-pointer feedback and the empty-to-RAM-address fanout.
  • Add an optional synchronous/registered read port to gs_async_fifo.
  • Enable that port only for the 16K x 92-bit Z/color request FIFO. Keep the smaller existing users on their original FWFT interface.
  • Add a one-cycle pending bit in gs_lpddr_zc_emit so its request-head stage captures the registered FIFO word on the following cycle and cannot issue a second pop while a word is in flight.
  • Make the standalone FIFO testbench explicitly qualify its randomized read requests, matching the documented production interface.

No clock, SDC, FIFO depth, fixture, draw, texture, blend, or Z behavior changes.

Pre-fit proof

  • Async FIFO scoreboard: 3,284 writes / 3,284 reads, zero order, duplicate, or drop errors, final empty asserted, PASS.
  • Ch405 worst three epochs, empty Z: 43,680 fed and passed, zero drops, high-water 12,953/16,384, exact color, exact Z, PASS.
  • Ch405 worst three epochs, checkerboard Z: 43,680 fed, 21,839 passed, zero drops, high-water 11,389/16,384, exact color, exact unchanged Z at all 307,200 pixels, PASS.
  • A sequential production sweep additionally replayed epochs 0 through 19: 291,597 fragments, zero drops, and every scene drain completed. It was stopped after this redundant prefix because the complete 287-epoch run would consume more than an hour; the maximum-pressure tail and both Z outcomes had already passed exact comparisons above.
  • Production RTL elaborates with the 16K request FIFO and registered-read path.

Owner fit gate

Run the next compile only in the owner-controlled Quartus 26.1 GUI. The fit must confirm that the request RAM remains inferred in device memory, resources still fit, setup and hold both pass, and the previous rempty feedback family is absent. Do not deploy an RBF unless those checks pass.