thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
20 lines
1.1 KiB
Plaintext
20 lines
1.1 KiB
Plaintext
Info: Generated by version: 26.1 build 110
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Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/hps_subsys.qsys --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/hps_subsys --family="Agilex 5" --part=A5EB013BB23BE4SCS
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Progress: Loading hps_subsys/hps_subsys.qsys
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Progress: Reading input file
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Progress: Parameterizing module agilex_hps
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Progress: Parameterizing module emif_hps
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: hps_subsys: "Transforming system: hps_subsys"
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Info: hps_subsys: "Naming system components in system: hps_subsys"
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Info: hps_subsys: "Processing generation queue"
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Info: hps_subsys: "Generating: hps_subsys"
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Info: hps_subsys: "Generating: agilex_hps"
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Info: hps_subsys: "Generating: emif_io96b_hps"
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Info: hps_subsys: Done "hps_subsys" with 3 modules, 1 files
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Info: Finished: Create HDL design files for synthesis
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