thejayman77
471c1af9cd
Candidate 2 from the accepted structural proposal. Adds a QUAD_WIDTH4_READ generate branch to gs_async_fifo: like QUADRANT_READ (2 depth x 2 width) but splits the payload into FOUR width banks, so each preserved read-address launch register drives ~half the M20K load (targets the 310MHz raddr_hi1_q->mem_hi1 setup family, WNS -0.103). Keeps QUADRANT_READ's proven 2:1 depth OUTPUT selector unchanged (no new/deeper mux, per the doc's warning). Depth (8192), one-cycle read latency, ordering, CDC, capacity, and interface are identical. zc_emit u_req switched QUADRANT_READ->QUAD_WIDTH4_READ. New default-off param leaves the other two gs_async_fifo instances byte-identical. TB gains a TEST_QUAD_WIDTH4 variant + standalone Makefile target tb_gs_async_fifo_quad_width4. NO simulations or Quartus run (per authorization). Awaiting review before any sim. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
sim/tb — Testbenches
Per-subsystem SystemVerilog / Verilog testbenches.
Planned layout (created as each subsystem lands its first stub):
tb/memory/— memory map and arbitration tests.tb/dmac/— EE DMAC channel tests.tb/gif_gs/— GIF packet intake and GS register decode tests.tb/sif/— EE<->IOP mailbox/DMA tests.tb/ee/— EE core directed tests.tb/iop/— IOP core and IOP-DMA directed tests.tb/vif_vu/— VIF unpack and VU microprogram tests.
Rule: no testbench directory is created until the matching subsystem has a
contract in docs/contracts/ and a stub in rtl/.