Files

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thejayman77 194f45bd05 Ch442 review fixes: fs_edge parity, dest snap_valid, sync attrs + SDC

Codex review containment/observability fixes (no behavior change, no redesign):

- scanout_lb: add !fs_edge_v to the diagnostic predicate so capture
  matches the underflow latch's frame-start CLEAR priority exactly
  (no capture on an fs_edge cycle the real latch suppresses).
- bridge: expose a destination snap_valid_q as 0x120[0] — set ON the
  payload-capture edge, cleared on synced source-valid deassert — so
  valid never leads the bundle by a cycle (was the middle sync stage).
- bridge: forced-synchronizer (SYNCHRONIZER_IDENTIFICATION FORCED) +
  dont_merge/preserve on the underflow/read-error/valid chains;
  preserve on the bundle capture regs (both domains).
- SDC: stage-0 async cuts on the three sync[0] inputs + the 37-bit
  stable bundle hold-false-path + 2ns max_skew + 2ns net_delay, with
  fail-closed src==37 / dst!=0 count checks (tile_ram_cdc idiom).
- tb_gs_scanout_diag: +fs_edge-suppression monitor (with coverage that
  the coincidence is exercised), +valid-ordering monitor, +snapshot
  stability after later misses, +production DUT (V_SOURCE_START=32,
  stretch, linear) proving cold-start scan_y=32, +cause/phase packing.
  32/32 checks pass.
- doc: production cold start is source row 32 (not 0), base+lookahead
  may both assert, and one snapshot narrows but does not prove
  starvation vs next_fetch CDC-lag.

Sim set all PASS: focused TB, tb_ps2_hps_bridge, scanout_lb
{binomial,hstretch,psm32_256}, complete f52 replay (FB byte-identical
Z 0/307200, COLOR 0/245760). No Quartus, board, push, or scanout
behavior change.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

2026-07-21 23:50:04 -04:00

clut_stage_cdc.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

cp437_8x8.mem

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

I2C_Controller.v

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

I2C_HDMI_Config.v

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

platform_video_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

ps2_hps_bridge_null.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

ps2_hps_bridge.sv

Ch442 review fixes: fs_edge parity, dest snap_valid, sync attrs + SDC

2026-07-21 23:50:04 -04:00

README.md

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

tile_ram_cdc.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

README.md

rtl/platform

retroDE-specific platform integration. Matches docs/contracts/platform.md.

Wave 1 contents

platform_video_stub.sv — free-running raster generator. Default VGA 640x480 timing (overridable per-testbench to tiny values for fast sim). Takes bg_{r,g,b} from gs_stub and flood-fills the active region. Emits one EV_MODE per completed frame so testbenches can count frames without sampling raw video.

Scope boundary

This directory owns:

clock/reset sequencing entry points,
retroDE-facing video and audio adaptation,
HPS bridge plumbing (future),
top-level wrappers not belonging inside PS2 subsystems.

It does not own GS/PCRTC semantics (that's rtl/gif_gs/), SPU2 audio synthesis (rtl/spu2/), or any PS2 register behavior.

Replacement path

platform_video_stub stays as the platform adaptation layer. What changes is the upstream pixel source: Wave 1 → flat BGCOLOR from gs_stub, later waves → fuller GS/PCRTC output including framebuffer scan-out.