thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
54 lines
4.3 KiB
Plaintext
54 lines
4.3 KiB
Plaintext
Info: Generated by version: 26.1 build 110
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Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/peripheral_subsys.qsys --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/peripheral_subsys --family="Agilex 5" --part=A5EB013BB23BE4SCS
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Progress: Loading peripheral_subsys/peripheral_subsys.qsys
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Progress: Reading input file
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Progress: Parameterizing module button_pio
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Progress: Parameterizing module dipsw_pio
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Progress: Parameterizing module led_pio
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Progress: Parameterizing module pb_cpu_0
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Progress: Parameterizing module periph_clk
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Progress: Parameterizing module periph_rst_in
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Progress: Parameterizing module sysid
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Component Instantiation Warning: peripheral_subsys.button_pio: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
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Component Instantiation Warning: peripheral_subsys.dipsw_pio: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
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Component Instantiation Warning: peripheral_subsys.led_pio: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
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Component Instantiation Warning: peripheral_subsys.pb_cpu_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
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Component Instantiation Warning: peripheral_subsys.periph_clk: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
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Component Instantiation Warning: peripheral_subsys.periph_rst_in: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
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Component Instantiation Warning: peripheral_subsys.sysid: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
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Info: peripheral_subsys.pb_cpu_0.m0/sysid.control_slave: pb_cpu_0.m0 has read and write while sysid.control_slave is read-only
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Info: peripheral_subsys: "Transforming system: peripheral_subsys"
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Info: peripheral_subsys: "Naming system components in system: peripheral_subsys"
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Info: peripheral_subsys: "Processing generation queue"
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Info: peripheral_subsys: "Generating: peripheral_subsys"
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Info: peripheral_subsys: "Generating: button_pio"
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Info: peripheral_subsys: "Generating: dipsw_pio"
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Info: peripheral_subsys: "Generating: led_pio"
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Info: peripheral_subsys: "Generating: pb_cpu_0"
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Info: peripheral_subsys: "Generating: periph_clk"
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Info: peripheral_subsys: "Generating: periph_rst_in"
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Info: peripheral_subsys: "Generating: sysid"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_mm_interconnect_1920_553jo7i"
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Info: peripheral_subsys: "Generating: altera_reset_controller"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_master_translator_193_lgcew2q"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_slave_translator_191_xg7rzxi"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_master_agent_1940_r3ep6da"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_slave_agent_1930_jxauz3i"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_avalon_sc_fifo_1932_22gxxgi"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_router_1921_iesulwy"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_router_1921_wxl7gvy"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_traffic_limiter_1922_y23fybq"
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Info: my_altera_avalon_sc_fifo_dest_id_fifo: "Generating: my_altera_avalon_sc_fifo_dest_id_fifo"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_multiplexer_1922_ufdjdoq"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_demultiplexer_1921_4xqokvi"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_multiplexer_1922_cbyifnq"
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Info: peripheral_subsys: "Generating: peripheral_subsys_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1922_25262sa"
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Info: peripheral_subsys: Done "peripheral_subsys" with 23 modules, 23 files
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Info: Finished: Create HDL design files for synthesis
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