Files

T

thejayman77 194f45bd05 Ch442 review fixes: fs_edge parity, dest snap_valid, sync attrs + SDC

Codex review containment/observability fixes (no behavior change, no redesign):

- scanout_lb: add !fs_edge_v to the diagnostic predicate so capture
  matches the underflow latch's frame-start CLEAR priority exactly
  (no capture on an fs_edge cycle the real latch suppresses).
- bridge: expose a destination snap_valid_q as 0x120[0] — set ON the
  payload-capture edge, cleared on synced source-valid deassert — so
  valid never leads the bundle by a cycle (was the middle sync stage).
- bridge: forced-synchronizer (SYNCHRONIZER_IDENTIFICATION FORCED) +
  dont_merge/preserve on the underflow/read-error/valid chains;
  preserve on the bundle capture regs (both domains).
- SDC: stage-0 async cuts on the three sync[0] inputs + the 37-bit
  stable bundle hold-false-path + 2ns max_skew + 2ns net_delay, with
  fail-closed src==37 / dst!=0 count checks (tile_ram_cdc idiom).
- tb_gs_scanout_diag: +fs_edge-suppression monitor (with coverage that
  the coincidence is exercised), +valid-ordering monitor, +snapshot
  stability after later misses, +production DUT (V_SOURCE_START=32,
  stretch, linear) proving cold-start scan_y=32, +cause/phase packing.
  32/32 checks pass.
- doc: production cold start is source row 32 (not 0), base+lookahead
  may both assert, and one snapshot narrows but does not prove
  starvation vs next_fetch CDC-lag.

Sim set all PASS: focused TB, tb_ps2_hps_bridge, scanout_lb
{binomial,hstretch,psm32_256}, complete f52 replay (FB byte-identical
Z 0/307200, COLOR 0/245760). No Quartus, board, push, or scanout
behavior change.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

2026-07-21 23:50:04 -04:00

clut_loader_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

clut_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

ee_gs_priv_bridge_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gif_image_xfer_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gif_packed_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gif_path_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_alpha_blend.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_async_fifo.sv

Ch440 review fixes: 93-bit per-bank test coverage + soften M20K claims [READY FOR REVIEW]

2026-07-21 10:28:31 -04:00

gs_axi_w_regbuf.sv

Ch441: one-entry fully-registered W buffer, Z-RMW master -> wr_arb s2 [READY FOR REVIEW]

2026-07-21 14:12:11 -04:00

gs_grad_divider.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_lpddr_axi_master.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

gs_lpddr_color_blend.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

gs_lpddr_fb_writer.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_lpddr_map_pkg.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

gs_lpddr_rd_arb.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

gs_lpddr_rd_probe.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

gs_lpddr_scanout_lb.sv

Ch442 review fixes: fs_edge parity, dest snap_valid, sync attrs + SDC

2026-07-21 23:50:04 -04:00

gs_lpddr_scanout.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_lpddr_wr_arb.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

gs_lpddr_wr_probe.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_lpddr_z_rmw.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

gs_lpddr_zc_emit.sv

Ch441: one-entry fully-registered W buffer, Z-RMW master -> wr_arb s2 [READY FOR REVIEW]

2026-07-21 14:12:11 -04:00

gs_pcrtc_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_persp_uv.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

gs_prim_list_feeder.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

gs_reciprocal_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_stub.sv

Add FOG_ENABLE param, prune fog cone on the board profile (fix -6.165ns setup)

2026-07-20 21:31:14 -04:00

gs_swizzle_psmct16_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_swizzle_psmct32_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_swizzle_psmt4_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_swizzle_psmt8_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_texel_addr.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_texture_cache.sv

Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)

2026-07-20 19:56:46 -04:00

gs_texture_unit.sv

Fix signoff timing: remove dead bilinear clamp (comb loop) + relax gray skew 2.0->2.5ns

2026-07-20 20:03:42 -04:00

gs_tile_ram.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_tile_reload.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

gs_z_flush_writer.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

README.md

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

vram_bram_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

vram_normalize_pkg.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

vram_stub.sv

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

2026-06-29 20:10:50 -04:00

README.md

rtl/gif_gs

GIF path and Graphics Synthesizer logic. Matches docs/contracts/gif_gs.md.

Current contents

gs_stub.sv — GS shell with two architecturally distinct write ports (Ch75 namespace split):
- reg_wr_* — privileged-block writes (16-bit offset within 0x12000000). Latches BGCOLOR (offset 0x00E0) into bg_{r,g,b}; other offsets emit EV_MODE.
- gif_reg_* — GIF A+D register-number writes (8-bit reg# + 64-bit data). Decodes PRIM=0x00, RGBAQ=0x01, XYZF2=0x04, XYZ2=0x05, FRAME_1=0x4C, ZBUF_1=0x4E into per-register 64-bit latches; unknown reg numbers emit EV_MODE.
- No VRAM, no drawing yet — that is the next architectural step.
gif_path_stub.sv — Wave 2 minimal GIF packet logger; project-local single-qword register-write format. Used by tb_bgcolor_via_dma.
gif_packed_stub.sv — real PS2 GIFtag parser (Ch72-Ch75). Handles PACKED (FLG=0), REGLIST (FLG=1), IMAGE (FLG=2), DISABLE (FLG=3). The REAL_AD_REG_MAP parameter selects the A+D dispatch port:
- REAL_AD_REG_MAP=0 (default, back-compat) — drives gs_stub.reg_wr_* using a project-local 16-bit offset carried in in_data[79:64].
- REAL_AD_REG_MAP=1 — drives gs_stub.gif_reg_* using the real PS2 8-bit reg# carried in in_data[71:64]. Source-of-truth: PCSX2 GSRegs.h.

BGCOLOR reset value

At reset, bg_{r,g,b} default to 0x40 each (mid-grey) rather than black. Rationale: this makes "gs_stub reset but no BGCOLOR write yet" visually distinct from "video output disabled / black frame" in Milestone A. Override is a BGCOLOR write from the test harness.

Pitfall: namespace conflation

Ch74 conflated GIF A+D reg numbers with GS privileged-block offsets and mapped e.g. 0x14→PMODE@0x0000. That is fiction — those are separate namespaces. Ch75 split them. ZBUF_1 is 0x4E, not 0x4F (that's ZBUF_2). When adding a new GIF-context register, source the reg# from PCSX2 GSRegs.h, never from the privileged-block map.