thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
3765 lines
194 KiB
Makefile
3765 lines
194 KiB
Makefile
# retroDE_ps2 simulation driver
|
||
#
|
||
# Targets:
|
||
# make lint run verilator --lint-only across all RTL (strict)
|
||
# make tb_ee_fetch build + run tb_ee_fetch_stub (iverilog)
|
||
# make tb_gs build + run tb_gs_stub
|
||
# make tb_intc build + run tb_intc_stub
|
||
# make tb_platform_video build + run tb_platform_video_stub (Milestone A)
|
||
# make tb_bgcolor_via_dma build + run tb_bgcolor_via_dma (Milestone A+)
|
||
# make tb_sif_mailbox build + run tb_sif_mailbox_stub
|
||
# make tb_sif_command_echo build + run tb_sif_command_echo (EE↔peer)
|
||
# make tb_sif_command_echo_rearm build + run re-armable multi-command TB
|
||
# make tb_sif_negative_path build + run stall/malformed-lifecycle TB
|
||
# make tb_sif_dma_smoke build + run first SIF DMA receive test (ch5)
|
||
# make tb_sif_dma_mid_stall build + run mid-transfer backpressure test
|
||
# make tb_sif_dma_overflow build + run full-stop backpressure test
|
||
# make tb_sif_combined_ctrl_data build + run first combined ctrl+data SIF handshake
|
||
# make tb_iop_ram build + run first IOP-side primitive test
|
||
# make tb_iop_memory_map build + run IOP memory map decode test
|
||
# make tb_iop_fetch_through_map build + run IOP fetch → map → RAM integration
|
||
# make tb_sif_iop_bridge_smoke build + run SIF-to-IOP-RAM bridge write test
|
||
# make tb_sif_iop_bridge_exec build + run execution-visible bridge test
|
||
# make tb_iop_to_sif_via_map build + run IOP reaches SIF via real map
|
||
# make tb_iop_dmac_via_map build + run IOP DMAC ch9 through the real map
|
||
# make tb_sif_ee_landing_via_dmac build + run first reverse-direction SIF DMA
|
||
# make tb_sif_iop_driven_combined build + run IOP-driven combined ctrl+data handshake
|
||
# make tb_ee_dmac_intc build + run first EE DMAC completion → INTC flow
|
||
# make tb_iop_dmac_intc build + run IOP DMAC ch9 → IOP INTC through real map
|
||
# make tb_iop_self_driven build + run first self-driven IOP transaction
|
||
# make tb_iop_autonomous_two_xfers build + run first autonomous multi-transaction script
|
||
# make tb_iop_core_basic build + run first real MIPS-decode IOP core run
|
||
# make tb_iop_core_interrupts build + run first exception-driven IOP program
|
||
# make tb_iop_core_bootstrap build + run first BIOS-sourced bootstrap (Phase 1)
|
||
# make tb_iop_core_bootstrap_intc build + run BIOS-sourced interrupt flow (Phase 2)
|
||
# make tb_iop_core_bios_smoke build + run strict-mode BIOS smoke (first-unsupported halt)
|
||
# make tb_ee_core_basic build + run first EE-side real-decode run
|
||
# make tb_ee_core_memops build + run EE CPU→RAM SW/LW round-trip
|
||
# make tb_ee_core_dmac build + run EE core programming DMAC ch2 via SW
|
||
# make tb_ee_core_dmac_poll build + run EE core polling CHCR + DONE_COUNT
|
||
# make tb_ee_core_dmac_intc build + run EE core DMAC-through-INTC exception flow
|
||
# make tb_ee_core_bios_smoke build + run EE strict-mode BIOS smoke (first-unsupported halt)
|
||
# make tb_ee_core_bios_smoke BIOS=/path/to/bios.hex # same TB, real BIOS image
|
||
# make tb_ee_core_slti build + run EE SLTI/SLTIU coverage (first real-BIOS-driven op growth)
|
||
# make tb_ee_core_addi build + run EE ADDI coverage (second real-BIOS-driven op growth)
|
||
# make tb_ee_core_andi build + run EE ANDI coverage (third real-BIOS-driven op growth)
|
||
# make tb_ee_core_rtype_logic build + run EE R-type AND/OR/XOR/NOR coverage (fourth growth)
|
||
# make tb_ee_core_sb build + run EE SB byte-store coverage (fifth growth)
|
||
# make tb_ee_core_lb build + run EE LB sign-extended byte-load (sixth growth)
|
||
# make tb_ee_core_jal build + run EE JAL jump-and-link (seventh growth)
|
||
# make tb_ee_core_rtype_addu build + run EE R-type ADDU/SUBU coverage (eighth growth)
|
||
# make tb_ee_core_slt build + run EE R-type SLT/SLTU coverage (ninth growth)
|
||
# make tb_ee_core_lh build + run EE LH sign-extended halfword load (tenth growth)
|
||
# make tb_ee_core_lhu build + run EE LHU zero-extended halfword load (tenth growth, paired)
|
||
# make tb_ee_core_shift build + run EE SLL/SRL/SRA shift family coverage (eleventh growth)
|
||
# make tb_ee_core_sh build + run EE SH halfword-store coverage (twelfth growth)
|
||
# make tb_ee_core_jalr build + run EE JALR register-indirect call + link (thirteenth growth)
|
||
# make tb_ee_core_add_sub build + run EE R-type ADD/SUB coverage (fourteenth growth; overflow-trap deferred)
|
||
# make tb_ee_core_cop0_count build + run EE COP0 Count coverage (first machine-state chapter)
|
||
# make tb_ee_bootstrap_mmio build + run EE bootstrap MMIO stub unit test (latched register file)
|
||
# make tb_ee_biu_mmio build + run EE BIU/cache-control stub unit test (0xFFFE_0xxx window)
|
||
# make run run all fifty-three testbenches
|
||
# make all_checks lint + run (RTL + benches; the default gate)
|
||
# make full_checks all_checks + test_compare (widest regression)
|
||
# make golden_nop generate the NOP-sled golden trace
|
||
# make compare_ee_fetch diff RTL ee_fetch.trace vs. NOP-sled golden
|
||
# make test_compare run the comparator against all three documented
|
||
# exit-code paths (acceptance criteria 4/5/6 from
|
||
# sim/golden/trace_compare_spec.md)
|
||
# make traces show what's in sim/traces/rtl/
|
||
# make clean remove build artifacts and traces
|
||
#
|
||
# Trace files are written to sim/traces/rtl/ (Make cds there before running
|
||
# each testbench so the trace_sink_stub FILENAME parameters resolve into
|
||
# that directory).
|
||
|
||
SIM_DIR := $(CURDIR)
|
||
REPO_ROOT := $(abspath $(SIM_DIR)/..)
|
||
# Ch245 — shared retroDE platform OSD lives in the sibling retroDE_splash
|
||
# repo, NOT inside this core. Sibling cores reference it the same way.
|
||
SPLASH_PLATFORM_RTL := $(abspath $(REPO_ROOT)/../retroDE_splash/rtl/platform)
|
||
BUILD_DIR := $(SIM_DIR)/build
|
||
TRACE_DIR := $(SIM_DIR)/traces/rtl
|
||
GOLD_TRC_DIR := $(SIM_DIR)/traces/golden
|
||
GOLDEN_DIR := $(SIM_DIR)/golden
|
||
|
||
RTL_ROOT := $(REPO_ROOT)/rtl
|
||
TB_ROOT := $(SIM_DIR)/tb
|
||
|
||
PYTHON := python3
|
||
|
||
# ---------------------------------------------------------------------
|
||
# Ch147 — Top-wrapper fixture bake (top_psmct32_raster_demo).
|
||
# ---------------------------------------------------------------------
|
||
# The Ch146 hardware top reads two .mem fixtures via $readmemh:
|
||
# bios.mem — 1024 32-bit words (4 KiB BIOS BRAM, 18 active)
|
||
# payload.mem — 256 128-bit qwords (4 KiB EE-RAM BRAM, 40 active)
|
||
# Both are produced deterministically by sim/data/top_psmct32_raster_demo/
|
||
# bake.py from the same procedural pattern Ch123 uses. Ch147 makes the
|
||
# bake first-class so the .mem files can't drift from the script:
|
||
# `make top_psmct32_raster_demo_mem` — re-runs the bake
|
||
# `make top_psmct32_raster_demo_mem_check` — verifies fixture sizes
|
||
# tb_top_psmct32_raster_demo depends on top_psmct32_raster_demo_mem
|
||
# so a stale fixture is impossible.
|
||
TOP_PSMCT32_DEMO_DATA_DIR := $(SIM_DIR)/data/top_psmct32_raster_demo
|
||
TOP_PSMCT32_DEMO_BAKE_PY := $(TOP_PSMCT32_DEMO_DATA_DIR)/bake.py
|
||
TOP_PSMCT32_DEMO_BIOS := $(TOP_PSMCT32_DEMO_DATA_DIR)/bios.mem
|
||
TOP_PSMCT32_DEMO_PAYLOAD := $(TOP_PSMCT32_DEMO_DATA_DIR)/payload.mem
|
||
|
||
# Both .mem files share a single recipe — they're produced atomically
|
||
# by one bake.py invocation. Make `bios.mem` the canonical target;
|
||
# `payload.mem` rebuilds whenever bios.mem does via the same recipe.
|
||
$(TOP_PSMCT32_DEMO_BIOS) $(TOP_PSMCT32_DEMO_PAYLOAD) &: $(TOP_PSMCT32_DEMO_BAKE_PY)
|
||
@echo "=== bake top_psmct32_raster_demo .mem fixtures ==="
|
||
$(PYTHON) $(TOP_PSMCT32_DEMO_BAKE_PY)
|
||
|
||
top_psmct32_raster_demo_mem: $(TOP_PSMCT32_DEMO_BIOS) $(TOP_PSMCT32_DEMO_PAYLOAD)
|
||
|
||
# Size check — bios.mem must be 1024 lines of payload (header lines
|
||
# excluded), payload.mem must be 256 lines of payload. We strip
|
||
# blanks + `// ...` comment-only lines and count the rest.
|
||
top_psmct32_raster_demo_mem_check: top_psmct32_raster_demo_mem
|
||
@echo "=== check top_psmct32_raster_demo fixture sizes ==="
|
||
@bios_lines=$$(grep -cvE '^\s*(//.*)?$$' $(TOP_PSMCT32_DEMO_BIOS)); \
|
||
if [ $$bios_lines -ne 1024 ]; then \
|
||
echo "FAIL: bios.mem has $$bios_lines payload lines, expected 1024"; \
|
||
exit 1; \
|
||
fi; \
|
||
echo " bios.mem : $$bios_lines payload lines (expected 1024) OK"
|
||
@payload_lines=$$(grep -cvE '^\s*(//.*)?$$' $(TOP_PSMCT32_DEMO_PAYLOAD)); \
|
||
if [ $$payload_lines -ne 256 ]; then \
|
||
echo "FAIL: payload.mem has $$payload_lines payload lines, expected 256"; \
|
||
exit 1; \
|
||
fi; \
|
||
echo " payload.mem : $$payload_lines payload lines (expected 256) OK"
|
||
|
||
# ---------------------------------------------------------------------
|
||
# Ch148 — synthesis scaffold validator (DE25-Nano).
|
||
# ---------------------------------------------------------------------
|
||
# Verifies that every path listed in
|
||
# synth/de25_nano/top_psmct32_raster_demo/files.f resolves to a real
|
||
# file relative to the repo root, AND that the two .mem fixtures
|
||
# exist. Strips comments / blank lines from files.f the same way the
|
||
# Quartus / Vivado parsers will. Exits non-zero on any miss.
|
||
TOP_PSMCT32_DEMO_SYNTH_DIR := $(REPO_ROOT)/synth/de25_nano/top_psmct32_raster_demo
|
||
TOP_PSMCT32_DEMO_FILELIST := $(TOP_PSMCT32_DEMO_SYNTH_DIR)/files.f
|
||
|
||
top_psmct32_raster_demo_synth_check: top_psmct32_raster_demo_mem_check
|
||
@echo "=== check top_psmct32_raster_demo synthesis scaffold ==="
|
||
@if [ ! -f $(TOP_PSMCT32_DEMO_FILELIST) ]; then \
|
||
echo "FAIL: filelist missing: $(TOP_PSMCT32_DEMO_FILELIST)"; \
|
||
exit 1; \
|
||
fi
|
||
@missing=0; total=0; \
|
||
while IFS= read -r line; do \
|
||
stripped=$$(echo "$$line" | sed -E 's/[#].*$$//; s/^[[:space:]]+//; s/[[:space:]]+$$//'); \
|
||
if [ -z "$$stripped" ]; then continue; fi; \
|
||
total=$$((total + 1)); \
|
||
if [ ! -f $(REPO_ROOT)/$$stripped ]; then \
|
||
echo " MISSING: $$stripped"; \
|
||
missing=$$((missing + 1)); \
|
||
fi; \
|
||
done < $(TOP_PSMCT32_DEMO_FILELIST); \
|
||
if [ $$missing -ne 0 ]; then \
|
||
echo "FAIL: $$missing of $$total files in files.f are missing"; \
|
||
exit 1; \
|
||
fi; \
|
||
echo " files.f : $$total entries, all resolve OK"
|
||
@echo " fixtures : bios.mem + payload.mem present OK"
|
||
|
||
# ---------------------------------------------------------------------
|
||
# Ch150 — Quartus scaffold validator (DE25-Nano).
|
||
# ---------------------------------------------------------------------
|
||
# Verifies the .qsf + .sdc exist next to files.f, that the .qsf names
|
||
# the Ch149 board wrapper as the top entity (NOT the inner Ch146 top),
|
||
# that the Ch150 in-scope pins (CLOCK2_50, KEY[0], LED[2:0]) each have
|
||
# a `set_location_assignment` line, that the deferred VIDEO_* outputs
|
||
# are marked `VIRTUAL_PIN ON` so Quartus can't auto-place them on
|
||
# arbitrary package pins, and that the .sdc declares the CLOCK2_50
|
||
# 50 MHz period clock constraint. Exits non-zero on any miss.
|
||
# Intended as a lightweight pre-Quartus sanity gate.
|
||
TOP_PSMCT32_DEMO_QSF := $(TOP_PSMCT32_DEMO_SYNTH_DIR)/de25_nano_psmct32_raster_demo_top.qsf
|
||
TOP_PSMCT32_DEMO_SDC := $(TOP_PSMCT32_DEMO_SYNTH_DIR)/de25_nano_psmct32_raster_demo_top.sdc
|
||
|
||
top_psmct32_raster_demo_quartus_scaffold_check: top_psmct32_raster_demo_synth_check
|
||
@echo "=== check top_psmct32_raster_demo Quartus scaffold ==="
|
||
@if [ ! -f $(TOP_PSMCT32_DEMO_QSF) ]; then \
|
||
echo "FAIL: .qsf missing: $(TOP_PSMCT32_DEMO_QSF)"; exit 1; \
|
||
fi
|
||
@if [ ! -f $(TOP_PSMCT32_DEMO_SDC) ]; then \
|
||
echo "FAIL: .sdc missing: $(TOP_PSMCT32_DEMO_SDC)"; exit 1; \
|
||
fi
|
||
@echo " qsf+sdc : both present OK"
|
||
@if ! grep -qE '^set_global_assignment -name TOP_LEVEL_ENTITY de25_nano_psmct32_raster_demo_top' $(TOP_PSMCT32_DEMO_QSF); then \
|
||
echo "FAIL: .qsf does not set TOP_LEVEL_ENTITY = de25_nano_psmct32_raster_demo_top"; exit 1; \
|
||
fi
|
||
@echo " top entity : de25_nano_psmct32_raster_demo_top OK"
|
||
@missing=0; \
|
||
for pin in CLOCK2_50 "KEY\\[0\\]" "LED\\[0\\]" "LED\\[1\\]" "LED\\[2\\]"; do \
|
||
if ! grep -qE "set_location_assignment .* -to $$pin\$$" $(TOP_PSMCT32_DEMO_QSF); then \
|
||
echo " MISSING pin assignment: $$pin"; \
|
||
missing=$$((missing + 1)); \
|
||
fi; \
|
||
done; \
|
||
if [ $$missing -ne 0 ]; then \
|
||
echo "FAIL: $$missing required pin assignments missing"; exit 1; \
|
||
fi; \
|
||
echo " pins : CLOCK2_50 + KEY[0] + LED[2:0] all assigned OK"
|
||
@missing_v=0; \
|
||
for vp in "VIDEO_R\\[0\\]" "VIDEO_G\\[0\\]" "VIDEO_B\\[0\\]" "VIDEO_HSYNC" "VIDEO_VSYNC" "VIDEO_DE"; do \
|
||
if ! grep -qE "set_instance_assignment -name VIRTUAL_PIN ON -to $$vp([[:space:]]|\$$)" $(TOP_PSMCT32_DEMO_QSF); then \
|
||
echo " MISSING VIRTUAL_PIN ON: $$vp"; \
|
||
missing_v=$$((missing_v + 1)); \
|
||
fi; \
|
||
done; \
|
||
if [ $$missing_v -ne 0 ]; then \
|
||
echo "FAIL: $$missing_v deferred video outputs are not marked VIRTUAL_PIN ON (Quartus may auto-place them on arbitrary package pins)"; exit 1; \
|
||
fi; \
|
||
echo " video pins : VIDEO_R/G/B/HSYNC/VSYNC/DE virtualized (sim/TB compat) OK"
|
||
@missing_h=0; missing_io=0; \
|
||
hdmi_pins="HDMI_TX_CLK HDMI_TX_HS HDMI_TX_VS HDMI_TX_DE"; \
|
||
for n in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23; do \
|
||
hdmi_pins="$$hdmi_pins HDMI_TX_D\\[$$n\\]"; \
|
||
done; \
|
||
for hp in $$hdmi_pins; do \
|
||
if ! grep -qE "set_location_assignment PIN_[A-Z0-9]+ +-to $$hp\$$" $(TOP_PSMCT32_DEMO_QSF); then \
|
||
echo " MISSING HDMI pin assignment: $$hp"; \
|
||
missing_h=$$((missing_h + 1)); \
|
||
fi; \
|
||
if ! grep -qE "set_instance_assignment -name IO_STANDARD .* -to $$hp([[:space:]]|\$$)" $(TOP_PSMCT32_DEMO_QSF); then \
|
||
echo " MISSING HDMI IO_STANDARD : $$hp"; \
|
||
missing_io=$$((missing_io + 1)); \
|
||
fi; \
|
||
done; \
|
||
if [ $$missing_h -ne 0 ] || [ $$missing_io -ne 0 ]; then \
|
||
echo "FAIL: $$missing_h missing pin assignments + $$missing_io missing IO_STANDARDs across the Ch164 HDMI pin set"; exit 1; \
|
||
fi; \
|
||
echo " hdmi pins : HDMI_TX_CLK + HDMI_TX_D[0..23] + HS/VS/DE all pin-assigned + IO_STANDARD'd (Ch164) OK"
|
||
@missing_c=0; \
|
||
for cp in "HDMI_I2C_SCL" "HDMI_I2C_SDA" "HDMI_TX_INT" "HDMI_MCLK"; do \
|
||
if ! grep -qE "set_location_assignment PIN_[A-Z0-9]+ +-to $$cp\$$" $(TOP_PSMCT32_DEMO_QSF); then \
|
||
echo " MISSING ADV7513 control pin: $$cp"; \
|
||
missing_c=$$((missing_c + 1)); \
|
||
fi; \
|
||
if ! grep -qE "set_instance_assignment -name IO_STANDARD .* -to $$cp([[:space:]]|\$$)" $(TOP_PSMCT32_DEMO_QSF); then \
|
||
echo " MISSING ADV7513 IO_STANDARD : $$cp"; \
|
||
missing_c=$$((missing_c + 1)); \
|
||
fi; \
|
||
done; \
|
||
if [ $$missing_c -ne 0 ]; then \
|
||
echo "FAIL: $$missing_c missing assignments across the Ch165 ADV7513 control pins"; exit 1; \
|
||
fi; \
|
||
echo " hdmi ctrl : HDMI_I2C_SCL/SDA + HDMI_TX_INT + HDMI_MCLK all pin-assigned + IO_STANDARD'd (Ch165) OK"
|
||
@if ! grep -qE 'create_clock -name CLOCK2_50 -period (20\.000|33\.333)' $(TOP_PSMCT32_DEMO_SDC); then \
|
||
echo "FAIL: .sdc does not declare CLOCK2_50 period 20.000 ns (50 MHz) or 33.333 ns (30 MHz Ch160 down-clock)"; exit 1; \
|
||
fi
|
||
@grep -E 'create_clock -name CLOCK2_50 -period (20\.000|33\.333)' $(TOP_PSMCT32_DEMO_SDC) | head -1 | awk '{print " clock : CLOCK2_50 period " $$5 " ns OK"}'
|
||
|
||
# ---------------------------------------------------------------------
|
||
# Quartus compile driver (DE25-Nano) — added Ch152, retargeted Ch160.
|
||
# ---------------------------------------------------------------------
|
||
# Runs the full quartus_syn → quartus_fit → quartus_sta → quartus_asm
|
||
# flow against the Ch150 .qsf scaffold via build_quartus.sh. The asm
|
||
# step is gated on a clean STA so a .sof is produced only when
|
||
# timing closes (Ch160). USE_PLL_IP stays undefined so the Ch151
|
||
# self-contained PLL stub path is what gets tested.
|
||
#
|
||
# Logs land in synth/de25_nano/top_psmct32_raster_demo/output_files/
|
||
# build_logs/. The companion report-parser target below summarizes
|
||
# resource usage, unconstrained paths, and key warning classes.
|
||
TOP_PSMCT32_DEMO_BUILD_SH := $(TOP_PSMCT32_DEMO_SYNTH_DIR)/build_quartus.sh
|
||
|
||
quartus_compile: top_psmct32_raster_demo_quartus_scaffold_check
|
||
@echo "=== quartus_compile : full syn → fit → sta flow ==="
|
||
@$(TOP_PSMCT32_DEMO_BUILD_SH)
|
||
|
||
quartus_compile_clean: top_psmct32_raster_demo_quartus_scaffold_check
|
||
@echo "=== quartus_compile_clean : wipe outputs then full flow ==="
|
||
@$(TOP_PSMCT32_DEMO_BUILD_SH) clean
|
||
|
||
quartus_syn_only: top_psmct32_raster_demo_quartus_scaffold_check
|
||
@echo "=== quartus_syn_only : synthesis only (fast smoke) ==="
|
||
@$(TOP_PSMCT32_DEMO_BUILD_SH) syn-only
|
||
|
||
quartus_compile_report: top_psmct32_raster_demo_quartus_scaffold_check
|
||
@echo "=== quartus_compile_report : parse + summarize last build ==="
|
||
@$(PYTHON) $(TOP_PSMCT32_DEMO_SYNTH_DIR)/parse_reports.py \
|
||
$(TOP_PSMCT32_DEMO_SYNTH_DIR)/output_files
|
||
|
||
# ---------------------------------------------------------------------
|
||
# Ch153 — memory-forensics experiments.
|
||
# ---------------------------------------------------------------------
|
||
# Compiles a small set of standalone Quartus projects (one per
|
||
# experiment subdirectory under synth/de25_nano/experiments/) that
|
||
# isolate one or more memory-shape features at a time. Each project
|
||
# targets the same Agilex 5 part as the main board top so resource
|
||
# deltas are apples-to-apples.
|
||
#
|
||
# Current experiments:
|
||
# exp_a_bram_friendly — single-port sync read + sync write +
|
||
# per-byte WE, 2048×32-bit (Intel-friendly).
|
||
# exp_b_vram_shape — exact vram_stub shape (8192×8-bit, dual
|
||
# combinational read, byte-WE + per-bit
|
||
# mask RMW).
|
||
EXPERIMENTS_DIR := $(REPO_ROOT)/synth/de25_nano/experiments
|
||
|
||
quartus_experiments:
|
||
@echo "=== quartus_experiments : compile Ch153 memory-forensics projects ==="
|
||
@$(EXPERIMENTS_DIR)/run_experiments.sh
|
||
|
||
quartus_experiments_clean:
|
||
@echo "=== quartus_experiments_clean : wipe outputs then compile ==="
|
||
@$(EXPERIMENTS_DIR)/run_experiments.sh clean
|
||
|
||
quartus_experiments_report:
|
||
@echo "=== quartus_experiments_report : side-by-side resource summary ==="
|
||
@$(PYTHON) $(EXPERIMENTS_DIR)/parse_experiments.py $(EXPERIMENTS_DIR)/exp_*
|
||
|
||
|
||
# Must compile in dependency order; trace_pkg first.
|
||
RTL_SRCS := \
|
||
$(RTL_ROOT)/debug/trace_pkg.sv \
|
||
$(RTL_ROOT)/debug/trace_sink_stub.sv \
|
||
$(RTL_ROOT)/memory/bios_rom_stub.sv \
|
||
$(RTL_ROOT)/memory/ee_memory_map_stub.sv \
|
||
$(RTL_ROOT)/memory/ee_ram_stub.sv \
|
||
$(RTL_ROOT)/ee/ee_fetch_stub.sv \
|
||
$(RTL_ROOT)/ee/ee_core_stub.sv \
|
||
$(RTL_ROOT)/ee/ee_bootstrap_mmio_stub.sv \
|
||
$(RTL_ROOT)/ee/ee_biu_mmio_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_grad_divider.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_prim_list_feeder.sv \
|
||
$(RTL_ROOT)/gif_gs/gif_path_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/gif_packed_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/vram_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/vram_bram_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/vram_normalize_pkg.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_pcrtc_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/clut_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/clut_loader_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/gif_image_xfer_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/ee_gs_priv_bridge_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_swizzle_psmct32_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_swizzle_psmct16_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_swizzle_psmt8_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_swizzle_psmt4_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_texel_addr.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_texture_unit.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_reciprocal_stub.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_persp_uv.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_tile_ram.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_alpha_blend.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_lpddr_fb_writer.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_async_fifo.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_lpddr_axi_master.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_lpddr_rd_probe.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_lpddr_scanout.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_lpddr_rd_arb.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_lpddr_scanout_lb.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_texture_cache.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_lpddr_wr_probe.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_lpddr_wr_arb.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_tile_reload.sv \
|
||
$(RTL_ROOT)/gif_gs/gs_z_flush_writer.sv \
|
||
$(RTL_ROOT)/platform/platform_video_stub.sv \
|
||
$(RTL_ROOT)/platform/I2C_Controller.v \
|
||
$(RTL_ROOT)/platform/I2C_HDMI_Config.v \
|
||
$(RTL_ROOT)/platform/ps2_hps_bridge_null.sv \
|
||
$(RTL_ROOT)/platform/ps2_hps_bridge.sv \
|
||
$(RTL_ROOT)/platform/tile_ram_cdc.sv \
|
||
$(SPLASH_PLATFORM_RTL)/osd_overlay.sv \
|
||
$(SPLASH_PLATFORM_RTL)/osd_font_rom.sv \
|
||
$(SPLASH_PLATFORM_RTL)/osd_menu_fsm.sv \
|
||
$(SPLASH_PLATFORM_RTL)/ds2_controller.sv \
|
||
$(REPO_ROOT)/qsys/qsys_top/qsys_top_bb.v \
|
||
$(RTL_ROOT)/intc/intc_stub.sv \
|
||
$(RTL_ROOT)/dmac/dmac_reg_stub.sv \
|
||
$(RTL_ROOT)/dmac/ee_dmac_ctrl_stub.sv \
|
||
$(RTL_ROOT)/dmac/ee_dmac_passive_chan_stub.sv \
|
||
$(RTL_ROOT)/sif/sif_mailbox_stub.sv \
|
||
$(RTL_ROOT)/sif/sif_mailbox_peer_stub.sv \
|
||
$(RTL_ROOT)/sif/sif_dma_stub.sv \
|
||
$(RTL_ROOT)/sif/sif_dma_ack_peer_stub.sv \
|
||
$(RTL_ROOT)/sif/sif_dma_iop_ram_bridge_stub.sv \
|
||
$(RTL_ROOT)/sif/sif_dma_ee_ram_bridge_stub.sv \
|
||
$(RTL_ROOT)/sif/sif_dma_ee_ack_peer_stub.sv \
|
||
$(RTL_ROOT)/sif/boot_install_agent_stub.sv \
|
||
$(RTL_ROOT)/iop/iop_ram_stub.sv \
|
||
$(RTL_ROOT)/iop/sio2_input_stub.sv \
|
||
$(RTL_ROOT)/iop/iop_memory_map_stub.sv \
|
||
$(RTL_ROOT)/iop/iop_fetch_stub.sv \
|
||
$(RTL_ROOT)/iop/iop_dmac_reg_stub.sv \
|
||
$(RTL_ROOT)/iop/iop_exec_stub.sv \
|
||
$(RTL_ROOT)/iop/iop_core_stub.sv \
|
||
$(RTL_ROOT)/top/top_psmct32_raster_demo.sv \
|
||
$(RTL_ROOT)/top/top_psmct32_raster_demo_bram.sv \
|
||
$(RTL_ROOT)/top/de25_nano_pll_stub.sv \
|
||
$(RTL_ROOT)/top/de25_nano_psmct32_raster_demo_top.sv
|
||
|
||
IVERILOG := iverilog
|
||
IVERILOG_FLGS := -g2012 -Wall
|
||
VVP := vvp
|
||
|
||
VERILATOR := verilator
|
||
VERILATOR_FLAGS := --lint-only -sv -Wall -Wno-UNUSED -Wno-DECLFILENAME \
|
||
--timing
|
||
|
||
.PHONY: tb_ee_core_bios_long
|
||
.PHONY: top_psmct32_raster_demo_mem top_psmct32_raster_demo_mem_check top_psmct32_raster_demo_synth_check top_psmct32_raster_demo_quartus_scaffold_check quartus_compile quartus_compile_clean quartus_syn_only quartus_compile_report quartus_experiments quartus_experiments_clean quartus_experiments_report
|
||
.PHONY: all lint run clean traces tb_ee_fetch tb_gs tb_intc tb_platform_video tb_bgcolor_via_dma \
|
||
tb_sif_mailbox tb_sif_command_echo tb_sif_command_echo_rearm tb_sif_negative_path \
|
||
tb_sif_dma_smoke tb_sif_dma_mid_stall tb_sif_dma_overflow tb_sif_combined_ctrl_data \
|
||
tb_iop_ram tb_iop_memory_map tb_iop_memory_map_collision tb_iop_fetch_through_map tb_sif_iop_bridge_smoke \
|
||
tb_sif_iop_bridge_exec tb_iop_to_sif_via_map tb_iop_dmac_via_map \
|
||
tb_sif_ee_landing_via_dmac tb_sif_iop_driven_combined \
|
||
tb_ee_dmac_intc tb_iop_dmac_intc tb_iop_self_driven \
|
||
tb_iop_autonomous_two_xfers tb_iop_responder_ee_ram_landing \
|
||
tb_iop_core_basic tb_iop_core_interrupts \
|
||
tb_iop_core_bootstrap tb_iop_core_bootstrap_intc tb_iop_core_bios_smoke \
|
||
tb_ee_core_basic tb_ee_core_memops tb_ee_core_dmac \
|
||
tb_ee_core_dmac_poll tb_ee_core_dmac_intc tb_ee_core_bios_smoke \
|
||
tb_ee_core_slti tb_ee_core_addi tb_ee_core_andi tb_ee_core_cache \
|
||
tb_ee_core_rtype_logic tb_ee_core_sb tb_ee_core_lb tb_ee_core_jal \
|
||
tb_ee_core_rtype_addu tb_ee_core_slt tb_ee_core_lh tb_ee_core_lhu \
|
||
tb_ee_core_shift tb_ee_core_sh tb_ee_core_jalr tb_ee_core_add_sub \
|
||
tb_ee_core_branch_zero tb_ee_core_lbu tb_ee_core_divu_mflo tb_ee_core_multu_mflo \
|
||
tb_ee_core_align tb_ee_core_align_exc tb_ee_core_bev \
|
||
tb_ee_core_cop0_count tb_ee_bootstrap_mmio tb_ee_biu_mmio \
|
||
tb_ee_core_gif_packed tb_ee_core_gif_reglist tb_ee_core_gif_primitive tb_ee_core_gif_primitive_observer tb_ee_core_gif_primitive_strip tb_ee_core_gif_primitive_gouraud tb_ee_core_gif_pixel_emit tb_ee_core_gif_pixel_emit_psm tb_ee_core_gif_raster_basic tb_ee_core_gif_raster_topleft tb_ee_core_gif_raster_gouraud tb_ee_core_gif_raster_queue tb_gs_raster_queue_full_pop tb_gs_raster_pipeline tb_gs_prim_list_feeder tb_gs_vram_writeback tb_vram_stub tb_vram_bram_stub_equivalence tb_vram_normalize_write tb_gs_scanout_basic tb_gs_scanout_dbx_dby tb_gs_scanout_display_window tb_gs_scanout_magh_magv tb_gs_scanout_psm16 tb_gs_scanout_psmt8 tb_gs_scanout_psmt8_clut tb_gs_tex0_clut tb_gs_clut_load tb_gs_clut_load_ct16 tb_gs_clut_load_cld_modes tb_gs_clut_load_csa_window tb_gs_scanout_psmt4_clut tb_gs_psmt4_round_trip tb_gs_raster_psmct16 tb_gs_raster_psmt8 tb_gs_textured_sprite tb_gs_textured_alpha_sprite tb_gs_psmt8_alpha_sprite tb_gs_psmt8_clut_triangle tb_clut_loader_csm1 tb_gs_raster_psmt4 tb_gs_demo_psmt4_e2e tb_gs_demo_psmt4_e2e_packed tb_gs_demo_psmt4_e2e_dmac tb_gs_demo_psmt4_e2e_trxdir tb_gs_demo_psmt4_e2e_eemmio tb_gs_demo_psmt4_e2e_eemap tb_gs_demo_psmt4_e2e_ee_program tb_gs_demo_psmt4_e2e_ee_full_bootlet tb_ee_ram_cpu_dmac_contention tb_gs_image_xfer_psmct16 tb_gs_image_xfer_psmt8 tb_gs_image_xfer_psmt4 tb_gs_swizzle_psmct32 tb_gs_swizzle_psmct16 tb_gs_swizzle_psmt8 tb_gs_swizzle_psmt4 tb_gs_scanout_swizzle_psmt4 tb_gs_image_xfer_swizzle_psmt4 tb_gs_raster_swizzle_psmt4 tb_gs_demo_psmt4_swizzle_e2e tb_gs_demo_psmt4_swizzle_trxdir_e2e tb_top_psmct32_raster_demo tb_top_psmct32_textured_demo tb_top_psmct32_raster_demo_bram tb_top_psmct32_raster_demo_bram_textured tb_top_psmct32_raster_demo_bram_ch171 tb_gs_raster_backpressure_stress tb_ps2_hps_bridge tb_gs_raster_bram_psmct16 tb_gs_raster_bram_psmt8 tb_gs_raster_bram_psmt4 tb_gs_scanout_bram_psmct16 tb_gs_scanout_bram_psmt8 tb_de25_nano_psmct32_raster_demo_top tb_hdmi_i2c_wake_smoke tb_gs_scanout_swizzle_psmt8 tb_gs_image_xfer_swizzle_psmt8 tb_gs_raster_swizzle_psmt8 tb_gs_demo_psmt8_swizzle_e2e tb_gs_demo_psmt8_swizzle_trxdir_e2e tb_gs_scanout_swizzle_psmct16 tb_gs_image_xfer_swizzle_psmct16 tb_gs_scanout_swizzle_psmct32 tb_gs_image_xfer_swizzle_psmct32 tb_gs_raster_swizzle_psmct32 tb_gs_raster_swizzle_psmct16 tb_gs_demo_psmct32_swizzle_e2e tb_gs_demo_psmct32_swizzle_trxdir_e2e tb_gs_demo_psmct16_swizzle_e2e tb_gs_demo_psmct16_swizzle_trxdir_e2e tb_ee_core_varshift tb_ee_install_agent_smoke tb_ee_install_agent_external_image tb_tile_ram_cdc tb_sio2_input_stub tb_bridge_iop_pad_input tb_pad_state_via_sif_to_ee tb_ee_pad_buffer_branch tb_lpddr_tex_staging tb_osd_platform_cell_adapter tb_ee_core_elf_runner tb_ee_core_sq tb_ee_core_daddu tb_ee_core_syscall_hle tb_ee_core_beql tb_ee_core_sd tb_ee_core_dsll tb_ee_core_bnel tb_ee_core_pcpyld tb_ee_core_lq tb_ee_core_psubb tb_ee_core_pnor tb_ee_core_pand tb_ee_core_pcpyud tb_ee_core_ld tb_ee_core_ei tb_ee_dmac_ctrl_stub tb_ee_dmac_passive_chan_stub tb_ee_core_sync tb_ee_core_pcpyh tb_ee_core_dsubu tb_gs_lpddr_fb_writer tb_gs_lpddr_axi_master tb_gs_lpddr_rd_probe tb_gs_lpddr_scanout tb_gs_lpddr_scanout_psm32 tb_gs_lpddr_scanout_concurrency tb_gs_lpddr_scanout_lb_psm32 tb_gs_lpddr_scanout_lb_psm32_256 tb_gs_lpddr_rd_arb tb_gs_lpddr_scanout_lb tb_gs_texture_cache tb_gs_lpddr_wr_probe tb_gs_lpddr_wr_arb tb_gs_tile_reload tb_gs_tile_reload_grid tb_gs_z_flush_writer tb_gs_alpha_blend tb_top_psmct32_alpha_blend_demo tb_top_psmct32_texalpha_demo tb_gs_zbuffer tb_top_psmct32_zbuffer_demo tb_gs_tri_interp tb_top_psmct32_triangle_demo tb_gs_textured_triangle tb_top_psmct32_raster_demo_bram_tritex tb_top_psmct32_raster_demo_bram_lpddrtex tb_gs_texture_psmt8_clut tb_gs_texture_wrap tb_gs_texture_bilinear tb_top_psmct32_raster_demo_bram_clut tb_gs_texture_psmt4_clut tb_gs_texture_swizzle_psmt4_clut tb_top_psmct32_raster_demo_bram_clut4 tb_top_psmct32_raster_demo_bram_swz4 tb_gs_texture_swizzle_psmt8_clut tb_top_psmct32_raster_demo_bram_swz8 tb_gs_texture_swizzle_psmct32 tb_top_psmct32_raster_demo_bram_swz32 tb_gs_reciprocal tb_gs_persp_uv tb_gs_persp_uv_farw tb_gs_grad_divider tb_top_psmct32_perspective_demo tb_top_psmct32_persp_floor_demo tb_top_psmct32_combined_demo tb_gs_tile_ram tb_top_psmct32_tile_demo tb_gs_tile_zflush tb_gs_tile_spill_reload tb_gs_tile_spill_lpddr tb_gs_tile_spill_grid_lpddr tb_gs_tile_spill_grid8x8_lpddr tb_gs_tile_spill_lpddr_neg tb_top_psmct32_tile2x2_demo tb_top_psmct32_tile_multiprim_demo tb_top_psmct32_tile_scissor_demo tb_top_psmct32_tile_wrap_demo tb_top_psmct32_tile_psmct16_demo tb_top_psmct32_tile_alpha_demo tb_top_psmct32_tile_bilinear_demo tb_top_psmct32_tile_bin_demo tb_top_psmct32_tile_bin4x4_demo tb_top_psmct32_tile_psmct16fb_demo tb_top_psmct32_tile_lpddr128_demo tb_top_psmct32_tile_palbilinear_demo tb_top_psmct32_tile_cap_demo tb_top_psmct32_tile_cap_overflow_demo tb_top_psmct32_tile_sprite18_demo tb_top_psmct32_tile_cap64_demo tb_top_psmct32_feeder_equiv_demo tb_top_psmct32_feeder_runtime_demo tb_top_psmct32_feeder_bridge_demo tb_top_psmct32_feeder_scenes_demo tb_top_psmct32_feeder_shapes_demo tb_top_psmct32_feeder_colors_demo tb_top_psmct32_feeder_native_demo tb_top_psmct32_feeder_gouraud_demo tb_top_psmct32_feeder_accum_demo tb_top_psmct32_feeder_scene_retrigger_demo tb_top_psmct32_feeder_zpersist_demo tb_top_psmct32_feeder_persp_demo tb_top_psmct32_feeder_sprite_demo tb_top_psmct32_tile_late_demo tb_top_psmct32_tile_lpddrfb_demo \
|
||
dirs all_checks full_checks golden_nop compare_ee_fetch test_compare
|
||
|
||
all: run
|
||
|
||
# ---------------------------------------------------------------------
|
||
# Aggregate quality gate
|
||
# ---------------------------------------------------------------------
|
||
#
|
||
# "make lint" alone does not compile the testbenches — it only runs
|
||
# Verilator over RTL. "make all_checks" is the documented gate: lint +
|
||
# every testbench builds and runs.
|
||
#
|
||
all_checks: lint run
|
||
@echo
|
||
@echo "=== all_checks: lint + all testbenches green ==="
|
||
|
||
# Full regression: lint + all testbenches + golden-harness comparator
|
||
# (exercises the 0/1/3 exit-code paths). Use this when you want the widest
|
||
# possible "everything green" gate; use `all_checks` when you only care
|
||
# about RTL + bench health.
|
||
full_checks: all_checks test_compare
|
||
@echo
|
||
@echo "=== full_checks: all_checks + test_compare green ==="
|
||
|
||
dirs:
|
||
@mkdir -p $(BUILD_DIR) $(TRACE_DIR) $(GOLD_TRC_DIR)
|
||
@# Ch245 — the platform osd_font_rom.sv uses a CWD-relative
|
||
@# `$$readmemh("rtl/platform/cp437_8x8.mem", ...)`. When vvp
|
||
@# runs from $(TRACE_DIR), it needs that path to resolve.
|
||
@# Symlink retroDE_splash/rtl tree under it so the read works.
|
||
@mkdir -p $(TRACE_DIR)/rtl
|
||
@if [ ! -L $(TRACE_DIR)/rtl/platform ]; then \
|
||
ln -snf $(SPLASH_PLATFORM_RTL) $(TRACE_DIR)/rtl/platform; \
|
||
fi
|
||
|
||
# ---------------------------------------------------------------------
|
||
# Lint (Verilator, strict)
|
||
# ---------------------------------------------------------------------
|
||
|
||
lint:
|
||
@echo "=== verilator lint ==="
|
||
$(VERILATOR) $(VERILATOR_FLAGS) \
|
||
--top-module trace_sink_stub \
|
||
$(RTL_SRCS)
|
||
@echo "lint: OK"
|
||
|
||
# ---------------------------------------------------------------------
|
||
# Individual testbenches (Icarus Verilog)
|
||
# ---------------------------------------------------------------------
|
||
|
||
tb_ee_fetch: dirs
|
||
@echo "=== build tb_ee_fetch_stub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_fetch_stub.vvp \
|
||
-s tb_ee_fetch_stub \
|
||
$(RTL_SRCS) $(TB_ROOT)/ee/tb_ee_fetch_stub.sv
|
||
@echo "=== run tb_ee_fetch_stub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_fetch_stub.vvp
|
||
|
||
tb_gs: dirs
|
||
@echo "=== build tb_gs_stub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_stub.vvp \
|
||
-s tb_gs_stub \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_stub.sv
|
||
@echo "=== run tb_gs_stub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_stub.vvp
|
||
|
||
tb_gs_prim_list_feeder: dirs
|
||
@echo "=== build tb_gs_prim_list_feeder ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_prim_list_feeder.vvp \
|
||
-s tb_gs_prim_list_feeder \
|
||
$(RTL_ROOT)/gif_gs/gs_prim_list_feeder.sv $(TB_ROOT)/gif_gs/tb_gs_prim_list_feeder.sv
|
||
@echo "=== run tb_gs_prim_list_feeder ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_prim_list_feeder.vvp
|
||
|
||
tb_gs_raster_queue_full_pop: dirs
|
||
@echo "=== build tb_gs_raster_queue_full_pop ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_queue_full_pop.vvp \
|
||
-s tb_gs_raster_queue_full_pop \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_queue_full_pop.sv
|
||
@echo "=== run tb_gs_raster_queue_full_pop ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_queue_full_pop.vvp
|
||
|
||
tb_gs_raster_pipeline: dirs
|
||
@echo "=== build tb_gs_raster_pipeline ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_pipeline.vvp \
|
||
-s tb_gs_raster_pipeline \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_pipeline.sv
|
||
@echo "=== run tb_gs_raster_pipeline ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_pipeline.vvp
|
||
|
||
tb_gs_vram_writeback: dirs
|
||
@echo "=== build tb_gs_vram_writeback ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_vram_writeback.vvp \
|
||
-s tb_gs_vram_writeback \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_vram_writeback.sv
|
||
@echo "=== run tb_gs_vram_writeback ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_vram_writeback.vvp
|
||
|
||
tb_vram_stub: dirs
|
||
@echo "=== build tb_vram_stub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_vram_stub.vvp \
|
||
-s tb_vram_stub \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_vram_stub.sv
|
||
@echo "=== run tb_vram_stub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_vram_stub.vvp
|
||
|
||
tb_vram_bram_stub_equivalence: dirs
|
||
@echo "=== build tb_vram_bram_stub_equivalence ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_vram_bram_stub_equivalence.vvp \
|
||
-s tb_vram_bram_stub_equivalence \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_vram_bram_stub_equivalence.sv
|
||
@echo "=== run tb_vram_bram_stub_equivalence ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_vram_bram_stub_equivalence.vvp
|
||
|
||
tb_vram_normalize_write: dirs
|
||
@echo "=== build tb_vram_normalize_write ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_vram_normalize_write.vvp \
|
||
-s tb_vram_normalize_write \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_vram_normalize_write.sv
|
||
@echo "=== run tb_vram_normalize_write ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_vram_normalize_write.vvp
|
||
|
||
tb_gs_scanout_basic: dirs
|
||
@echo "=== build tb_gs_scanout_basic ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_basic.vvp \
|
||
-s tb_gs_scanout_basic \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_basic.sv
|
||
@echo "=== run tb_gs_scanout_basic ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_basic.vvp
|
||
|
||
tb_gs_scanout_dbx_dby: dirs
|
||
@echo "=== build tb_gs_scanout_dbx_dby ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_dbx_dby.vvp \
|
||
-s tb_gs_scanout_dbx_dby \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_dbx_dby.sv
|
||
@echo "=== run tb_gs_scanout_dbx_dby ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_dbx_dby.vvp
|
||
|
||
tb_gs_scanout_display_window: dirs
|
||
@echo "=== build tb_gs_scanout_display_window ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_display_window.vvp \
|
||
-s tb_gs_scanout_display_window \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_display_window.sv
|
||
@echo "=== run tb_gs_scanout_display_window ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_display_window.vvp
|
||
|
||
tb_gs_scanout_magh_magv: dirs
|
||
@echo "=== build tb_gs_scanout_magh_magv ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_magh_magv.vvp \
|
||
-s tb_gs_scanout_magh_magv \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_magh_magv.sv
|
||
@echo "=== run tb_gs_scanout_magh_magv ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_magh_magv.vvp
|
||
|
||
tb_gs_scanout_psm16: dirs
|
||
@echo "=== build tb_gs_scanout_psm16 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_psm16.vvp \
|
||
-s tb_gs_scanout_psm16 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_psm16.sv
|
||
@echo "=== run tb_gs_scanout_psm16 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_psm16.vvp
|
||
|
||
tb_gs_raster_psmct16: dirs
|
||
@echo "=== build tb_gs_raster_psmct16 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_psmct16.vvp \
|
||
-s tb_gs_raster_psmct16 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_psmct16.sv
|
||
@echo "=== run tb_gs_raster_psmct16 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_psmct16.vvp
|
||
|
||
tb_gs_raster_psmt8: dirs
|
||
@echo "=== build tb_gs_raster_psmt8 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_psmt8.vvp \
|
||
-s tb_gs_raster_psmt8 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_psmt8.sv
|
||
@echo "=== run tb_gs_raster_psmt8 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_psmt8.vvp
|
||
|
||
tb_gs_textured_sprite: dirs
|
||
@echo "=== build tb_gs_textured_sprite ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_textured_sprite.vvp \
|
||
-s tb_gs_textured_sprite \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_textured_sprite.sv
|
||
@echo "=== run tb_gs_textured_sprite ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_textured_sprite.vvp
|
||
|
||
# Ch344 — synthetic textured + source-over alpha SPRITE unit test (SPRITE_TEX_ALPHA=1).
|
||
# Proves: no read2 overlap (tex_rd_en & fb_rd_en never both high), As from the texel, MODULATE by
|
||
# the vertex tint, output matches an independent software source-over reference.
|
||
tb_gs_textured_alpha_sprite: dirs
|
||
@echo "=== build tb_gs_textured_alpha_sprite ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_textured_alpha_sprite.vvp \
|
||
-s tb_gs_textured_alpha_sprite \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_textured_alpha_sprite.sv
|
||
@echo "=== run tb_gs_textured_alpha_sprite ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_textured_alpha_sprite.vvp
|
||
|
||
|
||
tb_gs_textured_triangle: dirs
|
||
@echo "=== build tb_gs_textured_triangle ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_textured_triangle.vvp \
|
||
-s tb_gs_textured_triangle \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_textured_triangle.sv
|
||
@echo "=== run tb_gs_textured_triangle ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_textured_triangle.vvp
|
||
|
||
# Ch296 — PSMT8 indexed texture sampling (gs_texture_unit + clut_stub):
|
||
# index-fetch -> CLUT lookup -> PSMCT32 color. The 4 sampler proofs.
|
||
tb_gs_texture_psmt8_clut: dirs
|
||
@echo "=== build tb_gs_texture_psmt8_clut ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_texture_psmt8_clut.vvp \
|
||
-s tb_gs_texture_psmt8_clut \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_psmt8_clut.sv
|
||
@echo "=== run tb_gs_texture_psmt8_clut ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_psmt8_clut.vvp
|
||
|
||
tb_gs_psmt8_alpha_sprite: dirs
|
||
@echo "=== build tb_gs_psmt8_alpha_sprite ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_psmt8_alpha_sprite.vvp \
|
||
-s tb_gs_psmt8_alpha_sprite \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_psmt8_alpha_sprite.sv
|
||
@echo "=== run tb_gs_psmt8_alpha_sprite ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_psmt8_alpha_sprite.vvp
|
||
|
||
tb_gs_psmt8_clut_triangle: dirs
|
||
@echo "=== build tb_gs_psmt8_clut_triangle ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_psmt8_clut_triangle.vvp \
|
||
-s tb_gs_psmt8_clut_triangle \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_psmt8_clut_triangle.sv
|
||
@echo "=== run tb_gs_psmt8_clut_triangle ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_psmt8_clut_triangle.vvp
|
||
|
||
tb_clut_loader_csm1: dirs
|
||
@echo "=== build tb_clut_loader_csm1 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_clut_loader_csm1.vvp \
|
||
-s tb_clut_loader_csm1 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_clut_loader_csm1.sv
|
||
@echo "=== run tb_clut_loader_csm1 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_clut_loader_csm1.vvp
|
||
|
||
tb_gs_sh3_clut_sprite: dirs
|
||
@echo "=== build tb_gs_sh3_clut_sprite ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_sh3_clut_sprite.vvp \
|
||
-s tb_gs_sh3_clut_sprite \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_sh3_clut_sprite.sv
|
||
@echo "=== run tb_gs_sh3_clut_sprite ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_sh3_clut_sprite.vvp
|
||
|
||
tb_gs_texture_wrap: dirs
|
||
@echo "=== build tb_gs_texture_wrap ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_texture_wrap.vvp \
|
||
-s tb_gs_texture_wrap \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_wrap.sv
|
||
@echo "=== run tb_gs_texture_wrap ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_wrap.vvp
|
||
|
||
tb_gs_texture_bilinear: dirs
|
||
@echo "=== build tb_gs_texture_bilinear ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_texture_bilinear.vvp \
|
||
-s tb_gs_texture_bilinear \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_bilinear.sv
|
||
@echo "=== run tb_gs_texture_bilinear ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_bilinear.vvp
|
||
|
||
# Ch297 — PSMT4 indexed texture sampling (gs_texture_unit nibble extract +
|
||
# clut_stub): nibble-select -> CLUT lookup -> PSMCT32 color. The 4 sampler
|
||
# proofs (incl. SEL_DELAY=1 nibble re-pair) + PSMT8/PSMCT32 bit-identical.
|
||
tb_gs_texture_psmt4_clut: dirs
|
||
@echo "=== build tb_gs_texture_psmt4_clut ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_texture_psmt4_clut.vvp \
|
||
-s tb_gs_texture_psmt4_clut \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_psmt4_clut.sv
|
||
@echo "=== run tb_gs_texture_psmt4_clut ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_psmt4_clut.vvp
|
||
|
||
# Ch298 — SWIZZLED PSMT4 texture sampling (gs_texture_unit PSMT4_SWIZZLE=1 ->
|
||
# gs_swizzle_psmt4_stub addr/nibble). Proves swizzled read recovers the logical
|
||
# pattern across BLOCK and PAGE boundaries, swizzled!=linear for the same bytes,
|
||
# CLUT indirection, and SEL_DELAY=1 alignment of the swizzled selectors.
|
||
tb_gs_texture_swizzle_psmt4_clut: dirs
|
||
@echo "=== build tb_gs_texture_swizzle_psmt4_clut ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_texture_swizzle_psmt4_clut.vvp \
|
||
-s tb_gs_texture_swizzle_psmt4_clut \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_swizzle_psmt4_clut.sv
|
||
@echo "=== run tb_gs_texture_swizzle_psmt4_clut ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_swizzle_psmt4_clut.vvp
|
||
|
||
tb_gs_texture_swizzle_psmt8_clut: dirs
|
||
@echo "=== build tb_gs_texture_swizzle_psmt8_clut ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_texture_swizzle_psmt8_clut.vvp \
|
||
-s tb_gs_texture_swizzle_psmt8_clut \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_swizzle_psmt8_clut.sv
|
||
@echo "=== run tb_gs_texture_swizzle_psmt8_clut ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_swizzle_psmt8_clut.vvp
|
||
|
||
tb_gs_texture_swizzle_psmct32: dirs
|
||
@echo "=== build tb_gs_texture_swizzle_psmct32 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_texture_swizzle_psmct32.vvp \
|
||
-s tb_gs_texture_swizzle_psmct32 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_swizzle_psmct32.sv
|
||
@echo "=== run tb_gs_texture_swizzle_psmct32 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_swizzle_psmct32.vvp
|
||
|
||
tb_gs_reciprocal: dirs
|
||
@echo "=== build tb_gs_reciprocal ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_reciprocal.vvp \
|
||
-s tb_gs_reciprocal \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_reciprocal.sv
|
||
@echo "=== run tb_gs_reciprocal ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_reciprocal.vvp
|
||
|
||
tb_gs_persp_uv_farw: dirs
|
||
@echo "=== build tb_gs_persp_uv_farw ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_persp_uv_farw.vvp \
|
||
-s tb_gs_persp_uv_farw \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_persp_uv_farw.sv
|
||
@echo "=== run tb_gs_persp_uv_farw ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_persp_uv_farw.vvp
|
||
|
||
tb_gs_persp_uv: dirs
|
||
@echo "=== build tb_gs_persp_uv ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_persp_uv.vvp \
|
||
-s tb_gs_persp_uv \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_persp_uv.sv
|
||
@echo "=== run tb_gs_persp_uv ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_persp_uv.vvp
|
||
|
||
tb_gs_tile_ram: dirs
|
||
@echo "=== build tb_gs_tile_ram ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_tile_ram.vvp \
|
||
-s tb_gs_tile_ram \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_tile_ram.sv
|
||
@echo "=== run tb_gs_tile_ram ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_ram.vvp
|
||
|
||
tb_gs_alpha_blend: dirs
|
||
@echo "=== build tb_gs_alpha_blend ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_alpha_blend.vvp \
|
||
-s tb_gs_alpha_blend \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_alpha_blend.sv
|
||
@echo "=== run tb_gs_alpha_blend ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_alpha_blend.vvp
|
||
|
||
tb_gs_lpddr_fb_writer: dirs
|
||
@echo "=== build tb_gs_lpddr_fb_writer ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_fb_writer.vvp \
|
||
-s tb_gs_lpddr_fb_writer \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_fb_writer.sv
|
||
@echo "=== run tb_gs_lpddr_fb_writer ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_fb_writer.vvp
|
||
|
||
tb_gs_lpddr_axi_master: dirs
|
||
@echo "=== build tb_gs_lpddr_axi_master ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_axi_master.vvp \
|
||
-s tb_gs_lpddr_axi_master \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_axi_master.sv
|
||
@echo "=== run tb_gs_lpddr_axi_master ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_axi_master.vvp
|
||
|
||
tb_gs_grad_divider: dirs
|
||
@echo "=== build tb_gs_grad_divider ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_grad_divider.vvp \
|
||
-s tb_gs_grad_divider \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_grad_divider.sv
|
||
@echo "=== run tb_gs_grad_divider ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_grad_divider.vvp
|
||
|
||
tb_gs_lpddr_rd_probe: dirs
|
||
@echo "=== build tb_gs_lpddr_rd_probe ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_rd_probe.vvp \
|
||
-s tb_gs_lpddr_rd_probe \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_rd_probe.sv
|
||
@echo "=== run tb_gs_lpddr_rd_probe ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_rd_probe.vvp
|
||
|
||
tb_gs_lpddr_scanout: dirs
|
||
@echo "=== build tb_gs_lpddr_scanout ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_scanout.vvp \
|
||
-s tb_gs_lpddr_scanout \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout.sv
|
||
@echo "=== run tb_gs_lpddr_scanout ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout.vvp
|
||
|
||
tb_gs_lpddr_scanout_lb_psm32_256: dirs
|
||
@echo "=== build tb_gs_lpddr_scanout_lb_psm32_256 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_psm32_256.vvp \
|
||
-s tb_gs_lpddr_scanout_lb_psm32_256 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_lb_psm32_256.sv
|
||
@echo "=== run tb_gs_lpddr_scanout_lb_psm32_256 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_psm32_256.vvp
|
||
|
||
tb_gs_lpddr_scanout_lb_psm32: dirs
|
||
@echo "=== build tb_gs_lpddr_scanout_lb_psm32 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_psm32.vvp \
|
||
-s tb_gs_lpddr_scanout_lb_psm32 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_lb_psm32.sv
|
||
@echo "=== run tb_gs_lpddr_scanout_lb_psm32 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_psm32.vvp
|
||
|
||
tb_gs_lpddr_scanout_concurrency: dirs
|
||
@echo "=== build tb_gs_lpddr_scanout_concurrency ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_scanout_concurrency.vvp \
|
||
-s tb_gs_lpddr_scanout_concurrency \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_concurrency.sv
|
||
@echo "=== run tb_gs_lpddr_scanout_concurrency ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_concurrency.vvp
|
||
|
||
tb_gs_lpddr_scanout_psm32: dirs
|
||
@echo "=== build tb_gs_lpddr_scanout_psm32 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_scanout_psm32.vvp \
|
||
-s tb_gs_lpddr_scanout_psm32 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_psm32.sv
|
||
@echo "=== run tb_gs_lpddr_scanout_psm32 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_psm32.vvp
|
||
|
||
tb_gs_lpddr_rd_arb: dirs
|
||
@echo "=== build tb_gs_lpddr_rd_arb ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_rd_arb.vvp \
|
||
-s tb_gs_lpddr_rd_arb \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_rd_arb.sv
|
||
@echo "=== run tb_gs_lpddr_rd_arb ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_rd_arb.vvp
|
||
|
||
tb_gs_lpddr_scanout_lb: dirs
|
||
@echo "=== build tb_gs_lpddr_scanout_lb ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_scanout_lb.vvp \
|
||
-s tb_gs_lpddr_scanout_lb \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_lb.sv
|
||
@echo "=== run tb_gs_lpddr_scanout_lb ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_lb.vvp
|
||
|
||
tb_gs_texture_cache: dirs
|
||
@echo "=== build tb_gs_texture_cache ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_texture_cache.vvp \
|
||
-s tb_gs_texture_cache \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_cache.sv
|
||
@echo "=== run tb_gs_texture_cache ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_cache.vvp
|
||
|
||
tb_gs_lpddr_wr_probe: dirs
|
||
@echo "=== build tb_gs_lpddr_wr_probe ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_wr_probe.vvp \
|
||
-s tb_gs_lpddr_wr_probe \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_wr_probe.sv
|
||
@echo "=== run tb_gs_lpddr_wr_probe ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_wr_probe.vvp
|
||
|
||
tb_gs_lpddr_wr_arb: dirs
|
||
@echo "=== build tb_gs_lpddr_wr_arb ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_lpddr_wr_arb.vvp \
|
||
-s tb_gs_lpddr_wr_arb \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_wr_arb.sv
|
||
@echo "=== run tb_gs_lpddr_wr_arb ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_wr_arb.vvp
|
||
|
||
tb_gs_tile_reload: dirs
|
||
@echo "=== build tb_gs_tile_reload ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_tile_reload.vvp \
|
||
-s tb_gs_tile_reload \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_tile_reload.sv
|
||
@echo "=== run tb_gs_tile_reload ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_reload.vvp
|
||
|
||
tb_gs_tile_reload_grid: dirs
|
||
@echo "=== build tb_gs_tile_reload_grid ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_tile_reload_grid.vvp \
|
||
-s tb_gs_tile_reload_grid \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_tile_reload_grid.sv
|
||
@echo "=== run tb_gs_tile_reload_grid ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_reload_grid.vvp
|
||
|
||
tb_gs_z_flush_writer: dirs
|
||
@echo "=== build tb_gs_z_flush_writer ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_z_flush_writer.vvp \
|
||
-s tb_gs_z_flush_writer \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_z_flush_writer.sv
|
||
@echo "=== run tb_gs_z_flush_writer ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_z_flush_writer.vvp
|
||
|
||
tb_gs_zbuffer: dirs
|
||
@echo "=== build tb_gs_zbuffer ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_zbuffer.vvp \
|
||
-s tb_gs_zbuffer \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_zbuffer.sv
|
||
@echo "=== run tb_gs_zbuffer ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_zbuffer.vvp
|
||
|
||
tb_top_psmct32_zbuffer_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_zbuffer_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_zbuffer.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_zbuffer.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_zbuffer_demo.vvp \
|
||
-s tb_top_psmct32_zbuffer_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_zbuffer_demo.sv
|
||
@echo "=== run tb_top_psmct32_zbuffer_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_zbuffer_demo.vvp
|
||
|
||
# Brick 3 — focused TRI affine interpolation (coverage + color + depth).
|
||
tb_gs_tri_interp: dirs
|
||
@echo "=== build tb_gs_tri_interp ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_tri_interp.vvp \
|
||
-s tb_gs_tri_interp \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_tri_interp.sv
|
||
@echo "=== run tb_gs_tri_interp ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tri_interp.vvp
|
||
|
||
# Brick 3 — top-level non-axis-aligned triangle demo on the BRAM board path.
|
||
tb_top_psmct32_triangle_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_triangle_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_triangle.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_triangle.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_triangle_demo.vvp \
|
||
-s tb_top_psmct32_triangle_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_triangle_demo.sv
|
||
@echo "=== run tb_top_psmct32_triangle_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_triangle_demo.vvp
|
||
|
||
tb_top_psmct32_alpha_blend_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_alpha_blend_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_alpha.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_alpha.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_alpha_blend_demo.vvp \
|
||
-s tb_top_psmct32_alpha_blend_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_alpha_blend_demo.sv
|
||
@echo "=== run tb_top_psmct32_alpha_blend_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_alpha_blend_demo.vvp
|
||
|
||
# Ch344 — TEXTURED + source-over alpha SPRITE demo on the bram board variant (SPRITE_TEX_ALPHA=1),
|
||
# registered-read2 integration. 8x8 alpha-checker texture blended over a blue BG.
|
||
tb_top_psmct32_texalpha_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_texalpha_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_texalpha.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_texalpha.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_texalpha_demo.vvp \
|
||
-s tb_top_psmct32_texalpha_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_texalpha_demo.sv
|
||
@echo "=== run tb_top_psmct32_texalpha_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_texalpha_demo.vvp
|
||
|
||
tb_gs_raster_psmt4: dirs
|
||
@echo "=== build tb_gs_raster_psmt4 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_psmt4.vvp \
|
||
-s tb_gs_raster_psmt4 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_psmt4.sv
|
||
@echo "=== run tb_gs_raster_psmt4 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_psmt4.vvp
|
||
|
||
tb_gs_demo_psmt4_e2e: dirs
|
||
@echo "=== build tb_gs_demo_psmt4_e2e ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e.vvp \
|
||
-s tb_gs_demo_psmt4_e2e \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e.sv
|
||
@echo "=== run tb_gs_demo_psmt4_e2e ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e.vvp
|
||
|
||
tb_gs_demo_psmt4_e2e_packed: dirs
|
||
@echo "=== build tb_gs_demo_psmt4_e2e_packed ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_packed.vvp \
|
||
-s tb_gs_demo_psmt4_e2e_packed \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_packed.sv
|
||
@echo "=== run tb_gs_demo_psmt4_e2e_packed ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_packed.vvp
|
||
|
||
tb_gs_demo_psmt4_e2e_dmac: dirs
|
||
@echo "=== build tb_gs_demo_psmt4_e2e_dmac ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_dmac.vvp \
|
||
-s tb_gs_demo_psmt4_e2e_dmac \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_dmac.sv
|
||
@echo "=== run tb_gs_demo_psmt4_e2e_dmac ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_dmac.vvp
|
||
|
||
tb_gs_demo_psmt4_e2e_trxdir: dirs
|
||
@echo "=== build tb_gs_demo_psmt4_e2e_trxdir ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_trxdir.vvp \
|
||
-s tb_gs_demo_psmt4_e2e_trxdir \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_trxdir.sv
|
||
@echo "=== run tb_gs_demo_psmt4_e2e_trxdir ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_trxdir.vvp
|
||
|
||
tb_gs_demo_psmt4_e2e_eemmio: dirs
|
||
@echo "=== build tb_gs_demo_psmt4_e2e_eemmio ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_eemmio.vvp \
|
||
-s tb_gs_demo_psmt4_e2e_eemmio \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_eemmio.sv
|
||
@echo "=== run tb_gs_demo_psmt4_e2e_eemmio ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_eemmio.vvp
|
||
|
||
tb_gs_demo_psmt4_e2e_eemap: dirs
|
||
@echo "=== build tb_gs_demo_psmt4_e2e_eemap ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_eemap.vvp \
|
||
-s tb_gs_demo_psmt4_e2e_eemap \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_eemap.sv
|
||
@echo "=== run tb_gs_demo_psmt4_e2e_eemap ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_eemap.vvp
|
||
|
||
tb_gs_demo_psmt4_e2e_ee_program: dirs
|
||
@echo "=== build tb_gs_demo_psmt4_e2e_ee_program ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_ee_program.vvp \
|
||
-s tb_gs_demo_psmt4_e2e_ee_program \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_ee_program.sv
|
||
@echo "=== run tb_gs_demo_psmt4_e2e_ee_program ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_ee_program.vvp
|
||
|
||
tb_gs_demo_psmt4_e2e_ee_full_bootlet: dirs
|
||
@echo "=== build tb_gs_demo_psmt4_e2e_ee_full_bootlet ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_ee_full_bootlet.vvp \
|
||
-s tb_gs_demo_psmt4_e2e_ee_full_bootlet \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_ee_full_bootlet.sv
|
||
@echo "=== run tb_gs_demo_psmt4_e2e_ee_full_bootlet ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_ee_full_bootlet.vvp
|
||
|
||
tb_ee_ram_cpu_dmac_contention: dirs
|
||
@echo "=== build tb_ee_ram_cpu_dmac_contention ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_ram_cpu_dmac_contention.vvp \
|
||
-s tb_ee_ram_cpu_dmac_contention \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_ram_cpu_dmac_contention.sv
|
||
@echo "=== run tb_ee_ram_cpu_dmac_contention ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_ram_cpu_dmac_contention.vvp
|
||
|
||
tb_gs_image_xfer_psmct16: dirs
|
||
@echo "=== build tb_gs_image_xfer_psmct16 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_image_xfer_psmct16.vvp \
|
||
-s tb_gs_image_xfer_psmct16 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_psmct16.sv
|
||
@echo "=== run tb_gs_image_xfer_psmct16 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_psmct16.vvp
|
||
|
||
tb_gs_image_xfer_psmt8: dirs
|
||
@echo "=== build tb_gs_image_xfer_psmt8 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_image_xfer_psmt8.vvp \
|
||
-s tb_gs_image_xfer_psmt8 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_psmt8.sv
|
||
@echo "=== run tb_gs_image_xfer_psmt8 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_psmt8.vvp
|
||
|
||
tb_gs_image_xfer_psmt4: dirs
|
||
@echo "=== build tb_gs_image_xfer_psmt4 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_image_xfer_psmt4.vvp \
|
||
-s tb_gs_image_xfer_psmt4 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_psmt4.sv
|
||
@echo "=== run tb_gs_image_xfer_psmt4 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_psmt4.vvp
|
||
|
||
tb_gs_swizzle_psmct32: dirs
|
||
@echo "=== build tb_gs_swizzle_psmct32 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_swizzle_psmct32.vvp \
|
||
-s tb_gs_swizzle_psmct32 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_swizzle_psmct32.sv
|
||
@echo "=== run tb_gs_swizzle_psmct32 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_swizzle_psmct32.vvp
|
||
|
||
tb_gs_swizzle_psmct16: dirs
|
||
@echo "=== build tb_gs_swizzle_psmct16 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_swizzle_psmct16.vvp \
|
||
-s tb_gs_swizzle_psmct16 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_swizzle_psmct16.sv
|
||
@echo "=== run tb_gs_swizzle_psmct16 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_swizzle_psmct16.vvp
|
||
|
||
tb_gs_swizzle_psmt8: dirs
|
||
@echo "=== build tb_gs_swizzle_psmt8 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_swizzle_psmt8.vvp \
|
||
-s tb_gs_swizzle_psmt8 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_swizzle_psmt8.sv
|
||
@echo "=== run tb_gs_swizzle_psmt8 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_swizzle_psmt8.vvp
|
||
|
||
tb_gs_swizzle_psmt4: dirs
|
||
@echo "=== build tb_gs_swizzle_psmt4 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_swizzle_psmt4.vvp \
|
||
-s tb_gs_swizzle_psmt4 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_swizzle_psmt4.sv
|
||
@echo "=== run tb_gs_swizzle_psmt4 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_swizzle_psmt4.vvp
|
||
|
||
tb_gs_scanout_swizzle_psmt4: dirs
|
||
@echo "=== build tb_gs_scanout_swizzle_psmt4 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_swizzle_psmt4.vvp \
|
||
-s tb_gs_scanout_swizzle_psmt4 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_swizzle_psmt4.sv
|
||
@echo "=== run tb_gs_scanout_swizzle_psmt4 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_swizzle_psmt4.vvp
|
||
|
||
tb_gs_image_xfer_swizzle_psmt4: dirs
|
||
@echo "=== build tb_gs_image_xfer_swizzle_psmt4 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmt4.vvp \
|
||
-s tb_gs_image_xfer_swizzle_psmt4 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_swizzle_psmt4.sv
|
||
@echo "=== run tb_gs_image_xfer_swizzle_psmt4 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmt4.vvp
|
||
|
||
tb_gs_raster_swizzle_psmt4: dirs
|
||
@echo "=== build tb_gs_raster_swizzle_psmt4 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_swizzle_psmt4.vvp \
|
||
-s tb_gs_raster_swizzle_psmt4 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_swizzle_psmt4.sv
|
||
@echo "=== run tb_gs_raster_swizzle_psmt4 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_swizzle_psmt4.vvp
|
||
|
||
tb_gs_demo_psmt4_swizzle_e2e: dirs
|
||
@echo "=== build tb_gs_demo_psmt4_swizzle_e2e ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt4_swizzle_e2e.vvp \
|
||
-s tb_gs_demo_psmt4_swizzle_e2e \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_swizzle_e2e.sv
|
||
@echo "=== run tb_gs_demo_psmt4_swizzle_e2e ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_swizzle_e2e.vvp
|
||
|
||
tb_gs_demo_psmt4_swizzle_trxdir_e2e: dirs
|
||
@echo "=== build tb_gs_demo_psmt4_swizzle_trxdir_e2e ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt4_swizzle_trxdir_e2e.vvp \
|
||
-s tb_gs_demo_psmt4_swizzle_trxdir_e2e \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_swizzle_trxdir_e2e.sv
|
||
@echo "=== run tb_gs_demo_psmt4_swizzle_trxdir_e2e ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_swizzle_trxdir_e2e.vvp
|
||
|
||
tb_top_psmct32_raster_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_raster_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_ch146.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_ch146.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_raster_demo.vvp \
|
||
-s tb_top_psmct32_raster_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo.sv
|
||
@echo "=== run tb_top_psmct32_raster_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo.vvp
|
||
|
||
# Brick 1 — TOP-LEVEL textured-sprite demo. Drives top_psmct32_raster_demo
|
||
# (PSMCT32_SWIZZLE=0) with the textured fixture (BITBLT texture upload +
|
||
# textured SPRITE + flat control sprite) and verifies the texture renders
|
||
# in the PCRTC scanout — i.e. a board load would SHOW a texture.
|
||
tb_top_psmct32_textured_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_textured_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_textured.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_textured.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_textured_demo.vvp \
|
||
-s tb_top_psmct32_textured_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_textured_demo.sv
|
||
@echo "=== run tb_top_psmct32_textured_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_textured_demo.vvp
|
||
|
||
# Ch171 — this TB exercises the legacy 16x8 Ch146 fixture (the
|
||
# pre-Ch171 pattern) because it does per-pixel VRAM + scanout
|
||
# assertions that don't survive scaling to 320x240. Synth/board
|
||
# uses bios.mem/payload.mem (the Ch171 320x240 pattern) via the
|
||
# QSF macro.
|
||
tb_top_psmct32_raster_demo_bram: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_raster_demo_bram ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_ch146.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_ch146.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram.vvp \
|
||
-s tb_top_psmct32_raster_demo_bram \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram.sv
|
||
@echo "=== run tb_top_psmct32_raster_demo_bram ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram.vvp
|
||
|
||
# Ch295 — TEXTURED-sprite demo on the BRAM BOARD VARIANT
|
||
# (top_psmct32_raster_demo_bram). Companion to tb_top_psmct32_textured_demo
|
||
# (vram_stub variant); proves the textured SPRITE path renders through the
|
||
# BRAM VRAM the de25_nano board top actually instantiates, despite
|
||
# vram_bram_stub.read2's 1-cycle registered read latency (gs_stub
|
||
# TEX_RD_REGISTERED=1). Built with the textured fixture + PSMCT32_SWIZZLE=0.
|
||
tb_top_psmct32_raster_demo_bram_textured: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_raster_demo_bram_textured ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_textured.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_textured.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_textured.vvp \
|
||
-s tb_top_psmct32_raster_demo_bram_textured \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_textured.sv
|
||
@echo "=== run tb_top_psmct32_raster_demo_bram_textured ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_textured.vvp
|
||
|
||
# Ch296 — PSMT8 INDEXED-TEXTURE + CLUT demo on the BRAM board variant.
|
||
# Proves the palettized texture path (texel index fetch -> clut_stub
|
||
# lookup -> PSMCT32 color) renders through the BRAM VRAM + the CLUT
|
||
# loader the board top instantiates. Uses the clut fixture
|
||
# (bios_clut.mem / payload_clut.mem) + PSMCT32_SWIZZLE=0.
|
||
tb_top_psmct32_raster_demo_bram_clut: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_raster_demo_bram_clut ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_clut.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_clut.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_clut.vvp \
|
||
-s tb_top_psmct32_raster_demo_bram_clut \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_clut.sv
|
||
@echo "=== run tb_top_psmct32_raster_demo_bram_clut ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_clut.vvp
|
||
|
||
# Ch347 — AUTHENTIC SH3 64x64-crop PSMT8+CLUT board integration (LOCAL assets; NOT in the regression).
|
||
# Fixtures from tools/gs_extract_sh3_clut.py + tools/gs_make_sh3_fixture.py (needs the local SH3 dump).
|
||
tb_top_psmct32_sh3_clut_demo: dirs
|
||
@echo "=== build tb_top_psmct32_sh3_clut_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_clut.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_clut.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_sh3_clut_demo.vvp \
|
||
-s tb_top_psmct32_sh3_clut_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_clut_demo.sv
|
||
@echo "=== run tb_top_psmct32_sh3_clut_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_clut_demo.vvp
|
||
|
||
# Ch297 — PSMT4 INDEXED-TEXTURE + CLUT demo on the BRAM board variant.
|
||
# Proves the 4-bit palettized texture path (nibble-select index fetch ->
|
||
# clut_stub lookup -> PSMCT32 color) renders through the BRAM VRAM + CLUT
|
||
# loader the board top instantiates. Uses the clut4 fixture
|
||
# (bios_clut4.mem / payload_clut4.mem) + PSMCT32_SWIZZLE=0.
|
||
tb_top_psmct32_raster_demo_bram_clut4: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_raster_demo_bram_clut4 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_clut4.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_clut4.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_clut4.vvp \
|
||
-s tb_top_psmct32_raster_demo_bram_clut4 \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_clut4.sv
|
||
@echo "=== run tb_top_psmct32_raster_demo_bram_clut4 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_clut4.vvp
|
||
|
||
# Ch298 — SWIZZLED PSMT4 INDEXED-TEXTURE + CLUT demo on the BRAM board variant.
|
||
# Built with PSMT4_SWIZZLE=1 so BOTH the gif_image_xfer texture UPLOAD and the
|
||
# gs_texture_unit SAMPLE use the real PS2 PSMT4 block layout. The 64x32 texture
|
||
# / 16x32 sampled sprite crosses the 16-px block-ROW boundary, so the same VRAM
|
||
# bytes read linearly would scramble. Uses the swz4 fixture (bios_swz4.mem /
|
||
# payload_swz4.mem).
|
||
tb_top_psmct32_raster_demo_bram_swz4: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_raster_demo_bram_swz4 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_swz4.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_swz4.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz4.vvp \
|
||
-s tb_top_psmct32_raster_demo_bram_swz4 \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_swz4.sv
|
||
@echo "=== run tb_top_psmct32_raster_demo_bram_swz4 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz4.vvp
|
||
|
||
tb_top_psmct32_raster_demo_bram_swz8: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_raster_demo_bram_swz8 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_swz8.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_swz8.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz8.vvp \
|
||
-s tb_top_psmct32_raster_demo_bram_swz8 \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_swz8.sv
|
||
@echo "=== run tb_top_psmct32_raster_demo_bram_swz8 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz8.vvp
|
||
|
||
tb_top_psmct32_raster_demo_bram_swz32: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_raster_demo_bram_swz32 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_swz32.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_swz32.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz32.vvp \
|
||
-s tb_top_psmct32_raster_demo_bram_swz32 \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_swz32.sv
|
||
@echo "=== run tb_top_psmct32_raster_demo_bram_swz32 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz32.vvp
|
||
|
||
tb_top_psmct32_perspective_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_perspective_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_persp.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_persp.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_perspective_demo.vvp \
|
||
-s tb_top_psmct32_perspective_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_perspective_demo.sv
|
||
@echo "=== run tb_top_psmct32_perspective_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_perspective_demo.vvp
|
||
|
||
tb_top_psmct32_persp_floor_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_persp_floor_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_persp_floor.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_persp_floor.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_persp_floor_demo.vvp \
|
||
-s tb_top_psmct32_persp_floor_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_persp_floor_demo.sv
|
||
@echo "=== run tb_top_psmct32_persp_floor_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_persp_floor_demo.vvp
|
||
|
||
tb_top_psmct32_combined_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_combined_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_combined.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_combined.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_combined_demo.vvp \
|
||
-s tb_top_psmct32_combined_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_combined_demo.sv
|
||
@echo "=== run tb_top_psmct32_combined_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_combined_demo.vvp
|
||
|
||
tb_top_psmct32_tile_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_demo.vvp \
|
||
-s tb_top_psmct32_tile_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_demo.vvp
|
||
|
||
tb_gs_tile_zflush: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_gs_tile_zflush ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile.mem"' \
|
||
-o $(BUILD_DIR)/tb_gs_tile_zflush.vvp \
|
||
-s tb_gs_tile_zflush \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_zflush.sv
|
||
@echo "=== run tb_gs_tile_zflush ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_zflush.vvp
|
||
|
||
tb_gs_tile_spill_reload: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_gs_tile_spill_reload ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_spill.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_spill.mem"' \
|
||
-o $(BUILD_DIR)/tb_gs_tile_spill_reload.vvp \
|
||
-s tb_gs_tile_spill_reload \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_spill_reload.sv
|
||
@echo "=== run tb_gs_tile_spill_reload ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_spill_reload.vvp
|
||
|
||
tb_gs_tile_spill_lpddr: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_gs_tile_spill_lpddr ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_spill.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_spill.mem"' \
|
||
-o $(BUILD_DIR)/tb_gs_tile_spill_lpddr.vvp \
|
||
-s tb_gs_tile_spill_lpddr \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_spill_lpddr.sv
|
||
@echo "=== run tb_gs_tile_spill_lpddr ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_spill_lpddr.vvp
|
||
|
||
tb_gs_tile_spill_grid_lpddr: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_gs_tile_spill_grid_lpddr ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_spill4x4.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_spill4x4.mem"' \
|
||
-o $(BUILD_DIR)/tb_gs_tile_spill_grid_lpddr.vvp \
|
||
-s tb_gs_tile_spill_grid_lpddr \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_spill_grid_lpddr.sv
|
||
@echo "=== run tb_gs_tile_spill_grid_lpddr ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_spill_grid_lpddr.vvp
|
||
|
||
tb_gs_tile_spill_grid8x8_lpddr: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_gs_tile_spill_grid8x8_lpddr ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_spill8x8.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_spill8x8.mem"' \
|
||
-o $(BUILD_DIR)/tb_gs_tile_spill_grid8x8_lpddr.vvp \
|
||
-s tb_gs_tile_spill_grid8x8_lpddr \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_spill_grid8x8_lpddr.sv
|
||
@echo "=== run tb_gs_tile_spill_grid8x8_lpddr ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_spill_grid8x8_lpddr.vvp
|
||
|
||
tb_gs_tile_spill_lpddr_neg: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_gs_tile_spill_lpddr_neg ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_spill.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_spill.mem"' \
|
||
-o $(BUILD_DIR)/tb_gs_tile_spill_lpddr_neg.vvp \
|
||
-s tb_gs_tile_spill_lpddr_neg \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_spill_lpddr_neg.sv
|
||
@echo "=== run tb_gs_tile_spill_lpddr_neg ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_spill_lpddr_neg.vvp
|
||
|
||
tb_top_psmct32_tile2x2_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile2x2_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile2x2.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile2x2.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile2x2_demo.vvp \
|
||
-s tb_top_psmct32_tile2x2_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile2x2_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile2x2_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile2x2_demo.vvp
|
||
|
||
tb_top_psmct32_tile_multiprim_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_multiprim_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_multiprim.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_multiprim.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_multiprim_demo.vvp \
|
||
-s tb_top_psmct32_tile_multiprim_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_multiprim_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_multiprim_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_multiprim_demo.vvp
|
||
|
||
tb_top_psmct32_tile_scissor_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_scissor_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_scissor.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_scissor.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_scissor_demo.vvp \
|
||
-s tb_top_psmct32_tile_scissor_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_scissor_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_scissor_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_scissor_demo.vvp
|
||
|
||
tb_top_psmct32_tile_wrap_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_wrap_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_wrap.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_wrap.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_wrap_demo.vvp \
|
||
-s tb_top_psmct32_tile_wrap_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_wrap_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_wrap_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_wrap_demo.vvp
|
||
|
||
tb_top_psmct32_tile_psmct16_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_psmct16_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_psmct16.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_psmct16.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_psmct16_demo.vvp \
|
||
-s tb_top_psmct32_tile_psmct16_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_psmct16_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_psmct16_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_psmct16_demo.vvp
|
||
|
||
tb_top_psmct32_tile_alpha_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_alpha_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_alpha.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_alpha.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_alpha_demo.vvp \
|
||
-s tb_top_psmct32_tile_alpha_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_alpha_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_alpha_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_alpha_demo.vvp
|
||
|
||
tb_top_psmct32_tile_bilinear_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_bilinear_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_bilinear.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_bilinear.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_bilinear_demo.vvp \
|
||
-s tb_top_psmct32_tile_bilinear_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_bilinear_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_bilinear_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_bilinear_demo.vvp
|
||
|
||
tb_top_psmct32_tile_palbilinear_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_palbilinear_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_palbilinear.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_palbilinear.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_palbilinear_demo.vvp \
|
||
-s tb_top_psmct32_tile_palbilinear_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_palbilinear_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_palbilinear_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_palbilinear_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_equiv_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_equiv_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_STG_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_equiv_demo.vvp \
|
||
-s tb_top_psmct32_feeder_equiv_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_equiv_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_equiv_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_equiv_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_runtime_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_runtime_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_STG_A_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4.mem"' \
|
||
-DFEEDER_STG_B_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4_B.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_runtime_demo.vvp \
|
||
-s tb_top_psmct32_feeder_runtime_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_runtime_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_runtime_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_runtime_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_bridge_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_bridge_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_STG_A_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4.mem"' \
|
||
-DFEEDER_STG_B_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4_B.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_bridge_demo.vvp \
|
||
-s tb_top_psmct32_feeder_bridge_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_bridge_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_bridge_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_bridge_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_scenes_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_scenes_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_SCENE_C1_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_scene_c1.mem"' \
|
||
-DFEEDER_SCENE_C2_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_scene_c2.mem"' \
|
||
-DFEEDER_SCENE_C3_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_scene_c3.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_scenes_demo.vvp \
|
||
-s tb_top_psmct32_feeder_scenes_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_scenes_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_scenes_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_scenes_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_shapes_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_shapes_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_SHAPE_TRI_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_shape_tri.mem"' \
|
||
-DFEEDER_SHAPE_RECT_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_shape_rect.mem"' \
|
||
-DFEEDER_SHAPE_MIXED_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_shape_mixed.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_shapes_demo.vvp \
|
||
-s tb_top_psmct32_feeder_shapes_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_shapes_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_shapes_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_shapes_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_colors_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_colors_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_COLOR_TRI_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_color_tri.mem"' \
|
||
-DFEEDER_COLOR_RECT_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_color_rect.mem"' \
|
||
-DFEEDER_COLOR_MIX_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_color_mix.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_colors_demo.vvp \
|
||
-s tb_top_psmct32_feeder_colors_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_colors_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_colors_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_colors_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_native_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_native_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_NATIVE_RECT_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_native_rect.mem"' \
|
||
-DFEEDER_NATIVE_MIX_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_native_mix.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_native_demo.vvp \
|
||
-s tb_top_psmct32_feeder_native_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_native_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_native_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_native_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_gouraud_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_gouraud_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_GOURAUD_TRI_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_gouraud_tri.mem"' \
|
||
-DFEEDER_GOURAUD_RECT_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_gouraud_rect.mem"' \
|
||
-DFEEDER_GOURAUD_MIX_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_gouraud_mix.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_gouraud_demo.vvp \
|
||
-s tb_top_psmct32_feeder_gouraud_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_gouraud_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_gouraud_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_gouraud_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_accum_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_accum_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_ACCUM_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_accum.mem"' \
|
||
-DFEEDER_LISTA_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_accum_demo.vvp \
|
||
-s tb_top_psmct32_feeder_accum_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_accum_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_accum_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_accum_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_scene_retrigger_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_scene_retrigger_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_SCENE_A_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_scene_a.mem"' \
|
||
-DFEEDER_SCENE_B_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_scene_b.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_scene_retrigger_demo.vvp \
|
||
-s tb_top_psmct32_feeder_scene_retrigger_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_scene_retrigger_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_scene_retrigger_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_scene_retrigger_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_zpersist_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_zpersist_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_ZPN_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_zpersist_near_first.mem"' \
|
||
-DFEEDER_ZPF_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_zpersist_far_first.mem"' \
|
||
-DFEEDER_ZPG_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_zpersist_grad.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_zpersist_demo.vvp \
|
||
-s tb_top_psmct32_feeder_zpersist_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_zpersist_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_zpersist_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_zpersist_demo.vvp
|
||
|
||
tb_top_psmct32_feeder_persp_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_persp_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
|
||
-DFEEDER_PERSP_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_persp.mem"' \
|
||
-DFEEDER_PERSP_TEX_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_persp_tex.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_persp_demo.vvp \
|
||
-s tb_top_psmct32_feeder_persp_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_persp_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_persp_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_persp_demo.vvp
|
||
|
||
# Ch348 — AUTHENTIC SH3 PSMT8+CLUT through the perspective feeder path (LOCAL assets; NOT in the regression).
|
||
# Fixtures: tools/gs_extract_sh3_clut.py + tools/gs_make_sh3_persp_fixture.py (needs the local SH3 dump).
|
||
tb_top_psmct32_sh3_persp_demo: dirs
|
||
@echo "=== build tb_top_psmct32_sh3_persp_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_persp.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_persp.mem"' \
|
||
-DFEEDER_SH3_PERSP_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_sh3_persp.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_sh3_persp_demo.vvp \
|
||
-s tb_top_psmct32_sh3_persp_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_persp_demo.sv
|
||
@echo "=== run tb_top_psmct32_sh3_persp_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_persp_demo.vvp
|
||
|
||
tb_top_psmct32_sh3_real_draw_demo: dirs
|
||
@echo "=== build tb_top_psmct32_sh3_real_draw_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-I$(SIM_DIR)/data/top_psmct32_raster_demo \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_real.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_real.mem"' \
|
||
-DFEEDER_SH3_REAL_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_sh3_real.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_sh3_real_draw_demo.vvp \
|
||
-s tb_top_psmct32_sh3_real_draw_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_real_draw_demo.sv
|
||
@echo "=== run tb_top_psmct32_sh3_real_draw_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_real_draw_demo.vvp
|
||
|
||
# Ch345a — RUNTIME FEEDER textured-alpha SPRITE demo (sprite_mode staging + SPRITE_TEX_ALPHA). Setup bootlet
|
||
# uploads an 8x8 alpha texture + blue BG; the feeder streams 3 textured-alpha sprites over it.
|
||
tb_top_psmct32_feeder_sprite_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_sprite_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sprite_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sprite_setup.mem"' \
|
||
-DFEEDER_SPRITE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_sprite.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_sprite_demo.vvp \
|
||
-s tb_top_psmct32_feeder_sprite_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_sprite_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_sprite_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_sprite_demo.vvp
|
||
|
||
# Ch343 — LOCAL authentic-cube smoke (NOT in `run:`; needs dump-derived cube fixtures from
|
||
# `python3 tools/gs_make_cube_fixture.py`). Full boot: 64x64 cube texture upload (QWC=1030, 32 KiB EE
|
||
# RAM) + 27 perspective triangles through the S1 feeder path. De-risks the feeder_cube fit.
|
||
tb_top_psmct32_feeder_cube_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_feeder_cube_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_cube_setup.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_cube_setup.mem"' \
|
||
-DFEEDER_CUBE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_cube_persp.mem"' \
|
||
-DFEEDER_CUBE_TEX_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_cube_tex.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_feeder_cube_demo.vvp \
|
||
-s tb_top_psmct32_feeder_cube_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_cube_demo.sv
|
||
@echo "=== run tb_top_psmct32_feeder_cube_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_cube_demo.vvp
|
||
|
||
tb_top_psmct32_tile_sprite18_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_sprite18_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_sprite18.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_sprite18.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_sprite18_demo.vvp \
|
||
-s tb_top_psmct32_tile_sprite18_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_sprite18_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_sprite18_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_sprite18_demo.vvp
|
||
|
||
tb_top_psmct32_tile_cap64_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_cap64_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_cap64.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_cap64.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_cap64_demo.vvp \
|
||
-s tb_top_psmct32_tile_cap64_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_cap64_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_cap64_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_cap64_demo.vvp
|
||
|
||
tb_top_psmct32_tile_cap_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_cap_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_cap.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_cap.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_cap_demo.vvp \
|
||
-s tb_top_psmct32_tile_cap_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_cap_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_cap_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_cap_demo.vvp
|
||
|
||
tb_top_psmct32_tile_cap_overflow_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_cap_overflow_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_cap.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_cap.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_cap_overflow_demo.vvp \
|
||
-s tb_top_psmct32_tile_cap_overflow_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_cap_overflow_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_cap_overflow_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_cap_overflow_demo.vvp
|
||
|
||
tb_top_psmct32_tile_late_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_late_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_late.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_late.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_late_demo.vvp \
|
||
-s tb_top_psmct32_tile_late_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_late_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_late_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_late_demo.vvp
|
||
|
||
tb_top_psmct32_tile_lpddrfb_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_lpddrfb_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_psmct16fb.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_psmct16fb.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_lpddrfb_demo.vvp \
|
||
-s tb_top_psmct32_tile_lpddrfb_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_lpddrfb_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_lpddrfb_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_lpddrfb_demo.vvp
|
||
|
||
tb_top_psmct32_tile_bin_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_bin_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_bin.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_bin.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_bin_demo.vvp \
|
||
-s tb_top_psmct32_tile_bin_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_bin_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_bin_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_bin_demo.vvp
|
||
|
||
tb_top_psmct32_tile_bin4x4_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_bin4x4_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_bin4x4.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_bin4x4.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_bin4x4_demo.vvp \
|
||
-s tb_top_psmct32_tile_bin4x4_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_bin4x4_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_bin4x4_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_bin4x4_demo.vvp
|
||
|
||
tb_top_psmct32_tile_psmct16fb_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_psmct16fb_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_psmct16fb.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_psmct16fb.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_psmct16fb_demo.vvp \
|
||
-s tb_top_psmct32_tile_psmct16fb_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_psmct16fb_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_psmct16fb_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_psmct16fb_demo.vvp
|
||
|
||
tb_top_psmct32_tile_lpddr128_demo: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_tile_lpddr128_demo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_lpddr128.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_lpddr128.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_tile_lpddr128_demo.vvp \
|
||
-s tb_top_psmct32_tile_lpddr128_demo \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_lpddr128_demo.sv
|
||
@echo "=== run tb_top_psmct32_tile_lpddr128_demo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_lpddr128_demo.vvp
|
||
|
||
# Textured-TRIANGLE demo on the BRAM board variant. Proves the
|
||
# textured-triangle rung (affine U/V into the texel-fetch path) renders
|
||
# through the BRAM VRAM the board top instantiates. Uses the tritex
|
||
# fixture (bios_tritex.mem / payload_tritex.mem) + PSMCT32_SWIZZLE=0.
|
||
tb_top_psmct32_raster_demo_bram_tritex: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_raster_demo_bram_tritex ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tritex.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tritex.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_tritex.vvp \
|
||
-s tb_top_psmct32_raster_demo_bram_tritex \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_tritex.sv
|
||
@echo "=== run tb_top_psmct32_raster_demo_bram_tritex ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_tritex.vvp
|
||
|
||
tb_top_psmct32_raster_demo_bram_lpddrtex: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_raster_demo_bram_lpddrtex ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tritex.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tritex.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_lpddrtex.vvp \
|
||
-s tb_top_psmct32_raster_demo_bram_lpddrtex \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_lpddrtex.sv
|
||
@echo "=== run tb_top_psmct32_raster_demo_bram_lpddrtex ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_lpddrtex.vvp
|
||
|
||
# Ch171 — spot-check TB for the 320x240 four-quadrant test card. Uses the
|
||
# Ch171 production fixtures (bios.mem / payload.mem) so its expectations
|
||
# match the synth/board build exactly. Instantiates the inner bram wrapper
|
||
# with board overrides (640x480 raster, 512 KiB VRAM) and probes a small
|
||
# set of inside/boundary/outside coordinates rather than every pixel.
|
||
tb_top_psmct32_raster_demo_bram_ch171: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_top_psmct32_raster_demo_bram_ch171 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload.mem"' \
|
||
-o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_ch171.vvp \
|
||
-s tb_top_psmct32_raster_demo_bram_ch171 \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_ch171.sv
|
||
@echo "=== run tb_top_psmct32_raster_demo_bram_ch171 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_ch171.vvp
|
||
|
||
# Ch172 — backpressure stress TB. Procedurally builds an 8-sprite GIF
|
||
# payload directly into ee_ram + bios_rom backings (no $readmemh image
|
||
# load) so the fixture .mem files don't need to grow. Asserts that
|
||
# gif_packed_stub.in_ready goes LOW at least once under FIFO_DEPTH=2 and
|
||
# that all 8 sprites still land in VRAM with raster_overflow=0.
|
||
# Ch173 — focused unit-test TB for the HPS↔fabric status bridge.
|
||
# Drives AXI4 reads directly + verifies the Ch173 register map
|
||
# (identity, CORE_STATUS, FRAME_COUNT, DMA_DONE_COUNT,
|
||
# RASTER_OVERFLOW_COUNT) + writes are ACK'd-and-ignored.
|
||
tb_ps2_hps_bridge: dirs
|
||
@echo "=== build tb_ps2_hps_bridge ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ps2_hps_bridge.vvp \
|
||
-s tb_ps2_hps_bridge \
|
||
$(RTL_ROOT)/platform/ps2_hps_bridge.sv \
|
||
$(TB_ROOT)/platform/tb_ps2_hps_bridge.sv
|
||
@echo "=== run tb_ps2_hps_bridge ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ps2_hps_bridge.vvp
|
||
|
||
# Ch245 — focused unit-test for the platform-OSD cell adapter. Mocks
|
||
# the 32-bit-word tile_ram_cdc shadow and verifies the 32→16
|
||
# low/high-half mux returns the right cell for several pack patterns
|
||
# (low, high, mid-row, corner, unwritten-neighbor). Pure
|
||
# combinational adapter + a single register; no platform overlay
|
||
# instantiated. Cross-checks the integration glue introduced in
|
||
# rtl/top/de25_nano_psmct32_raster_demo_top.sv.
|
||
tb_osd_platform_cell_adapter: dirs
|
||
@echo "=== build tb_osd_platform_cell_adapter ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_osd_platform_cell_adapter.vvp \
|
||
-s tb_osd_platform_cell_adapter \
|
||
$(TB_ROOT)/platform/tb_osd_platform_cell_adapter.sv
|
||
@echo "=== run tb_osd_platform_cell_adapter ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_osd_platform_cell_adapter.vvp
|
||
|
||
# Ch229 — toggle-based bridge-clock → design-clock tile RAM CDC.
|
||
# Drives synthetic bridge writes at 100 MHz; verifies the 33 MHz
|
||
# design-side shadow RAM receives writes correctly through the 2-FF
|
||
# synchronizer + edge detector. Includes a static-toggle check
|
||
# proving writes are edge-triggered, not level-triggered.
|
||
tb_tile_ram_cdc: dirs
|
||
@echo "=== build tb_tile_ram_cdc ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_tile_ram_cdc.vvp \
|
||
-s tb_tile_ram_cdc \
|
||
$(RTL_ROOT)/platform/tile_ram_cdc.sv \
|
||
$(TB_ROOT)/platform/tb_tile_ram_cdc.sv
|
||
@echo "=== run tb_tile_ram_cdc ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_tile_ram_cdc.vvp
|
||
|
||
tb_gs_raster_backpressure_stress: dirs
|
||
@echo "=== build tb_gs_raster_backpressure_stress ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='""' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='""' \
|
||
-o $(BUILD_DIR)/tb_gs_raster_backpressure_stress.vvp \
|
||
-s tb_gs_raster_backpressure_stress \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_gs_raster_backpressure_stress.sv
|
||
@echo "=== run tb_gs_raster_backpressure_stress ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_backpressure_stress.vvp
|
||
|
||
tb_de25_nano_psmct32_raster_demo_top: dirs top_psmct32_raster_demo_mem
|
||
@echo "=== build tb_de25_nano_psmct32_raster_demo_top ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios.mem"' \
|
||
-DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload.mem"' \
|
||
-o $(BUILD_DIR)/tb_de25_nano_psmct32_raster_demo_top.vvp \
|
||
-s tb_de25_nano_psmct32_raster_demo_top \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_de25_nano_psmct32_raster_demo_top.sv
|
||
@echo "=== run tb_de25_nano_psmct32_raster_demo_top ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_de25_nano_psmct32_raster_demo_top.vvp
|
||
|
||
tb_hdmi_i2c_wake_smoke: dirs
|
||
@echo "=== build tb_hdmi_i2c_wake_smoke ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_hdmi_i2c_wake_smoke.vvp \
|
||
-s tb_hdmi_i2c_wake_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/top/tb_hdmi_i2c_wake_smoke.sv
|
||
@echo "=== run tb_hdmi_i2c_wake_smoke ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_hdmi_i2c_wake_smoke.vvp
|
||
|
||
tb_gs_scanout_swizzle_psmt8: dirs
|
||
@echo "=== build tb_gs_scanout_swizzle_psmt8 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_swizzle_psmt8.vvp \
|
||
-s tb_gs_scanout_swizzle_psmt8 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_swizzle_psmt8.sv
|
||
@echo "=== run tb_gs_scanout_swizzle_psmt8 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_swizzle_psmt8.vvp
|
||
|
||
tb_gs_image_xfer_swizzle_psmt8: dirs
|
||
@echo "=== build tb_gs_image_xfer_swizzle_psmt8 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmt8.vvp \
|
||
-s tb_gs_image_xfer_swizzle_psmt8 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_swizzle_psmt8.sv
|
||
@echo "=== run tb_gs_image_xfer_swizzle_psmt8 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmt8.vvp
|
||
|
||
tb_gs_raster_swizzle_psmt8: dirs
|
||
@echo "=== build tb_gs_raster_swizzle_psmt8 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_swizzle_psmt8.vvp \
|
||
-s tb_gs_raster_swizzle_psmt8 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_swizzle_psmt8.sv
|
||
@echo "=== run tb_gs_raster_swizzle_psmt8 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_swizzle_psmt8.vvp
|
||
|
||
tb_gs_demo_psmt8_swizzle_e2e: dirs
|
||
@echo "=== build tb_gs_demo_psmt8_swizzle_e2e ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt8_swizzle_e2e.vvp \
|
||
-s tb_gs_demo_psmt8_swizzle_e2e \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt8_swizzle_e2e.sv
|
||
@echo "=== run tb_gs_demo_psmt8_swizzle_e2e ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt8_swizzle_e2e.vvp
|
||
|
||
tb_gs_demo_psmt8_swizzle_trxdir_e2e: dirs
|
||
@echo "=== build tb_gs_demo_psmt8_swizzle_trxdir_e2e ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmt8_swizzle_trxdir_e2e.vvp \
|
||
-s tb_gs_demo_psmt8_swizzle_trxdir_e2e \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt8_swizzle_trxdir_e2e.sv
|
||
@echo "=== run tb_gs_demo_psmt8_swizzle_trxdir_e2e ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt8_swizzle_trxdir_e2e.vvp
|
||
|
||
tb_gs_scanout_swizzle_psmct16: dirs
|
||
@echo "=== build tb_gs_scanout_swizzle_psmct16 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_swizzle_psmct16.vvp \
|
||
-s tb_gs_scanout_swizzle_psmct16 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_swizzle_psmct16.sv
|
||
@echo "=== run tb_gs_scanout_swizzle_psmct16 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_swizzle_psmct16.vvp
|
||
|
||
tb_gs_image_xfer_swizzle_psmct16: dirs
|
||
@echo "=== build tb_gs_image_xfer_swizzle_psmct16 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmct16.vvp \
|
||
-s tb_gs_image_xfer_swizzle_psmct16 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_swizzle_psmct16.sv
|
||
@echo "=== run tb_gs_image_xfer_swizzle_psmct16 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmct16.vvp
|
||
|
||
tb_gs_scanout_swizzle_psmct32: dirs
|
||
@echo "=== build tb_gs_scanout_swizzle_psmct32 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_swizzle_psmct32.vvp \
|
||
-s tb_gs_scanout_swizzle_psmct32 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_swizzle_psmct32.sv
|
||
@echo "=== run tb_gs_scanout_swizzle_psmct32 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_swizzle_psmct32.vvp
|
||
|
||
tb_gs_image_xfer_swizzle_psmct32: dirs
|
||
@echo "=== build tb_gs_image_xfer_swizzle_psmct32 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmct32.vvp \
|
||
-s tb_gs_image_xfer_swizzle_psmct32 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_swizzle_psmct32.sv
|
||
@echo "=== run tb_gs_image_xfer_swizzle_psmct32 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmct32.vvp
|
||
|
||
tb_gs_raster_swizzle_psmct32: dirs
|
||
@echo "=== build tb_gs_raster_swizzle_psmct32 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_swizzle_psmct32.vvp \
|
||
-s tb_gs_raster_swizzle_psmct32 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_swizzle_psmct32.sv
|
||
@echo "=== run tb_gs_raster_swizzle_psmct32 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_swizzle_psmct32.vvp
|
||
|
||
tb_gs_raster_swizzle_psmct16: dirs
|
||
@echo "=== build tb_gs_raster_swizzle_psmct16 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_swizzle_psmct16.vvp \
|
||
-s tb_gs_raster_swizzle_psmct16 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_swizzle_psmct16.sv
|
||
@echo "=== run tb_gs_raster_swizzle_psmct16 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_swizzle_psmct16.vvp
|
||
|
||
tb_gs_raster_bram_psmct16: dirs
|
||
@echo "=== build tb_gs_raster_bram_psmct16 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_bram_psmct16.vvp \
|
||
-s tb_gs_raster_bram_psmct16 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_bram_psmct16.sv
|
||
@echo "=== run tb_gs_raster_bram_psmct16 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_bram_psmct16.vvp
|
||
|
||
tb_gs_raster_bram_psmt8: dirs
|
||
@echo "=== build tb_gs_raster_bram_psmt8 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_bram_psmt8.vvp \
|
||
-s tb_gs_raster_bram_psmt8 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_bram_psmt8.sv
|
||
@echo "=== run tb_gs_raster_bram_psmt8 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_bram_psmt8.vvp
|
||
|
||
tb_gs_raster_bram_psmt4: dirs
|
||
@echo "=== build tb_gs_raster_bram_psmt4 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_raster_bram_psmt4.vvp \
|
||
-s tb_gs_raster_bram_psmt4 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_bram_psmt4.sv
|
||
@echo "=== run tb_gs_raster_bram_psmt4 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_bram_psmt4.vvp
|
||
|
||
tb_gs_scanout_bram_psmct16: dirs
|
||
@echo "=== build tb_gs_scanout_bram_psmct16 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_bram_psmct16.vvp \
|
||
-s tb_gs_scanout_bram_psmct16 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_bram_psmct16.sv
|
||
@echo "=== run tb_gs_scanout_bram_psmct16 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_bram_psmct16.vvp
|
||
|
||
tb_gs_scanout_bram_psmt8: dirs
|
||
@echo "=== build tb_gs_scanout_bram_psmt8 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_bram_psmt8.vvp \
|
||
-s tb_gs_scanout_bram_psmt8 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_bram_psmt8.sv
|
||
@echo "=== run tb_gs_scanout_bram_psmt8 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_bram_psmt8.vvp
|
||
|
||
tb_gs_demo_psmct32_swizzle_e2e: dirs
|
||
@echo "=== build tb_gs_demo_psmct32_swizzle_e2e ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmct32_swizzle_e2e.vvp \
|
||
-s tb_gs_demo_psmct32_swizzle_e2e \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmct32_swizzle_e2e.sv
|
||
@echo "=== run tb_gs_demo_psmct32_swizzle_e2e ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmct32_swizzle_e2e.vvp
|
||
|
||
tb_gs_demo_psmct16_swizzle_e2e: dirs
|
||
@echo "=== build tb_gs_demo_psmct16_swizzle_e2e ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmct16_swizzle_e2e.vvp \
|
||
-s tb_gs_demo_psmct16_swizzle_e2e \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmct16_swizzle_e2e.sv
|
||
@echo "=== run tb_gs_demo_psmct16_swizzle_e2e ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmct16_swizzle_e2e.vvp
|
||
|
||
tb_gs_demo_psmct16_swizzle_trxdir_e2e: dirs
|
||
@echo "=== build tb_gs_demo_psmct16_swizzle_trxdir_e2e ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmct16_swizzle_trxdir_e2e.vvp \
|
||
-s tb_gs_demo_psmct16_swizzle_trxdir_e2e \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmct16_swizzle_trxdir_e2e.sv
|
||
@echo "=== run tb_gs_demo_psmct16_swizzle_trxdir_e2e ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmct16_swizzle_trxdir_e2e.vvp
|
||
|
||
tb_gs_demo_psmct32_swizzle_trxdir_e2e: dirs
|
||
@echo "=== build tb_gs_demo_psmct32_swizzle_trxdir_e2e ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_demo_psmct32_swizzle_trxdir_e2e.vvp \
|
||
-s tb_gs_demo_psmct32_swizzle_trxdir_e2e \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmct32_swizzle_trxdir_e2e.sv
|
||
@echo "=== run tb_gs_demo_psmct32_swizzle_trxdir_e2e ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmct32_swizzle_trxdir_e2e.vvp
|
||
|
||
tb_gs_scanout_psmt8: dirs
|
||
@echo "=== build tb_gs_scanout_psmt8 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_psmt8.vvp \
|
||
-s tb_gs_scanout_psmt8 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_psmt8.sv
|
||
@echo "=== run tb_gs_scanout_psmt8 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_psmt8.vvp
|
||
|
||
tb_gs_scanout_psmt8_clut: dirs
|
||
@echo "=== build tb_gs_scanout_psmt8_clut ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_psmt8_clut.vvp \
|
||
-s tb_gs_scanout_psmt8_clut \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_psmt8_clut.sv
|
||
@echo "=== run tb_gs_scanout_psmt8_clut ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_psmt8_clut.vvp
|
||
|
||
tb_gs_tex0_clut: dirs
|
||
@echo "=== build tb_gs_tex0_clut ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_tex0_clut.vvp \
|
||
-s tb_gs_tex0_clut \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_tex0_clut.sv
|
||
@echo "=== run tb_gs_tex0_clut ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tex0_clut.vvp
|
||
|
||
tb_gs_clut_load: dirs
|
||
@echo "=== build tb_gs_clut_load ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_clut_load.vvp \
|
||
-s tb_gs_clut_load \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_clut_load.sv
|
||
@echo "=== run tb_gs_clut_load ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_clut_load.vvp
|
||
|
||
tb_gs_clut_load_ct16: dirs
|
||
@echo "=== build tb_gs_clut_load_ct16 ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_clut_load_ct16.vvp \
|
||
-s tb_gs_clut_load_ct16 \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_clut_load_ct16.sv
|
||
@echo "=== run tb_gs_clut_load_ct16 ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_clut_load_ct16.vvp
|
||
|
||
tb_gs_clut_load_cld_modes: dirs
|
||
@echo "=== build tb_gs_clut_load_cld_modes ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_clut_load_cld_modes.vvp \
|
||
-s tb_gs_clut_load_cld_modes \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_clut_load_cld_modes.sv
|
||
@echo "=== run tb_gs_clut_load_cld_modes ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_clut_load_cld_modes.vvp
|
||
|
||
tb_gs_clut_load_csa_window: dirs
|
||
@echo "=== build tb_gs_clut_load_csa_window ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_clut_load_csa_window.vvp \
|
||
-s tb_gs_clut_load_csa_window \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_clut_load_csa_window.sv
|
||
@echo "=== run tb_gs_clut_load_csa_window ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_clut_load_csa_window.vvp
|
||
|
||
tb_gs_scanout_psmt4_clut: dirs
|
||
@echo "=== build tb_gs_scanout_psmt4_clut ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_scanout_psmt4_clut.vvp \
|
||
-s tb_gs_scanout_psmt4_clut \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_psmt4_clut.sv
|
||
@echo "=== run tb_gs_scanout_psmt4_clut ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_psmt4_clut.vvp
|
||
|
||
tb_gs_psmt4_round_trip: dirs
|
||
@echo "=== build tb_gs_psmt4_round_trip ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_gs_psmt4_round_trip.vvp \
|
||
-s tb_gs_psmt4_round_trip \
|
||
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_psmt4_round_trip.sv
|
||
@echo "=== run tb_gs_psmt4_round_trip ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_psmt4_round_trip.vvp
|
||
|
||
tb_intc: dirs
|
||
@echo "=== build tb_intc_stub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_intc_stub.vvp \
|
||
-s tb_intc_stub \
|
||
$(RTL_SRCS) $(TB_ROOT)/intc/tb_intc_stub.sv
|
||
@echo "=== run tb_intc_stub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_intc_stub.vvp
|
||
|
||
tb_platform_video: dirs
|
||
@echo "=== build tb_platform_video_stub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_platform_video_stub.vvp \
|
||
-s tb_platform_video_stub \
|
||
$(RTL_SRCS) $(TB_ROOT)/platform/tb_platform_video_stub.sv
|
||
@echo "=== run tb_platform_video_stub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_platform_video_stub.vvp
|
||
|
||
tb_bgcolor_via_dma: dirs
|
||
@echo "=== build tb_bgcolor_via_dma ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_bgcolor_via_dma.vvp \
|
||
-s tb_bgcolor_via_dma \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_bgcolor_via_dma.sv
|
||
@echo "=== run tb_bgcolor_via_dma ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_bgcolor_via_dma.vvp
|
||
|
||
tb_sif_mailbox: dirs
|
||
@echo "=== build tb_sif_mailbox_stub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_mailbox_stub.vvp \
|
||
-s tb_sif_mailbox_stub \
|
||
$(RTL_SRCS) $(TB_ROOT)/sif/tb_sif_mailbox_stub.sv
|
||
@echo "=== run tb_sif_mailbox_stub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_mailbox_stub.vvp
|
||
|
||
tb_sif_command_echo: dirs
|
||
@echo "=== build tb_sif_command_echo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_command_echo.vvp \
|
||
-s tb_sif_command_echo \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_command_echo.sv
|
||
@echo "=== run tb_sif_command_echo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_command_echo.vvp
|
||
|
||
tb_sif_command_echo_rearm: dirs
|
||
@echo "=== build tb_sif_command_echo_rearm ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_command_echo_rearm.vvp \
|
||
-s tb_sif_command_echo_rearm \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_command_echo_rearm.sv
|
||
@echo "=== run tb_sif_command_echo_rearm ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_command_echo_rearm.vvp
|
||
|
||
tb_sif_negative_path: dirs
|
||
@echo "=== build tb_sif_negative_path ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_negative_path.vvp \
|
||
-s tb_sif_negative_path \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_negative_path.sv
|
||
@echo "=== run tb_sif_negative_path ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_negative_path.vvp
|
||
|
||
tb_sif_dma_smoke: dirs
|
||
@echo "=== build tb_sif_dma_smoke ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_dma_smoke.vvp \
|
||
-s tb_sif_dma_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_dma_smoke.sv
|
||
@echo "=== run tb_sif_dma_smoke ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_dma_smoke.vvp
|
||
|
||
tb_sif_dma_mid_stall: dirs
|
||
@echo "=== build tb_sif_dma_mid_stall ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_dma_mid_stall.vvp \
|
||
-s tb_sif_dma_mid_stall \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_dma_mid_stall.sv
|
||
@echo "=== run tb_sif_dma_mid_stall ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_dma_mid_stall.vvp
|
||
|
||
tb_sif_dma_overflow: dirs
|
||
@echo "=== build tb_sif_dma_overflow ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_dma_overflow.vvp \
|
||
-s tb_sif_dma_overflow \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_dma_overflow.sv
|
||
@echo "=== run tb_sif_dma_overflow ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_dma_overflow.vvp
|
||
|
||
tb_sif_combined_ctrl_data: dirs
|
||
@echo "=== build tb_sif_combined_ctrl_data ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_combined_ctrl_data.vvp \
|
||
-s tb_sif_combined_ctrl_data \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_combined_ctrl_data.sv
|
||
@echo "=== run tb_sif_combined_ctrl_data ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_combined_ctrl_data.vvp
|
||
|
||
tb_iop_ram: dirs
|
||
@echo "=== build tb_iop_ram_stub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_ram_stub.vvp \
|
||
-s tb_iop_ram_stub \
|
||
$(RTL_SRCS) $(TB_ROOT)/iop/tb_iop_ram_stub.sv
|
||
@echo "=== run tb_iop_ram_stub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_ram_stub.vvp
|
||
|
||
tb_iop_memory_map: dirs
|
||
@echo "=== build tb_iop_memory_map_stub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_memory_map_stub.vvp \
|
||
-s tb_iop_memory_map_stub \
|
||
$(RTL_SRCS) $(TB_ROOT)/iop/tb_iop_memory_map_stub.sv
|
||
@echo "=== run tb_iop_memory_map_stub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_memory_map_stub.vvp
|
||
|
||
# Ch261 — focused arbitration test for the deferred-CPU-RAM-read slot
|
||
# added to iop_memory_map_stub. Drives CPU and DMA reads to different
|
||
# addresses on the same cycle and asserts DMA wins immediately while
|
||
# CPU's read services one cycle later via the pending slot.
|
||
tb_iop_memory_map_collision: dirs
|
||
@echo "=== build tb_iop_memory_map_collision ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_memory_map_collision.vvp \
|
||
-s tb_iop_memory_map_collision \
|
||
$(RTL_SRCS) $(TB_ROOT)/iop/tb_iop_memory_map_collision.sv
|
||
@echo "=== run tb_iop_memory_map_collision ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_memory_map_collision.vvp
|
||
|
||
# Ch234 — focused unit-test TB for sio2_input_stub. Drives the stub
|
||
# directly (without the IOP map) and verifies the active-high→active-low
|
||
# Sony pad-word translation, P1/P2 independence, PAD_STATUS, and
|
||
# write-ignored contract.
|
||
tb_sio2_input_stub: dirs
|
||
@echo "=== build tb_sio2_input_stub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sio2_input_stub.vvp \
|
||
-s tb_sio2_input_stub \
|
||
$(RTL_ROOT)/iop/sio2_input_stub.sv \
|
||
$(TB_ROOT)/iop/tb_sio2_input_stub.sv
|
||
@echo "=== run tb_sio2_input_stub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sio2_input_stub.vvp
|
||
|
||
# Ch235 — bridge + IOP integration TB. Wires ps2_hps_bridge → iop_map
|
||
# across two distinct clocks (100 MHz bridge, 33 MHz IOP); TB drives
|
||
# AXI writes to INPUT_P1/P2 at 0x040/0x044 and reads PAD_P1/P2_STATE
|
||
# at 0x1F80_8500/0x1F80_8504. Verifies the full end-to-end input
|
||
# path including the bridge-clk → IOP-clk CDC inside sio2_input_stub.
|
||
tb_bridge_iop_pad_input: dirs
|
||
@echo "=== build tb_bridge_iop_pad_input ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_bridge_iop_pad_input.vvp \
|
||
-s tb_bridge_iop_pad_input \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_bridge_iop_pad_input.sv
|
||
@echo "=== run tb_bridge_iop_pad_input ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_bridge_iop_pad_input.vvp
|
||
|
||
tb_lpddr_tex_staging: dirs
|
||
@echo "=== build tb_lpddr_tex_staging ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_lpddr_tex_staging.vvp \
|
||
-s tb_lpddr_tex_staging \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_lpddr_tex_staging.sv
|
||
@echo "=== run tb_lpddr_tex_staging ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_lpddr_tex_staging.vvp
|
||
|
||
# Ch238 — pad-state via SIF DMA to EE RAM integration TB. Wires
|
||
# ps2_hps_bridge → iop_memory_map_stub (PAD_P1_STATE) +
|
||
# sif_dma_ee_ram_bridge_stub → ee_memory_map_stub → ee_ram_stub. TB
|
||
# drives AXI writes to INPUT_P1, reads the Sony pad word from the
|
||
# IOP map, packs a 16-byte libpad-compatible buffer into 4 SIF beats,
|
||
# and verifies the qword that lands in EE RAM at the agreed
|
||
# EE_PAD_BUFFER_BASE = 0x0008_0000. No new production RTL —
|
||
# composes existing primitives end-to-end.
|
||
tb_pad_state_via_sif_to_ee: dirs
|
||
@echo "=== build tb_pad_state_via_sif_to_ee ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_pad_state_via_sif_to_ee.vvp \
|
||
-s tb_pad_state_via_sif_to_ee \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_pad_state_via_sif_to_ee.sv
|
||
@echo "=== run tb_pad_state_via_sif_to_ee ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_pad_state_via_sif_to_ee.vvp
|
||
|
||
# Ch240 — EE-side pad-buffer consumer integration TB. Adds an ee_core_stub
|
||
# + bios_rom_stub to the Ch239 pad-transfer harness. EE program is loaded
|
||
# into BIOS at the reset vector; it loops reading byte 3 of the pad buffer
|
||
# at EE_PAD_BUFFER_BASE and branches to one of three markers (A/B/C) based
|
||
# on the controller state. TB drives 4 scenarios (no buttons / RIGHT only /
|
||
# RIGHT+SELECT / re-clear) and verifies the marker bytes the EE wrote.
|
||
tb_ee_pad_buffer_branch: dirs
|
||
@echo "=== build tb_ee_pad_buffer_branch ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_pad_buffer_branch.vvp \
|
||
-s tb_ee_pad_buffer_branch \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_pad_buffer_branch.sv
|
||
@echo "=== run tb_ee_pad_buffer_branch ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_pad_buffer_branch.vvp
|
||
|
||
tb_iop_fetch_through_map: dirs
|
||
@echo "=== build tb_iop_fetch_through_map ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_fetch_through_map.vvp \
|
||
-s tb_iop_fetch_through_map \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_fetch_through_map.sv
|
||
@echo "=== run tb_iop_fetch_through_map ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_fetch_through_map.vvp
|
||
|
||
tb_sif_iop_bridge_smoke: dirs
|
||
@echo "=== build tb_sif_iop_bridge_smoke ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_iop_bridge_smoke.vvp \
|
||
-s tb_sif_iop_bridge_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_iop_bridge_smoke.sv
|
||
@echo "=== run tb_sif_iop_bridge_smoke ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_iop_bridge_smoke.vvp
|
||
|
||
tb_sif_iop_bridge_exec: dirs
|
||
@echo "=== build tb_sif_iop_bridge_exec ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_iop_bridge_exec.vvp \
|
||
-s tb_sif_iop_bridge_exec \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_iop_bridge_exec.sv
|
||
@echo "=== run tb_sif_iop_bridge_exec ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_iop_bridge_exec.vvp
|
||
|
||
tb_iop_to_sif_via_map: dirs
|
||
@echo "=== build tb_iop_to_sif_via_map ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_to_sif_via_map.vvp \
|
||
-s tb_iop_to_sif_via_map \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_to_sif_via_map.sv
|
||
@echo "=== run tb_iop_to_sif_via_map ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_to_sif_via_map.vvp
|
||
|
||
tb_iop_dmac_via_map: dirs
|
||
@echo "=== build tb_iop_dmac_via_map ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_dmac_via_map.vvp \
|
||
-s tb_iop_dmac_via_map \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_dmac_via_map.sv
|
||
@echo "=== run tb_iop_dmac_via_map ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_dmac_via_map.vvp
|
||
|
||
tb_sif_ee_landing_via_dmac: dirs
|
||
@echo "=== build tb_sif_ee_landing_via_dmac ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_ee_landing_via_dmac.vvp \
|
||
-s tb_sif_ee_landing_via_dmac \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_ee_landing_via_dmac.sv
|
||
@echo "=== run tb_sif_ee_landing_via_dmac ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_ee_landing_via_dmac.vvp
|
||
|
||
tb_sif_iop_driven_combined: dirs
|
||
@echo "=== build tb_sif_iop_driven_combined ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_sif_iop_driven_combined.vvp \
|
||
-s tb_sif_iop_driven_combined \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_iop_driven_combined.sv
|
||
@echo "=== run tb_sif_iop_driven_combined ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_iop_driven_combined.vvp
|
||
|
||
tb_ee_dmac_intc: dirs
|
||
@echo "=== build tb_ee_dmac_intc ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_dmac_intc.vvp \
|
||
-s tb_ee_dmac_intc \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_dmac_intc.sv
|
||
@echo "=== run tb_ee_dmac_intc ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_dmac_intc.vvp
|
||
|
||
tb_iop_dmac_intc: dirs
|
||
@echo "=== build tb_iop_dmac_intc ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_dmac_intc.vvp \
|
||
-s tb_iop_dmac_intc \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_dmac_intc.sv
|
||
@echo "=== run tb_iop_dmac_intc ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_dmac_intc.vvp
|
||
|
||
tb_iop_self_driven: dirs
|
||
@echo "=== build tb_iop_self_driven ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_self_driven.vvp \
|
||
-s tb_iop_self_driven \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_self_driven.sv
|
||
@echo "=== run tb_iop_self_driven ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_self_driven.vvp
|
||
|
||
# Ch261 — IOP responder skeleton. Composes iop_exec_stub + iop map
|
||
# + iop_ram + iop_dmac (ch9) + sif_dma_ee_ram_bridge_stub + ee_ram_stub
|
||
# to prove the IOP can produce one EE-visible side effect autonomously
|
||
# from a single go_i pulse. Foundation for Ch262 (wire into BIOS-long).
|
||
tb_iop_responder_ee_ram_landing: dirs
|
||
@echo "=== build tb_iop_responder_ee_ram_landing ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_responder_ee_ram_landing.vvp \
|
||
-s tb_iop_responder_ee_ram_landing \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_responder_ee_ram_landing.sv
|
||
@echo "=== run tb_iop_responder_ee_ram_landing ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_responder_ee_ram_landing.vvp
|
||
|
||
tb_iop_autonomous_two_xfers: dirs
|
||
@echo "=== build tb_iop_autonomous_two_xfers ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_autonomous_two_xfers.vvp \
|
||
-s tb_iop_autonomous_two_xfers \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_autonomous_two_xfers.sv
|
||
@echo "=== run tb_iop_autonomous_two_xfers ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_autonomous_two_xfers.vvp
|
||
|
||
tb_iop_core_basic: dirs
|
||
@echo "=== build tb_iop_core_basic ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_core_basic.vvp \
|
||
-s tb_iop_core_basic \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_core_basic.sv
|
||
@echo "=== run tb_iop_core_basic ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_core_basic.vvp
|
||
|
||
tb_iop_core_interrupts: dirs
|
||
@echo "=== build tb_iop_core_interrupts ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_core_interrupts.vvp \
|
||
-s tb_iop_core_interrupts \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_core_interrupts.sv
|
||
@echo "=== run tb_iop_core_interrupts ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_core_interrupts.vvp
|
||
|
||
tb_iop_core_bootstrap: dirs
|
||
@echo "=== build tb_iop_core_bootstrap ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_core_bootstrap.vvp \
|
||
-s tb_iop_core_bootstrap \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_core_bootstrap.sv
|
||
@echo "=== run tb_iop_core_bootstrap ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_core_bootstrap.vvp
|
||
|
||
tb_iop_core_bootstrap_intc: dirs
|
||
@echo "=== build tb_iop_core_bootstrap_intc ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_core_bootstrap_intc.vvp \
|
||
-s tb_iop_core_bootstrap_intc \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_core_bootstrap_intc.sv
|
||
@echo "=== run tb_iop_core_bootstrap_intc ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_core_bootstrap_intc.vvp
|
||
|
||
# BIOS iteration: set BIOS=<path> on the command line to point the
|
||
# smoke harness at a real BIOS hex image (one 32-bit word per line, no
|
||
# 0x prefix — see sim/golden/bin_to_hex.py to convert a .bin dump).
|
||
# Relative paths are resolved against the repo root so the user can
|
||
# drop a dump anywhere and reference it consistently.
|
||
# make tb_iop_core_bios_smoke # synthetic (CI)
|
||
# make tb_iop_core_bios_smoke BIOS=/tmp/ps2_bios.hex # real iteration
|
||
BIOS ?=
|
||
BIOS_ABS := $(if $(BIOS),$(abspath $(BIOS)))
|
||
BIOS_PLUSARG := $(if $(BIOS_ABS),+BIOS=$(BIOS_ABS))
|
||
|
||
# Ch40 diagnostic preload of a `JR $31; NOP` stub at useg 0xC0 (see
|
||
# tb_ee_core_bios_smoke.sv "Chapter 40" block). Opt-in so the
|
||
# baseline real-BIOS run still exhibits the pre-stub install-gap
|
||
# failure (trap at pc=0x200). Enable with CH40_STUB=1 on the make
|
||
# command line.
|
||
CH40_STUB ?=
|
||
CH40_STUB_PLUSARG := $(if $(CH40_STUB),+CH40_STUB)
|
||
|
||
# Ch49 alignment-exception mode: when set, tb_ee_core_bios_smoke
|
||
# compiles ee_core_stub with TRAP_ALIGN_ERROR=1'b0 so misaligned
|
||
# SW/LW/SH/LH/LHU vector to EXC_VECTOR through the standard MIPS
|
||
# exception path instead of halting. Debugging aid for real-BIOS
|
||
# iteration only — the per-TB focused benches (tb_ee_core_align,
|
||
# tb_ee_core_align_exc) set the parameter directly and ignore this
|
||
# flag.
|
||
CH49_ALIGN_EXC ?=
|
||
CH49_ALIGN_EXC_DEFINE := $(if $(CH49_ALIGN_EXC),-DCH49_ALIGN_EXC)
|
||
|
||
# Ch64 narrow useg->ee_ram CPU-write mirror. When set, the bios-smoke
|
||
# build compiles with `CH64_USEG_MIRROR defined, which causes the TB's
|
||
# u_ee_map instantiation to override CPU_USEG_TO_RAM_MIRROR_EN to 1
|
||
# for the phys window [0x00044000..0x00044700). Experimental; default
|
||
# off to keep the Ch33 de-aliased model intact for every other test.
|
||
CH64_USEG_MIRROR ?=
|
||
CH64_USEG_MIRROR_DEFINE := $(if $(CH64_USEG_MIRROR),-DCH64_USEG_MIRROR)
|
||
|
||
# Ch65 narrow kseg0->useg_shadow CPU-write mirror (symmetric to Ch64).
|
||
# When set, the bios-smoke build compiles with `CH65_KSEG_MIRROR
|
||
# defined, and the TB overrides u_ee_map's
|
||
# CPU_KSEG0_TO_USEG_SHADOW_MIRROR_EN to 1 for phys window
|
||
# [0x001A4000..0x001A5000). Default off.
|
||
CH65_KSEG_MIRROR ?=
|
||
CH65_KSEG_MIRROR_DEFINE := $(if $(CH65_KSEG_MIRROR),-DCH65_KSEG_MIRROR)
|
||
|
||
# Ch70 — single coherent RAM-alias mode covering [0..4MiB), bidirectional.
|
||
# Subsumes the legacy Ch64+Ch65 narrow knobs when set. Default off; same
|
||
# regression compatibility story.
|
||
# make ... BIOS=... CH49_ALIGN_EXC=1 CH55_INSTALL=1 CH70_RAM_ALIAS=1
|
||
CH70_RAM_ALIAS ?=
|
||
CH70_RAM_ALIAS_DEFINE := $(if $(CH70_RAM_ALIAS),-DCH70_RAM_ALIAS)
|
||
|
||
# Ch71 — patient progress runner. Compiles the same bios-smoke TB
|
||
# with -DCH71_LONG_RUN, which bumps the timeout 10x and gates the
|
||
# heaviest observer (LOOP_RING per-retire writes + tail print).
|
||
# Default off; only set by the tb_ee_core_bios_long target below.
|
||
CH71_LONG_RUN ?=
|
||
CH71_LONG_RUN_DEFINE := $(if $(CH71_LONG_RUN),-DCH71_LONG_RUN)
|
||
|
||
# Ch52 diagnostic preload of a minimal AdES/AdEL exception handler
|
||
# stub at useg_shadow[0x80..0x8C] (see tb_ee_core_bios_smoke.sv
|
||
# "Chapter 52" block). 4-instruction handler skips the faulting
|
||
# instruction via EPC+=4 and RFEs back. Forwarded as +CH52_EXC_STUB
|
||
# plusarg. Requires CH40_STUB=1 CH49_ALIGN_EXC=1 to reach the fault
|
||
# point in the first place. Opt-in diagnostic only.
|
||
CH52_EXC_STUB ?=
|
||
CH52_EXC_STUB_PLUSARG := $(if $(CH52_EXC_STUB),+CH52_EXC_STUB)
|
||
|
||
# Ch53 intermediate-richness variant: saves EPC/BadVAddr/Cause into
|
||
# useg 0xA8/0xAC/0xB0 before EPC+=4 + RFE. Designed to answer "does
|
||
# the BIOS care about the handler bytes beyond mere presence?" —
|
||
# if CH53_EXC_STUB advances the BIOS meaningfully further than
|
||
# CH52_EXC_STUB, install-source modeling (SIF/IOP) is next; if not,
|
||
# handler semantics need work. If both are set, CH53 wins (both
|
||
# initial blocks fire on the same r31_to_target edge).
|
||
CH53_EXC_STUB ?=
|
||
CH53_EXC_STUB_PLUSARG := $(if $(CH53_EXC_STUB),+CH53_EXC_STUB)
|
||
|
||
# Ch54 atomic coordinated install for useg 0x80..0x1FF. Single
|
||
# coherent image: AdES handler at 0x80..0x8C, (JR $31; NOP) pairs
|
||
# filling 0x90..0x1FC. Tests whether the BIOS's RAM-handler
|
||
# install is primarily about coordinated coverage of the whole
|
||
# shared surface (exception entry + ch37 dispatch targets at
|
||
# 0xB0/0xC0 + runway slots). Opt-in CH54_BLOB=1 on make command
|
||
# line. Supersedes CH40/CH52 content for overlapping slots.
|
||
CH54_BLOB ?=
|
||
CH54_BLOB_PLUSARG := $(if $(CH54_BLOB),+CH54_BLOB)
|
||
|
||
# Ch55 external install seam: instantiate the boot_install_agent_stub
|
||
# + sif_dma_ee_ram_bridge_stub inside tb_ee_core_bios_smoke, pulse the
|
||
# agent before core_go, and let it stream the Ch54-image payload into
|
||
# useg_shadow via the real SIF bridge-write port. No TB direct poke
|
||
# into useg_shadow_mem for the installed region. Opt-in CH55_INSTALL=1
|
||
# on make. Do not combine with CH54_BLOB (they would both populate
|
||
# the same image but via different seams; pick one).
|
||
CH55_INSTALL ?=
|
||
CH55_INSTALL_PLUSARG := $(if $(CH55_INSTALL),+CH55_INSTALL)
|
||
|
||
# Ch56 runtime image override for the boot_install_agent_stub payload
|
||
# in tb_ee_core_bios_smoke. Transport is unchanged; the TB's opt-in
|
||
# initial block uses $readmemh to overwrite u_install_agent.payload
|
||
# before the install agent is pulsed. Requires CH55_INSTALL=1.
|
||
# make ... CH55_INSTALL=1 CH56_IMAGE=$(SIM_DIR)/data/ch56_ch54_equivalent.mem
|
||
CH56_IMAGE ?=
|
||
CH56_IMAGE_ABS := $(if $(CH56_IMAGE),$(abspath $(CH56_IMAGE)))
|
||
CH56_IMAGE_PLUSARG := $(if $(CH56_IMAGE_ABS),+CH56_IMAGE=$(CH56_IMAGE_ABS))
|
||
|
||
tb_iop_core_bios_smoke: dirs
|
||
@echo "=== build tb_iop_core_bios_smoke ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_iop_core_bios_smoke.vvp \
|
||
-s tb_iop_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_core_bios_smoke.sv
|
||
@echo "=== run tb_iop_core_bios_smoke ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then \
|
||
echo " real BIOS: $(BIOS_ABS)"; \
|
||
fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_core_bios_smoke.vvp $(BIOS_PLUSARG)
|
||
|
||
tb_ee_core_basic: dirs
|
||
@echo "=== build tb_ee_core_basic ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_basic.vvp \
|
||
-s tb_ee_core_basic \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_basic.sv
|
||
@echo "=== run tb_ee_core_basic ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_basic.vvp
|
||
|
||
tb_ee_core_memops: dirs
|
||
@echo "=== build tb_ee_core_memops ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_memops.vvp \
|
||
-s tb_ee_core_memops \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_memops.sv
|
||
@echo "=== run tb_ee_core_memops ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_memops.vvp
|
||
|
||
tb_ee_core_dmac: dirs
|
||
@echo "=== build tb_ee_core_dmac ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_dmac.vvp \
|
||
-s tb_ee_core_dmac \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_dmac.sv
|
||
@echo "=== run tb_ee_core_dmac ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_dmac.vvp
|
||
|
||
tb_ee_core_dmac_poll: dirs
|
||
@echo "=== build tb_ee_core_dmac_poll ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_dmac_poll.vvp \
|
||
-s tb_ee_core_dmac_poll \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_dmac_poll.sv
|
||
@echo "=== run tb_ee_core_dmac_poll ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_dmac_poll.vvp
|
||
|
||
tb_ee_core_dmac_intc: dirs
|
||
@echo "=== build tb_ee_core_dmac_intc ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_dmac_intc.vvp \
|
||
-s tb_ee_core_dmac_intc \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_dmac_intc.sv
|
||
@echo "=== run tb_ee_core_dmac_intc ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_dmac_intc.vvp
|
||
|
||
# The same BIOS=/path/to/bios.hex plusarg convention used by the IOP-side
|
||
# smoke (see tb_iop_core_bios_smoke rule above) — BIOS_ABS and
|
||
# BIOS_PLUSARG already defined there. Leave this target in the same mode
|
||
# so `make tb_ee_core_bios_smoke BIOS=...` works the same way.
|
||
tb_ee_core_bios_smoke: dirs
|
||
@echo "=== build tb_ee_core_bios_smoke ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) $(CH49_ALIGN_EXC_DEFINE) $(CH64_USEG_MIRROR_DEFINE) $(CH65_KSEG_MIRROR_DEFINE) $(CH70_RAM_ALIAS_DEFINE) \
|
||
-o $(BUILD_DIR)/tb_ee_core_bios_smoke.vvp \
|
||
-s tb_ee_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
|
||
@echo "=== run tb_ee_core_bios_smoke ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then \
|
||
echo " real BIOS: $(BIOS_ABS)"; \
|
||
fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_smoke.vvp $(BIOS_PLUSARG) $(CH40_STUB_PLUSARG) $(CH52_EXC_STUB_PLUSARG) $(CH53_EXC_STUB_PLUSARG) $(CH54_BLOB_PLUSARG) $(CH55_INSTALL_PLUSARG) $(CH56_IMAGE_PLUSARG)
|
||
|
||
# Ch71 — patient progress runner. Reuses the same TB source compiled
|
||
# with the bring-up bring-up defines + CH71_LONG_RUN to bump timeout
|
||
# and trim the heaviest observer. Build artifact is separate so the
|
||
# main smoke build is undisturbed.
|
||
# make tb_ee_core_bios_long BIOS=/path/to/bios.hex
|
||
tb_ee_core_bios_long: dirs
|
||
@echo "=== build tb_ee_core_bios_long (=tb_ee_core_bios_smoke + CH49_ALIGN_EXC + CH70_RAM_ALIAS + CH71_LONG_RUN + CH215_JMPBUF_RESTORE) ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE \
|
||
-o $(BUILD_DIR)/tb_ee_core_bios_long.vvp \
|
||
-s tb_ee_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
|
||
@echo "=== run tb_ee_core_bios_long ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then \
|
||
echo " real BIOS: $(BIOS_ABS)"; \
|
||
fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long.vvp $(BIOS_PLUSARG) +CH55_INSTALL
|
||
|
||
# Ch260 — opt-in INTC diagnostic build. Same TB + same defines as
|
||
# tb_ee_core_bios_long, plus -DCH259_INTC_DIAG which unmutes the
|
||
# compact INTC transaction observer ([ch218] lines) gated off in the
|
||
# routine build. Closed-arc artefact: routine BIOS runs no longer
|
||
# need to wade through the observer output, but the compile-time
|
||
# knob is preserved for any future BIOS-mmio probe revival.
|
||
# make tb_ee_core_bios_long_intc_diag BIOS=/path/to/bios.hex
|
||
# ... or with synthetic source bit injection:
|
||
# make tb_ee_core_bios_long_intc_diag BIOS=... IOP_INTC_BOOT_SRC=0001
|
||
.PHONY: tb_ee_core_bios_long_intc_diag
|
||
tb_ee_core_bios_long_intc_diag: dirs
|
||
@echo "=== build tb_ee_core_bios_long_intc_diag (=tb_ee_core_bios_long + CH259_INTC_DIAG) ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH259_INTC_DIAG \
|
||
-o $(BUILD_DIR)/tb_ee_core_bios_long_intc_diag.vvp \
|
||
-s tb_ee_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
|
||
@echo "=== run tb_ee_core_bios_long_intc_diag ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then echo " real BIOS: $(BIOS_ABS)"; fi
|
||
@if [ -n "$(IOP_INTC_BOOT_SRC)" ]; then echo " IOP_INTC_BOOT_SRC=$(IOP_INTC_BOOT_SRC)"; fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_intc_diag.vvp $(BIOS_PLUSARG) +CH55_INSTALL \
|
||
$(if $(IOP_INTC_BOOT_SRC),+IOP_INTC_BOOT_SRC=$(IOP_INTC_BOOT_SRC))
|
||
|
||
# Ch262 — BIOS-long + Ch259 INTC observer + Ch262 synthetic IOP
|
||
# responder. The responder runs once mid-treadmill (~50 ms sim time)
|
||
# and emits a 1-cycle pulse on bridge.last_seen rising edge that ORs
|
||
# into the EE-side iop_intc_inject_src_i path. Designed to answer
|
||
# whether a timed, causally linked IOP-side event changes BIOS
|
||
# behaviour relative to the Ch260 baseline. Opt-in/diagnostic only —
|
||
# routine tb_ee_core_bios_long is unaffected.
|
||
.PHONY: tb_ee_core_bios_long_iop_responder
|
||
tb_ee_core_bios_long_iop_responder: dirs
|
||
@echo "=== build tb_ee_core_bios_long_iop_responder (=tb_ee_core_bios_long + CH259_INTC_DIAG + CH262_IOP_RESPONDER) ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH259_INTC_DIAG -DCH262_IOP_RESPONDER \
|
||
-o $(BUILD_DIR)/tb_ee_core_bios_long_iop_responder.vvp \
|
||
-s tb_ee_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
|
||
@echo "=== run tb_ee_core_bios_long_iop_responder ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then echo " real BIOS: $(BIOS_ABS)"; fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_iop_responder.vvp $(BIOS_PLUSARG) +CH55_INSTALL
|
||
|
||
# Ch263 — Ch262 + retarget the responder DMA into the BIOS-polled
|
||
# kernel-data scan range (EE virt 0x80030200 / phys 0x00030200). The
|
||
# Ch262 INTC pulse path is preserved; the responder now ALSO leaves a
|
||
# real EE-RAM mutation at a slot BIOS empirically scans every pass.
|
||
# Three-way verdict: kernel_mutation_unobserved / observed_no_flow /
|
||
# perturbed_flow. Cross-reference with Ch217 verdict for the flow
|
||
# change call.
|
||
.PHONY: tb_ee_core_bios_long_kernel_mutate
|
||
tb_ee_core_bios_long_kernel_mutate: dirs
|
||
@echo "=== build tb_ee_core_bios_long_kernel_mutate (=tb_ee_core_bios_long_iop_responder + CH263_KERNEL_DATA_MUTATE) ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH259_INTC_DIAG -DCH262_IOP_RESPONDER -DCH263_KERNEL_DATA_MUTATE \
|
||
-o $(BUILD_DIR)/tb_ee_core_bios_long_kernel_mutate.vvp \
|
||
-s tb_ee_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
|
||
@echo "=== run tb_ee_core_bios_long_kernel_mutate ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then echo " real BIOS: $(BIOS_ABS)"; fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_kernel_mutate.vvp $(BIOS_PLUSARG) +CH55_INSTALL
|
||
|
||
# Ch264 — narrow callee-read autopsy. Re-uses the BIOS-long flow with
|
||
# the Ch218-style observer scoped to the longjmp-return callee body at
|
||
# 0xBFC52984..0xBFC52A04 (Codex's candidate C). Captures every data
|
||
# read in that PC range (sampled directly from ee_rd_data, not the
|
||
# arg1-zeroed event), tags each with the region classifier (ev_arg3),
|
||
# and on exit emits the ordered stream + a dedup table that flags the
|
||
# stable polled address(es) the callee gates on. Off by default.
|
||
# make tb_ee_core_bios_long_callee_autopsy BIOS=/path/to/bios.hex
|
||
.PHONY: tb_ee_core_bios_long_callee_autopsy
|
||
tb_ee_core_bios_long_callee_autopsy: dirs
|
||
@echo "=== build tb_ee_core_bios_long_callee_autopsy (=tb_ee_core_bios_long + CH264_CALLEE_AUTOPSY) ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH264_CALLEE_AUTOPSY \
|
||
-o $(BUILD_DIR)/tb_ee_core_bios_long_callee_autopsy.vvp \
|
||
-s tb_ee_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
|
||
@echo "=== run tb_ee_core_bios_long_callee_autopsy ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then echo " real BIOS: $(BIOS_ABS)"; fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_callee_autopsy.vvp $(BIOS_PLUSARG) +CH55_INSTALL
|
||
|
||
# Ch265 — helper-body autopsy at 0xBFC4D370..0xBFC4D470 (one frame
|
||
# deeper than Ch264). Re-uses the Ch264 capture pattern with
|
||
# additions: control-flow tracking (J/JAL/JR/JALR retires inside
|
||
# helper, with statically-decoded J/JAL targets and "LEAVES helper"
|
||
# notes), per-invocation $a0-in / $v0-out / $v1-out snapshots,
|
||
# 5-way verdict (helper_static_{mmio,ram}_gate_found,
|
||
# helper_no_data_reads, helper_is_thunk, helper_reads_vary_but_flow_static).
|
||
# Off by default.
|
||
# make tb_ee_core_bios_long_helper_autopsy BIOS=/path/to/bios.hex
|
||
.PHONY: tb_ee_core_bios_long_helper_autopsy
|
||
tb_ee_core_bios_long_helper_autopsy: dirs
|
||
@echo "=== build tb_ee_core_bios_long_helper_autopsy (=tb_ee_core_bios_long + CH265_HELPER_AUTOPSY) ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH265_HELPER_AUTOPSY \
|
||
-o $(BUILD_DIR)/tb_ee_core_bios_long_helper_autopsy.vvp \
|
||
-s tb_ee_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
|
||
@echo "=== run tb_ee_core_bios_long_helper_autopsy ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then echo " real BIOS: $(BIOS_ABS)"; fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_helper_autopsy.vvp $(BIOS_PLUSARG) +CH55_INSTALL
|
||
|
||
# Ch266 — dispatcher autopsy at 0xBFC4F320..0xBFC4F520 (one frame
|
||
# deeper than Ch265; widened to 0x200 = 128 instructions because
|
||
# this is suspected to be the real dispatcher body, not a thunk).
|
||
# Upgrades over Ch265: captures WRITES as well as reads, snapshots
|
||
# $sp on entry, groups by $a0 selector, and applies a stack-frame
|
||
# filter (discount EAs in $sp..$sp+0x40 and values matching any
|
||
# captured $ra_in). New verdict label `dispatcher_selector_table_found`
|
||
# detects function-pointer-table lookups where read EAs scale as
|
||
# base + $a0 * K. Off by default.
|
||
# make tb_ee_core_bios_long_dispatcher_autopsy BIOS=/path/to/bios.hex
|
||
.PHONY: tb_ee_core_bios_long_dispatcher_autopsy
|
||
tb_ee_core_bios_long_dispatcher_autopsy: dirs
|
||
@echo "=== build tb_ee_core_bios_long_dispatcher_autopsy (=tb_ee_core_bios_long + CH266_DISPATCHER_AUTOPSY) ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH266_DISPATCHER_AUTOPSY \
|
||
-o $(BUILD_DIR)/tb_ee_core_bios_long_dispatcher_autopsy.vvp \
|
||
-s tb_ee_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
|
||
@echo "=== run tb_ee_core_bios_long_dispatcher_autopsy ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then echo " real BIOS: $(BIOS_ABS)"; fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_dispatcher_autopsy.vvp $(BIOS_PLUSARG) +CH55_INSTALL
|
||
|
||
# Ch267 Phase 1 — passive observer keyed on physical address
|
||
# 0x0000A8C8 (the gate STORAGE found by Ch266). Accepts all three
|
||
# kseg/kuseg aliases. Classifies each access as clearer (write 0,
|
||
# especially from the Ch266 dispatcher PC window), writer (non-zero
|
||
# write), or poller (read). Suppresses dispatcher clears beyond the
|
||
# first per Ch217 pass to keep the stream readable. Verdicts:
|
||
# gate_only_cleared_never_polled, gate_polled_zero_no_writer,
|
||
# gate_nonzero_writer_found, gate_alias_mismatch, gate_no_traffic.
|
||
# Off by default.
|
||
# make tb_ee_core_bios_long_gate_observer BIOS=/path/to/bios.hex
|
||
.PHONY: tb_ee_core_bios_long_gate_observer
|
||
tb_ee_core_bios_long_gate_observer: dirs
|
||
@echo "=== build tb_ee_core_bios_long_gate_observer (=tb_ee_core_bios_long + CH267_GATE_OBSERVER) ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH267_GATE_OBSERVER \
|
||
-o $(BUILD_DIR)/tb_ee_core_bios_long_gate_observer.vvp \
|
||
-s tb_ee_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
|
||
@echo "=== run tb_ee_core_bios_long_gate_observer ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then echo " real BIOS: $(BIOS_ABS)"; fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_gate_observer.vvp $(BIOS_PLUSARG) +CH55_INSTALL
|
||
|
||
# Ch268 — widened read autopsy for the longjmp-return OUTER CALLER
|
||
# body (PC 0xBFC52340..0xBFC52400). After Ch267 ruled out
|
||
# 0xA000A8C8, this scans every non-fetch READ the outer caller
|
||
# emits across treadmill passes, buckets by alias-normalized phys
|
||
# EA, and reports per-bucket PCs, per-pass values, alias mask, and
|
||
# stack-filtered gate verdict. 5-way verdicts:
|
||
# outer_static_{mmio,ram}_gate_found, outer_only_stack_reads,
|
||
# outer_no_reads, outer_reads_vary_but_flow_static. Off by default.
|
||
# make tb_ee_core_bios_long_outer_read_autopsy BIOS=/path/to/bios.hex
|
||
.PHONY: tb_ee_core_bios_long_outer_read_autopsy
|
||
tb_ee_core_bios_long_outer_read_autopsy: dirs
|
||
@echo "=== build tb_ee_core_bios_long_outer_read_autopsy (=tb_ee_core_bios_long + CH268_OUTER_READ_AUTOPSY) ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH268_OUTER_READ_AUTOPSY \
|
||
-o $(BUILD_DIR)/tb_ee_core_bios_long_outer_read_autopsy.vvp \
|
||
-s tb_ee_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
|
||
@echo "=== run tb_ee_core_bios_long_outer_read_autopsy ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then echo " real BIOS: $(BIOS_ABS)"; fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_outer_read_autopsy.vvp $(BIOS_PLUSARG) +CH55_INSTALL
|
||
|
||
# Ch269 — $v0 lineage check (Codex's hard-stop chapter). Taps
|
||
# u_core.regfile[2] every cycle, captures each change with the
|
||
# FSM state at the prior cycle (the state that drove the write).
|
||
# Verdict v0_set_by_ch215_restore confirms the BEQ-at-0xBFC52350
|
||
# treadmill is an artifact of our Ch215 jmp_buf restore shim, not
|
||
# a hidden BIOS load — closing the post-Ch215 thunk-chain search.
|
||
# Off by default.
|
||
# make tb_ee_core_bios_long_v0_lineage BIOS=/path/to/bios.hex
|
||
.PHONY: tb_ee_core_bios_long_v0_lineage
|
||
tb_ee_core_bios_long_v0_lineage: dirs
|
||
@echo "=== build tb_ee_core_bios_long_v0_lineage (=tb_ee_core_bios_long + CH269_V0_LINEAGE) ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH269_V0_LINEAGE \
|
||
-o $(BUILD_DIR)/tb_ee_core_bios_long_v0_lineage.vvp \
|
||
-s tb_ee_core_bios_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
|
||
@echo "=== run tb_ee_core_bios_long_v0_lineage ==="
|
||
@if [ -n "$(BIOS_ABS)" ]; then echo " real BIOS: $(BIOS_ABS)"; fi
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_v0_lineage.vvp $(BIOS_PLUSARG) +CH55_INSTALL
|
||
|
||
# Ch270 — BIOS-bypass EE ELF runner. Loads a PS2 EE ELF (or the
|
||
# tiny synthetic test image) into EE RAM, bootstraps the EE core
|
||
# via a LUI/ORI/JR trampoline at 0xBFC00000 pointing at the ELF
|
||
# entry, and runs with STRICT_UNSUPPORTED=1. Emits a 5-way verdict:
|
||
# elf_first_unsupported_opcode → next chapter implements the opcode
|
||
# elf_first_unmapped_mmio → next chapter adds the missing region
|
||
# elf_halted → ELF self-halted
|
||
# elf_timeout_with_hot_pc → ELF ran; reports most-frequent PC
|
||
# elf_entry_unreached / no_retires → bootstrap failure (fail fast)
|
||
#
|
||
# Two variants:
|
||
# tb_ee_core_elf_runner — synthetic loop-to-self ELF
|
||
# (regression default; no env needed)
|
||
# tb_ee_core_elf_runner_real — user-supplied real PS2 ELF via
|
||
# ELF=<path> on the command line
|
||
ELF_IMAGE_SYN := $(BUILD_DIR)/ch270_synth.image.hex
|
||
ELF_MANIFEST_SYN := $(BUILD_DIR)/ch270_synth.manifest.hex
|
||
ELF_TO_EERAM := $(REPO_ROOT)/tools/elf_to_eeram.py
|
||
ELF_GEN_SYN := $(REPO_ROOT)/tools/generate_synthetic_image.py
|
||
|
||
$(ELF_IMAGE_SYN) $(ELF_MANIFEST_SYN): $(ELF_GEN_SYN) | dirs
|
||
@echo "=== generate Ch270 synthetic EE-RAM image ==="
|
||
$(PYTHON) $(ELF_GEN_SYN) --out-prefix $(BUILD_DIR)/ch270_synth
|
||
|
||
.PHONY: tb_ee_core_elf_runner
|
||
tb_ee_core_elf_runner: dirs $(ELF_IMAGE_SYN) $(ELF_MANIFEST_SYN)
|
||
@echo "=== build tb_ee_core_elf_runner ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_elf_runner.vvp \
|
||
-s tb_ee_core_elf_runner \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_elf_runner.sv
|
||
@echo "=== run tb_ee_core_elf_runner (synthetic) ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_elf_runner.vvp \
|
||
+ELF_IMAGE=$(ELF_IMAGE_SYN) +ELF_MANIFEST=$(ELF_MANIFEST_SYN)
|
||
|
||
# User-supplied real ELF: invoke with `ELF=/path/to/game.elf`.
|
||
ELF ?=
|
||
ELF_REAL_IMAGE := $(BUILD_DIR)/ch270_real.image.hex
|
||
ELF_REAL_MANIFEST := $(BUILD_DIR)/ch270_real.manifest.hex
|
||
|
||
.PHONY: tb_ee_core_elf_runner_real
|
||
tb_ee_core_elf_runner_real: dirs
|
||
@if [ -z "$(ELF)" ]; then \
|
||
echo "ERROR: pass ELF=/path/to/game.elf"; exit 2; fi
|
||
@echo "=== convert ELF to EE-RAM image ==="
|
||
$(PYTHON) $(ELF_TO_EERAM) --in $(ELF) --out-prefix $(BUILD_DIR)/ch270_real
|
||
@echo "=== build tb_ee_core_elf_runner ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_elf_runner.vvp \
|
||
-s tb_ee_core_elf_runner \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_elf_runner.sv
|
||
@echo "=== run tb_ee_core_elf_runner (real ELF: $(ELF)) ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_elf_runner.vvp \
|
||
+ELF_IMAGE=$(ELF_REAL_IMAGE) +ELF_MANIFEST=$(ELF_REAL_MANIFEST)
|
||
|
||
tb_ee_core_slti: dirs
|
||
@echo "=== build tb_ee_core_slti ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_slti.vvp \
|
||
-s tb_ee_core_slti \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_slti.sv
|
||
@echo "=== run tb_ee_core_slti ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_slti.vvp
|
||
|
||
tb_ee_core_addi: dirs
|
||
@echo "=== build tb_ee_core_addi ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_addi.vvp \
|
||
-s tb_ee_core_addi \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_addi.sv
|
||
@echo "=== run tb_ee_core_addi ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_addi.vvp
|
||
|
||
# Ch271 — R5900 EE Store Quadword. Implements SQ as a 4-beat 32-bit
|
||
# write FSM (sq_beat counter) through the existing map_wr 32-bit
|
||
# port. Focused TB sets $v0 = 0x80000400, pre-pokes the EE RAM
|
||
# target with non-zero junk, executes `sq $zero, 0($v0)`, then
|
||
# LW-and-BNE-FAILs each of the four words back to verify zeros.
|
||
tb_ee_core_sq: dirs
|
||
@echo "=== build tb_ee_core_sq ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_sq.vvp \
|
||
-s tb_ee_core_sq \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_sq.sv
|
||
@echo "=== run tb_ee_core_sq ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_sq.vvp
|
||
|
||
# Ch272 — R5900 EE DADDU. MIPS-III SPECIAL funct 0x2D. Treated
|
||
# as ADDU (low 32 bits) for our 32-bit-GPR model. Focused TB
|
||
# covers normal add, the exact qbert move-case (0x0080E02D),
|
||
# and unsigned wraparound (no overflow trap).
|
||
tb_ee_core_daddu: dirs
|
||
@echo "=== build tb_ee_core_daddu ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_daddu.vvp \
|
||
-s tb_ee_core_daddu \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_daddu.sv
|
||
@echo "=== run tb_ee_core_daddu ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_daddu.vvp
|
||
|
||
# Ch273 — minimal EE syscall HLE dispatcher. Three known $v1 values
|
||
# from the PS2 crt0 prolog get stub returns and resume at PC+4
|
||
# (EndOfHeap=0x3C, InitMainThread=0x3D, FlushCache=0x64); unknown
|
||
# $v1 still halts so the next blocker surfaces. Gated behind
|
||
# EE_SYSCALL_HLE_ENABLE parameter (default OFF for backwards
|
||
# compat with existing "syscall = halt-PASS" TBs).
|
||
tb_ee_core_syscall_hle: dirs
|
||
@echo "=== build tb_ee_core_syscall_hle ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_syscall_hle.vvp \
|
||
-s tb_ee_core_syscall_hle \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_syscall_hle.sv
|
||
@echo "=== run tb_ee_core_syscall_hle ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_syscall_hle.vvp
|
||
|
||
# Ch274 — MIPS-II BEQL (Branch on Equal Likely). Same compare as
|
||
# BEQ, but on the not-taken path the delay slot is SQUASHED
|
||
# (PC <- PC+8). qbert.elf needs this in its C++ ctor walker
|
||
# where the delay slot at PC+4 clobbers $a0.
|
||
tb_ee_core_beql: dirs
|
||
@echo "=== build tb_ee_core_beql ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_beql.vvp \
|
||
-s tb_ee_core_beql \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_beql.sv
|
||
@echo "=== run tb_ee_core_beql ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_beql.vvp
|
||
|
||
# Ch275 — MIPS-III SD (Store Doubleword), opcode 0x3F. Implemented
|
||
# as a 2-beat 32-bit-stripe write FSM (reusing the SQ sq_beat
|
||
# counter). qbert.elf needs this for `sd $ra, 0x20($sp)` in a
|
||
# function prologue.
|
||
tb_ee_core_sd: dirs
|
||
@echo "=== build tb_ee_core_sd ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_sd.vvp \
|
||
-s tb_ee_core_sd \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_sd.sv
|
||
@echo "=== run tb_ee_core_sd ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_sd.vvp
|
||
|
||
# Ch276 — MIPS-III DSLL (Doubleword Shift Left Logical), SPECIAL
|
||
# funct 0x38. Treated as SLL low-32-bit semantics for our 32-bit
|
||
# regfile model. Focused TB covers exact qbert encoding, low-bit
|
||
# shift, low-32 wrap (bit-31 falls off), and sa=0 identity.
|
||
tb_ee_core_dsll: dirs
|
||
@echo "=== build tb_ee_core_dsll ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_dsll.vvp \
|
||
-s tb_ee_core_dsll \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_dsll.sv
|
||
@echo "=== run tb_ee_core_dsll ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_dsll.vvp
|
||
|
||
# Ch277 — MIPS-II BNEL (Branch on Not Equal Likely), opcode 0x15.
|
||
# Mirror of Ch274 BEQL: taken when rs!=rt (delay fires), not-taken
|
||
# when rs==rt (delay SQUASHED). Reuses the generalized
|
||
# is_branch_likely_squash mechanism added in Ch274.
|
||
tb_ee_core_bnel: dirs
|
||
@echo "=== build tb_ee_core_bnel ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_bnel.vvp \
|
||
-s tb_ee_core_bnel \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bnel.sv
|
||
@echo "=== run tb_ee_core_bnel ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bnel.vvp
|
||
|
||
# Ch278 — R5900 EE MMI2/PCPYLD only (opcode 0x1C, funct 0x09,
|
||
# sa 0x0E). Architectural rd[127:64]=rs[63:0], rd[63:0]=rt[63:0]
|
||
# collapses in our 32-bit model to rd_low32 = rt_low32. Any
|
||
# other MMI sub-instruction still strict-traps so the runner
|
||
# surfaces the next concrete blocker (do NOT NOP the whole MMI
|
||
# group).
|
||
tb_ee_core_pcpyld: dirs
|
||
@echo "=== build tb_ee_core_pcpyld ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_pcpyld.vvp \
|
||
-s tb_ee_core_pcpyld \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_pcpyld.sv
|
||
@echo "=== run tb_ee_core_pcpyld ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_pcpyld.vvp
|
||
|
||
# Ch279 — R5900 EE LQ (Load Quadword), opcode 0x1E. 128-bit
|
||
# load symmetric to Ch271 SQ. Single 32-bit read at the
|
||
# 16-byte-aligned EA; upper 96 bits unrepresentable in our
|
||
# 32-bit-GPR model and discarded.
|
||
tb_ee_core_lq: dirs
|
||
@echo "=== build tb_ee_core_lq ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_lq.vvp \
|
||
-s tb_ee_core_lq \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_lq.sv
|
||
@echo "=== run tb_ee_core_lq ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_lq.vvp
|
||
|
||
# Ch280 — R5900 EE MMI0/PSUBB (Parallel Subtract Byte) only.
|
||
# opcode 0x1C, funct 0x08, sa 0x09. 4 parallel byte subtracts
|
||
# on the low 32 bits (architectural 16-way on 128 bits); no
|
||
# cross-byte borrow.
|
||
tb_ee_core_psubb: dirs
|
||
@echo "=== build tb_ee_core_psubb ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_psubb.vvp \
|
||
-s tb_ee_core_psubb \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_psubb.sv
|
||
@echo "=== run tb_ee_core_psubb ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_psubb.vvp
|
||
|
||
# Ch281 — R5900 EE MMI3/PNOR (Parallel Not-OR) only. opcode
|
||
# 0x1C, funct 0x29 (MMI3), sa 0x13. Bit-identical to standard
|
||
# NOR for the low 32 bits; reuses the NOR writeback arm.
|
||
# With rs=$zero this is the canonical MIPS "NOT" pseudo.
|
||
tb_ee_core_pnor: dirs
|
||
@echo "=== build tb_ee_core_pnor ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_pnor.vvp \
|
||
-s tb_ee_core_pnor \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_pnor.sv
|
||
@echo "=== run tb_ee_core_pnor ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_pnor.vvp
|
||
|
||
# Ch282 — R5900 EE MMI2/PAND (Parallel AND) only. opcode 0x1C,
|
||
# funct 0x09 (MMI2), sa 0x12. Bit-identical to standard AND for
|
||
# the low 32 bits; reuses the AND writeback arm.
|
||
tb_ee_core_pand: dirs
|
||
@echo "=== build tb_ee_core_pand ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_pand.vvp \
|
||
-s tb_ee_core_pand \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_pand.sv
|
||
@echo "=== run tb_ee_core_pand ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_pand.vvp
|
||
|
||
# Ch283 — R5900 EE MMI3/PCPYUD (Parallel Copy Upper Doubleword).
|
||
# opcode 0x1C, funct 0x29 (MMI3), sa 0x0E. First MMI op that reads
|
||
# from the upper 64 bits of source registers; introduces the gpr128
|
||
# shadow that LQ/SQ/SD/PCPYLD/PSUBB/PNOR/PAND now also flow through.
|
||
tb_ee_core_pcpyud: dirs
|
||
@echo "=== build tb_ee_core_pcpyud ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_pcpyud.vvp \
|
||
-s tb_ee_core_pcpyud \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_pcpyud.sv
|
||
@echo "=== run tb_ee_core_pcpyud ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_pcpyud.vvp
|
||
|
||
# Ch284 — MIPS-III LD (Load Doubleword), opcode 0x37. The read-side
|
||
# of SD; 2-beat 32-bit load FSM (terminal sq_beat = 1) writing two
|
||
# lanes of gpr128[rt] and mirroring low 32 to regfile[rt]. 8-byte
|
||
# alignment required.
|
||
tb_ee_core_ld: dirs
|
||
@echo "=== build tb_ee_core_ld ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_ld.vvp \
|
||
-s tb_ee_core_ld \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_ld.sv
|
||
@echo "=== run tb_ee_core_ld ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_ld.vvp
|
||
|
||
# Ch286 — R5900 EI (Enable Interrupts), narrow exact-32-bit decode
|
||
# of the canonical encoding 0x42000038. Side-effect-free accept;
|
||
# every other COP0/CO encoding still traps under strict mode.
|
||
tb_ee_core_ei: dirs
|
||
@echo "=== build tb_ee_core_ei ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_ei.vvp \
|
||
-s tb_ee_core_ei \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_ei.sv
|
||
@echo "=== run tb_ee_core_ei ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_ei.vvp
|
||
|
||
# Ch287 — EE DMAC global control/status stub (D_CTRL/D_STAT/D_PCR/
|
||
# D_SQWC/D_RBSR/D_RBOR at 0x1000_E000+). Instantiated INTERNALLY in
|
||
# ee_memory_map_stub so existing TBs don't need new ports.
|
||
tb_ee_dmac_ctrl_stub: dirs
|
||
@echo "=== build tb_ee_dmac_ctrl_stub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_dmac_ctrl_stub.vvp \
|
||
-s tb_ee_dmac_ctrl_stub \
|
||
$(RTL_SRCS) $(TB_ROOT)/dmac/tb_ee_dmac_ctrl_stub.sv
|
||
@echo "=== run tb_ee_dmac_ctrl_stub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_dmac_ctrl_stub.vvp
|
||
|
||
# Ch288 — EE DMAC passive per-channel surface (ch0/1/3/4/5). Covers
|
||
# the unmodeled channels qbert touches during init clear. Latched
|
||
# CHCR/MADR/QWC/TADR; no transfer FSM. Instantiated INTERNALLY in
|
||
# ee_memory_map_stub.
|
||
tb_ee_dmac_passive_chan_stub: dirs
|
||
@echo "=== build tb_ee_dmac_passive_chan_stub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_dmac_passive_chan_stub.vvp \
|
||
-s tb_ee_dmac_passive_chan_stub \
|
||
$(RTL_SRCS) $(TB_ROOT)/dmac/tb_ee_dmac_passive_chan_stub.sv
|
||
@echo "=== run tb_ee_dmac_passive_chan_stub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_dmac_passive_chan_stub.vvp
|
||
|
||
# Ch292 — MIPS SYNC (SPECIAL funct 0x0F). Narrow side-effect-free
|
||
# accept; neighbor SPECIAL funct 0x0E still traps under strict mode.
|
||
tb_ee_core_sync: dirs
|
||
@echo "=== build tb_ee_core_sync ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_sync.vvp \
|
||
-s tb_ee_core_sync \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_sync.sv
|
||
@echo "=== run tb_ee_core_sync ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_sync.vvp
|
||
|
||
# Ch300 — R5900 EE MMI3/PCPYH (Parallel Copy Halfword), opcode
|
||
# 0x1C, funct 0x29 (MMI3), sa 0x1B. Broadcasts low halfword of each
|
||
# $rt doubleword across the corresponding $rd doubleword. Full-128
|
||
# writeback via the gpr128 shadow.
|
||
tb_ee_core_pcpyh: dirs
|
||
@echo "=== build tb_ee_core_pcpyh ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_pcpyh.vvp \
|
||
-s tb_ee_core_pcpyh \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_pcpyh.sv
|
||
@echo "=== run tb_ee_core_pcpyh ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_pcpyh.vvp
|
||
|
||
# Ch305 — R5900 DSUBU (doubleword subtract unsigned), SPECIAL funct
|
||
# 0x2F. Modelled as SUBU low-32 (sibling of Ch272 DADDU); no
|
||
# overflow trap.
|
||
tb_ee_core_dsubu: dirs
|
||
@echo "=== build tb_ee_core_dsubu ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_dsubu.vvp \
|
||
-s tb_ee_core_dsubu \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_dsubu.sv
|
||
@echo "=== run tb_ee_core_dsubu ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_dsubu.vvp
|
||
|
||
tb_ee_core_andi: dirs
|
||
@echo "=== build tb_ee_core_andi ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_andi.vvp \
|
||
-s tb_ee_core_andi \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_andi.sv
|
||
@echo "=== run tb_ee_core_andi ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_andi.vvp
|
||
|
||
# Ch178 — focused TB pinning CACHE-as-NOP. Issues the exact BIOS
|
||
# encoding (CACHE op=0x05, 0x29B0($30) = 0xBFC529B0) that triggered
|
||
# the Ch177 strict trap plus a second sub-op to prove "whole class
|
||
# accepted". Then verifies $2 wasn't clobbered.
|
||
tb_ee_core_cache: dirs
|
||
@echo "=== build tb_ee_core_cache ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_cache.vvp \
|
||
-s tb_ee_core_cache \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_cache.sv
|
||
@echo "=== run tb_ee_core_cache ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_cache.vvp
|
||
|
||
tb_ee_core_rtype_logic: dirs
|
||
@echo "=== build tb_ee_core_rtype_logic ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_rtype_logic.vvp \
|
||
-s tb_ee_core_rtype_logic \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_rtype_logic.sv
|
||
@echo "=== run tb_ee_core_rtype_logic ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_rtype_logic.vvp
|
||
|
||
tb_ee_core_sb: dirs
|
||
@echo "=== build tb_ee_core_sb ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_sb.vvp \
|
||
-s tb_ee_core_sb \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_sb.sv
|
||
@echo "=== run tb_ee_core_sb ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_sb.vvp
|
||
|
||
tb_ee_core_lb: dirs
|
||
@echo "=== build tb_ee_core_lb ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_lb.vvp \
|
||
-s tb_ee_core_lb \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_lb.sv
|
||
@echo "=== run tb_ee_core_lb ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_lb.vvp
|
||
|
||
tb_ee_core_jal: dirs
|
||
@echo "=== build tb_ee_core_jal ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_jal.vvp \
|
||
-s tb_ee_core_jal \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_jal.sv
|
||
@echo "=== run tb_ee_core_jal ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_jal.vvp
|
||
|
||
tb_ee_core_rtype_addu: dirs
|
||
@echo "=== build tb_ee_core_rtype_addu ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_rtype_addu.vvp \
|
||
-s tb_ee_core_rtype_addu \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_rtype_addu.sv
|
||
@echo "=== run tb_ee_core_rtype_addu ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_rtype_addu.vvp
|
||
|
||
tb_ee_core_slt: dirs
|
||
@echo "=== build tb_ee_core_slt ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_slt.vvp \
|
||
-s tb_ee_core_slt \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_slt.sv
|
||
@echo "=== run tb_ee_core_slt ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_slt.vvp
|
||
|
||
tb_ee_core_lh: dirs
|
||
@echo "=== build tb_ee_core_lh ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_lh.vvp \
|
||
-s tb_ee_core_lh \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_lh.sv
|
||
@echo "=== run tb_ee_core_lh ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_lh.vvp
|
||
|
||
tb_ee_core_lhu: dirs
|
||
@echo "=== build tb_ee_core_lhu ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_lhu.vvp \
|
||
-s tb_ee_core_lhu \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_lhu.sv
|
||
@echo "=== run tb_ee_core_lhu ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_lhu.vvp
|
||
|
||
tb_ee_core_shift: dirs
|
||
@echo "=== build tb_ee_core_shift ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_shift.vvp \
|
||
-s tb_ee_core_shift \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_shift.sv
|
||
@echo "=== run tb_ee_core_shift ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_shift.vvp
|
||
|
||
tb_ee_core_sh: dirs
|
||
@echo "=== build tb_ee_core_sh ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_sh.vvp \
|
||
-s tb_ee_core_sh \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_sh.sv
|
||
@echo "=== run tb_ee_core_sh ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_sh.vvp
|
||
|
||
tb_ee_core_jalr: dirs
|
||
@echo "=== build tb_ee_core_jalr ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_jalr.vvp \
|
||
-s tb_ee_core_jalr \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_jalr.sv
|
||
@echo "=== run tb_ee_core_jalr ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_jalr.vvp
|
||
|
||
tb_ee_core_add_sub: dirs
|
||
@echo "=== build tb_ee_core_add_sub ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_add_sub.vvp \
|
||
-s tb_ee_core_add_sub \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_add_sub.sv
|
||
@echo "=== run tb_ee_core_add_sub ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_add_sub.vvp
|
||
|
||
tb_ee_core_branch_zero: dirs
|
||
@echo "=== build tb_ee_core_branch_zero ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_branch_zero.vvp \
|
||
-s tb_ee_core_branch_zero \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_branch_zero.sv
|
||
@echo "=== run tb_ee_core_branch_zero ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_branch_zero.vvp
|
||
|
||
tb_ee_core_lbu: dirs
|
||
@echo "=== build tb_ee_core_lbu ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_lbu.vvp \
|
||
-s tb_ee_core_lbu \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_lbu.sv
|
||
@echo "=== run tb_ee_core_lbu ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_lbu.vvp
|
||
|
||
tb_ee_core_divu_mflo: dirs
|
||
@echo "=== build tb_ee_core_divu_mflo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_divu_mflo.vvp \
|
||
-s tb_ee_core_divu_mflo \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_divu_mflo.sv
|
||
@echo "=== run tb_ee_core_divu_mflo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_divu_mflo.vvp
|
||
|
||
tb_ee_core_multu_mflo: dirs
|
||
@echo "=== build tb_ee_core_multu_mflo ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_multu_mflo.vvp \
|
||
-s tb_ee_core_multu_mflo \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_multu_mflo.sv
|
||
@echo "=== run tb_ee_core_multu_mflo ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_multu_mflo.vvp
|
||
|
||
tb_ee_core_align: dirs
|
||
@echo "=== build tb_ee_core_align ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_align.vvp \
|
||
-s tb_ee_core_align \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_align.sv
|
||
@echo "=== run tb_ee_core_align ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_align.vvp
|
||
|
||
tb_ee_core_align_exc: dirs
|
||
@echo "=== build tb_ee_core_align_exc ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_align_exc.vvp \
|
||
-s tb_ee_core_align_exc \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_align_exc.sv
|
||
@echo "=== run tb_ee_core_align_exc ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_align_exc.vvp
|
||
|
||
tb_ee_core_bev: dirs
|
||
@echo "=== build tb_ee_core_bev ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_bev.vvp \
|
||
-s tb_ee_core_bev \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bev.sv
|
||
@echo "=== run tb_ee_core_bev ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bev.vvp
|
||
|
||
tb_ee_core_cop0_count: dirs
|
||
@echo "=== build tb_ee_core_cop0_count ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_cop0_count.vvp \
|
||
-s tb_ee_core_cop0_count \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_cop0_count.sv
|
||
@echo "=== run tb_ee_core_cop0_count ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_cop0_count.vvp
|
||
|
||
tb_ee_bootstrap_mmio: dirs
|
||
@echo "=== build tb_ee_bootstrap_mmio ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_bootstrap_mmio.vvp \
|
||
-s tb_ee_bootstrap_mmio \
|
||
$(RTL_SRCS) $(TB_ROOT)/ee/tb_ee_bootstrap_mmio.sv
|
||
@echo "=== run tb_ee_bootstrap_mmio ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_bootstrap_mmio.vvp
|
||
|
||
tb_ee_biu_mmio: dirs
|
||
@echo "=== build tb_ee_biu_mmio ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_biu_mmio.vvp \
|
||
-s tb_ee_biu_mmio \
|
||
$(RTL_SRCS) $(TB_ROOT)/ee/tb_ee_biu_mmio.sv
|
||
@echo "=== run tb_ee_biu_mmio ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_biu_mmio.vvp
|
||
|
||
tb_ee_core_gif_packed: dirs
|
||
@echo "=== build tb_ee_core_gif_packed ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_packed.vvp \
|
||
-s tb_ee_core_gif_packed \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_packed.sv
|
||
@echo "=== run tb_ee_core_gif_packed ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_packed.vvp
|
||
|
||
tb_ee_core_gif_reglist: dirs
|
||
@echo "=== build tb_ee_core_gif_reglist ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_reglist.vvp \
|
||
-s tb_ee_core_gif_reglist \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_reglist.sv
|
||
@echo "=== run tb_ee_core_gif_reglist ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_reglist.vvp
|
||
|
||
tb_ee_core_gif_primitive: dirs
|
||
@echo "=== build tb_ee_core_gif_primitive ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_primitive.vvp \
|
||
-s tb_ee_core_gif_primitive \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_primitive.sv
|
||
@echo "=== run tb_ee_core_gif_primitive ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_primitive.vvp
|
||
|
||
tb_ee_core_gif_primitive_observer: dirs
|
||
@echo "=== build tb_ee_core_gif_primitive_observer ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_primitive_observer.vvp \
|
||
-s tb_ee_core_gif_primitive_observer \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_primitive_observer.sv
|
||
@echo "=== run tb_ee_core_gif_primitive_observer ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_primitive_observer.vvp
|
||
|
||
tb_ee_core_gif_primitive_strip: dirs
|
||
@echo "=== build tb_ee_core_gif_primitive_strip ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_primitive_strip.vvp \
|
||
-s tb_ee_core_gif_primitive_strip \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_primitive_strip.sv
|
||
@echo "=== run tb_ee_core_gif_primitive_strip ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_primitive_strip.vvp
|
||
|
||
tb_ee_core_gif_primitive_gouraud: dirs
|
||
@echo "=== build tb_ee_core_gif_primitive_gouraud ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_primitive_gouraud.vvp \
|
||
-s tb_ee_core_gif_primitive_gouraud \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_primitive_gouraud.sv
|
||
@echo "=== run tb_ee_core_gif_primitive_gouraud ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_primitive_gouraud.vvp
|
||
|
||
tb_ee_core_gif_pixel_emit: dirs
|
||
@echo "=== build tb_ee_core_gif_pixel_emit ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_pixel_emit.vvp \
|
||
-s tb_ee_core_gif_pixel_emit \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_pixel_emit.sv
|
||
@echo "=== run tb_ee_core_gif_pixel_emit ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_pixel_emit.vvp
|
||
|
||
tb_ee_core_gif_pixel_emit_psm: dirs
|
||
@echo "=== build tb_ee_core_gif_pixel_emit_psm ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_pixel_emit_psm.vvp \
|
||
-s tb_ee_core_gif_pixel_emit_psm \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_pixel_emit_psm.sv
|
||
@echo "=== run tb_ee_core_gif_pixel_emit_psm ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_pixel_emit_psm.vvp
|
||
|
||
tb_ee_core_gif_raster_basic: dirs
|
||
@echo "=== build tb_ee_core_gif_raster_basic ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_raster_basic.vvp \
|
||
-s tb_ee_core_gif_raster_basic \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_raster_basic.sv
|
||
@echo "=== run tb_ee_core_gif_raster_basic ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_raster_basic.vvp
|
||
|
||
tb_ee_core_gif_raster_topleft: dirs
|
||
@echo "=== build tb_ee_core_gif_raster_topleft ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_raster_topleft.vvp \
|
||
-s tb_ee_core_gif_raster_topleft \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_raster_topleft.sv
|
||
@echo "=== run tb_ee_core_gif_raster_topleft ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_raster_topleft.vvp
|
||
|
||
tb_ee_core_gif_raster_gouraud: dirs
|
||
@echo "=== build tb_ee_core_gif_raster_gouraud ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_raster_gouraud.vvp \
|
||
-s tb_ee_core_gif_raster_gouraud \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_raster_gouraud.sv
|
||
@echo "=== run tb_ee_core_gif_raster_gouraud ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_raster_gouraud.vvp
|
||
|
||
tb_ee_core_gif_raster_queue: dirs
|
||
@echo "=== build tb_ee_core_gif_raster_queue ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_gif_raster_queue.vvp \
|
||
-s tb_ee_core_gif_raster_queue \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_raster_queue.sv
|
||
@echo "=== run tb_ee_core_gif_raster_queue ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_raster_queue.vvp
|
||
|
||
tb_ee_core_varshift: dirs
|
||
@echo "=== build tb_ee_core_varshift ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_core_varshift.vvp \
|
||
-s tb_ee_core_varshift \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_varshift.sv
|
||
@echo "=== run tb_ee_core_varshift ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_varshift.vvp
|
||
|
||
tb_ee_install_agent_smoke: dirs
|
||
@echo "=== build tb_ee_install_agent_smoke ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-o $(BUILD_DIR)/tb_ee_install_agent_smoke.vvp \
|
||
-s tb_ee_install_agent_smoke \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_install_agent_smoke.sv
|
||
@echo "=== run tb_ee_install_agent_smoke ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_install_agent_smoke.vvp
|
||
|
||
tb_ee_install_agent_external_image: dirs
|
||
@echo "=== build tb_ee_install_agent_external_image ==="
|
||
$(IVERILOG) $(IVERILOG_FLGS) \
|
||
-DCH56_TB_IMAGE_PATH='"$(SIM_DIR)/data/ch56_test_image_4w.mem"' \
|
||
-o $(BUILD_DIR)/tb_ee_install_agent_external_image.vvp \
|
||
-s tb_ee_install_agent_external_image \
|
||
$(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_install_agent_external_image.sv
|
||
@echo "=== run tb_ee_install_agent_external_image ==="
|
||
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_install_agent_external_image.vvp
|
||
|
||
run: tb_ee_fetch tb_gs tb_intc tb_platform_video tb_bgcolor_via_dma tb_sif_mailbox \
|
||
tb_sif_command_echo tb_sif_command_echo_rearm tb_sif_negative_path \
|
||
tb_sif_dma_smoke tb_sif_dma_mid_stall tb_sif_dma_overflow tb_sif_combined_ctrl_data \
|
||
tb_iop_ram tb_iop_memory_map tb_iop_memory_map_collision tb_iop_fetch_through_map tb_sif_iop_bridge_smoke \
|
||
tb_sif_iop_bridge_exec tb_iop_to_sif_via_map tb_iop_dmac_via_map \
|
||
tb_sif_ee_landing_via_dmac tb_sif_iop_driven_combined \
|
||
tb_ee_dmac_intc tb_iop_dmac_intc tb_iop_self_driven \
|
||
tb_iop_autonomous_two_xfers tb_iop_responder_ee_ram_landing \
|
||
tb_iop_core_basic tb_iop_core_interrupts \
|
||
tb_iop_core_bootstrap tb_iop_core_bootstrap_intc tb_iop_core_bios_smoke \
|
||
tb_ee_core_basic tb_ee_core_memops tb_ee_core_dmac tb_ee_core_dmac_poll \
|
||
tb_ee_core_dmac_intc tb_ee_core_bios_smoke tb_ee_core_slti \
|
||
tb_ee_core_addi tb_ee_core_andi tb_ee_core_cache tb_ee_core_rtype_logic \
|
||
tb_ee_core_sb tb_ee_core_lb tb_ee_core_jal tb_ee_core_rtype_addu \
|
||
tb_ee_core_slt tb_ee_core_lh tb_ee_core_lhu tb_ee_core_shift \
|
||
tb_ee_core_sh tb_ee_core_jalr tb_ee_core_add_sub \
|
||
tb_ee_core_branch_zero tb_ee_core_lbu tb_ee_core_divu_mflo tb_ee_core_multu_mflo \
|
||
tb_ee_core_align tb_ee_core_align_exc tb_ee_core_bev \
|
||
tb_ee_core_cop0_count tb_ee_bootstrap_mmio tb_ee_biu_mmio \
|
||
tb_ee_core_gif_packed tb_ee_core_gif_reglist tb_ee_core_gif_primitive tb_ee_core_gif_primitive_observer tb_ee_core_gif_primitive_strip tb_ee_core_gif_primitive_gouraud tb_ee_core_gif_pixel_emit tb_ee_core_gif_pixel_emit_psm tb_ee_core_gif_raster_basic tb_ee_core_gif_raster_topleft tb_ee_core_gif_raster_gouraud tb_ee_core_gif_raster_queue tb_gs_raster_queue_full_pop tb_gs_raster_pipeline tb_gs_prim_list_feeder tb_gs_vram_writeback tb_vram_stub tb_vram_bram_stub_equivalence tb_vram_normalize_write tb_gs_scanout_basic tb_gs_scanout_dbx_dby tb_gs_scanout_display_window tb_gs_scanout_magh_magv tb_gs_scanout_psm16 tb_gs_scanout_psmt8 tb_gs_scanout_psmt8_clut tb_gs_tex0_clut tb_gs_clut_load tb_gs_clut_load_ct16 tb_gs_clut_load_cld_modes tb_gs_clut_load_csa_window tb_gs_scanout_psmt4_clut tb_gs_psmt4_round_trip tb_gs_raster_psmct16 tb_gs_raster_psmt8 tb_gs_textured_sprite tb_gs_textured_alpha_sprite tb_gs_psmt8_alpha_sprite tb_gs_psmt8_clut_triangle tb_clut_loader_csm1 tb_gs_raster_psmt4 tb_gs_demo_psmt4_e2e tb_gs_demo_psmt4_e2e_packed tb_gs_demo_psmt4_e2e_dmac tb_gs_demo_psmt4_e2e_trxdir tb_gs_demo_psmt4_e2e_eemmio tb_gs_demo_psmt4_e2e_eemap tb_gs_demo_psmt4_e2e_ee_program tb_gs_demo_psmt4_e2e_ee_full_bootlet tb_ee_ram_cpu_dmac_contention tb_gs_image_xfer_psmct16 tb_gs_image_xfer_psmt8 tb_gs_image_xfer_psmt4 tb_gs_swizzle_psmct32 tb_gs_swizzle_psmct16 tb_gs_swizzle_psmt8 tb_gs_swizzle_psmt4 tb_gs_scanout_swizzle_psmt4 tb_gs_image_xfer_swizzle_psmt4 tb_gs_raster_swizzle_psmt4 tb_gs_demo_psmt4_swizzle_e2e tb_gs_demo_psmt4_swizzle_trxdir_e2e tb_top_psmct32_raster_demo tb_top_psmct32_textured_demo tb_top_psmct32_raster_demo_bram tb_top_psmct32_raster_demo_bram_textured tb_top_psmct32_raster_demo_bram_ch171 tb_gs_raster_backpressure_stress tb_ps2_hps_bridge tb_gs_raster_bram_psmct16 tb_gs_raster_bram_psmt8 tb_gs_raster_bram_psmt4 tb_gs_scanout_bram_psmct16 tb_gs_scanout_bram_psmt8 tb_de25_nano_psmct32_raster_demo_top tb_hdmi_i2c_wake_smoke tb_gs_scanout_swizzle_psmt8 tb_gs_image_xfer_swizzle_psmt8 tb_gs_raster_swizzle_psmt8 tb_gs_demo_psmt8_swizzle_e2e tb_gs_demo_psmt8_swizzle_trxdir_e2e tb_gs_scanout_swizzle_psmct16 tb_gs_image_xfer_swizzle_psmct16 tb_gs_scanout_swizzle_psmct32 tb_gs_image_xfer_swizzle_psmct32 tb_gs_raster_swizzle_psmct32 tb_gs_raster_swizzle_psmct16 tb_gs_demo_psmct32_swizzle_e2e tb_gs_demo_psmct32_swizzle_trxdir_e2e tb_gs_demo_psmct16_swizzle_e2e tb_gs_demo_psmct16_swizzle_trxdir_e2e tb_ee_core_varshift tb_ee_install_agent_smoke tb_ee_install_agent_external_image tb_tile_ram_cdc tb_sio2_input_stub tb_bridge_iop_pad_input tb_pad_state_via_sif_to_ee tb_ee_pad_buffer_branch tb_lpddr_tex_staging tb_osd_platform_cell_adapter tb_ee_core_elf_runner tb_ee_core_sq tb_ee_core_daddu tb_ee_core_syscall_hle tb_ee_core_beql tb_ee_core_sd tb_ee_core_dsll tb_ee_core_bnel tb_ee_core_pcpyld tb_ee_core_lq tb_ee_core_psubb tb_ee_core_pnor tb_ee_core_pand tb_ee_core_pcpyud tb_ee_core_ld tb_ee_core_ei tb_ee_dmac_ctrl_stub tb_ee_dmac_passive_chan_stub tb_ee_core_sync tb_ee_core_pcpyh tb_ee_core_dsubu tb_gs_lpddr_fb_writer tb_gs_lpddr_axi_master tb_gs_lpddr_rd_probe tb_gs_lpddr_scanout tb_gs_lpddr_scanout_psm32 tb_gs_lpddr_scanout_concurrency tb_gs_lpddr_scanout_lb_psm32 tb_gs_lpddr_scanout_lb_psm32_256 tb_gs_lpddr_rd_arb tb_gs_lpddr_scanout_lb tb_gs_texture_cache tb_gs_lpddr_wr_probe tb_gs_lpddr_wr_arb tb_gs_tile_reload tb_gs_tile_reload_grid tb_gs_z_flush_writer tb_gs_alpha_blend tb_top_psmct32_alpha_blend_demo tb_top_psmct32_texalpha_demo tb_gs_zbuffer tb_top_psmct32_zbuffer_demo tb_gs_tri_interp tb_top_psmct32_triangle_demo tb_gs_textured_triangle tb_top_psmct32_raster_demo_bram_tritex tb_top_psmct32_raster_demo_bram_lpddrtex tb_gs_texture_psmt8_clut tb_gs_texture_wrap tb_gs_texture_bilinear tb_top_psmct32_raster_demo_bram_clut tb_gs_texture_psmt4_clut tb_gs_texture_swizzle_psmt4_clut tb_top_psmct32_raster_demo_bram_clut4 tb_top_psmct32_raster_demo_bram_swz4 tb_gs_texture_swizzle_psmt8_clut tb_top_psmct32_raster_demo_bram_swz8 tb_gs_texture_swizzle_psmct32 tb_top_psmct32_raster_demo_bram_swz32 tb_gs_reciprocal tb_gs_persp_uv tb_gs_persp_uv_farw tb_gs_grad_divider tb_top_psmct32_perspective_demo tb_top_psmct32_persp_floor_demo tb_top_psmct32_combined_demo tb_gs_tile_ram tb_top_psmct32_tile_demo tb_gs_tile_zflush tb_gs_tile_spill_reload tb_gs_tile_spill_lpddr tb_gs_tile_spill_grid_lpddr tb_gs_tile_spill_grid8x8_lpddr tb_gs_tile_spill_lpddr_neg tb_top_psmct32_tile2x2_demo tb_top_psmct32_tile_multiprim_demo tb_top_psmct32_tile_scissor_demo tb_top_psmct32_tile_wrap_demo tb_top_psmct32_tile_psmct16_demo tb_top_psmct32_tile_alpha_demo tb_top_psmct32_tile_bilinear_demo tb_top_psmct32_tile_bin_demo tb_top_psmct32_tile_bin4x4_demo tb_top_psmct32_tile_psmct16fb_demo tb_top_psmct32_tile_lpddr128_demo tb_top_psmct32_tile_palbilinear_demo tb_top_psmct32_tile_cap_demo tb_top_psmct32_tile_cap_overflow_demo tb_top_psmct32_tile_sprite18_demo tb_top_psmct32_tile_cap64_demo tb_top_psmct32_feeder_equiv_demo tb_top_psmct32_feeder_runtime_demo tb_top_psmct32_feeder_bridge_demo tb_top_psmct32_feeder_scenes_demo tb_top_psmct32_feeder_shapes_demo tb_top_psmct32_feeder_colors_demo tb_top_psmct32_feeder_native_demo tb_top_psmct32_feeder_gouraud_demo tb_top_psmct32_feeder_accum_demo tb_top_psmct32_feeder_scene_retrigger_demo tb_top_psmct32_feeder_zpersist_demo tb_top_psmct32_feeder_persp_demo tb_top_psmct32_feeder_sprite_demo tb_top_psmct32_tile_late_demo tb_top_psmct32_tile_lpddrfb_demo
|
||
@echo
|
||
@echo "=== all testbenches complete ==="
|
||
|
||
# ---------------------------------------------------------------------
|
||
# Inspection + cleanup
|
||
# ---------------------------------------------------------------------
|
||
|
||
traces:
|
||
@echo "traces in $(TRACE_DIR):"
|
||
@ls -la $(TRACE_DIR) 2>/dev/null || echo "(none yet)"
|
||
|
||
clean:
|
||
rm -rf $(BUILD_DIR) $(TRACE_DIR) $(GOLD_TRC_DIR)
|
||
@echo "cleaned build, rtl trace, and golden trace directories"
|
||
|
||
# ---------------------------------------------------------------------
|
||
# Golden-reference harness (Milestone B track)
|
||
# ---------------------------------------------------------------------
|
||
#
|
||
# Spec: sim/golden/trace_compare_spec.md
|
||
# Tools:
|
||
# sim/golden/make_nop_golden.py — generates the NOP-sled golden trace
|
||
# sim/golden/trace_compare.py — filtered order-based diff
|
||
|
||
GOLDEN_NOP := $(GOLD_TRC_DIR)/nop_sled.trace
|
||
RTL_FETCH := $(TRACE_DIR)/ee_fetch.trace
|
||
|
||
golden_nop: dirs
|
||
@echo "=== generate NOP-sled golden ==="
|
||
$(PYTHON) $(GOLDEN_DIR)/make_nop_golden.py --count 32 -o $(GOLDEN_NOP)
|
||
|
||
compare_ee_fetch: tb_ee_fetch golden_nop
|
||
@echo "=== compare RTL ee_fetch.trace against NOP-sled golden ==="
|
||
$(PYTHON) $(GOLDEN_DIR)/trace_compare.py $(RTL_FETCH) $(GOLDEN_NOP)
|
||
|
||
# Meta-test that exercises the comparator against the three documented
|
||
# exit-code paths (acceptance criteria 4, 5, 6 in trace_compare_spec.md).
|
||
test_compare: tb_ee_fetch golden_nop
|
||
@echo
|
||
@echo "=== test_compare: clean run must exit 0 ==="
|
||
$(PYTHON) $(GOLDEN_DIR)/trace_compare.py $(RTL_FETCH) $(GOLDEN_NOP)
|
||
@echo
|
||
@echo "=== test_compare: corrupted golden must exit 1 ==="
|
||
@cp $(GOLDEN_NOP) $(BUILD_DIR)/corrupt_golden.trace
|
||
@sed -i '5s/0x0000000000000000 0x0000000000000000 0x0000000000000000 -/0x00000000deadbeef 0x0000000000000000 0x0000000000000000 -/' $(BUILD_DIR)/corrupt_golden.trace
|
||
@$(PYTHON) $(GOLDEN_DIR)/trace_compare.py $(RTL_FETCH) $(BUILD_DIR)/corrupt_golden.trace; \
|
||
rc=$$?; \
|
||
if [ $$rc -eq 1 ]; then echo " (correctly reported mismatch with exit=1)"; else echo " FAIL: expected exit=1, got $$rc"; exit 1; fi
|
||
@echo
|
||
@echo "=== test_compare: malformed trace must exit 3 ==="
|
||
@cp $(GOLDEN_NOP) $(BUILD_DIR)/malformed_golden.trace
|
||
@sed -i '5s/.*/this line has too few columns/' $(BUILD_DIR)/malformed_golden.trace
|
||
@$(PYTHON) $(GOLDEN_DIR)/trace_compare.py $(RTL_FETCH) $(BUILD_DIR)/malformed_golden.trace; \
|
||
rc=$$?; \
|
||
if [ $$rc -eq 3 ]; then echo " (correctly reported malformed input with exit=3)"; else echo " FAIL: expected exit=3, got $$rc"; exit 1; fi
|
||
@echo
|
||
@echo "=== test_compare: all three exit-code paths verified ==="
|
||
|