thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
46 lines
1.7 KiB
Systemverilog
46 lines
1.7 KiB
Systemverilog
// retroDE_ps2 — de25_nano_pll_stub (Ch151)
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//
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// Sim-friendly stub matching the Quartus IOPLL "pll" module signature
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// used by sibling cores (retroDE_nes/ip/pll/pll_bb.v and
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// retroDE_splash/ip/sys_pll/sys_pll_bb.v). Real synthesis swaps this
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// stub for Terasic-supplied IP via Quartus's IP catalog and a
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// `\`ifdef USE_PLL_IP` gate in the board top.
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//
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// Behavior:
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// - `outclk_0` is a direct pass-through of `refclk` (no PLL
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// multiplication; sim doesn't need a different frequency, and a
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// pass-through still exercises the PLL-gated reset bridge in the
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// Ch149 board top).
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// - `locked` rises after a small post-reset delay (~32 cycles),
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// mimicking real-IP behavior where lock acquires after rst goes
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// low. Held LOW while `rst` is HIGH.
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//
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// The signature matches Quartus's IOPLL exactly so swapping in the
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// real IP is a single `\`ifdef` at instantiation; the rest of the
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// board top is unchanged.
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`timescale 1ns/1ps
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module de25_nano_pll_stub (
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input wire refclk, // reference clock from CLOCK2_50
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input wire rst, // active-HIGH async reset (Quartus convention)
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output wire outclk_0, // pass-through of refclk
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output wire locked // high once "lock" is acquired
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);
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assign outclk_0 = refclk;
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// Lock counter — tick up while rst is low; saturate at 32 and hold
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// `locked` high. While rst is high, hold counter at 0 and locked low.
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logic [5:0] lock_cnt;
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always_ff @(posedge refclk or posedge rst) begin
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if (rst)
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lock_cnt <= 6'd0;
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else if (lock_cnt < 6'd32)
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lock_cnt <= lock_cnt + 6'd1;
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end
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assign locked = (lock_cnt == 6'd32);
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endmodule : de25_nano_pll_stub
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