thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
218 lines
8.0 KiB
Systemverilog
218 lines
8.0 KiB
Systemverilog
// retroDE_ps2 — boot_install_agent_stub (Ch55 / Ch56)
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//
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// Minimal external producer that streams a coordinated low-RAM handler
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// image into EE RAM through the SIF EE-RAM bridge. Emits 32-bit beats
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// on a ready/valid handshake compatible with sif_dma_ee_ram_bridge_stub.
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//
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// NOT an IOP, NOT a full boot firmware. This is the thinnest possible
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// stand-in for "whatever on real PS2 populates EE useg [0x80..0x1FF]
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// with exception-entry + safe-return stubs before the EE starts
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// faulting" (IOP→EE SIF DMA, BootROM/CDVD handoff, etc.). The point
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// is to validate the transport path and the coordinated-install
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// thesis, not to model the producer's identity.
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//
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// Payload source (Ch56):
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// USE_IMAGE_FILE=0 (default) — built-in Ch54 image, hardcoded below
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// USE_IMAGE_FILE=1 — $readmemh(IMAGE_FILE, payload) once
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// at sim start, expects TOTAL_WORDS
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// hex words
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// Transport (timing, handshake, trace) is identical across both modes.
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//
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// Built-in image (USE_IMAGE_FILE=0):
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// word[0..3] → AdES handler at useg 0x80..0x8C:
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// MFC0 $26, $14 (32'h401A7000)
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// ADDIU $26, $26, 4 (32'h275A0004)
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// JR $26 (32'h03400008)
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// RFE (32'h42000010)
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// word[4..95] → 46× (JR $31; NOP) safe-return pairs covering
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// useg 0x90..0x1FC.
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//
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// Downstream contract (matches sif_dma_ee_ram_bridge_stub upstream):
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// out_valid / out_data[31:0] / out_last / out_ready
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// out_last asserted on the final word. One-beat-per-cycle while
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// out_ready is high.
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//
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// Trace:
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// SUBSYS_SIF / EV_DMA_START once on go.
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// SUBSYS_SIF / EV_DMA_BEAT per accepted beat.
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// arg0 = word index, arg1 = word data, arg2 = MASTER_ID,
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// arg3 = TOTAL_WORDS, flags bit0 = out_last.
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// SUBSYS_SIF / EV_DMA_DONE once on completion.
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`timescale 1ns/1ps
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module boot_install_agent_stub
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import trace_pkg::*;
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#(
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parameter int TOTAL_WORDS = 96,
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parameter logic [7:0] MASTER_ID = 8'd6, // install agent
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parameter bit USE_IMAGE_FILE = 1'b0, // 0: built-in ROM, 1: $readmemh
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parameter string IMAGE_FILE = ""
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) (
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input logic clk,
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input logic rst_n,
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input logic go_i,
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output logic out_valid,
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output logic [31:0] out_data,
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output logic out_last,
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input logic out_ready,
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output logic busy_o,
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output logic done_o,
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output logic ev_valid,
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output subsys_e ev_subsys,
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output event_e ev_event,
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output logic [63:0] ev_arg0,
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output logic [63:0] ev_arg1,
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output logic [63:0] ev_arg2,
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output logic [63:0] ev_arg3,
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output logic [31:0] ev_flags
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);
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// ------------------------------------------------------------------
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// Payload ROM
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// ------------------------------------------------------------------
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// The 4-word exception-return stub at [0..3] plus (JR $31; NOP)
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// pairs filling the rest requires TOTAL_WORDS to be even and at
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// least 4. Guard explicitly (Ch55 audit low-1): odd values would
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// walk past the array end in the pair loop.
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initial begin
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if (TOTAL_WORDS < 4 || (TOTAL_WORDS & 1) != 0) begin
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$fatal(1, "boot_install_agent_stub: TOTAL_WORDS must be even and >= 4, got %0d",
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TOTAL_WORDS);
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end
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end
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logic [31:0] payload [0:TOTAL_WORDS-1];
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initial begin
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if (USE_IMAGE_FILE) begin
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if (IMAGE_FILE == "") begin
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$fatal(1, "boot_install_agent_stub: USE_IMAGE_FILE=1 but IMAGE_FILE is empty");
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end
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$readmemh(IMAGE_FILE, payload);
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end else begin
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payload[0] = 32'h401A7000; // MFC0 $26, $14
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payload[1] = 32'h275A0004; // ADDIU $26, $26, 4
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payload[2] = 32'h03400008; // JR $26
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payload[3] = 32'h42000010; // RFE (delay slot)
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for (int i = 4; i < TOTAL_WORDS; i = i + 2) begin
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payload[i] = 32'h03E00008; // JR $31
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payload[i + 1] = 32'h00000000; // NOP
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end
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end
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end
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// ------------------------------------------------------------------
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// Streaming FSM
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// ------------------------------------------------------------------
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typedef enum logic [1:0] {
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S_IDLE = 2'd0,
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S_STREAM = 2'd1,
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S_DONE = 2'd2
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} state_e;
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state_e state;
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logic [31:0] idx; // next word to emit
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logic accept_beat;
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assign accept_beat = out_valid && out_ready;
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assign out_valid = (state == S_STREAM);
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assign out_data = (state == S_STREAM) ? payload[idx[$clog2(TOTAL_WORDS)-1:0]]
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: 32'd0;
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assign out_last = (state == S_STREAM) && (idx == TOTAL_WORDS - 1);
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assign busy_o = (state == S_STREAM);
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assign done_o = (state == S_DONE);
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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state <= S_IDLE;
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idx <= 32'd0;
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end else begin
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unique case (state)
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S_IDLE: begin
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if (go_i) begin
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state <= S_STREAM;
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idx <= 32'd0;
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end
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end
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S_STREAM: begin
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if (accept_beat) begin
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if (idx == TOTAL_WORDS - 1) state <= S_DONE;
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else idx <= idx + 32'd1;
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end
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end
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S_DONE: ; // terminal
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default: state <= S_IDLE;
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endcase
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end
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end
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// ------------------------------------------------------------------
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// Trace
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// ------------------------------------------------------------------
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// START fires combinationally on the cycle the caller pulses go_i
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// while we're still in S_IDLE. That cycle has out_valid=0 and
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// accept_beat=0, so the event doesn't compete with a BEAT event
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// in the priority if-else below (the bug pre-fix: flopping
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// go_latched delayed START onto the same cycle as beat 0, dropping
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// one of the two).
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logic go_pulse;
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assign go_pulse = (state == S_IDLE) && go_i;
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logic done_edge;
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state_e state_prev;
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always_ff @(posedge clk) begin
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if (!rst_n) state_prev <= S_IDLE;
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else state_prev <= state;
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end
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assign done_edge = (state == S_DONE) && (state_prev != S_DONE);
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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ev_valid <= 1'b0;
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ev_subsys <= SUBSYS_SIF;
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ev_event <= EV_DMA_START;
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ev_arg0 <= 64'd0;
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ev_arg1 <= 64'd0;
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ev_arg2 <= 64'd0;
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ev_arg3 <= 64'd0;
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ev_flags <= 32'd0;
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end else if (go_pulse) begin
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ev_valid <= 1'b1;
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ev_subsys <= SUBSYS_SIF;
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ev_event <= EV_DMA_START;
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ev_arg0 <= 64'd0;
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ev_arg1 <= 64'd0;
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ev_arg2 <= {56'd0, MASTER_ID};
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ev_arg3 <= 64'(TOTAL_WORDS);
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ev_flags <= 32'd0;
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end else if (accept_beat) begin
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ev_valid <= 1'b1;
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ev_subsys <= SUBSYS_SIF;
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ev_event <= EV_DMA_BEAT;
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ev_arg0 <= {32'd0, idx};
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ev_arg1 <= {32'd0, out_data};
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ev_arg2 <= {56'd0, MASTER_ID};
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ev_arg3 <= 64'(TOTAL_WORDS);
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ev_flags <= {31'd0, out_last};
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end else if (done_edge) begin
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ev_valid <= 1'b1;
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ev_subsys <= SUBSYS_SIF;
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ev_event <= EV_DMA_DONE;
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ev_arg0 <= 64'(TOTAL_WORDS);
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ev_arg1 <= 64'd0;
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ev_arg2 <= {56'd0, MASTER_ID};
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ev_arg3 <= 64'(TOTAL_WORDS);
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ev_flags <= 32'd0;
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end else begin
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ev_valid <= 1'b0;
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end
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end
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endmodule : boot_install_agent_stub
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