thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
129 lines
4.2 KiB
Systemverilog
129 lines
4.2 KiB
Systemverilog
// retroDE_ps2 — ee_fetch_stub
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//
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// Minimal sequential-fetch stand-in for the R5900. Wave 1 scope only: enough
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// to drive ee_memory_map_stub → bios_rom_stub for Milestone B.
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//
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// Contract refs:
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// docs/stub_module_plan.md (Wave 1, item 4)
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// docs/contracts/ee.md
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//
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// Behavior:
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// - On reset, PC = RESET_VECTOR (default 0xBFC00000, the MIPS BIOS
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// reset vector in kseg1).
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// - Each cycle while `enable` is high: issue a read at PC, advance
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// PC += 4. No decode, no branches, no exceptions, no retirement
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// fidelity (all out-of-scope per plan).
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// - Responses return 1 cycle later via rd_valid/rd_data from the
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// memory map. The issued address is latched so the trace line can
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// pair address with data.
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//
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// Non-goals for this wave (stub plan, explicit):
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// - full decode,
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// - exceptions beyond deterministic fault handling,
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// - FPU/MMI behavior,
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// - instruction retirement fidelity.
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//
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// Trace payload schema (per stub plan):
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// EE RESET arg0=reset_vector
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// EE IFETCH arg0=pc arg1=data arg2=resp_kind arg3=-
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// resp_kind: 0=OK (only path in Wave 1)
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`timescale 1ns/1ps
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module ee_fetch_stub
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import trace_pkg::*;
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#(
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parameter logic [31:0] RESET_VECTOR = 32'hBFC00000
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) (
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input logic clk,
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input logic rst_n,
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input logic enable,
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// Memory-facing fetch port
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output logic rd_en,
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output logic [31:0] rd_addr,
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input logic [31:0] rd_data,
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input logic rd_valid,
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// Trace
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output logic ev_valid,
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output subsys_e ev_subsys,
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output event_e ev_event,
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output logic [63:0] ev_arg0,
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output logic [63:0] ev_arg1,
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output logic [63:0] ev_arg2,
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output logic [63:0] ev_arg3,
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output logic [31:0] ev_flags
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);
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// ------------------------------------------------------------------
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// PC and one-cycle issued-address shadow
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//
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// pc is the address being issued THIS cycle (rd_addr)
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// pc_d1 is the address whose response arrives THIS cycle on rd_valid
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//
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// pc_d1 only advances alongside pc when enable is high, so it stays
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// aligned with the in-flight request.
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// ------------------------------------------------------------------
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logic [31:0] pc;
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logic [31:0] pc_d1;
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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pc <= RESET_VECTOR;
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pc_d1 <= RESET_VECTOR;
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end else if (enable) begin
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pc_d1 <= pc;
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pc <= pc + 32'd4;
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end
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end
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assign rd_en = enable;
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assign rd_addr = pc;
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// ------------------------------------------------------------------
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// Trace
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// - Single EV_RESET pulse at reset exit.
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// - EV_IFETCH one cycle after each rd_valid response.
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// ------------------------------------------------------------------
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logic reset_emit_pending;
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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ev_valid <= 1'b0;
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ev_subsys <= SUBSYS_EE;
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ev_event <= EV_RESET;
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ev_arg0 <= 64'd0;
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ev_arg1 <= 64'd0;
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ev_arg2 <= 64'd0;
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ev_arg3 <= 64'd0;
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ev_flags <= 32'd0;
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reset_emit_pending <= 1'b1;
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end else if (reset_emit_pending) begin
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ev_valid <= 1'b1;
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ev_subsys <= SUBSYS_EE;
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ev_event <= EV_RESET;
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ev_arg0 <= {32'd0, RESET_VECTOR};
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ev_arg1 <= 64'd0;
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ev_arg2 <= 64'd0;
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ev_arg3 <= 64'd0;
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ev_flags <= 32'd0;
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reset_emit_pending <= 1'b0;
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end else if (rd_valid) begin
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ev_valid <= 1'b1;
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ev_subsys <= SUBSYS_EE;
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ev_event <= EV_IFETCH;
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ev_arg0 <= {32'd0, pc_d1};
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ev_arg1 <= {32'd0, rd_data};
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ev_arg2 <= 64'd0; // resp_kind: 0 = OK
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ev_arg3 <= 64'd0;
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ev_flags <= 32'd0;
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end else begin
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ev_valid <= 1'b0;
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end
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end
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endmodule : ee_fetch_stub
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