thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
543 lines
70 KiB
Verilog
543 lines
70 KiB
Verilog
// qsys_top.v
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// Generated using ACDS version 26.1 110
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`timescale 1 ps / 1 ps
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module qsys_top (
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input wire clk_100_clk, // clk_100.clk
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input wire reset_reset_n, // reset.reset_n
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output wire ninit_done_ninit_done, // ninit_done.ninit_done
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output wire h2f_reset_reset, // h2f_reset.reset
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output wire [3:0] subsys_hps_hps2fpga_awid, // subsys_hps_hps2fpga.awid
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output wire [37:0] subsys_hps_hps2fpga_awaddr, // .awaddr
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output wire [7:0] subsys_hps_hps2fpga_awlen, // .awlen
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output wire [2:0] subsys_hps_hps2fpga_awsize, // .awsize
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output wire [1:0] subsys_hps_hps2fpga_awburst, // .awburst
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output wire subsys_hps_hps2fpga_awlock, // .awlock
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output wire [3:0] subsys_hps_hps2fpga_awcache, // .awcache
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output wire [2:0] subsys_hps_hps2fpga_awprot, // .awprot
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output wire subsys_hps_hps2fpga_awvalid, // .awvalid
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input wire subsys_hps_hps2fpga_awready, // .awready
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output wire [127:0] subsys_hps_hps2fpga_wdata, // .wdata
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output wire [15:0] subsys_hps_hps2fpga_wstrb, // .wstrb
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output wire subsys_hps_hps2fpga_wlast, // .wlast
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output wire subsys_hps_hps2fpga_wvalid, // .wvalid
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input wire subsys_hps_hps2fpga_wready, // .wready
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input wire [3:0] subsys_hps_hps2fpga_bid, // .bid
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input wire [1:0] subsys_hps_hps2fpga_bresp, // .bresp
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input wire subsys_hps_hps2fpga_bvalid, // .bvalid
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output wire subsys_hps_hps2fpga_bready, // .bready
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output wire [3:0] subsys_hps_hps2fpga_arid, // .arid
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output wire [37:0] subsys_hps_hps2fpga_araddr, // .araddr
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output wire [7:0] subsys_hps_hps2fpga_arlen, // .arlen
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output wire [2:0] subsys_hps_hps2fpga_arsize, // .arsize
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output wire [1:0] subsys_hps_hps2fpga_arburst, // .arburst
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output wire subsys_hps_hps2fpga_arlock, // .arlock
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output wire [3:0] subsys_hps_hps2fpga_arcache, // .arcache
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output wire [2:0] subsys_hps_hps2fpga_arprot, // .arprot
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output wire subsys_hps_hps2fpga_arvalid, // .arvalid
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input wire subsys_hps_hps2fpga_arready, // .arready
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input wire [3:0] subsys_hps_hps2fpga_rid, // .rid
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input wire [127:0] subsys_hps_hps2fpga_rdata, // .rdata
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input wire [1:0] subsys_hps_hps2fpga_rresp, // .rresp
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input wire subsys_hps_hps2fpga_rlast, // .rlast
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input wire subsys_hps_hps2fpga_rvalid, // .rvalid
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output wire subsys_hps_hps2fpga_rready, // .rready
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output wire subsys_hps_h2f_warm_reset_handshake_reset_req, // subsys_hps_h2f_warm_reset_handshake.reset_req
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input wire subsys_hps_h2f_warm_reset_handshake_reset_ack, // .reset_ack
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input wire hps_io_hps_osc_clk, // hps_io.hps_osc_clk
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inout wire hps_io_sdmmc_data0, // .sdmmc_data0
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inout wire hps_io_sdmmc_data1, // .sdmmc_data1
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output wire hps_io_sdmmc_cclk, // .sdmmc_cclk
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inout wire hps_io_sdmmc_data2, // .sdmmc_data2
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inout wire hps_io_sdmmc_data3, // .sdmmc_data3
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inout wire hps_io_sdmmc_cmd, // .sdmmc_cmd
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input wire hps_io_usb0_clk, // .usb0_clk
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output wire hps_io_usb0_stp, // .usb0_stp
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input wire hps_io_usb0_dir, // .usb0_dir
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inout wire hps_io_usb0_data0, // .usb0_data0
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inout wire hps_io_usb0_data1, // .usb0_data1
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input wire hps_io_usb0_nxt, // .usb0_nxt
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inout wire hps_io_usb0_data2, // .usb0_data2
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inout wire hps_io_usb0_data3, // .usb0_data3
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inout wire hps_io_usb0_data4, // .usb0_data4
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inout wire hps_io_usb0_data5, // .usb0_data5
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inout wire hps_io_usb0_data6, // .usb0_data6
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inout wire hps_io_usb0_data7, // .usb0_data7
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output wire hps_io_emac0_tx_clk, // .emac0_tx_clk
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output wire hps_io_emac0_tx_ctl, // .emac0_tx_ctl
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input wire hps_io_emac0_rx_clk, // .emac0_rx_clk
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input wire hps_io_emac0_rx_ctl, // .emac0_rx_ctl
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output wire hps_io_emac0_txd0, // .emac0_txd0
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output wire hps_io_emac0_txd1, // .emac0_txd1
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input wire hps_io_emac0_rxd0, // .emac0_rxd0
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input wire hps_io_emac0_rxd1, // .emac0_rxd1
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output wire hps_io_emac0_txd2, // .emac0_txd2
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output wire hps_io_emac0_txd3, // .emac0_txd3
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input wire hps_io_emac0_rxd2, // .emac0_rxd2
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input wire hps_io_emac0_rxd3, // .emac0_rxd3
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inout wire hps_io_mdio0_mdio, // .mdio0_mdio
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output wire hps_io_mdio0_mdc, // .mdio0_mdc
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output wire hps_io_uart1_tx, // .uart1_tx
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input wire hps_io_uart1_rx, // .uart1_rx
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inout wire hps_io_i2c1_sda, // .i2c1_sda
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inout wire hps_io_i2c1_scl, // .i2c1_scl
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inout wire hps_io_gpio28, // .gpio28
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inout wire hps_io_gpio34, // .gpio34
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inout wire hps_io_gpio40, // .gpio40
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inout wire hps_io_gpio41, // .gpio41
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input wire [31:0] f2h_irq1_in_irq, // f2h_irq1_in.irq
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input wire [31:0] f2sdram_araddr, // f2sdram.araddr
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input wire [1:0] f2sdram_arburst, // .arburst
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input wire [3:0] f2sdram_arcache, // .arcache
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input wire [4:0] f2sdram_arid, // .arid
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input wire [7:0] f2sdram_arlen, // .arlen
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input wire f2sdram_arlock, // .arlock
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input wire [2:0] f2sdram_arprot, // .arprot
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input wire [3:0] f2sdram_arqos, // .arqos
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output wire f2sdram_arready, // .arready
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input wire [2:0] f2sdram_arsize, // .arsize
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input wire f2sdram_arvalid, // .arvalid
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input wire [31:0] f2sdram_awaddr, // .awaddr
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input wire [1:0] f2sdram_awburst, // .awburst
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input wire [3:0] f2sdram_awcache, // .awcache
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input wire [4:0] f2sdram_awid, // .awid
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input wire [7:0] f2sdram_awlen, // .awlen
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input wire f2sdram_awlock, // .awlock
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input wire [2:0] f2sdram_awprot, // .awprot
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input wire [3:0] f2sdram_awqos, // .awqos
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output wire f2sdram_awready, // .awready
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input wire [2:0] f2sdram_awsize, // .awsize
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input wire f2sdram_awvalid, // .awvalid
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output wire [4:0] f2sdram_bid, // .bid
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input wire f2sdram_bready, // .bready
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output wire [1:0] f2sdram_bresp, // .bresp
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output wire f2sdram_bvalid, // .bvalid
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output wire [255:0] f2sdram_rdata, // .rdata
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output wire [4:0] f2sdram_rid, // .rid
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output wire f2sdram_rlast, // .rlast
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input wire f2sdram_rready, // .rready
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output wire [1:0] f2sdram_rresp, // .rresp
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output wire f2sdram_rvalid, // .rvalid
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input wire [255:0] f2sdram_wdata, // .wdata
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input wire f2sdram_wlast, // .wlast
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output wire f2sdram_wready, // .wready
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input wire [31:0] f2sdram_wstrb, // .wstrb
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input wire f2sdram_wvalid, // .wvalid
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input wire [7:0] f2sdram_aruser, // .aruser
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input wire [7:0] f2sdram_awuser, // .awuser
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input wire [7:0] f2sdram_wuser, // .wuser
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output wire [7:0] f2sdram_buser, // .buser
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input wire [3:0] f2sdram_arregion, // .arregion
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output wire [7:0] f2sdram_ruser, // .ruser
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input wire [3:0] f2sdram_awregion, // .awregion
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output wire [0:0] emif_hps_emif_mem_0_mem_cs, // emif_hps_emif_mem_0.mem_cs
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output wire [5:0] emif_hps_emif_mem_0_mem_ca, // .mem_ca
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output wire [0:0] emif_hps_emif_mem_0_mem_cke, // .mem_cke
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inout wire [31:0] emif_hps_emif_mem_0_mem_dq, // .mem_dq
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inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_t, // .mem_dqs_t
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inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_c, // .mem_dqs_c
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inout wire [3:0] emif_hps_emif_mem_0_mem_dmi, // .mem_dmi
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output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_t, // emif_hps_emif_mem_ck_0.mem_ck_t
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output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_c, // .mem_ck_c
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output wire emif_hps_emif_mem_reset_n_mem_reset_n, // emif_hps_emif_mem_reset_n.mem_reset_n
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input wire emif_hps_emif_oct_0_oct_rzqin, // emif_hps_emif_oct_0.oct_rzqin
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input wire emif_hps_emif_ref_clk_0_clk, // emif_hps_emif_ref_clk_0.clk
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input wire [3:0] button_pio_external_connection_export, // button_pio_external_connection.export
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input wire [3:0] dipsw_pio_external_connection_export, // dipsw_pio_external_connection.export
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input wire [2:0] led_pio_external_connection_in_port, // led_pio_external_connection.in_port
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output wire [2:0] led_pio_external_connection_out_port // .out_port
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);
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wire clk_100_out_clk_clk; // clk_100:out_clk -> [mm_interconnect_0:clk_100_out_clk_clk, rst_controller:clk, subsys_hps:f2sdram_clk_clk, subsys_hps:hps2fpga_clk_clk, subsys_hps:lwhps2fpga_clk_clk, subsys_periph:clk_clk]
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wire rst_in_out_reset_reset; // rst_in:out_reset_n -> [rst_controller:reset_in0, subsys_hps:f2sdram_rst_reset, subsys_hps:hps2fpga_rst_reset, subsys_hps:lwhps2fpga_rst_reset, subsys_periph:reset_reset_n]
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wire [1:0] subsys_hps_lwhps2fpga_awburst; // subsys_hps:lwhps2fpga_awburst -> mm_interconnect_0:subsys_hps_lwhps2fpga_awburst
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wire [7:0] subsys_hps_lwhps2fpga_arlen; // subsys_hps:lwhps2fpga_arlen -> mm_interconnect_0:subsys_hps_lwhps2fpga_arlen
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wire [3:0] subsys_hps_lwhps2fpga_wstrb; // subsys_hps:lwhps2fpga_wstrb -> mm_interconnect_0:subsys_hps_lwhps2fpga_wstrb
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wire subsys_hps_lwhps2fpga_wready; // mm_interconnect_0:subsys_hps_lwhps2fpga_wready -> subsys_hps:lwhps2fpga_wready
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wire [3:0] subsys_hps_lwhps2fpga_rid; // mm_interconnect_0:subsys_hps_lwhps2fpga_rid -> subsys_hps:lwhps2fpga_rid
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wire subsys_hps_lwhps2fpga_rready; // subsys_hps:lwhps2fpga_rready -> mm_interconnect_0:subsys_hps_lwhps2fpga_rready
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wire [7:0] subsys_hps_lwhps2fpga_awlen; // subsys_hps:lwhps2fpga_awlen -> mm_interconnect_0:subsys_hps_lwhps2fpga_awlen
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wire [3:0] subsys_hps_lwhps2fpga_arcache; // subsys_hps:lwhps2fpga_arcache -> mm_interconnect_0:subsys_hps_lwhps2fpga_arcache
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wire subsys_hps_lwhps2fpga_wvalid; // subsys_hps:lwhps2fpga_wvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_wvalid
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wire [28:0] subsys_hps_lwhps2fpga_araddr; // subsys_hps:lwhps2fpga_araddr -> mm_interconnect_0:subsys_hps_lwhps2fpga_araddr
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wire [2:0] subsys_hps_lwhps2fpga_arprot; // subsys_hps:lwhps2fpga_arprot -> mm_interconnect_0:subsys_hps_lwhps2fpga_arprot
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wire [2:0] subsys_hps_lwhps2fpga_awprot; // subsys_hps:lwhps2fpga_awprot -> mm_interconnect_0:subsys_hps_lwhps2fpga_awprot
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wire [31:0] subsys_hps_lwhps2fpga_wdata; // subsys_hps:lwhps2fpga_wdata -> mm_interconnect_0:subsys_hps_lwhps2fpga_wdata
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wire subsys_hps_lwhps2fpga_arvalid; // subsys_hps:lwhps2fpga_arvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_arvalid
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wire [3:0] subsys_hps_lwhps2fpga_awcache; // subsys_hps:lwhps2fpga_awcache -> mm_interconnect_0:subsys_hps_lwhps2fpga_awcache
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wire [3:0] subsys_hps_lwhps2fpga_arid; // subsys_hps:lwhps2fpga_arid -> mm_interconnect_0:subsys_hps_lwhps2fpga_arid
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wire subsys_hps_lwhps2fpga_arlock; // subsys_hps:lwhps2fpga_arlock -> mm_interconnect_0:subsys_hps_lwhps2fpga_arlock
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wire subsys_hps_lwhps2fpga_awlock; // subsys_hps:lwhps2fpga_awlock -> mm_interconnect_0:subsys_hps_lwhps2fpga_awlock
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wire [28:0] subsys_hps_lwhps2fpga_awaddr; // subsys_hps:lwhps2fpga_awaddr -> mm_interconnect_0:subsys_hps_lwhps2fpga_awaddr
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wire [1:0] subsys_hps_lwhps2fpga_bresp; // mm_interconnect_0:subsys_hps_lwhps2fpga_bresp -> subsys_hps:lwhps2fpga_bresp
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wire subsys_hps_lwhps2fpga_arready; // mm_interconnect_0:subsys_hps_lwhps2fpga_arready -> subsys_hps:lwhps2fpga_arready
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wire [31:0] subsys_hps_lwhps2fpga_rdata; // mm_interconnect_0:subsys_hps_lwhps2fpga_rdata -> subsys_hps:lwhps2fpga_rdata
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wire subsys_hps_lwhps2fpga_awready; // mm_interconnect_0:subsys_hps_lwhps2fpga_awready -> subsys_hps:lwhps2fpga_awready
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wire [1:0] subsys_hps_lwhps2fpga_arburst; // subsys_hps:lwhps2fpga_arburst -> mm_interconnect_0:subsys_hps_lwhps2fpga_arburst
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wire [2:0] subsys_hps_lwhps2fpga_arsize; // subsys_hps:lwhps2fpga_arsize -> mm_interconnect_0:subsys_hps_lwhps2fpga_arsize
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wire subsys_hps_lwhps2fpga_bready; // subsys_hps:lwhps2fpga_bready -> mm_interconnect_0:subsys_hps_lwhps2fpga_bready
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wire subsys_hps_lwhps2fpga_rlast; // mm_interconnect_0:subsys_hps_lwhps2fpga_rlast -> subsys_hps:lwhps2fpga_rlast
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wire subsys_hps_lwhps2fpga_wlast; // subsys_hps:lwhps2fpga_wlast -> mm_interconnect_0:subsys_hps_lwhps2fpga_wlast
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wire [1:0] subsys_hps_lwhps2fpga_rresp; // mm_interconnect_0:subsys_hps_lwhps2fpga_rresp -> subsys_hps:lwhps2fpga_rresp
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wire [3:0] subsys_hps_lwhps2fpga_awid; // subsys_hps:lwhps2fpga_awid -> mm_interconnect_0:subsys_hps_lwhps2fpga_awid
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wire [3:0] subsys_hps_lwhps2fpga_bid; // mm_interconnect_0:subsys_hps_lwhps2fpga_bid -> subsys_hps:lwhps2fpga_bid
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wire subsys_hps_lwhps2fpga_bvalid; // mm_interconnect_0:subsys_hps_lwhps2fpga_bvalid -> subsys_hps:lwhps2fpga_bvalid
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wire [2:0] subsys_hps_lwhps2fpga_awsize; // subsys_hps:lwhps2fpga_awsize -> mm_interconnect_0:subsys_hps_lwhps2fpga_awsize
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wire subsys_hps_lwhps2fpga_awvalid; // subsys_hps:lwhps2fpga_awvalid -> mm_interconnect_0:subsys_hps_lwhps2fpga_awvalid
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wire subsys_hps_lwhps2fpga_rvalid; // mm_interconnect_0:subsys_hps_lwhps2fpga_rvalid -> subsys_hps:lwhps2fpga_rvalid
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wire [31:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata; // subsys_periph:pb_cpu_0_s0_readdata -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_readdata
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wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest; // subsys_periph:pb_cpu_0_s0_waitrequest -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_waitrequest
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wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_debugaccess -> subsys_periph:pb_cpu_0_s0_debugaccess
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wire [16:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_address -> subsys_periph:pb_cpu_0_s0_address
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wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_read -> subsys_periph:pb_cpu_0_s0_read
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wire [3:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_byteenable -> subsys_periph:pb_cpu_0_s0_byteenable
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wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid; // subsys_periph:pb_cpu_0_s0_readdatavalid -> mm_interconnect_0:subsys_periph_pb_cpu_0_s0_readdatavalid
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wire mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_write -> subsys_periph:pb_cpu_0_s0_write
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wire [31:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_writedata -> subsys_periph:pb_cpu_0_s0_writedata
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wire [0:0] mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount; // mm_interconnect_0:subsys_periph_pb_cpu_0_s0_burstcount -> subsys_periph:pb_cpu_0_s0_burstcount
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wire irq_mapper_receiver0_irq; // subsys_periph:button_pio_irq_irq -> irq_mapper:receiver0_irq
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wire irq_mapper_receiver1_irq; // subsys_periph:dipsw_pio_irq_irq -> irq_mapper:receiver1_irq
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wire [31:0] subsys_hps_f2h_irq0_in_irq; // irq_mapper:sender_irq -> subsys_hps:f2h_irq0_in_irq
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wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_0:subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset]
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clk_100 clk_100 (
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.in_clk (clk_100_clk), // input, width = 1, in_clk.clk
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.out_clk (clk_100_out_clk_clk) // output, width = 1, out_clk.clk
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|
);
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|
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rst_in rst_in (
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.in_reset_n (reset_reset_n), // input, width = 1, in_reset.reset_n
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.out_reset_n (rst_in_out_reset_reset) // output, width = 1, out_reset.reset_n
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|
);
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user_rst_clkgate_0 user_rst_clkgate_0 (
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.ninit_done (ninit_done_ninit_done) // output, width = 1, ninit_done.ninit_done
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);
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hps_subsys subsys_hps (
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.h2f_reset_reset (h2f_reset_reset), // output, width = 1, h2f_reset.reset
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|
.hps2fpga_clk_clk (clk_100_out_clk_clk), // input, width = 1, hps2fpga_clk.clk
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|
.hps2fpga_rst_reset (~rst_in_out_reset_reset), // input, width = 1, hps2fpga_rst.reset
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|
.hps2fpga_awid (subsys_hps_hps2fpga_awid), // output, width = 4, hps2fpga.awid
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|
.hps2fpga_awaddr (subsys_hps_hps2fpga_awaddr), // output, width = 38, .awaddr
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|
.hps2fpga_awlen (subsys_hps_hps2fpga_awlen), // output, width = 8, .awlen
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|
.hps2fpga_awsize (subsys_hps_hps2fpga_awsize), // output, width = 3, .awsize
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|
.hps2fpga_awburst (subsys_hps_hps2fpga_awburst), // output, width = 2, .awburst
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|
.hps2fpga_awlock (subsys_hps_hps2fpga_awlock), // output, width = 1, .awlock
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|
.hps2fpga_awcache (subsys_hps_hps2fpga_awcache), // output, width = 4, .awcache
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|
.hps2fpga_awprot (subsys_hps_hps2fpga_awprot), // output, width = 3, .awprot
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|
.hps2fpga_awvalid (subsys_hps_hps2fpga_awvalid), // output, width = 1, .awvalid
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|
.hps2fpga_awready (subsys_hps_hps2fpga_awready), // input, width = 1, .awready
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|
.hps2fpga_wdata (subsys_hps_hps2fpga_wdata), // output, width = 128, .wdata
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|
.hps2fpga_wstrb (subsys_hps_hps2fpga_wstrb), // output, width = 16, .wstrb
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|
.hps2fpga_wlast (subsys_hps_hps2fpga_wlast), // output, width = 1, .wlast
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|
.hps2fpga_wvalid (subsys_hps_hps2fpga_wvalid), // output, width = 1, .wvalid
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|
.hps2fpga_wready (subsys_hps_hps2fpga_wready), // input, width = 1, .wready
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.hps2fpga_bid (subsys_hps_hps2fpga_bid), // input, width = 4, .bid
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|
.hps2fpga_bresp (subsys_hps_hps2fpga_bresp), // input, width = 2, .bresp
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|
.hps2fpga_bvalid (subsys_hps_hps2fpga_bvalid), // input, width = 1, .bvalid
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|
.hps2fpga_bready (subsys_hps_hps2fpga_bready), // output, width = 1, .bready
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|
.hps2fpga_arid (subsys_hps_hps2fpga_arid), // output, width = 4, .arid
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|
.hps2fpga_araddr (subsys_hps_hps2fpga_araddr), // output, width = 38, .araddr
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|
.hps2fpga_arlen (subsys_hps_hps2fpga_arlen), // output, width = 8, .arlen
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.hps2fpga_arsize (subsys_hps_hps2fpga_arsize), // output, width = 3, .arsize
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|
.hps2fpga_arburst (subsys_hps_hps2fpga_arburst), // output, width = 2, .arburst
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|
.hps2fpga_arlock (subsys_hps_hps2fpga_arlock), // output, width = 1, .arlock
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|
.hps2fpga_arcache (subsys_hps_hps2fpga_arcache), // output, width = 4, .arcache
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|
.hps2fpga_arprot (subsys_hps_hps2fpga_arprot), // output, width = 3, .arprot
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|
.hps2fpga_arvalid (subsys_hps_hps2fpga_arvalid), // output, width = 1, .arvalid
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|
.hps2fpga_arready (subsys_hps_hps2fpga_arready), // input, width = 1, .arready
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|
.hps2fpga_rid (subsys_hps_hps2fpga_rid), // input, width = 4, .rid
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|
.hps2fpga_rdata (subsys_hps_hps2fpga_rdata), // input, width = 128, .rdata
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|
.hps2fpga_rresp (subsys_hps_hps2fpga_rresp), // input, width = 2, .rresp
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|
.hps2fpga_rlast (subsys_hps_hps2fpga_rlast), // input, width = 1, .rlast
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|
.hps2fpga_rvalid (subsys_hps_hps2fpga_rvalid), // input, width = 1, .rvalid
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|
.hps2fpga_rready (subsys_hps_hps2fpga_rready), // output, width = 1, .rready
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|
.lwhps2fpga_clk_clk (clk_100_out_clk_clk), // input, width = 1, lwhps2fpga_clk.clk
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|
.lwhps2fpga_rst_reset (~rst_in_out_reset_reset), // input, width = 1, lwhps2fpga_rst.reset
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|
.lwhps2fpga_awid (subsys_hps_lwhps2fpga_awid), // output, width = 4, lwhps2fpga.awid
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|
.lwhps2fpga_awaddr (subsys_hps_lwhps2fpga_awaddr), // output, width = 29, .awaddr
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|
.lwhps2fpga_awlen (subsys_hps_lwhps2fpga_awlen), // output, width = 8, .awlen
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|
.lwhps2fpga_awsize (subsys_hps_lwhps2fpga_awsize), // output, width = 3, .awsize
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|
.lwhps2fpga_awburst (subsys_hps_lwhps2fpga_awburst), // output, width = 2, .awburst
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|
.lwhps2fpga_awlock (subsys_hps_lwhps2fpga_awlock), // output, width = 1, .awlock
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|
.lwhps2fpga_awcache (subsys_hps_lwhps2fpga_awcache), // output, width = 4, .awcache
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|
.lwhps2fpga_awprot (subsys_hps_lwhps2fpga_awprot), // output, width = 3, .awprot
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|
.lwhps2fpga_awvalid (subsys_hps_lwhps2fpga_awvalid), // output, width = 1, .awvalid
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|
.lwhps2fpga_awready (subsys_hps_lwhps2fpga_awready), // input, width = 1, .awready
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|
.lwhps2fpga_wdata (subsys_hps_lwhps2fpga_wdata), // output, width = 32, .wdata
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|
.lwhps2fpga_wstrb (subsys_hps_lwhps2fpga_wstrb), // output, width = 4, .wstrb
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|
.lwhps2fpga_wlast (subsys_hps_lwhps2fpga_wlast), // output, width = 1, .wlast
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|
.lwhps2fpga_wvalid (subsys_hps_lwhps2fpga_wvalid), // output, width = 1, .wvalid
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|
.lwhps2fpga_wready (subsys_hps_lwhps2fpga_wready), // input, width = 1, .wready
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|
.lwhps2fpga_bid (subsys_hps_lwhps2fpga_bid), // input, width = 4, .bid
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|
.lwhps2fpga_bresp (subsys_hps_lwhps2fpga_bresp), // input, width = 2, .bresp
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|
.lwhps2fpga_bvalid (subsys_hps_lwhps2fpga_bvalid), // input, width = 1, .bvalid
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|
.lwhps2fpga_bready (subsys_hps_lwhps2fpga_bready), // output, width = 1, .bready
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|
.lwhps2fpga_arid (subsys_hps_lwhps2fpga_arid), // output, width = 4, .arid
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|
.lwhps2fpga_araddr (subsys_hps_lwhps2fpga_araddr), // output, width = 29, .araddr
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|
.lwhps2fpga_arlen (subsys_hps_lwhps2fpga_arlen), // output, width = 8, .arlen
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|
.lwhps2fpga_arsize (subsys_hps_lwhps2fpga_arsize), // output, width = 3, .arsize
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|
.lwhps2fpga_arburst (subsys_hps_lwhps2fpga_arburst), // output, width = 2, .arburst
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|
.lwhps2fpga_arlock (subsys_hps_lwhps2fpga_arlock), // output, width = 1, .arlock
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|
.lwhps2fpga_arcache (subsys_hps_lwhps2fpga_arcache), // output, width = 4, .arcache
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|
.lwhps2fpga_arprot (subsys_hps_lwhps2fpga_arprot), // output, width = 3, .arprot
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|
.lwhps2fpga_arvalid (subsys_hps_lwhps2fpga_arvalid), // output, width = 1, .arvalid
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|
.lwhps2fpga_arready (subsys_hps_lwhps2fpga_arready), // input, width = 1, .arready
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|
.lwhps2fpga_rid (subsys_hps_lwhps2fpga_rid), // input, width = 4, .rid
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|
.lwhps2fpga_rdata (subsys_hps_lwhps2fpga_rdata), // input, width = 32, .rdata
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|
.lwhps2fpga_rresp (subsys_hps_lwhps2fpga_rresp), // input, width = 2, .rresp
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|
.lwhps2fpga_rlast (subsys_hps_lwhps2fpga_rlast), // input, width = 1, .rlast
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|
.lwhps2fpga_rvalid (subsys_hps_lwhps2fpga_rvalid), // input, width = 1, .rvalid
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|
.lwhps2fpga_rready (subsys_hps_lwhps2fpga_rready), // output, width = 1, .rready
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|
.h2f_warm_reset_handshake_reset_req (subsys_hps_h2f_warm_reset_handshake_reset_req), // output, width = 1, h2f_warm_reset_handshake.reset_req
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|
.h2f_warm_reset_handshake_reset_ack (subsys_hps_h2f_warm_reset_handshake_reset_ack), // input, width = 1, .reset_ack
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|
.hps_io_hps_osc_clk (hps_io_hps_osc_clk), // input, width = 1, hps_io.hps_osc_clk
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|
.hps_io_sdmmc_data0 (hps_io_sdmmc_data0), // inout, width = 1, .sdmmc_data0
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|
.hps_io_sdmmc_data1 (hps_io_sdmmc_data1), // inout, width = 1, .sdmmc_data1
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|
.hps_io_sdmmc_cclk (hps_io_sdmmc_cclk), // output, width = 1, .sdmmc_cclk
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|
.hps_io_sdmmc_data2 (hps_io_sdmmc_data2), // inout, width = 1, .sdmmc_data2
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|
.hps_io_sdmmc_data3 (hps_io_sdmmc_data3), // inout, width = 1, .sdmmc_data3
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|
.hps_io_sdmmc_cmd (hps_io_sdmmc_cmd), // inout, width = 1, .sdmmc_cmd
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|
.hps_io_usb0_clk (hps_io_usb0_clk), // input, width = 1, .usb0_clk
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|
.hps_io_usb0_stp (hps_io_usb0_stp), // output, width = 1, .usb0_stp
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|
.hps_io_usb0_dir (hps_io_usb0_dir), // input, width = 1, .usb0_dir
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|
.hps_io_usb0_data0 (hps_io_usb0_data0), // inout, width = 1, .usb0_data0
|
|
.hps_io_usb0_data1 (hps_io_usb0_data1), // inout, width = 1, .usb0_data1
|
|
.hps_io_usb0_nxt (hps_io_usb0_nxt), // input, width = 1, .usb0_nxt
|
|
.hps_io_usb0_data2 (hps_io_usb0_data2), // inout, width = 1, .usb0_data2
|
|
.hps_io_usb0_data3 (hps_io_usb0_data3), // inout, width = 1, .usb0_data3
|
|
.hps_io_usb0_data4 (hps_io_usb0_data4), // inout, width = 1, .usb0_data4
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|
.hps_io_usb0_data5 (hps_io_usb0_data5), // inout, width = 1, .usb0_data5
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|
.hps_io_usb0_data6 (hps_io_usb0_data6), // inout, width = 1, .usb0_data6
|
|
.hps_io_usb0_data7 (hps_io_usb0_data7), // inout, width = 1, .usb0_data7
|
|
.hps_io_emac0_tx_clk (hps_io_emac0_tx_clk), // output, width = 1, .emac0_tx_clk
|
|
.hps_io_emac0_tx_ctl (hps_io_emac0_tx_ctl), // output, width = 1, .emac0_tx_ctl
|
|
.hps_io_emac0_rx_clk (hps_io_emac0_rx_clk), // input, width = 1, .emac0_rx_clk
|
|
.hps_io_emac0_rx_ctl (hps_io_emac0_rx_ctl), // input, width = 1, .emac0_rx_ctl
|
|
.hps_io_emac0_txd0 (hps_io_emac0_txd0), // output, width = 1, .emac0_txd0
|
|
.hps_io_emac0_txd1 (hps_io_emac0_txd1), // output, width = 1, .emac0_txd1
|
|
.hps_io_emac0_rxd0 (hps_io_emac0_rxd0), // input, width = 1, .emac0_rxd0
|
|
.hps_io_emac0_rxd1 (hps_io_emac0_rxd1), // input, width = 1, .emac0_rxd1
|
|
.hps_io_emac0_txd2 (hps_io_emac0_txd2), // output, width = 1, .emac0_txd2
|
|
.hps_io_emac0_txd3 (hps_io_emac0_txd3), // output, width = 1, .emac0_txd3
|
|
.hps_io_emac0_rxd2 (hps_io_emac0_rxd2), // input, width = 1, .emac0_rxd2
|
|
.hps_io_emac0_rxd3 (hps_io_emac0_rxd3), // input, width = 1, .emac0_rxd3
|
|
.hps_io_mdio0_mdio (hps_io_mdio0_mdio), // inout, width = 1, .mdio0_mdio
|
|
.hps_io_mdio0_mdc (hps_io_mdio0_mdc), // output, width = 1, .mdio0_mdc
|
|
.hps_io_uart1_tx (hps_io_uart1_tx), // output, width = 1, .uart1_tx
|
|
.hps_io_uart1_rx (hps_io_uart1_rx), // input, width = 1, .uart1_rx
|
|
.hps_io_i2c1_sda (hps_io_i2c1_sda), // inout, width = 1, .i2c1_sda
|
|
.hps_io_i2c1_scl (hps_io_i2c1_scl), // inout, width = 1, .i2c1_scl
|
|
.hps_io_gpio28 (hps_io_gpio28), // inout, width = 1, .gpio28
|
|
.hps_io_gpio34 (hps_io_gpio34), // inout, width = 1, .gpio34
|
|
.hps_io_gpio40 (hps_io_gpio40), // inout, width = 1, .gpio40
|
|
.hps_io_gpio41 (hps_io_gpio41), // inout, width = 1, .gpio41
|
|
.f2h_irq1_in_irq (f2h_irq1_in_irq), // input, width = 32, f2h_irq1_in.irq
|
|
.f2h_irq0_in_irq (subsys_hps_f2h_irq0_in_irq), // input, width = 32, f2h_irq0_in.irq
|
|
.f2sdram_clk_clk (clk_100_out_clk_clk), // input, width = 1, f2sdram_clk.clk
|
|
.f2sdram_rst_reset (~rst_in_out_reset_reset), // input, width = 1, f2sdram_rst.reset
|
|
.f2sdram_araddr (f2sdram_araddr), // input, width = 32, f2sdram.araddr
|
|
.f2sdram_arburst (f2sdram_arburst), // input, width = 2, .arburst
|
|
.f2sdram_arcache (f2sdram_arcache), // input, width = 4, .arcache
|
|
.f2sdram_arid (f2sdram_arid), // input, width = 5, .arid
|
|
.f2sdram_arlen (f2sdram_arlen), // input, width = 8, .arlen
|
|
.f2sdram_arlock (f2sdram_arlock), // input, width = 1, .arlock
|
|
.f2sdram_arprot (f2sdram_arprot), // input, width = 3, .arprot
|
|
.f2sdram_arqos (f2sdram_arqos), // input, width = 4, .arqos
|
|
.f2sdram_arready (f2sdram_arready), // output, width = 1, .arready
|
|
.f2sdram_arsize (f2sdram_arsize), // input, width = 3, .arsize
|
|
.f2sdram_arvalid (f2sdram_arvalid), // input, width = 1, .arvalid
|
|
.f2sdram_awaddr (f2sdram_awaddr), // input, width = 32, .awaddr
|
|
.f2sdram_awburst (f2sdram_awburst), // input, width = 2, .awburst
|
|
.f2sdram_awcache (f2sdram_awcache), // input, width = 4, .awcache
|
|
.f2sdram_awid (f2sdram_awid), // input, width = 5, .awid
|
|
.f2sdram_awlen (f2sdram_awlen), // input, width = 8, .awlen
|
|
.f2sdram_awlock (f2sdram_awlock), // input, width = 1, .awlock
|
|
.f2sdram_awprot (f2sdram_awprot), // input, width = 3, .awprot
|
|
.f2sdram_awqos (f2sdram_awqos), // input, width = 4, .awqos
|
|
.f2sdram_awready (f2sdram_awready), // output, width = 1, .awready
|
|
.f2sdram_awsize (f2sdram_awsize), // input, width = 3, .awsize
|
|
.f2sdram_awvalid (f2sdram_awvalid), // input, width = 1, .awvalid
|
|
.f2sdram_bid (f2sdram_bid), // output, width = 5, .bid
|
|
.f2sdram_bready (f2sdram_bready), // input, width = 1, .bready
|
|
.f2sdram_bresp (f2sdram_bresp), // output, width = 2, .bresp
|
|
.f2sdram_bvalid (f2sdram_bvalid), // output, width = 1, .bvalid
|
|
.f2sdram_rdata (f2sdram_rdata), // output, width = 256, .rdata
|
|
.f2sdram_rid (f2sdram_rid), // output, width = 5, .rid
|
|
.f2sdram_rlast (f2sdram_rlast), // output, width = 1, .rlast
|
|
.f2sdram_rready (f2sdram_rready), // input, width = 1, .rready
|
|
.f2sdram_rresp (f2sdram_rresp), // output, width = 2, .rresp
|
|
.f2sdram_rvalid (f2sdram_rvalid), // output, width = 1, .rvalid
|
|
.f2sdram_wdata (f2sdram_wdata), // input, width = 256, .wdata
|
|
.f2sdram_wlast (f2sdram_wlast), // input, width = 1, .wlast
|
|
.f2sdram_wready (f2sdram_wready), // output, width = 1, .wready
|
|
.f2sdram_wstrb (f2sdram_wstrb), // input, width = 32, .wstrb
|
|
.f2sdram_wvalid (f2sdram_wvalid), // input, width = 1, .wvalid
|
|
.f2sdram_aruser (f2sdram_aruser), // input, width = 8, .aruser
|
|
.f2sdram_awuser (f2sdram_awuser), // input, width = 8, .awuser
|
|
.f2sdram_wuser (f2sdram_wuser), // input, width = 8, .wuser
|
|
.f2sdram_buser (f2sdram_buser), // output, width = 8, .buser
|
|
.f2sdram_arregion (f2sdram_arregion), // input, width = 4, .arregion
|
|
.f2sdram_ruser (f2sdram_ruser), // output, width = 8, .ruser
|
|
.f2sdram_awregion (f2sdram_awregion), // input, width = 4, .awregion
|
|
.emif_hps_emif_mem_0_mem_cs (emif_hps_emif_mem_0_mem_cs), // output, width = 1, emif_hps_emif_mem_0.mem_cs
|
|
.emif_hps_emif_mem_0_mem_ca (emif_hps_emif_mem_0_mem_ca), // output, width = 6, .mem_ca
|
|
.emif_hps_emif_mem_0_mem_cke (emif_hps_emif_mem_0_mem_cke), // output, width = 1, .mem_cke
|
|
.emif_hps_emif_mem_0_mem_dq (emif_hps_emif_mem_0_mem_dq), // inout, width = 32, .mem_dq
|
|
.emif_hps_emif_mem_0_mem_dqs_t (emif_hps_emif_mem_0_mem_dqs_t), // inout, width = 4, .mem_dqs_t
|
|
.emif_hps_emif_mem_0_mem_dqs_c (emif_hps_emif_mem_0_mem_dqs_c), // inout, width = 4, .mem_dqs_c
|
|
.emif_hps_emif_mem_0_mem_dmi (emif_hps_emif_mem_0_mem_dmi), // inout, width = 4, .mem_dmi
|
|
.emif_hps_emif_mem_ck_0_mem_ck_t (emif_hps_emif_mem_ck_0_mem_ck_t), // output, width = 1, emif_hps_emif_mem_ck_0.mem_ck_t
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|
.emif_hps_emif_mem_ck_0_mem_ck_c (emif_hps_emif_mem_ck_0_mem_ck_c), // output, width = 1, .mem_ck_c
|
|
.emif_hps_emif_mem_reset_n_mem_reset_n (emif_hps_emif_mem_reset_n_mem_reset_n), // output, width = 1, emif_hps_emif_mem_reset_n.mem_reset_n
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|
.emif_hps_emif_oct_0_oct_rzqin (emif_hps_emif_oct_0_oct_rzqin), // input, width = 1, emif_hps_emif_oct_0.oct_rzqin
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|
.emif_hps_emif_ref_clk_clk (emif_hps_emif_ref_clk_0_clk) // input, width = 1, emif_hps_emif_ref_clk.clk
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);
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peripheral_subsys subsys_periph (
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.button_pio_external_connection_export (button_pio_external_connection_export), // input, width = 4, button_pio_external_connection.export
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.button_pio_irq_irq (irq_mapper_receiver0_irq), // output, width = 1, button_pio_irq.irq
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.dipsw_pio_external_connection_export (dipsw_pio_external_connection_export), // input, width = 4, dipsw_pio_external_connection.export
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.dipsw_pio_irq_irq (irq_mapper_receiver1_irq), // output, width = 1, dipsw_pio_irq.irq
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.led_pio_external_connection_in_port (led_pio_external_connection_in_port), // input, width = 3, led_pio_external_connection.in_port
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.led_pio_external_connection_out_port (led_pio_external_connection_out_port), // output, width = 3, .out_port
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.pb_cpu_0_s0_waitrequest (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest), // output, width = 1, pb_cpu_0_s0.waitrequest
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.pb_cpu_0_s0_readdata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata), // output, width = 32, .readdata
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.pb_cpu_0_s0_readdatavalid (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid), // output, width = 1, .readdatavalid
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.pb_cpu_0_s0_burstcount (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount), // input, width = 1, .burstcount
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.pb_cpu_0_s0_writedata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata), // input, width = 32, .writedata
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.pb_cpu_0_s0_address (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address), // input, width = 17, .address
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.pb_cpu_0_s0_write (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write), // input, width = 1, .write
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.pb_cpu_0_s0_read (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read), // input, width = 1, .read
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.pb_cpu_0_s0_byteenable (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable), // input, width = 4, .byteenable
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.pb_cpu_0_s0_debugaccess (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess), // input, width = 1, .debugaccess
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.clk_clk (clk_100_out_clk_clk), // input, width = 1, clk.clk
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.reset_reset_n (rst_in_out_reset_reset) // input, width = 1, reset.reset_n
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);
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qsys_top_altera_mm_interconnect_1920_ykfyxdi mm_interconnect_0 (
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.subsys_hps_lwhps2fpga_awid (subsys_hps_lwhps2fpga_awid), // input, width = 4, subsys_hps_lwhps2fpga.awid
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.subsys_hps_lwhps2fpga_awaddr (subsys_hps_lwhps2fpga_awaddr), // input, width = 29, .awaddr
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.subsys_hps_lwhps2fpga_awlen (subsys_hps_lwhps2fpga_awlen), // input, width = 8, .awlen
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.subsys_hps_lwhps2fpga_awsize (subsys_hps_lwhps2fpga_awsize), // input, width = 3, .awsize
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.subsys_hps_lwhps2fpga_awburst (subsys_hps_lwhps2fpga_awburst), // input, width = 2, .awburst
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.subsys_hps_lwhps2fpga_awlock (subsys_hps_lwhps2fpga_awlock), // input, width = 1, .awlock
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.subsys_hps_lwhps2fpga_awcache (subsys_hps_lwhps2fpga_awcache), // input, width = 4, .awcache
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.subsys_hps_lwhps2fpga_awprot (subsys_hps_lwhps2fpga_awprot), // input, width = 3, .awprot
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.subsys_hps_lwhps2fpga_awvalid (subsys_hps_lwhps2fpga_awvalid), // input, width = 1, .awvalid
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|
.subsys_hps_lwhps2fpga_awready (subsys_hps_lwhps2fpga_awready), // output, width = 1, .awready
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|
.subsys_hps_lwhps2fpga_wdata (subsys_hps_lwhps2fpga_wdata), // input, width = 32, .wdata
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.subsys_hps_lwhps2fpga_wstrb (subsys_hps_lwhps2fpga_wstrb), // input, width = 4, .wstrb
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|
.subsys_hps_lwhps2fpga_wlast (subsys_hps_lwhps2fpga_wlast), // input, width = 1, .wlast
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|
.subsys_hps_lwhps2fpga_wvalid (subsys_hps_lwhps2fpga_wvalid), // input, width = 1, .wvalid
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.subsys_hps_lwhps2fpga_wready (subsys_hps_lwhps2fpga_wready), // output, width = 1, .wready
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|
.subsys_hps_lwhps2fpga_bid (subsys_hps_lwhps2fpga_bid), // output, width = 4, .bid
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|
.subsys_hps_lwhps2fpga_bresp (subsys_hps_lwhps2fpga_bresp), // output, width = 2, .bresp
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|
.subsys_hps_lwhps2fpga_bvalid (subsys_hps_lwhps2fpga_bvalid), // output, width = 1, .bvalid
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.subsys_hps_lwhps2fpga_bready (subsys_hps_lwhps2fpga_bready), // input, width = 1, .bready
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.subsys_hps_lwhps2fpga_arid (subsys_hps_lwhps2fpga_arid), // input, width = 4, .arid
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|
.subsys_hps_lwhps2fpga_araddr (subsys_hps_lwhps2fpga_araddr), // input, width = 29, .araddr
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|
.subsys_hps_lwhps2fpga_arlen (subsys_hps_lwhps2fpga_arlen), // input, width = 8, .arlen
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|
.subsys_hps_lwhps2fpga_arsize (subsys_hps_lwhps2fpga_arsize), // input, width = 3, .arsize
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|
.subsys_hps_lwhps2fpga_arburst (subsys_hps_lwhps2fpga_arburst), // input, width = 2, .arburst
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|
.subsys_hps_lwhps2fpga_arlock (subsys_hps_lwhps2fpga_arlock), // input, width = 1, .arlock
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|
.subsys_hps_lwhps2fpga_arcache (subsys_hps_lwhps2fpga_arcache), // input, width = 4, .arcache
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|
.subsys_hps_lwhps2fpga_arprot (subsys_hps_lwhps2fpga_arprot), // input, width = 3, .arprot
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|
.subsys_hps_lwhps2fpga_arvalid (subsys_hps_lwhps2fpga_arvalid), // input, width = 1, .arvalid
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|
.subsys_hps_lwhps2fpga_arready (subsys_hps_lwhps2fpga_arready), // output, width = 1, .arready
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|
.subsys_hps_lwhps2fpga_rid (subsys_hps_lwhps2fpga_rid), // output, width = 4, .rid
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|
.subsys_hps_lwhps2fpga_rdata (subsys_hps_lwhps2fpga_rdata), // output, width = 32, .rdata
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|
.subsys_hps_lwhps2fpga_rresp (subsys_hps_lwhps2fpga_rresp), // output, width = 2, .rresp
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|
.subsys_hps_lwhps2fpga_rlast (subsys_hps_lwhps2fpga_rlast), // output, width = 1, .rlast
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|
.subsys_hps_lwhps2fpga_rvalid (subsys_hps_lwhps2fpga_rvalid), // output, width = 1, .rvalid
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|
.subsys_hps_lwhps2fpga_rready (subsys_hps_lwhps2fpga_rready), // input, width = 1, .rready
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|
.subsys_periph_pb_cpu_0_s0_address (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_address), // output, width = 17, subsys_periph_pb_cpu_0_s0.address
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|
.subsys_periph_pb_cpu_0_s0_write (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_write), // output, width = 1, .write
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|
.subsys_periph_pb_cpu_0_s0_read (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_read), // output, width = 1, .read
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|
.subsys_periph_pb_cpu_0_s0_readdata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdata), // input, width = 32, .readdata
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|
.subsys_periph_pb_cpu_0_s0_writedata (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_writedata), // output, width = 32, .writedata
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|
.subsys_periph_pb_cpu_0_s0_burstcount (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_burstcount), // output, width = 1, .burstcount
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|
.subsys_periph_pb_cpu_0_s0_byteenable (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_byteenable), // output, width = 4, .byteenable
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|
.subsys_periph_pb_cpu_0_s0_readdatavalid (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_readdatavalid), // input, width = 1, .readdatavalid
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|
.subsys_periph_pb_cpu_0_s0_waitrequest (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_waitrequest), // input, width = 1, .waitrequest
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|
.subsys_periph_pb_cpu_0_s0_debugaccess (mm_interconnect_0_subsys_periph_pb_cpu_0_s0_debugaccess), // output, width = 1, .debugaccess
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|
.subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // input, width = 1, subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset.reset
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|
.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // input, width = 1, subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset.reset
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|
.clk_100_out_clk_clk (clk_100_out_clk_clk) // input, width = 1, clk_100_out_clk.clk
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|
);
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|
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|
qsys_top_altera_irq_mapper_2001_lp4cnei irq_mapper (
|
|
.clk (), // input, width = 1, clk.clk
|
|
.reset (), // input, width = 1, clk_reset.reset
|
|
.receiver0_irq (irq_mapper_receiver0_irq), // input, width = 1, receiver0.irq
|
|
.receiver1_irq (irq_mapper_receiver1_irq), // input, width = 1, receiver1.irq
|
|
.sender_irq (subsys_hps_f2h_irq0_in_irq) // output, width = 32, sender.irq
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|
);
|
|
|
|
altera_reset_controller #(
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|
.NUM_RESET_INPUTS (1),
|
|
.OUTPUT_RESET_SYNC_EDGES ("both"),
|
|
.SYNC_DEPTH (2),
|
|
.RESET_REQUEST_PRESENT (0),
|
|
.RESET_REQ_WAIT_TIME (1),
|
|
.MIN_RST_ASSERTION_TIME (3),
|
|
.RESET_REQ_EARLY_DSRT_TIME (1),
|
|
.USE_RESET_REQUEST_IN0 (0),
|
|
.USE_RESET_REQUEST_IN1 (0),
|
|
.USE_RESET_REQUEST_IN2 (0),
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|
.USE_RESET_REQUEST_IN3 (0),
|
|
.USE_RESET_REQUEST_IN4 (0),
|
|
.USE_RESET_REQUEST_IN5 (0),
|
|
.USE_RESET_REQUEST_IN6 (0),
|
|
.USE_RESET_REQUEST_IN7 (0),
|
|
.USE_RESET_REQUEST_IN8 (0),
|
|
.USE_RESET_REQUEST_IN9 (0),
|
|
.USE_RESET_REQUEST_IN10 (0),
|
|
.USE_RESET_REQUEST_IN11 (0),
|
|
.USE_RESET_REQUEST_IN12 (0),
|
|
.USE_RESET_REQUEST_IN13 (0),
|
|
.USE_RESET_REQUEST_IN14 (0),
|
|
.USE_RESET_REQUEST_IN15 (0),
|
|
.ADAPT_RESET_REQUEST (0)
|
|
) rst_controller (
|
|
.reset_in0 (~rst_in_out_reset_reset), // input, width = 1, reset_in0.reset
|
|
.clk (clk_100_out_clk_clk), // input, width = 1, clk.clk
|
|
.reset_out (rst_controller_reset_out_reset), // output, width = 1, reset_out.reset
|
|
.reset_req (), // (terminated),
|
|
.reset_req_in0 (1'b0), // (terminated),
|
|
.reset_in1 (1'b0), // (terminated),
|
|
.reset_req_in1 (1'b0), // (terminated),
|
|
.reset_in2 (1'b0), // (terminated),
|
|
.reset_req_in2 (1'b0), // (terminated),
|
|
.reset_in3 (1'b0), // (terminated),
|
|
.reset_req_in3 (1'b0), // (terminated),
|
|
.reset_in4 (1'b0), // (terminated),
|
|
.reset_req_in4 (1'b0), // (terminated),
|
|
.reset_in5 (1'b0), // (terminated),
|
|
.reset_req_in5 (1'b0), // (terminated),
|
|
.reset_in6 (1'b0), // (terminated),
|
|
.reset_req_in6 (1'b0), // (terminated),
|
|
.reset_in7 (1'b0), // (terminated),
|
|
.reset_req_in7 (1'b0), // (terminated),
|
|
.reset_in8 (1'b0), // (terminated),
|
|
.reset_req_in8 (1'b0), // (terminated),
|
|
.reset_in9 (1'b0), // (terminated),
|
|
.reset_req_in9 (1'b0), // (terminated),
|
|
.reset_in10 (1'b0), // (terminated),
|
|
.reset_req_in10 (1'b0), // (terminated),
|
|
.reset_in11 (1'b0), // (terminated),
|
|
.reset_req_in11 (1'b0), // (terminated),
|
|
.reset_in12 (1'b0), // (terminated),
|
|
.reset_req_in12 (1'b0), // (terminated),
|
|
.reset_in13 (1'b0), // (terminated),
|
|
.reset_req_in13 (1'b0), // (terminated),
|
|
.reset_in14 (1'b0), // (terminated),
|
|
.reset_req_in14 (1'b0), // (terminated),
|
|
.reset_in15 (1'b0), // (terminated),
|
|
.reset_req_in15 (1'b0) // (terminated),
|
|
);
|
|
|
|
endmodule
|