thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
35 lines
1.4 KiB
Tcl
35 lines
1.4 KiB
Tcl
# (C) 2001-2026 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions and
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# other software and tools, and its AMPP partner logic functions, and
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# any output files any of the foregoing (including device programming
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# or simulation files), and any associated documentation or information
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# are expressly subject to the terms and conditions of the Intel
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# Program License Subscription Agreement, Intel MegaCore Function
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# License Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Intel and sold by Intel
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# or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# ACDS 26.1 110 linux 2026.04.08.10:52:56
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# ----------------------------------------
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# Auto-generated simulation script run_rivierapro_setup.tcl
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# ----------------------------------------
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# This script provides commands to run the rivierapro_setup.tcl script for the following IP detected in
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# your Quartus project:
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# qsys_top
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#
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#
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# Intel recommends that you source this Quartus-generated IP simulation
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# script to compile, elab and run the design without any customization.
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# For customization, please follow the steps mentioned in rivierapro_setup.tcl.
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if ![info exists QSYS_SIMDIR] {
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set QSYS_SIMDIR "./../"
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}
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source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
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ld
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run -all
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quit
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