retroDE_ps2/qsys/qsys_top/qsys_top.spd

<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
 <file
   path="altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_axi_translator_1987" />
 <file
   path="altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_slave_translator_191" />
 <file
   path="altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_axi_master_ni_19117" />
 <file
   path="altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_axi_master_ni_19117" />
 <file
   path="altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_slave_agent_1930" />
 <file
   path="altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_slave_agent_1930" />
 <file
   path="altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v"
   type="VERILOG"
   library="altera_avalon_sc_fifo_1932" />
 <file
   path="altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_router_1921" />
 <file
   path="altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_router_1921" />
 <file
   path="altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv"
   type="SYSTEM_VERILOG"
   library="altera_avalon_st_pipeline_stage_1930" />
 <file
   path="altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v"
   type="SYSTEM_VERILOG"
   library="altera_avalon_st_pipeline_stage_1930" />
 <file
   path="altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v"
   type="VERILOG"
   library="altera_merlin_burst_adapter_1940"
   hasInlineConfiguration="true" />
 <file
   path="altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_burst_adapter_1940" />
 <file
   path="altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_burst_adapter_1940" />
 <file
   path="altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_burst_adapter_1940" />
 <file
   path="altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_burst_adapter_1940" />
 <file
   path="altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_burst_adapter_1940" />
 <file
   path="altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_burst_adapter_1940" />
 <file
   path="altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_burst_adapter_1940" />
 <file
   path="altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_burst_adapter_1940" />
 <file
   path="altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_demultiplexer_1921" />
 <file
   path="altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_multiplexer_1922" />
 <file
   path="altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_multiplexer_1922" />
 <file
   path="altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_demultiplexer_1921" />
 <file
   path="altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_multiplexer_1922" />
 <file
   path="altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"
   type="SYSTEM_VERILOG"
   library="altera_merlin_multiplexer_1922" />
 <file
   path="altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v"
   type="VERILOG"
   library="altera_mm_interconnect_1920"
   hasInlineConfiguration="true" />
 <file
   path="altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv"
   type="SYSTEM_VERILOG"
   library="altera_irq_mapper_2001" />
 <file
   path="altera_reset_controller_1924/sim/altera_reset_controller.v"
   type="VERILOG"
   library="altera_reset_controller_1924" />
 <file
   path="altera_reset_controller_1924/sim/altera_reset_synchronizer.v"
   type="VERILOG"
   library="altera_reset_controller_1924" />
 <file
   path="altera_reset_controller_1924/sim/altera_reset_controller.sdc"
   type="SDC_ENTITY"
   library="altera_reset_controller_1924" />
 <file
   path="sim/qsys_top.v"
   type="VERILOG"
   library="qsys_top"
   hasInlineConfiguration="true" />
 <topLevel name="qsys_top.qsys_top" />
 <deviceFamily name="agilex5" />
 <device name="A5EB013BB23BE4SCS" />
</simPackage>